International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
INVESTIGATION ON SINGLE PHASE MULTI LEVEL
INVERTER WITH SERIES CONNECTION OF SUB
MULTI LEVEL INVERTERS
V.ARUN#1, B.SHANTHI#2, K.RAJA#3
#1 Department of EEE, Arunai Engineering College, Thiruvannamalai, Tamilnadu, India.
#2 Centralised Instrumentation and Service Laboratory, Annamalai University, Chidambaram,
Tamilnadu, India.
#3 Department of EEE, Arunai Engineering College, Thiruvannamalai, Tamilnadu, India.
ABSTRACT
This paper focuses on a new topology with a reversing-voltage component is
proposed to improve the multilevel performance. This topology requires fewer components
compared to conventional inverters and requires fewer carrier signals and gate drives.
Unipolar Sine Pulse Width Modulating (USPWM) strategies using sine reference and 60
degree PWM reference with triangular carriers. It includes Phase Disposition (PD) strategy,
Alternate Phase Opposition Disposition (APOD) strategy, Carrier Overlapping (CO) strategy
and Variable Frequency (VF) strategy. The performance measures like Total Harmonic
Distortion (THD), VRMS (fundamental), crest factor, form factor and distortion factor are
evaluated for various modulation indices. Simulation is performed using MATLABSIMULINK.
Key words: APOD, CO, PD,VF, PWM.
INTRODUCTION
Multilevel inverter have gained much attention in the area distribution and control due to
its advantages in high power applications with low harmonics. Corzine et al [1] developed
asymmetrical cascade multilevel converters With noninteger or dynamically changing dc
Voltage. Varschavsky et al [2] proposed cascaded nine-level inverter for hybrid-series active
power filter. Pereda and Dixon [3] introduced only one dc power source in asymmetric cascade
multilevel inverter. Govindaraju and Baskaran[4] introduced efficient sequential switching
hybrid-modulation techniques for cascaded multilevel inverters. Kevin in [5] analyzed
pulsewidth-modulation methods for three-level neutral-point-clamped medium-voltage industrial
drives. Cougo et al [6] proposed PD modulation control techniques for Three-Phase Parallel
Multilevel Inverters. Kangarlu and Babaei[7] proposed Generalized Cascaded Multilevel Inverter
Using Series Connection of Submultilevel Inverters. . Mariethoz[8] developed Hybrid Cascaded
Multilevel Inverters With Active Voltage Balance and Minimum Switching Losses. Hagiwara et
al[4] developed start-up and low-speed operation of an Electric Motor Driven by a Modular
Multilevel Cascade Inverte. Rajeevan et al [9] introduced Nine-Level Inverter Topology for
Medium-Voltage Induction Motor Drive With Open-End Stator Winding. . Hagiwara et al[10]
R S. Publication, rspublicationhouse@gmail.com
Page 511
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
developed start-up and low-speed operation of an Electric Motor Driven by a Modular Multilevel
Cascade Inverter. This paper presents a single phase binary DC source 15 level inverter topology
for investigation with various USPWM switching strategies. Simulations were performed using
MATLAB-SIMULINK. Harmonic analysis and evaluation of different performance measures
for various modulation indices have been carried out and presented.
PROPOSED ASYMMETRICAL MULTILEVEL INVERTER
The proposed new asymmetric cascaded multilevel inverter is shown in Figure 1. inverter
consists of 3 sub multilevel inverter and H bridge. Conversion cell consists of separate voltage
sources(V1,V2,V3) connected in cascade and two active switching elements that can make the
output voltage in positive polarity with several levels.H bridge consists of four active switching
element that can make the output voltage in positive or in negative polarity depending on the
switching condition. By using Vdc,2Vdcand 4Vdc, it can synthesize 15 output levels;-7Vdc,6Vdc,-5Vdc, -4Vdc, -3Vdc, -2Vdc, -Vdc, 0, Vdc, 2Vdc, 3Vdc, 4Vdc,5Vdc,6Vdc,7Vdc.
Expected output voltage level is given by
Vn=2n+1-1,where n=1,2,4…….
Fig 1: proposed multilevel inverter
MULTI CARRIER BASED PWM METHODS
In this proposed work a unipolar sine wave with a triangular carrier is used to generate
firing pulses for a 15 level inverter. For an m-level inverter using unipolar multi-carrier
Strategies, (m-1)/2 carriers with the same frequency fc and same peak-to-peak amplitude Ac are
used. The reference waveform has amplitude Am and frequency fm and it is placed at the zero
reference. The reference wave is continuously compared with each of the carrier signals. If the
reference wave is more than a carrier signal, then the active devices corresponding to that carrier
are switched on. Otherwise, the device switches off. There are many alternative strategies are
possible, some of them are tried in this paper and they are:
R S. Publication, rspublicationhouse@gmail.com
Page 512
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
a. Phase disposition PWM strategy.(UPDPWM)
b. Alternate phase opposition disposition PWM strategy.(UAPODPWM)
c. Carrier overlapping PWM strategy.(UCOPWM)
d. Variable frequency PWM strategy.(UVFPWM)
The formulae to find the Amplitude of modulation indices are as follows:
For PDPWM, APODPWM and VFPWM:
ma= 2Am /( m-1)Ac )
For COPWM:
ma =Am /(2*Ac)
A. Unipolar Phase disposition PWM strategy
In case of UPDPWM strategy, all the carrier waveforms are in phase. The carrier
arrangement of sinusoidal references and 60 degree reference are illustrated in figures 2 and 3
respectively.
Fig 2: Carrier arrangements for UPDPWM strategy with sinusoidal reference (ma = 0.9 and mf =
40)
Fig 3:Carrier arrangements for UPDPWM strategy with 60 Degree PWM reference (ma = 0.9 and
mf = 40)
R S. Publication, rspublicationhouse@gmail.com
Page 513
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
B. Unipolar Alternate phase opposition disposition PWM strategy
In case of UAPOD PWM, every carrier waveform is in out of phase with its neighboring
carrier by 180°. The carrier arrangement of sinusoidal references and 60 degree pwm reference
are illustrated in figures 4 and 5 respectively.
Fig 4: Carrier arrangements for UAPODPWM strategy with sinusoidal reference (ma = 0.9 and
mf = 40)
Fig. 5. Carrier arrangements for UAPODPWM strategy with 60 Degree PWM reference (ma =
0.9 and mf = 40)
C. Unipolar Carrier overlapping PWM strategy
In carrier overlapping technique, (m-1)/2 carriers are disposed such that the bands they
occupy overlap each other; the overlapping vertical distance between each carrier is Ac/2. The
carrier arrangement of sinusoidal references and 60 degree pwm reference are illustrated in
figures 6 and 7 respectively.
R S. Publication, rspublicationhouse@gmail.com
Page 514
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 6: Carrier arrangements for UCOPWM strategy with sinusoidal reference (ma = 0.9 and mf =
40)
Fig 7: Carrier arrangements for UCOPWM strategy with 60 Degree PWM reference (ma = 0.9
and mf = 40)
D. Unipolar Variable frequency PWM strategy
The number of switching for upper and lower devices of chosen MLI is much more than
that of intermediate switches in PDPWM using constant frequency carriers. In order to equalize
the number of switching for all the switches, variable frequency PWM strategy is used. The
carrier arrangement of sinusoidal references and 60 degree pwm reference are illustrated in
figures 8 and 9 respectively.
Fig 8: Carrier arrangements for UVFPWM strategy with sinusoidal reference (ma = 0.9
and mf = 40)
R S. Publication, rspublicationhouse@gmail.com
Page 515
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 9: Carrier arrangements for UVFPWM strategy with 60 Degree PWM reference (ma = 0.9
and mf = 40)
SIMULATION RESULT
The single phase binary DC source 15 level inverter is modeled in SIMULINK using
power system block set. Switching signals for binary multilevel inverter using USPWM
strategies are simulated .Fig .10 (a) and (b) respectively shows the 15 level output voltage
generated by UPDPWM strategies with sine sinusoidal reference and its FFT plot. Fig .11 (a)
and (b) respectively shows the 15 level output voltage generated by UPDPWM strategies with 60
degree PWM reference and its FFT plot. Fig .12 (a) and (b) respectively shows the 15 level
output voltage generated by UAPODPWM strategies with sine sinusoidal reference and its FFT
plot. . Fig .13 (a) and (b) respectively shows the 15 level output voltage generated by
UAPODPWM strategies with 60 degree PWM reference and its FFT plot.Fig .14 (a) and (b)
respectively shows the 15 level output voltage generated by UCOPWM strategies with
sinusoidal reference and its FFT plot. Fig .15 (a) and (b) respectively shows the 15 level output
voltage generated by UCOPWM strategies with 60 degree PWM reference and its FFT plot.
Fig .16 (a) and (b) respectively shows the 15 level output voltage generated by UVFPWM
strategies with sine sinusoidal reference and its FFT plot. . Fig .17 (a) and (b) respectively shows
the 15 level output voltage generated by UCOPWM strategies with 60 degree PWM reference
and its FFT plot. Simulations were performed for different values of ma ranging from 0.8 to 1
and the corresponding %THD are measured using the FFT block and their values are shown in
Table 1. Table 2 represents the VRMS of the inverter output voltage. Table 3 represents the crest
factor of the output voltage. Table 4 and 5 represents the form factor and distortion factor of
the output voltage. For ma= 0.9, it is observed that 10b 11b 12b 13b 14b 15b 16b 17b harmonic
energy is dominant in:10b) 39th order in UPDPWM strategy with sinusoidal reference.11b)
7th,35th ,37th ,39th order in UPDPWM strategy with 60 degree PWM reference.12b) 39th order in
UAPODPWM strategy with sinusoidal reference.13b) 5th,19th,39th, order in UAPODPWM
strategy with 60 degree PWM reference.14b) 38th ,39th, order in UCOPWM strategy with
sinusoidal reference.15b) 3rd ,5th,38th,39th order in UCOPWM strategy with degree PWM
reference.16b) 19th,31st,33th,37th ,39th order in UVFPWM strategy with sinusoidal reference.17b)
3rd ,5th,17th,19th,39th,order in UVFPWM strategy with 60 degree PWM reference. The following
parameter values are used for simulation: Vdc =21.5V, R (load) = 100 ohms, fc=2000 Hz and
fm=50Hz.
R S. Publication, rspublicationhouse@gmail.com
Page 516
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 10(a): Output voltage generated by UPDPWM strategy with sinusoidal reference
Fig 10 (b): FFT plot for output voltage of UPDPWM strategy with sinusoidal reference
Fig 11 (a): Output voltage generated by UPDPWM strategy with 60 degree PWM reference
Fig 11 (b): FFT plot for output voltage of UPDPWM strategy with 60 degree PWM reference
R S. Publication, rspublicationhouse@gmail.com
Page 517
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 12 (a): Output voltage generated by UAPODPWM strategy with sinusoidal reference
Fig 12 (b): FFT plot for output voltage of UAPODPWM strategy with sinusoidal reference
Fig 13 (a): Output voltage generated by UAPODPWM strategy with 60 degree PWM reference
Fig 13 (b): FFT plot for output voltage of UAPODPWM strategy with 60 degree PWM reference
R S. Publication, rspublicationhouse@gmail.com
Page 518
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 14 (a): Output voltage generated by UCOPWM strategy with sinusoidal reference
Fig 14 (b): FFT plot for output voltage of UCOPWM strategy with sinusoidal reference
Fig 15 (a): Output voltage generated by UCOPWM strategy with 60 degree PWM reference
Fig 15(b): FFT plot for output voltage of UCOPWM strategy with 60 degree PWM reference
R S. Publication, rspublicationhouse@gmail.com
Page 519
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
Fig 16 (a): Output voltage generated by UVFPWM strategy with sinusoidal reference
Fig 16 (b): FFT plot for output voltage of UVFPWM strategy with sinusoidal reference
Fig 17 (a): Output voltage generated by UVFPWM strategy with 60 degree PWM reference
Fig 17 (b): FFT plot for output voltage of UVFPWM strategy with 60 degree PWM reference
R S. Publication, rspublicationhouse@gmail.com
Page 520
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
TABLE 1. %THD FOR DIFFERENT MODULATION INDICES
Ma
1
0.95
0.9
UPDPWM
Sine Ref. 60 Degree
PWM Ref
8.62
8.47
8.56
11.09
8.29
11.41
UAPODPWM
Sine Ref. 60 Degree
PWM Ref
8.10
8.62
8.40
10.12
8.97
10.61
UCOPWM
Sine Ref. 60 Degree
PWM Ref
11.15
11.62
12.43
12.39
13.87
12.66
UVFPWM
Sine Ref. 60 Degree
PWM Ref
7.67
7.73
8.38
10.07
8.66
10.30
TABLE 2.VRMS FOR DIFFERENT MODULATION INDICES
Ma
1
0.95
0.9
UPDPWM
Sine Ref. 60 Degree
PWM Ref
106.1
106.1
100.7
100.7
95.47
95.47
UAPODPWM
Sine Ref. 60 Degree
PWM Ref
106.4
106.4
101.1
101.1
95.76
95.76
UCOPWM
Sine Ref.
60 Degree
PWM Ref
106.6
109
104.6
104.6
99.44
99.44
UVFPWM
Sine Ref. 60 Degree
PWMRef
106.5
106.5
101.6
101.6
95.4
95.4
TABLE 3.CF FOR DIFFERENT MODULATION INDICES
Ma
1
0.95
0.9
UPDPWM
Sine Ref. 60 Degree
PWM Ref
1.41371
1.414445
1.41318
1.414941
1.41405
1.413628
UAPODPWM
Sine Ref.
60 Degree
PWM Ref
1.41444
1.41415
1.41441
1.414325
1.41395
1.415311
UCOPWM
Sine Ref. 60 Degree
PWM Ref
1.41467
1.413823
1.41491
1.41364
1.41495
1.414365
UVFPWM
Sine Ref. 60 Degree
PWM Ref
1.41408
1.413403
1.41437
1.414013
1.41404
1.414423
TABLE 4. FORM FACTOR FOR DIFFERENT MODULATION INDICES
Ma
UPDPWM
UAPODPWM
UCOPWM
Sine Ref.
60 Degree
PWM Ref
1.918E+9 2.24E+04
Sine Ref.
Sine Ref.
1.924E+9
60 Degree
PWM Ref
2.27E+04
0.95 1.94E+09 1.91E+09
1.92E+09
0.9
1.91E+09
1
1.8E+09
1.31E+06
UVFPWM
Sine Ref.
1.95609
60 Degree
PWM Ref
1.98E+09
2.03E+09
60 Degree
PWM Ref
2.20E+04
2.00E+09
1.97E+09
1.99E+09
1.98E+09
1.96E+09
2.10E+09
1.9E+09
1.98E+09
1.77E+09
2.08E+09
R S. Publication, rspublicationhouse@gmail.com
Page 521
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
TABLE 5. DISTORTION FACTOR FOR DIFFERENT MODULATION INDICES
Ma
1
0.95
UPDPWM
Sine Ref. 60 Degree
PWM Ref
0.0009727 0.006226
0.0013283 0.007029
UAPODPWM
Sine Ref. 60 Degree
PWM Ref
9.3E-05
0.005598
9.4E-05
0.005725
UCOPWM
Sine Ref. 60 Degree
PWM Ref
0.001235 0.006684
0.001808 0.005192
UVFPWM
Sine Ref. 60 Degree
PWM Ref
0.00083
0.004196
0.000683 0.005146
0.9
0.0007261 0.005531
9.0E-05
0.003449
0.000667
0.005793
0.004024
0.005003
CONCLUSION
In this paper, USPWM techniques for binary DC source 15 level inverter have been
presented. Binary DC source multilevel inverter gives higher output voltage with reduced switch
count and low harmonics. Performance factors like % THD,VRMS,CF,FF and DF have been
evaluated presented and analyzed. It is found that the UPDPWM strategy with 60 degree PWM
reference provides relatively lower %THD, UCOPWM strategy with 60 degree PWM reference
is found to perform relatively higher fundamental RMS output voltage. CF is almost same for all
the strategies. FF is almost same for all the strategies. DF relatively low in UPDPWM strategy
with sinusoidal reference.
REFERENCES
[1] S. Lu, S. Mariéthoz, and K. A. Corzine, “Asymmetrical Cascade Multilevel Converters With
Noninteger or Dynamically Changing DC Voltage Ratios : Concepts and Modulation
Techniques,” IEEE Transactions on Industrial Electronics, vol. 57, no. 7, pp. 2411–2418, 2010.
[2] A. Varschavsky, J. Dixon, M. Rotella, and L. Morán, “Cascaded Nine-Level Inverter for
Hybrid-Series Active Power Filter , Using Industrial Controller,” IEEE Transactions on
Industrial Electronics, vol. 57, no. 8, pp. 2761–2767, 2010.
[3] J. Pereda and J. Dixon, “High-Frequency Link : A Solution for Using Only One DC Source in
Asymmetric Cascaded Multilevel Inverters,” IEEE Transactions on Industrial Electronics, vol.
58, no. 9, pp. 3884–3892, 2011.
[4] C. Govindaraju and K. Baskaran, “Efficient Sequential Switching Hybrid-Modulation
Techniques for Cascaded Multilevel Inverters,” IEEE Transactions on Power Electronics, vol.
26, no. 6, pp. 1639–1648, 2011.
[5] G. N. Kevin Lee, “Quantitative Power Quality and Characteristic Analysis of Multilevel
Pulsewidth-Modulation Methods for Three-Level Neutral-Point-Clamped Medium-Voltage
Industrial Drives,” IEEE Transactions on Industry Applications, vol. 48, no. 4, pp. 1364–1373,
2012.
R S. Publication, rspublicationhouse@gmail.com
Page 522
International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 5, Sep.-Oct. 2013
ISSN 2249-9954
[6] B. Cougo, G. Gateau, T. Meynard, M. Bobrowska-rafal, and M. Cousineau, “PD Modulation
Scheme for Three-Phase Parallel Multilevel Inverters,” IEEE Transactions on Industrical
Electronics, vol. 59, no. 2, pp. 690–700, 2012.
[7] M. F. Kangarlu and E. Babaei, “A Generalized Cascaded Multilevel Inverter Using Series
Connection of Submultilevel Inverters,” IEEE Transactions on Power Electronics, vol. 28, no. 2,
pp. 625–636, 2013.
[8] S. Mariethoz, “Systematic Design of High-Performance Hybrid Cascaded Multilevel
Inverters With Active Voltage Balance and Minimum Switching Losses,” IEEE Transactions on
Power Electronics, vol. 28, no. 7, pp. 3100–3113, 2013.
[9] P. P. Rajeevan, K. Sivakumar, K. Gopakumar, C. Patel, and H. Abu-rub, “A Nine-Level
Inverter Topology for Medium-Voltage Induction Motor Drive With Open-End Stator Winding,”
IEEE Transactions on Industrical Electronics, vol. 60, no. 9, pp. 3627–3636, 2013.
[10] M. Hagiwara, I. Hasegawa, and H. Akagi, “Start-Up and Low-Speed Operation of an
Electric Motor Driven by a Modular Multilevel Cascade Inverter,” IEEE Transactions on
Industry Applications, vol. 49, no. 4, pp. 1556–1565, 2013.
R S. Publication, rspublicationhouse@gmail.com
Page 523