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SYMMETRICAL HYBRID MULTILEVEL DC-AC CONVERTER IN CASCADE Héctor Vergara* Miguel Lopez* Samir Ahmad Mussa** Domingo Ruiz-Caballero* René Sanhueza* Marcelo L. Heldwein** Member Member *Pontificia Universidad Católica de Valparaíso School of Electrical Engineering – EIE Power Electronic Laboratory – LEP Av. Brasil 2147, P.O. BOX 4059, Valparaíso, CHILE. e-mail: [email protected] Abstract—This paper studies the cascading of Symmetrical Hybrid Multilevel Inverter based on the cell of three-levels (TC) of voltage. The inverter operates with DC power sources of equal value and with two technologies switches. Besides, this inverter has as great advantage to be completely modular, which makes it very reliable because it can be designed with redundancy in the modules. The modulation strategy for driving the switches is based on the sinusoidal PWM technique known as Phase-Shifted Disposition (PSD). By means of Fourier series are represented the output voltages for N cells connected in cascade. To validate the operating principle a single-phase low power prototype has been built, operating at 1.5 kHz for the fast switches and 50 Hz for the slow switches. Index Terms: DC-AC converters, Hybrid Inverters, Symmetrical Multilevel Inverters, Cascaded Inverters. I. INTRODUCTION The late technology improvements regarding switched power capacity and operating frequency for turn-off high power semiconductor devices (IGBT's, GTO's, IGCT's and others), has consolidated static converters based on multilevel topologies. The advances in this field make the medium and high voltage applications increasingly common, especially in the ac motor drives [3], [4]. Another prominent field of application is the high resolution converters [15], which typically are implemented through voltage source multilevel inverters that generate output voltage waveforms from a large set of dc voltage sources and are capable of synthesizing waveforms that approximate sine waves. This goal is achieved by applying suitable multilevel topologies, increasing the switching frequency to the limits of the semiconductor technology and applying proper modulation strategies to meet a compromise between reduction of total harmonic distortion, switching losses minimization, common mode voltage mitigation, among other requirements [1-15]. Different multilevel converter topologies have been **Federal University of Santa Catarina Department of Electrical Engineering/Power Electronics Institute – INEP P. O. BOX 5119 – 88040-970 Florianopolis – SC – BRAZIL e-mail: [email protected] introduced and reviewed [5,8] in the literature, presenting advantages and disadvantages depending on application, power and voltage levels, need for modularity, insulation and other requirements. In this context, one of the first multilevel topologies is the symmetrical cascaded H-bridge converter [2,5,10]. This is a multilevel topology that profits from the series connection of several three-level H-bridge converters in order to achieve a high number of voltage levels at its output voltages. Asymmetrical cascaded converters have been proposed [11] as alternatives to this type of converter, presenting a lower number of semiconductor devices with unbalanced stresses in the power semiconductors. Hybrid multilevel converters [13,14], i.e., integrating different circuit topologies present less modularity, but advantages in other characteristics. This work introduces the cascading of symmetric multilevel cells based on the hybrid multilevel inverter topology presented in [1]. The presented study generalizes the topology to accommodate any number of three-level cells (TC). Thus, a high number of voltage levels are generated and waveforms with reduced harmonic contents are produced. Furthermore, a proper fixed frequency PWM modulation scheme is applied and the theoretical voltage waveforms are derived for the Cascaded Symmetrical Hybrid Multilevel Inverter based on Three-Level Cells. Finally, experimental results are presented in accordance to the performed theoretical analysis. II. CASCADED SYMMETRICAL HYBRID MULTILEVEL INVERTER BASED ON TC CELLS The basis for the proposed topology is the hybrid multilevel inverter topology presented in [1] and shown for clarity in Fig. 1(a). The number of levels that can be synthesized through this DC-AC converter is five, as exemplarily drawn in Fig. 1(b) for a single pulse modulation scheme that leads to the following voltage levels for a full modulation cycle: 0, E, 2E, E, 0, E, 2E, E and 0. Another characteristic of such a converter is that the threelevel cell (TC) comprising switches Sj, with j=1..4, operates twice per modulation period switching at the PWM carrier frequency, while the inverting bridge consisting of Si , with i=5..8, switches at the modulation frequency. In this converter, the TC switches can be implemented with faster semiconductors, for instance IGBTs switching at some kilohertz, while the inverting bridge requires devices with twice the voltage ratings that can be slow, for instance GTOs or IGCTs switching at frequencies up to 60 Hz. Based on the aforementioned multilevel topology, two cascading strategies are possible in order to increase the number of output voltage levels. The first strategy is the direct series connection of the five-level topology as seen in a cascaded H-bridge converter. This leads to a highly modular design where the circuit shown in Fig. 1(a) is simply replicated as many times as desired, employing points a and b as input and output terminals. This approach is suitable for high power/voltage converters since voltage levels are reduced in all semiconductors. Another approach for a cascaded converter is to series connect only the TC cells, while a single inverting bridge is responsible for the low frequency inversion. This strategy is introduced in Fig. 1(c) and presents a clear advantage on the lower number of insulated gate drive circuits that are required, whereas the inverting bridge switches, even though in lower quantity, must withstand the sum of all input dc voltage sources. This approach can be taken when the main goal of the multilevel converter is to generate a near-sinus waveform, i.e., in the case of high a high resolution converter where the voltage across the switches is not the main limitation. The topology drawn in Fig. 1(c) presents N cascaded TC cells. Both approaches lead to a high number of output voltage levels and, with a proper modulation scheme, reduce the total harmonic distortion (THD) of the output voltage. Redundancy can be applied to both approaches as well, where a higher number of cascaded cells still guarantees that in case of a given number of cells fails, these are shorted and the others continue to operate accordingly. E NL 4N 1, (1) and, conversely, for a given number of voltage levels, the number of cascaded TC cells is N NL 1 . 4 (2) Each TC cell requires two series connected dc sources x S5 S3 S7 E S6 S2 (a) S8 y N A S4 Load v ab vab 2E E (b) S1 S4 S2 S1 S2 S3 S3 S4 S5 S8 S2 S1 S 2 S4 S3 S 3 S2 S 1 S2 S4 S 3 S3 S 1 S2 S 3 S4 S6 S7 E 2E t S1 S4 S11 E S12 Cell 1 E S13 S14 E S21 S22 Inverting bridge Cell 2 E S23 S5 S24 E E S7 Sj1 S6 vab a (c) b Load S8 Sj2 Cell j Sj3 Sj4 A. The Hybrid Cascaded TC Cells Topology Five voltage levels can be generated for each of the TC cells in a cascaded TC cells topology (cf. Fig. 1(c)). Twocascaded cells produce nine levels, three cells generate thirteen distinct voltage levels and so on. From this rule, the total number NL of synthesizable voltage levels for a generic number of cascaded TC cells N is given by, TC cell Inverting bridge S1 SN1 E SN2 Cell N E SN3 SN4 Fig. 1 – (a) Single-phase symmetrical hybrid multilevel inverter [1]; (b) an example of its output voltage, and; (c) single-phase multilevel symmetrical hybrid circuit obtained with cascading N TC cells. that must be insulated from the dc sources of other cells. Thus, the total number of insulated dc sources is half of the total number of dc sources F, which is F 2N NL 1 . 2 (3) v t1 + vM v t2 from which, the total number of high frequency switches STC, i.e., switches at the TC cells is found with, v t2’ 4N S bridge 4 N 1 NL 3 , + v t1’ (4) S total S11 S12 S14 S13 S21 S22 S24 + ST C 1 . NL v tj Modulation Strategy NL 1 . 2 2N (6) Considering that the number of carriers depends on the number of cascaded cells, the displacement angle between carriers P is found with 2 P P NL 1 360 . NL 1 (7) As an example, four carriers with a 90° phase-shift between them are required to implement the modulation for two cascaded cells. The inverting H-bridge is driven by the comparison of the modulating sinusoidal signal with level zero. Thus, the inverting H-bridge switches at the fundamental frequency of the modulating waveform. C. Output Voltage Time Behavior The generated output voltage of a Five-Level SinglePhase Symmetrical Hybrid Multilevel Inverter [1] employing the PSM-PWM is obtained through from the pulse signal that represent switching the switches, which is given in Fourier series form by e t E m i sin n 1 t 2E sen n m i sin n t cos m f n t , (8) where mi is the modulation index, given by mi Sj1 Sj2 Sj4 Sj3 Vm V p , mf is the frequency index, defined with (9) + v tj’ v tN v tN’ abs + Ts vM S5 , S 8 0 SN3 vM vM vtj vtj’ SN1 SN2 SN4 + The chosen modulation strategy for driving the switches is based on the sinusoidal pulse width modulation (PWM) technique known as Phase-Shifted Disposition (PSD). The switching signals for each TC cell are derived from the comparison of a modulating signal vm with two triangular carrier signals vtj and vtj’, with j=1..N (cf. Fig. 2) displaced rad from each other. Therefore, the required total number of triangular carriers P to implement Phase-Shifted Disposition modulation for the proposed cascaded converter is P S23 (5) + B. 4 N + + The total number of switches (and diodes) is given by the four switches in the inverting bridge (Sbridge = 4) summed to four more switches for each cascaded TC cell. Thus, the total number of switches for the hybrid cascaded TC cells inverter is S6 , S 7 Fig. 2 – Implemented modulation based on the PSD-PWM, where the inverting bridge switching signals are generated by the comparison of the modulating signal to zero. mf f p fm . (10) Vm is the amplitude of the sinusoidal modulating signal, Vp is the peak-to-peak amplitude of the triangular carrier signals, fm is the modulating signal frequency (the fundamental frequency), and fp is the frequency of the triangular carrier signals. The generalized Fourier series for the output voltage of the cascaded converter with N cells is found employing equation (7) and considering the carrier signals phase-shift given by (6). The resulting output voltage vab is vab t n 1 2Nm i E sin t 2E sin 2N m i n sin n t cos 2N m f n t . (11) Equation (11) is employed to generate the waveforms shown in Fig. 3 for a frequency index mf = 20, a modulation index mi = 0.94 and a total number of harmonics nh = 1000. Fig. 3(a) shows the output voltage for a single Five-Level Single-Phase Symmetrical Hybrid Multilevel Inverter [1], i.e. N=1. Three cascaded cells (N=3) produce the voltage plotted in Fig. 3(b), while six cells (N=6) generate the waveform in Fig. 3(c). The harmonic contents are clearly reduced for higher number of cascaded cells, as the synthesized output voltage approximates a pure sinusoid with more voltage levels. The number of voltage levels is NL=5, 13 and 25 for N=1, 3 and 5, respectively, which N=1 N=1 N=1 (a) (a) N=3 N=3 N=3 (b) (b) N=6 N=6 N=6 (c) Fig. 3 – Normalized output voltage waveforms (vab/E) for N=1, 3 and 6 cascaded TC cells, computed with equation (11) for mi=0.94 and mf =20. (c) Fig. 4 – Output voltage waveforms (vab) for N=1, 3 and 6 cascaded TC cells, obtained from numerical simulations (PSIM©). Simulation conditions: E=760 V, mi=0.94 and mf =20. matches the value predicted with equation (1). Computer simulations for a converter based on the following specifications were carried out in order to verify the output voltage waveforms theoretical analysis for the same conditions employed in the calculations for Fig. 3. Converter: E = 760 V; mi = 0,94; fm= 50 Hz; mf = 20. Load: R = 21,33 ; L = 51 mH; cos( )= 0,8. The results obtained with the computer simulations for N=1, 3 and 6 are shown in Fig. 4 and closely follow the theoretically derived voltages. number of harmonics n = 1000. Fig. 3(a) shows the output voltage for a single Five-Level Single-Phase Symmetrical Hybrid Multilevel Inverter [1], i.e. N=1. Three cascaded cells (N=3) produce the voltage plotted in Fig. 3(b), while six cells (N=6) generate the waveform in Fig. 3(c). The harmonic contents are clearly reduced for higher number of cascaded cells, as the synthesized output voltage approximates a pure sinusoid with more voltage levels. The number of voltage levels is NL=5, 13 and 25 for N=1, 3 and 5, respectively, which matches the value predicted with equation (1). III. OUTPUT VOLTAGE TOTAL HARMONIC DISTORTION An important figure of merit for the analysis of high resolution multilevel inverters is the output voltage total harmonic distortion THDv%. Equation (11) is employed to generate the waveforms shown in Fig. 3 for a frequency index mf = 20, a modulation index mi = 0.94 and a total The THDv% is defined with V h2 T HDv % 100% h 2 V1 , (12) which requires the rms value of each generated voltage N=1 (a) Fig. 6 – Derived relation between THDv% and the modulation index for N=3 cells, mi=0.94 and mf =20, curve fitted through minimum squares regression. N=3 vab t 2Nm i sin t n 1k 0 1 sin 2Nm f n 2 (b) harmonics. In this equation, h represents the order of the corresponding harmonic, while the sub-index 1 corresponds to the fundamental frequency. As harmonics are generated at the multiples of the switching frequency with side-bands influenced by the modulation frequency, the switching frequency impacts the THDv%. This is supported by the theoretical analysis of the output voltage considering equation (11) through the use of k 0 2 J n 2k , sin 2Nm f n 2k 1 t TABLE I OUTPUT VOLTAGE FREQUENCY COMPONENTS (MAGNITUDE) Fig. 5 – Output voltage frequency spectra for N=1, 3 and 6 cascaded TC cells, obtained from numerical simulations (PSIM©). Simulation conditions: E=760 V, mi=0.94 and mf =20. 2 t 2 Nm i n (14) (c) t 1 1 from where the magnitudes are explicitly given in Table I. The harmonic components according to Table I show that the high frequency components of the output voltage are shifted up by N when compared to a single five-level inverter. Furthermore, only odd harmonics are observed. N=6 sin 2 Nm in sin 2k 4 J n 2k 1 2 Nm i n sin 2k 1 t (13) and other trigonometric identities, where Jx is the Bessel function of first kind and order x. Thus, the magnitude of each harmonic component can be directly derived from rewriting equation (11), which leads to Components Amplitude Fundamental 2N m i E Harmonics (n,k) n=1,2,3... k=0,1,2... 4E J 2k n 1 Frequency 1 2Nm f n 2k 1 2Nm n 2k 1 1 2N m in Applying the Fast Fourier Transform (FFT) to the simulated voltages shown in Fig. 4 and limiting the calculation bandwidth to 2 MHz lead to the frequency spectra shown in Fig. 5 for inverters with N=1, 3 and 6 cascaded TC cells and modulation index mi =0.94 and frequency index mf =20. The frequency spectra present only odd harmonics and consist of sidebands around multiples of 2.N.mf. Computing the THDv% for different numbers of cascaded cells leads to the values presented in Table II. The total harmonic distortion reduces with increasing number of cascaded cells as expected by the visual inspection of, both, time domain waveforms and frequency spectra. A relationship between THDv% and N could be derived even considering that N is a natural number. This relationship would be of help when a system is designed with redundant cells that could be excluded in order to evaluate the impact of this measure to the voltage quality. TABLE II THDV% FOR DIFFERENT SIMULATED CASCADED CONFIGURATIONS N 1 2 3 4 5 6 mi 0.3 0.4 0.6 0.7 0.8 0.94 THDv% 30,92 15,97 10,68 7,96 6,31 5,199 THDv% 35.55 24.58 16.94 13.27 12.49 10.68 Another parameter that strongly influences the THDv% is the modulation index. During the normal inverter operation, the modulation index varies depending on load condition and input voltage regulation. This impacts the output voltage distortion and a mathematical expression that relates the THDv% to the modulation index is of help. This relationship is exemplarily obtained in the following for a multilevel inverter composed of N=3 cascaded TC cells with a frequency index mf =20. The inverter circuit is simulated for several values of mi and the computed FFT of its output voltage is recorded, from where a minimum squares regression is performed. The fitted curve is T HDv %(m i ) 9.693m i 1.0448 , (15) and the computed THDv% values are given in Table III. The fitted THDv% function presents a mean square error R2=0.9927, which is reasonable for this type of function. The exponent –1.0448 approaches unity, from where the total harmonic distortion is inversely proportional to the modulation index, as observed in Fig. 6. IV. EXPERIMENTAL RESULTS The proposed inverter topology has been implemented in a N=2 laboratory prototype employing dc bus voltages E=100 V; a total output power Po=500 W; switching frequency fs=1.5 kHz; and, modulation frequency fo=50 Hz. In addition, a small LC filter with L=8 mH and C=8 µF was included at the load. The applied modulation strategy is based on the aforementioned Phase-Shifted Disposition (PSD) PWM. This is implemented on a DSP TMS320F2812 that generates the open loop switching signals required for correct inverter operation. Computer simulations were carried out with these design specifications, obtaining the results shown in Fig. 7, where the output PWM voltage generated by the inverter, the load voltage and current are shown. Fig. 8 shows the experimentally obtained results TABLE III DEPENDENCE OF THE THDV% FOR N=3 TO THE MODULATION INDEX Fig. 7 – Simulation results: multilevel inverter output voltage vab (upper trace), load voltage (larger sinusoid) and current (smaller sinusoid). Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. Fig. 8 – Experimental results: multilevel inverter output voltage vab (channel 3 – 250 V/div), load voltage (channel 2 – 250 V/div) and current (channel 1 – 5 A/div). Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. Fig. 9 – Simulation results: multilevel inverter output voltage vab frequency spectrum with a computed THDv%=15.93%. Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. Fig. 10 – Experimental results: multilevel inverter output voltage vab frequency spectrum with a computed THDv%=18.11%. Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. Fig. 11 – Simulation results: voltages across the inverting bridge switches (upper traces) and, across the switches of a TC cell (lower traces). Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. employing the same circuit specifications. Here, the PWM inverter output voltage (channel 3), the load voltage (channel 1), which is measured after the LC filter, and finally, (channel 2) the current through the load are presented. Good agreement is observed by comparing these results with those obtained by simulation. Fig. 12 – Experimental results: voltages across the inverting bridge switches (channels 2 and 3 – 100 V/div) and, across the switches of a TC cell (channels 1 and 4 – 100 V/div). Conditions: N=2 cascaded cells, E=100 V, mi=0.94 and mf =20. Fig. 9 shows the computed frequency spectrum from the inverter output PWM voltage, whereas Fig. 10 presents the calculated experimental spectrum for the same voltage. The spectra are highly correlated, validating the theoretical analysis. However, the digital switching signals generation creates asymmetries and more spread side-bands when compared to ideally simulated conditions. Another observation is that the high frequency harmonics present lower values for the experimental results, but this comes from the fact that the simulation results show peak values, while the experimental results represent rms values. Considering all differences, the voltage THDv% presents a difference lower than 9%. Fig. 11 and Fig.12 show, respectively, simulation and experimental results for voltages across the multilevel inverter switches. Maximum voltage across the high frequency (TC) switches (channels 1 and 4) is close to 100 V, while the inverting bridge switches (channels 2 and 3) block 400 V as expected. Finally, a photograph of the built prototype is shown in Fig. 13. V. CONCLUSIONS This work introduced two ways of generating a Cascaded Symmetrical Hybrid Multilevel Inverter based on ThreeLevel Cells, namely: the cascading of complete five-level inverter cells and, the cascading of the TC cells with a single inverting bridge. The second topology has been theoretically analyzed with respect to the total number of dc voltage sources, semiconductors and their respective characteristics, and the total number of output voltage levels. The analyzed topology presents advantages regarding the total number of semiconductors required to generate a given number of output voltage levels, since only four Fig. 13 – Photograph of the implemented lab prototype. semiconductors are employed to invert the cascaded multilevel voltages, even though, these four switches block the sum of the voltages of all dc sources. In this sense, the topology is well adapted for applications that require high resolution converters, such as, switch-mode amplifiers. A modulation strategy based on the Phase-Shifted Disposition PSD-PWM for the switches of the TC cells and on the direct comparison of the modulation signal with zero to drive the inverting bridge switches. It has been demonstrated that the proposed topology is capable of synthesizing the expected theoretical number of output voltage levels, where an increased number of cascaded TC cells creates a higher number of output voltage levels and, thus, reduced harmonic contents. The influence of the number of cascaded cells and of the modulation index has been studied, where the total harmonic distortion is reduced with increasing the number of cascaded cells and is increased with reduced modulation index. Finally, experimental results on a nine-level inverter validated the theoretical analyzes and proved that the converter is feasible. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] D. Ruiz-caballero, R. Ramos, S. A. Mussa, M. L. Heldwein, “Symmetrical Hybrid Multilevel Dc-Ac Converters with Reduced Number of Insulated Dc Supplies,” IEEE Transactions on Industrial Electronics, to be published in 2010. F. Z. Peng, “A Generalized Multilevel Inverter Topology with Self Voltage Balancing,” IEEE Transactions on Industry Applications, vol. 37, N° 2, marzo-abril 2001. E. L. M. Tolbert et al., “Multilevel Converters for Large Electric Drives,” IEEE Transactions on Industry Applications, vol. 35, N° 1, January - February 1999. F. Z. Peng, J.-S. Lai et al. “A Multilevel Voltage-Source Inverter with Separate DC Sources for Static Var Generation,” IEEE Transactions on Industry Applications, vol. 32, N° 5, Sept.-Oct., 1996. J.-S. Lai and F. Z. Peng, “Multilevel Converters – A New Breed of Power Converters,” IEEE Transactions on Industry Applications, vol. 32, N° 3, may/june 1996. J. Rodríguez et al., “Multilevel Inverters: A Survey of Topologies, Controls, and Applications,” IEEE Transactions on Industrial Electronics, vol. 49, N° 4, agosto 2002. T. A. Meynard, H. Foch, F. Forest et al., “Multicell Converters: Derived Topologies,” IEEE Transactions on Industrial Electronics, vol. 49, N° 5, octubre 2002. I. Nabae, I. Takahashi and H. Akagi, “A New Neutral-Point-Clamped PWM Inverter,” IEEE Transactions on Industry Applications, vol. IA17, No. 5, pp 518-523, 1981. K.A. Corzine, M.W. Wielebski, et al., “Control of Cascaded Multi-Level Inverters,” Publisher Item identifier S 0-7803-7817-2/03, IEEE 2003. Baker, R. H. B., Lawrence H., Electric Power Converter, U. S. Patent no. 3,867,643, 1975. Mariethoz, S.; Rufer, A., “New configurations for the three-phase asymmetrical multilevel inverter”, 39th IAS Annual Meeting Industry Applications Conference, vol. 2, pp. 828-835 vol.2, 2004. Corzine, K.; Familiant, Y., “A new cascaded multilevel H-bridge drive,” IEEE Transactions on Power Electronics, vol. 17, n°. 1, pp. 125-131, 2002. LIPO, B.-S. S. Y.-H. L. D.-S. H. T. A., “A New Multilevel Inverter Topology with a Hybrid Approach,” European Conf. on Power Electronics and Applications (EPE), vol., pp. pg 1 – 9, 1999. DING, K.; ZOU, Y.-P.; CAI, Z.-Y. et al., “A novel single-phase 5-level asymmetric inverter,” Power Electronics and Motion Control Conference IPEMC 2004, vol. 2, pp. 793-798 Vol.2, 2004. Ertl, H.; Kolar, J. W.; Zach, F. C., “Basic considerations and topologies of switched-mode assisted linear power amplifiers,” IEEE Transactions on Industrial Electronics, vol. 44, n°. 1, pp. 116-123, 1997.