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R EPLACING 6 2 2 M H Z VCSO
DEVICES W I T H T HE
Si55 X V C X O
1. Introduction
The Silicon Laboratories Si550 is a high-performance, voltage-controlled crystal oscillator (VCXO) device that is
suitable for use in SONET/SDH phase-locked loop (PLL) applications. The Si550 is available in a 5x7 mm package
with an industry-standard footprint and pin-out and can be used as a replacement for voltage-controlled SAW
oscillator (VCSO) or VCXO devices in existing PLL designs. This application note discusses use of the Si550 as a
replacement for a leading 622 MHz VCSO device with respect to the following device characteristics:
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Modulation bandwidth
Phase noise and jitter
Nominal VCO gain (Kvco)
Variation in Kvco over normal operating conditions
Power supply rejection ratio (PSRR)
2. Modulation Bandwidth
The phase shift associated with the modulation bandwidth of a VCO can be a factor in calculating the phase margin
around the PLL loop if the loop bandwidth is relatively close to the VCO modulation bandwidth. In order to facilitate
these phase margin calculations, the Si550 modulation bandwidth is specified as the modulation frequency at
which the phase shift reaches –45 degrees, rather than the frequency at which the modulation amplitude reaches –
3 dB. The Si550 modulation bandwidth, measured using the –45 degree phase shift criteria, is 10 kHz typical. The
PLL circuits used for clock recovery and jitter attenuation ("clock cleaning") in high-speed communications systems
typically have loop bandwidths in the 1 to 2 kHz range, so the phase shift associated with the Si550 modulation
bandwidth is not a significant factor in these designs.
3. Phase Noise and Jitter
At the device level, both the Si550 and the 622 MHz VCSO devices have output jitter specifications of well below
1 psRMS for the standard SONET/SDH measurement bandwidths. However, several other factors, such as VCO
gain and PSRR can have a significant affect on the PLL's jitter performance at the system level. These factors are
addressed in the following sections.
4. Nominal VCO Gain—Kvco
The VCO gain, Kvco, specifies the amount of change in VCO output frequency that will result from a change in
voltage at the VCONTROL input pin of the VCO. The VCO gain multiplied by the operating voltage range of the
VCONTROL pin gives the "total pull range" of the VCO. "Absolute Pull Range" (APR) is a measure of the amount of
VCO pull range that is available for PLL tracking of variations in the reference clock signal after allowing for the
total frequency accuracy of the VCO.
APR = (Total Pull Range) – (Total Frequency Stability)
Total Pull Range = Kvco x VCONTROL Range
Total Frequency Stability = Initial Accuracy + Temperature Stability + Aging + Other
("Other" includes Supply variation, Load variation, Shock & Vibration, and Reflow)
From a jitter generation and noise susceptibility perspective, it is desirable to use the lowest Kvco value that can
still provide the minimum APR required for the application (PLLs for SONET/SDH applications typically need at
least ±20 ppm APR). However, the poorer the frequency stability of the VCO, the larger the Kvco value must be to
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Copyright © 2009 by Silicon Laboratories
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achieve a given APR. The 622 MHz VCSO device has a gain of Kvco = 390 ppm/V, and provides an APR of
±50 ppm. The Si550 is able to provide the same APR of ±50 ppm with a much lower gain of Kvco = 90 ppm/V. The
lower Kvco value of the Si550 device can yield significant jitter performance benefits at the system level, as
discussed in the following paragraphs.
PLL circuits are commonly implemented using a charge-pump design or an op-amp active filter design. Simplified
block diagrams for these two PLL topologies are given in Figure 1 and Figure 2, respectively. The loop bandwidth
for a typical PLL design is proportional to the VCO gain and to the gain of the phase/frequency detector circuit.
Selection of a particular VCO device determines the VCO gain. The loop bandwidth is then set by adjusting the
gain of the phase/frequency detector circuit. The gain of the phase/frequency detector is typically set by adjusting
the value of a resistor in the PFD filter circuit. This resistor is denoted Rg in both Figure 1 and in Figure 2. A
capacitor, denoted Cz, is typically used with the resistor Rg to set the frequency of the loop zero. When replacing
the VCO in an existing PLL design, it may be necessary to change the values of these discrete components in
order to maintain the original loop bandwidth and zero location.
up
CLKIN
PFD
VCO
dn
CLKOUT
Rg
Cz
(C << C z)
÷N
Figure 1. Charge-Pump PLL
Rg
CLKIN
Cz
(R)
XOR
VCO
CLKOUT
+
(C << C z)
÷N
Figure 2. Op-Amp Active Filter PLL
For example, when replacing a VCSO having Kvco = 390 ppm/V with the Si550, if none of the discrete component
values are changed then the PLL loop bandwidth would be scaled by a factor of 90/390. Scaling of the resistor
value Rg by a factor of 390/90 would maintain loop bandwidth of the original design. The capacitor value Cz should
then be scaled in by a factor of 90/390 in order to maintain the original zero location. The original values and new
values for these component changes are summarized in Table 1.
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Table 1. Summary of Component Value Changes
Original Value
New Value
622 MHz VCSO
Si550 VCXO
VCO APR
±50 ppm
±50 ppm
VCO Gain
390 ppm/V
90 ppm/V
PFD Gain Resistor
Rg
Rnew = Rg x 390/90
Zero location Capacitor
Cz
Cnew = Cz x 90/390
VCO Device
In this example, the new VCO gain value is smaller than the original, and the new resistor value is made larger in
order to maintain the original loop bandwidth. This is a beneficial tradeoff from a system-level jitter perspective,
because any noise that is coupled into the Vcontrol pin of the VCO is converted to jitter at the VCO output with a
gain factor equal to Kvco. One small source of noise at the Vcontrol pin is noise voltage generated by the resistor
Rg. The noise voltage generated by a resistor is proportional to the square root of the resistance, so the resistor
noise voltage is roughly doubled in our example ((390/90)^0.5 = 2.08). However, Kvco has been reduced by a
factor of four (90/390 = 0.23), so the net effect is that the jitter due to resistor noise has been cut in half. A more
significant source of noise at the Vcontrol pin in typical PLL designs is the conducted or radiated emissions from
other circuits in the equipment. Jitter resulting from these sources will be cut by a factor of four.
The system level jitter implications discussed in the previous paragraph are summarized in Table 2. The Vcontrol
pin of the VCO is generally considered the most sensitive node in any PLL design, and PLL designers must work
hard to minimize noise at this point. Reducing the VCO gain, Kvco, reduces the sensitivity at this node, which
results in lower PLL output jitter and also simplifies the PLL design task.
Table 2. System Jitter Implications of Suggested Component Value Changes
Output Jitter Source
Effect of Component Changes
Output Jitter Due to Resistor Noise at VCONTROL pin.
Jitter reduced by a factor of two.
Output Jitter due to radiated/conducted noise at VCONTROL pin.
Jitter reduced by a factor of four.
An additional potential benefit of the component value changes suggested in Table 1 is the reduction of the
capacitor value. The large capacitance required for designs that have high VCO gain can cause difficulties for PLL
designers. Reduction of this value may allow use of a capacitor with a smaller footprint and/or better a dielectric
material. Alternatively, if the resistor value is scaled as indicated in Table 1 but the original capacitor value is
retained, the effect is a lowering of the zero location, which can improve loop stability and reduce jitter peaking.
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5. Variation in Kvco over Normal Operating Conditions
As stated earlier, typical PLL designs have a loop bandwidth that is proportional to the VCO gain, Kvco. As the
VCO gain varies over the normal operating temperature and frequency of the application, the PLL loop bandwidth
will also change. The PLL loop bandwidth, of course, affects critical performance characteristics such as jitter
attenuation capability and loop stability/jitter peaking, so minimizing Kvco variation is important.
The Si550 exhibits less variation in Kvco over temperature and operating frequency than does the 622 MHz VCSO
device. To measure the difference in Kvco variation, one PLL circuit was built using the 622 MHz VCSO device,
and a second PLL circuit was built using the Si550 VCXO with component value substitutions as indicated in
Table 1. These two PLL circuits were built using identical circuit boards and using the same phase/frequency
detector integrated circuit. The VCO gain for each device was measured by locking the PLL at two different
frequencies that represented small offsets from the nominal operating frequency (i.e., 622 MHz ±5 ppm) and
measuring the control voltage at the VCONTROL pin of the VCO at each frequency. The gain was then calculated as
the difference in frequencies divided by the incremental change in control voltage:
K VCO =  f2 – f1    V CONTROL2 – V CONTROL1 
This measurement was repeated at a number of different temperatures, ranging from –20 to +85 Cº, and the
results were plotted as a graph of Kvco vs. temperature. To demonstrate the correlation between Kvco variation
and PLL bandwidth variation, a jitter transfer measurement was made at the same temperature points for both PLL
boards using an Anritsu MP1777A Jitter Analyzer. The –3 dB cutoff frequencies from the measured jitter transfer
curves were then also plotted as a function of temperature. The results from these measurements are shown in
Figure 3 and Figure 4.
To view this information another way, consider the task of designing a PLL to operate with a 1 kHz loop bandwidth
and jitter peaking of less than 0.1 dB at a nominal operating temperature of +45 Cº. The component values can be
adjusted to achieve the desired loop bandwidth and stability at the target temperature. It would then be desirable to
know what the expected variation in Kvco would be relative to its value at +45 Cº. The variation in Kvco relative to
+45 Cº is plotted in Figure 5 for the Si550 and for the 622 MHz VCSO. The total variation over –20 to +45 Cº for the
Si550 is 12.7% (–7% to +5.7%), while the total variation for the 622 MHz VCSO is 19.6% (+2% to –17.6%).
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350
1310
340
1260
330
1160
310
1110
300
Loop BW (Hz)
Kvco (ppm/V)
1210
320
1060
290
Kvco
Loop Bandwidth
280
1010
270
-40
-20
0
20
40
60
80
960
100
Temperature (deg C)
Figure 3. Kvco v. Temp and Loop Bandwidth v. Temp for 622 MHz VCSO
105
103
1740
Kvco
1690
Loop Bandwidth
99
1640
97
1590
95
Loop BW (Hz)
Kvco (ppm/V)
101
1540
93
91
1490
89
1440
100
-40
-20
0
20
40
60
80
Temperature (deg C)
Figure 4. Kvco v. Temp and Loop Bandwidth v. Temp for Si550
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% Change in Kvco relative to value @
+45degC
10.0%
5.0%
0.0%
-5.0%
-10.0%
-15.0%
622 MHz VCSO
Si550 VCXO
-20.0%
-40
-20
0
20
40
60
80
Temperature (degC)
Figure 5. Kvco Variation over Temperature, Relative to Value at +45 Cº
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6. Power Supply Rejection Ratio (PSRR)
Jitter due to 1mV Sinusodal
Noise (ps/mVrms)
Noise that is present on the VCO supply voltage (VDD) may be converted to jitter on the VCO clock output. To
measure the relative sensitivities of the Si550 and the 622 MHz VCSO devices with respect to supply noise, a
sinusoidal noise source was added to the dc supply voltage, and the incremental increase in jitter present on the
VCO output was measured. This test was repeated for a number of different sinusoidal noise frequencies, the
results are plotted in the graph given in Figure 6. Here it can be seen that the Si550 device, which employs integral
on-board voltage regulators, is much less susceptible to supply noise than the 622 MHz VCSO. The benefits of
higher PSRR afforded by the Si550 device are most pronounced in the 1 to 10 kHz frequency range, where noise
generated by switching ICs is often most problematic.
622 MHz VCSO
Si550 VCXO
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1
10
100
1,000
Modulation Frequency (kHz)
Figure 6. Jitter Due to Power Supply Noise
7. Summary
The Si550 VCXO is an excellent choice for use in new PLL designs or for replacement of 622 MHz VCSO or VCXO
devices in existing PLL designs. The lower nominal Kvco value of this device, combined with improved Kvco
temperature stability and superior power supply rejection ratio, serve to reduce overall PLL output jitter, reduce PLL
noise sensitivity, and simplify the PLL design task.
8. Update
Since this application note was initially written, the Si55x family of hybrid oscillators has added more Kv selections.
In particular, a higher Kv = 356 ppm/V selection is now available. This feature gives the engineer another option to
consider when replacing a VCSO. Depending on the PLL design, a high Kv VCSO may be drop-in replaced by a Kv
= 356 ppm/V Si550 without needing to change any loop filter components. If the design allows, the Si55x linearity
and power supply rejection advantages may then be accrued without otherwise changing the bill of materials.
Review the current Si55x data sheets for the latest specifications.
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
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8
Added "8. Update" on page 7 noting Si55x Rev. D
higher Kv option available.
Rev. 0.2
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NOTES:
Rev. 0.2
9
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