Overview
Sequential versus combinational
! Last lecture
" Adders
A
# Ripple-carry
# Carry-lookahead
# Carry-select
"
C
B
clock
The conclusion of combinational logic!!!
Apply fixed inputs A, B
Wait for clock edge
Observe C
Wait for another clock edge
Observe C again
! Today
" Introduction to sequential logic and systems
# The basic concepts
# A simple example
Combinational: C will stay the same
Sequential: C may be different
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CSE370, Lecture 14
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Sequential logic
Sequential versus combinational (again)
! Two types
" Synchronous = clocked
" Asynchronous = self-timed
! Combinational systems are memoryless
" Outputs depend only on the present inputs
! Has state
" State = memory
Inputs
! Employs feedback
Outputs
System
! Sequential systems have memory
" Outputs depend on the present and the previous inputs
! Assumes steady-state signals
" Signals are valid after they have settled
" State elements hold their settled output values
Inputs
Outputs
System
Feedback
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Synchronous sequential systems
Steady-state abstraction
! Memory holds a system’s state
" Changes in state occur at specific times
" A periodic signal times or clocks the state changes
" The clock period is the time between state changes
! Outputs retain their settled values
" The clock period must be long enough for all voltages to
settle to a steady state before the next state change
A
A
C
B
clock
pulsewidth
clock
State changes occur
at rising edge of clock
duty cycle = pulsewidth/period
(here it is 50%)
Clock hides transient
behavior
clock
C
clock
Settled value
period
CSE370, Lecture 14
C
B
5
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Example: A sequential system
Understand the problem
! Door combination lock
" Enter 3 numbers in sequence and the door opens
" If there is an error the lock must be reset
" After the door opens the lock must be reset
" Inputs: Sequence of numbers, reset
" Outputs: Door open/close
" Memory: Must remember the combination
! Consider I/O and unknowns
" How many bits per input?
" How many inputs in sequence?
" How do we know a new input is entered?
" How do we represent the system states?
new value reset
clock
open/closed
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Implement using sequential logic
Finite-state diagram
! Behavior
" Clock tells us when to look at inputs
! States: 5
"
# After inputs have settled
"
"
# Enter 3 numbers serially
# Remember if error occurred
"
All states have outputs
comparisons
We use state diagrams to
represent sequential logic
new value reset
ERR
System transitions between
finite numbers of states
closed
C1!= value
& new
clock
S1
closed
reset
# Lock open or closed
open/closed
9
C2!= value
& new
S3
S2
C1== value
& new
not new
CSE370, Lecture 14
Assume synchronous inputs
"
! Outputs: open/closed
Sequential: Enter sequence of numbers
Sequential: Remember if error occurred
! Need a finite-state diagram
" Assume synchronous inputs
" State sequence
! Inputs: reset, new, results of
Each state has outputs
closed
closed
C2== value
& new
not new
C3!= value
& new
C3== value
& new
not new
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Separate data path and control
Refine diagram; generate state table
! Data path
" Stores combination
" Compares inputs with
combination
! Refine state diagram to
! Control
" Finite state-machine controller
" Control for data path
" State changes clocked
C2
4
C3
4
multiplexer
new
not equal
& new
value
4
comparator
! Generate
controller
state table
clock
equal
open/closed
CSE370, Lecture 14
S1
closed
mux=C1 equal
& new
not new
reset
mux
control
4
ERR
closed
include internal structure
reset
C1
4
11
OPEN
open
CSE370, Lecture 14
reset
1
0
0
0
...
0
...
S2
closed
mux=C2 equal
& new
not new
not equal
not equal
& new
& new
S3
OPEN
closed
open
mux=C3 equal
& new
not new
new
–
0
1
1
equal
–
–
0
1
state
–
S1
S1
S1
next
state
S1
S1
ERR
S2
1
1
S3
OPEN –
mux
C1
C1
–
C2
open/closed
closed
closed
closed
closed
open
12
Encode state table
Encode state table (con’t)
! State can be: S1, S2, S3, OPEN, or ERR
" Need at least 3 bits to encode: 000, 001, 010, 011, 100
" Can use 5 bits: 00001, 00010, 00100, 01000, 10000
" Choose 4 bits: 0001, 0010, 0100, 1000, 0000
! Good encoding choice!
" Mux control is identical to last 3 state bits
" Open/closed is identical to first state bit
" Output encoding ⇒ the outputs and state bits are the same
! Output to mux can be: C1, C2, or C3
" Need 2 or 3 bits to encode
" Choose 3 bits: 001, 010, 100
reset
1
0
0
0
...
0
...
! Output open/closed can be: Open or closed
" Need 1 or 2 bits to encode
" Choose 1 bit: 1, 0
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Implementing the controller
! We will learn how to
mux
control
state
–
0001
0001
0001
mux
001
001
–
010
1
1
0100 1000 –
open/closed
0
0
0
0
1
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"
Four 3:1 multiplexers
"
Four single-bit comparators
# 2-input ANDs and 3-input OR
equal
valuei C1i
C2i
C3i
mux
control
# 2-input XNORs
"
new
equal
–
–
0
1
Designing the datapath
special circuit element,
called a register, for
storing inputs when
told to by the clock
design the controller
given the encoded
state-transition table
next
state
0001
0001
0000
0010
new
–
0
1
1
4-input AND
reset
C1
4
comb. logic
state
clock
C2
4
C3
4
multiplexer
mux
control
4
value
open/closed
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comparator
4
equal
equal
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Where did we use memory?
Where did we use feedback?
! Memory: Stored combination, state (errors or
! Feedback: Comparator output ("equal" signal)
successes in past inputs)
new equal reset
new equal reset
value
C1
C2
C3
multiplexer
C1
mux
control
controller
comparator
equal
CSE370, Lecture 14
value
C2
C3
multiplexer
mux
control
controller
clock
comparator
clock
equal
open/closed
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open/closed
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Where did we use clock?
Then next 5 weeks...
! Clock synchronizes the inputs
" Accept inputs when clock goes high
! We learn the details
" Latches, flip-flops, registers
" Shift registers, counters
" State machines
" Timing and timing diagrams
" Synchronous and asynchronous inputs
! Controller is clocked
" Mux-control and open/closed signals change on the clock edge
# Metastability
new equal reset
"
value
C1
C2
C3
multiplexer
"
mux
control
CSE370, Lecture 14
"
clock
comparator
equal
"
controller
Clock skew
Moore and Mealy machines
One-hot encoding
More...
open/closed
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