Lecture Notes Insulated Gate Bipolar Transistors (IGBTs) William P. Robbins Professor, Dept. of Electrical and Computer Engineering University of Minnesota Outline • Construction and I-V characteristics • Physical operation • Switching characteristics • Limitations and safe operating area • PSPICE simulation models IGBTs - 1 W.P. Robbins Multi-cell Structure of IGBT • IGBT = insulated gate bipolar transistor. emitter conductor contact to source diffusion f ield oxide gate oxide N+ P N+ NN+ P+ gate conductor N+ P N+ gate width buffer layer (not essential) collector metallization IGBTs - 2 W.P. Robbins Cross-section of IGBT Cell gate emitter SiO 2 J 3 J N 2 + P N + Ls N+ N P+ J - Unique feature of IGBT 1 collector Parasitic thyristor Buffer layer (not essential) • Cell structure similar to power MOSFET (VDMOS) cell. • P-region at collector end unique feature of IGBT compared to MOSFET. • Punch-through (PT) IGBT - N+ buffer layer present. • Non-punch-through (NPT) IGBT - N+ buffer layer absent. IGBTs - 3 W.P. Robbins Cross-section of Trench-Gate IGBT Unit Cell • Non-punch-thru IGBT • Punch-thru IGBT IGBTs - 4 W.P. Robbins IGBT I-V Characteristics and Circuit Symbols i C increasing V GE i v GE4 C • No Buffer Layer v GE3 VRM ≈ BV CES v • With Buffer Layer V GE(th) GE2 v RM GE v GE1 V ≈0 RM V v • Output characteristics BV CES • Transfer curve CE collector drain • N-channel IGBT circuit symbols gate gate source emitter IGBTs - 5 W.P. Robbins Blocking (Off) State Operation of IGBT gate SiO 2 J 3 J 2 J - Unique feature of IGBT 1 emitter N + N P + Ls N+ N P+ collector Parasitic thyristor Buffer layer (not essential) • With N+ buffer layer, junction J1 has small breakdownvoltage and thus IGBT has little reverse blocking capability anti-symmetric IGBT • Buffer layer speeds up device turn-off IGBTs - 6 W.P. Robbins IGBT On-state Operation gate emitter N + N + • MOSFET section designed to carry most of the IGBT collector current P lateral (spreading) resistance N + + + + N- + P + + + + + collector gate emitter N + • On-state VCE(on) = VJ1 + Vdrift + ICRchannel N + • Hole injection into drift region from J1 minimizes Vdrift. P NN + P+ collector IGBTs - 7 W.P. Robbins Approximate Equivalent Circuits for IGBTs drift region r e s i s t a n ce V gate I C V drift R J1 channel • Approximate equivalent circuit for IGBT valid for normal operating conditions. • VCE(on) = VJ1 + Vdrift + IC Rchannel • IGBT equivalent circuit showing transistors comprising the parasitic thyristor. IGBTs - 8 W.P. Robbins Static Latchup of IGBTs lateral (spreading) resistance J N 3 emitter + N gate + P J2 J1 NN + + + + P+ + + + + collector Conduction paths causing lateral voltage drops and turn-on of parasitic thyristor if current in this path is too large • Lateral voltage drops, if too large, will forward bias junction J3. • Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor. • Large power dissipation in latchup will destroy IGBT unless terminated quickly. External circuit must terminate latchup - no gate control in latchup. IGBTs - 9 W.P. Robbins Dynamic Latchup Mechanism in IGBTs J N emitter 3 + N gate + J2 P lateral (spreading) resistance J1 NN expansion of depletion region + P+ collector • MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into N- layer, the base region of the pnp BJT. • Expansion of depletion layer reduces base width of pnp BJT and its a increases. • More injected holes survive traversal of drift region and become “collected” at junction J2. • Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and latchup soon occurs. • Manufacturers usually specify maximum allowable drain current on basis of dynamic latchup. IGBTs - 10 W.P. Robbins Internal Capacitances Vs Spec Sheet Capacitances C C gc G bridge C +V b C ce C ge C gc E G C Bridge balanced (Vb=0) Cbridge = C gc = C res G C ies C E C ies = C g e + C gc C oes E C oes = C gc + C ce IGBTs - 11 W.P. Robbins IGBT Turn-on Waveforms • Turn-on waveforms for IGBT embedded in a stepdown converter. • Very similar to turn-on waveforms of MOSFETs. • Contributions to tvf2. v GE t t d(on) Io i (t) C • Increase in Cge of MOSFET section at low collector-emitter voltages. • Slower turn-on of pnp BJT section. V GG+ (t) t V v CE t ri V DD C E(on) (t) t fv1 t t fv2 IGBTs - 12 W.P. Robbins IGBT Turn-off Waveforms • Turn-off waveforms for IGBT embedded in a stepdown converter. • Current “tailing” (tfi2) due to stored charge trapped in drift region (base of pnp BJT) by rapid turn-off of MOSFET section. • Shorten tailing interval by either reducing carrier lifetime or by putting N+ buffer layer adjacent to injecting P+ layer at drain. • Buffer layer acts as a sink for excess holes otherwise trapped in drift region becasue lifetime in buffer layer can be made small without effecting on-state losses buffer layer thin compared to drift region. IGBTs - 13 W.P. Robbins IGBT Safe Operating Area i •Maximum collector-emitter voltages set by breakdown voltage of pnp transistor 2500 v devices available. C 10 FBSOA 10 -5 -4 sec sec DC i C dv CE re-applied dt 1000 V/ µs v CE •Maximum junction temp. = 150 C. 2000 V/ µs RBSOA •Maximum collector current set by latchup considerations - 100 A devices can conduct 1000 A for 10 µsec and still turn-off via gate control. 3000 V/ µ s v CE •Manufacturer specifies a maximum rate of increase of re-applied collector-emitter voltage in order to avoid latchup. IGBTs - 14 W.P. Robbins Development of PSpice IGBT Model Cm Coxs source N + N gate Coxd + Cgdj P Cdsj Ccer Drain-body or base-collector depletion layer N+ N P Rb Cebj + Cebd + drain • Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer. • Nonlinear capacitor Cebj + Cebd due to P+N+ junction • MOSFET and PNP BJT are intrinsic (no parasitics) devices • Nonlinear resistor Rb due to conductivity modulation of N- drain drift region of MOSFET portion. • Reference - “An Experimentally Verified IGBT Model Implemented in the SABER Circuit Simulator”, Allen R. Hefner, Jr. and Daniel M. Diebolt, IEEE Trans. on Power Electronics, Vol. 9, No. 5, pp. 532-542, (Sept., 1994) • Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N-P junction). • Circuit model assumes that latchup does not occur and parasitic thyristor does not turn. IGBTs - 15 W.P. Robbins Parameter Estimation for PSpice IGBT Model • Built-in IGBT model requires nine parameter values. • Parameters described in Help files of Parts utility program. • Parts utility program guides users through parameter estimation process. • IGBT specification sheets provided by manufacturer provide sufficient informaiton for general purpose simulations. • Detailed accurate simulations, for example device dissipation studies, may require the user to carefully characterize the selected IGBTs. Drain Cgdj Coxd Gate Cm + Coxs Cebj + Cebd Ccer Rb Cdsj • Built-in model does not model ultrafast IGBTs with buffer layers (punch-through IGBTs) or reverse free-wheeling diodes Source IGBTs - 16 W.P. Robbins PSpice IGBT - Simulation Vs Experiment IGBTs - 17 W.P. Robbins