Lecture Notes
Insulated Gate Bipolar Transistors (IGBTs)
Outline
• Construction and I-V characteristics
• Physical operation
• Switching characteristics
• Limitations and safe operating area
• PSPICE simulation models
Copyright © by John Wiley & Sons 2003
IGBTs - 1
Multi-cell Structure of IGBT
• IGBT = insulated gate bipolar transistor.
emitter
conductor
contact to source
diffusion
field
oxide
gate
oxide
N+
P
N+
NN+
P+
gate
conductor
Copyright © by John Wiley & Sons 2003
N+
P
N+
gate
width
buffer layer
(not essential)
collector
metallization
IGBTs - 2
Cross-section of IGBT Cell
gate
emitter
SiO
2
J
3
J
N
+
2
P
N
+
Ls
N+
N
P+
J - Unique feature of IGBT
1
collector
Parasitic thyristor
Buffer layer
(not essential)
• Cell structure similar to power MOSFET (VDMOS) cell.
• P-region at collector end unique feature of IGBT compared to MOSFET.
• Punch-through (PT) IGBT - N+ buffer layer present.
• Non-punch-through (NPT) IGBT - N+ buffer layer absent.
Copyright © by John Wiley & Sons 2003
IGBTs - 3
Cross-section of Trench-Gate IGBT Unit Cell
Emitter
boddy-source short
Oxide
N+
P
Parasitic
SCR
N+
Channel
P
length
Gate
conductor
N-
ID
• Non-punch-thru IGBT
ID
P+
Collector
Emitter
boddy-source short
Oxide
N+
P
Parasitic
SCR
N+
Channel
P
length
Gate
conductor
I
N-
D
P+
• Punch-thru IGBT
ID
N+
Collector
Copyright © by John Wiley & Sons 2003
IGBTs - 4
IGBT I-V Characteristics and Circuit Symbols
i
C
increasing V
GE
i
v
GE4
C
• No Buffer Layer
v GE3
VRM ≈ BV
CES
v
• With Buffer Layer
V
GE(th)
GE2
v GE1
V ≈0
RM
v
V
RM
• Output characteristics
BV
CES
GE
• Transfer curve
CE
collector
drain
• N-channel IGBT circuit symbols
gate
v
gate
source
emitter
Copyright © by John Wiley & Sons 2003
IGBTs - 5
Blocking (Off) State Operation of IGBT
gate
SiO
2
J
3
J
emitter
N
+
P
2
J - Unique feature of IGBT
1
+
Ls
N+
N
P+
collector
Parasitic thyristor
• Blocking state operation - VGE < VGE(th)
• Junction J2 is blocking junction - n+ drift
region holds depletion layer of blocking
junction.
• Without N+ buffer layer, IGBT has large
reverse blocking capability - so-called
symmetric IGBT
Copyright © by John Wiley & Sons 2003
N
Buffer layer
(not essential)
• With N+ buffer layer, junction J1 has
small breakdownvoltage and thus IGBT
has little reverse blocking capability anti-symmetric IGBT
• Buffer layer speeds up device turn-off
IGBTs - 6
IGBT On-state Operation
gate
emitter
N
+
N
+
• MOSFET section designed
to carry most of the IGBT
collector current
P
lateral (spreading)
resistance
N
+
+
+
N-
+
P+
+
+
+
+
+
collector
gate
emitter
N
+
N
P
NN
P
+
+
• On-state VCE(on) =
VJ1 + Vdrift + ICRchannel
+
• Hole injection into drift
region from J1 minimizes
Vdrift.
collector
Copyright © by John Wiley & Sons 2003
IGBTs - 7
Approximate Equivalent Circuits for IGBTs
drift region
resistance
V
gate
I
C
V
drift
R
J1
channel
• Approximate equivalent circuit for
IGBT valid for normal operating
conditions.
•
Conduction path resulting
in thyristor turn-on (IGBT
latchup) if current in this
path is too large
gate
Principal
(desired)
path of
collector
current
VCE(on) = VJ1 + Vdrift + IC Rchannel
Copyright © by John Wiley & Sons 2003
collector
Body region
spreading
resistance
emitter
• IGBT equivalent circuit showing
transistors comprising the parasitic
thyristor.
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Static Latchup of IGBTs
lateral (spreading)
resistance
J
N
gate
emitter
3
+
N
+
P
J2
J1
NN
+
+
+
+
P+
+
+
+
+
collector
Conduction paths causing lateral voltage drops and turn-on
of parasitic thyristor if current in this path is too large
• Lateral voltage drops, if too large, will forward bias junction J3.
• Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor.
• Large power dissipation in latchup will destroy IGBT unless terminated quickly.
External circuit must terminate latchup - no gate control in latchup.
Copyright © by John Wiley & Sons 2003
IGBTs - 9
Dynamic Latchup Mechanism in IGBTs
J
N
emitter
3
+
N
gate
+
J2 P
lateral
(spreading)
resistance
J1
NN
expansion of
depletion region
+
P
+
collector
• MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into
N- layer, the base region of the pnp BJT.
• Expansion of depletion layer reduces base width of pnp BJT and its a increases.
• More injected holes survive traversal of drift region and become “collected” at junction J2.
• Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and
latchup soon occurs.
• Manufacturers usually specify maximum allowable drain current on basis of dynamic
latchup.
Copyright © by John Wiley & Sons 2003
IGBTs - 10
Internal Capacitances Vs Spec Sheet Capacitances
C
C gc
G
bridge
C
+V b
C ce
C ge
C gc
E
G
C
Bridge balanced (Vb=0) Cbridge = C gc = C res
G
C ies
C
E
C ies = C g e + C gc
C oes
E
C oes = C gc + C ce
Copyright © by John Wiley & Sons 2003
IGBTs - 11
IGBT Turn-on Waveforms
• Turn-on waveforms for
IGBT embedded in a
stepdown converter.
• Very similar to turn-on
waveforms of MOSFETs.
• Contributions to tvf2.
v
GE
t
t
d(on)
Io
i (t)
C
• Increase in Cge of
MOSFET section at low
collector-emitter
voltages.
• Slower turn-on of pnp
BJT section.
V
GG+
(t)
t
V
v
Copyright © by John Wiley & Sons 2003
CE
t
ri
V
DD
C E(on)
(t)
t fv1
t
t fv2
IGBTs - 12
IGBT Turn-off Waveforms
V
v
GE
(t)
GE(th
)
fi2
t d(off)
i (t)
C
t
rv
MOSFET
current
BJT
current
t
t
fi1
V
CE
V
GGt
t
v
• Turn-off waveforms for IGBT
embedded in a stepdown
converter.
DD
t
(t)
Copyright © by John Wiley & Sons 2003
• Current “tailing” (tfi2) due to
stored charge trapped in drift
region (base of pnp BJT) by rapid
turn-off of MOSFET section.
• Shorten tailing interval by either
reducing carrier lifetime or by
putting N+ buffer layer adjacent to
injecting P+ layer at drain.
• Buffer layer acts as a sink for
excess holes otherwise trapped
in drift region becasue lifetime in
buffer layer can be made small
without effecting on-state losses buffer layer thin compared to drift
region.
IGBTs - 13
IGBT Safe Operating Area
i
• Maximum collector-emitter
voltages set by breakdown
voltage of pnp transistor 2500 v devices available.
C
10
FBSOA
10
-5
-4
sec
sec
DC
i
C
v
dv
CE
re-applied
dt
1000 V/ ms
CE
• Maximum collector current set
by latchup considerations - 100
A devices can conduct 1000 A
for 10 µsec and still turn-off
via gate control.
• Maximum junction temp. = 150 C.
2000 V/ ms
RBSOA
3000 V/ m s
v
Copyright © by John Wiley & Sons 2003
CE
• Manufacturer specifies a
maximum rate of increase of
re-applied collector-emitter
voltage in order to avoid latchup.
IGBTs - 14
Development of PSpice IGBT Model
Cm
source
N
gate
Coxs
+
N
Coxd
+
Cgdj
P
Cdsj
Ccer
Drain-body or
base-collector
depletion
layer
N+
N
Rb
Cebj +
P+
Cebd
drain
• Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer.
•
•
•
•
•
• Reference - "An
Experimentally Verified
Nonlinear capacitor Cebj + Cebd due to P+N+ junction
IGBT Model
Implemented in the
MOSFET and PNP BJT are intrinsic (no parasitics) devices
SABER Circuit
Simulator", Allen R.
Nonlinear resistor Rb due to conductivity modulation of N- drain drift region of
Hefner, Jr. and Daniel
MOSFET portion.
M. Diebolt, IEEE Trans.
on Power Electronics,
Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N-P junction). Vol. 9, No. 5, pp. 532542, (Sept., 1994)
Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.
Copyright © by John Wiley & Sons 2003
IGBTs - 15
Parameter Estimation for PSpice IGBT Model
• Built-in IGBT model requires nine parameter values.
• Parameters described in Help files of Parts utility program.
• Parts utility program guides users through parameter estimation process.
• IGBT specification sheets provided by manufacturer provide sufficient
informaiton for general purpose simulations.
• Detailed accurate simulations, for example device dissipation studies, may
require the user to carefully characterize the selected IGBTs.
Drain
Cgdj
Coxd
Gate
Cm +
Coxs
Cebj +
Cebd
Ccer
Rb
Cdsj
• Built-in model does not model
ultrafast IGBTs with buffer
layers (punch-through IGBTs) or
reverse free-wheeling diodes
Source
Copyright © by John Wiley & Sons 2003
IGBTs - 16
PSpice IGBT - Simulation Vs Experiment
0V
10 V
5V
1
nF
15 V
20 V
25 V
Data from IXGH40N60 spec sheet
Simulated C
0.75
nF
GC
versus V CE
for IXGH40N60
V
=0V
GE
0.5
nF
0.25
nF
0
100 V
200 V
300 V
400 V
500 V
Collector - emitter Voltage
Copyright © by John Wiley & Sons 2003
IGBTs - 17