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CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Sources: TSR, Katz, Boriello & Vahid Two-level logic using NAND gates • Replace minterm AND gates with NAND gates • Place compensating inversion at inputs of OR gate • OR gate with inverted inputs is a NAND gate – de Morgan’s: A’ + B’ = (A • B)’ • Two-level NAND-NAND network – inverted inputs are not counted – in a typical circuit, inversion is done once and signal distributed 2 Sources: TSR, Katz, Boriello & Vahid 1 Two-level logic using NAND and NOR gates • NAND-NAND and NOR-NOR networks – de Morgan’s law: (A + B)’ = A’ • B’ – written differently: A + B = (A’ • B’)’ (A • B)’ = A’ + B’ (A • B) = (A’ + B’)’ 3 Sources: TSR, Katz, Boriello & Vahid Conversion between forms • Introduce "bubbles“ - inversions – conservation of inversions – do not alter logic function A B Z C D 4 Sources: TSR, Katz, Boriello & Vahid 2 Conversion between forms • Example: map AND/OR network to NOR/NOR network A B C Z D 5 Sources: TSR, Katz, Boriello & Vahid Multiple-Output Circuits • Many circuits have more than one output • Can give each a separate circuit, or can share gates • Ex: F = ab + c’, G = ab + bc Option 1: Separate circuits Option 2: Shared gates 6 Sources: TSR, Katz, Boriello & Vahid 3 Multiple-Output Example: BCD to 7-Segment Converter a f b g e c d abcdefg = (a) 1111110 0110000 1101101 (b) a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z 7 Sources: TSR, Katz, Boriello & Vahid Multi-level logic • x=ADF + AEF + BDF + BEF + CDF + CEF + G – reduced sum-of-products form – already simplified – 6 x 3-input AND gates + 1 x 7-input OR gate – 25 wires (19 literals plus 6 internal wires) 8 Sources: TSR, Katz, Boriello & Vahid 4 Non-Ideal Gate Behavior – Delay a F a F Time • Real gates don’t respond immediately to input changes – Rise/fall time – Delay – Pulse width 9 Sources: TSR, Katz, Boriello & Vahid Momentary changes in outputs • Can be useful — pulse shaping circuits • Can be a problem — incorrect circuit operation (glitches/hazards) • Example: pulse shaping circuit A B C D F – A’ • A = 0 – delays matter D remains high for three gate delays after A changes from low to high F is not always 0 pulse 3 gate-delays wide 10 Sources: TSR, Katz, Boriello & Vahid 5 Hazards • Glitch – unwanted pulse on the output • Circuit with a potential for a glitch has a hazard • Three types: – Static-0 : output should be 0 but has a 1 glitch – Static-1 : output should be 1 but has a 0 glitch – Dynamic: transition 0->1 or 1->0 with a glitch 11 Sources: TSR, Katz, Boriello & Vahid Eliminating Hazards Example A • F(A,B,C,D)=Σm(1,3,5,7,8,9,12,13) • Test two single bit input transitions: – 1100 -> 1101 – 1100 -> 0101 A C C’ 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 D B Z D 12 Sources: TSR, Katz, Boriello & Vahid 6 CSE140: Components and Design Techniques for Digital Systems Regular logic implementation Tajana Simunic Rosing 13 Sources: TSR, Katz, Boriello & Vahid AND-OR-invert gates • AOI function: three stages of logic — AND, OR, Invert – multiple gates "packaged" as a single circuit block possible implementation logical concept A B Z C D AND OR 2x2 AOI gate symbol Z C D NAND Invert & + & A B NAND 3x2 AOI gate symbol Invert & + & 14 Sources: TSR, Katz, Boriello & Vahid 7 Conversion to AOI forms • General procedure to place in AOI form – compute the complement of the function in sum-of-products form – by grouping the 0s in the Karnaugh map • Example: XOR implementation – A xor B = A’ B + A B’ 15 Sources: TSR, Katz, Boriello & Vahid Programmable logic arrays • Pre-fabricated building block of many AND/OR gates – "personalized" by making/breaking connections among the gates – programmable array block diagram for sum of products form • • • inputs AND array product terms OR array outputs • • • 16 Sources: TSR, Katz, Boriello & Vahid 8 Enabling concept • Shared product terms among outputs 17 Sources: TSR, Katz, Boriello & Vahid Before & after programming • Two different technologies: – fuse (normally connected, break unwanted ones) – anti-fuse (normally disconnected, make wanted connections) A B C AB B'C AC' B'C' A F0 Before F1 After F2 F3 18 Sources: TSR, Katz, Boriello & Vahid 9 Programmable logic array example • Multiple functions of A, B, C – – – – – – F1 = A B C F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C F6 = A xnor B xnor C full decoder as for memory address bits stored in memory A B C A'B'C' A'B'C A'BC' A'BC A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 F2 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 F3 F4 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 F5 F6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 AB'C' AB'C ABC' ABC F1 F2 F3 F4 F5 F6 19 Sources: TSR, Katz, Boriello & Vahid PALs and PLAs • Programmable logic array (PLA) – what we've seen so far – unconstrained fully-general AND and OR arrays • Programmable array logic (PAL) – constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms 20 Sources: TSR, Katz, Boriello & Vahid 10 Example • Map the following functions to the PLA below: A B C – W = AB + A’C’ + BC’ – X = ABC + AB’ + A’B – Y = ABC’ + BC + B’C’ W X Y 21 Sources: TSR, Katz, Boriello & Vahid Read-only memories • Two dimensional array of 1s and 0s – – – – – entry (row) is called a "word" width of row = word-size index is called an "address" address is input selected word is output word lines 1 1 1 1 n 2 -1 decoder i word[i] = 0011 j word[j] = 1010 0 internal organization 0 n-1 Address bit lines (normally 1; set to 0 by a switch) 22 Sources: TSR, Katz, Boriello & Vahid 11 ROM structure • Similar to a PLA structure but with a fully decoded AND array – completely flexible OR array (unlike PAL) n address lines • • • inputs decoder 2n word lines memory array (2n words by m bits) outputs • • • m data lines 23 Sources: TSR, Katz, Boriello & Vahid Regular logic structures for two-level logic • ROM – full AND plane, general OR plane – cheap (high-volume component) – can implement any function of n inputs – medium speed • PAL – programmable AND plane, fixed OR plane – intermediate cost – can implement functions limited by number of terms – high speed (only one programmable plane that is much smaller than ROM's decoder) • PLA – programmable AND and OR planes – most expensive (most complex in design, need more sophisticated tools) – can implement any function up to a product term limit – slow (two programmable planes) 24 Sources: TSR, Katz, Boriello & Vahid 12 CSE140: Components and Design Techniques for Digital Systems Muxes and demuxes Tajana Simunic Rosing 25 Sources: TSR, Katz, Boriello & Vahid Multiplexor (Mux) • Mux routes one of its N data inputs to its one output, based on binary value of select inputs • 4 input mux Æ needs 2 select inputs to indicate which input to route through • 8 input mux Æ 3 select inputs • N inputs Æ log2(N) selects 26 Sources: TSR, Katz, Boriello & Vahid 13 Mux Internal Design 2×1 i0 2×1 i0 d i1 d i1 s0 2×1 i0 d i1 s0 0 s0 1 2x1 mux 27 Sources: TSR, Katz, Boriello & Vahid Muxes Commonly Together -- N-bit Mux a3 b3 i0 i1 2⋅ 1 d s0 a2 b2 i0 i1 2⋅ 1 d s0 a1 b1 2⋅ 1 i0 d i1 s0 a0 b0 s0 i0 i1 2⋅ 1 d s0 A 4 I0 4-bit 2x1 D 4 B I1 Simplifying notation: 4 C 4 C is short for s0 c3 s0 c2 c1 c0 • Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0) – 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B 28 Sources: TSR, Katz, Boriello & Vahid 14 Multiplexers/selectors (cont'd) • 2:1 mux: • 4:1 mux: • 8:1 mux: Z = A'I0 + AI1 Z = A'B'I0 + A'BI1 + AB'I2 + ABI3 Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7 • In general: Z = Σ 2 n -1(mkIk) k=0 – in minterm shorthand form for a 2n:1 Mux I0 I1 2:1 mux I0 I1 I2 I3 Z A 4:1 mux Z A B I0 I1 I2 I3 I4 I5 I6 I7 8:1 mux Z A B C 29 Sources: TSR, Katz, Boriello & Vahid N-bit Mux Example • Four possible display items – Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide – Choose which to display using two inputs x and y – Use 8-bit 4x1 mux 30 Sources: TSR, Katz, Boriello & Vahid 15 Multiplexers as general-purpose logic • A 2n-1:1 multiplexer can implement any function of n variables – with n-1 variables used as control inputs and – the data inputs tied to the last variable or its complement • Example: F(A,B,C) = m0 + m2 + m6 + m7 31 Sources: TSR, Katz, Boriello & Vahid Demultiplexers/decoders • Decoders/demultiplexers: general concept – single data input, n control inputs, 2n outputs – control inputs (called “selects” (S)) represent binary index of output to which the input is connected – data input usually called “enable” (G) 1:2 Decoder: O0 = G • S’ O1 = G • S O0 O1 O2 O3 2:4 Decoder: = G • S1’ • = G • S1’ • = G • S1 • = G • S1 • S0’ S0 S0’ S0 O0 O1 O2 O3 O4 O5 O6 O7 = = = = = = = = 3:8 Decoder: G • S2’ • S1’ • S0’ G • S2’ • S1’ • S0 G • S2’ • S1 • S0’ G • S2’ • S1 • S0 G • S2 • S1’ • S0’ G • S2 • S1’ • S0 G • S2 • S1 • S0’ G • S2 • S1 • S0 32 Sources: TSR, Katz, Boriello & Vahid 16 Gate level implementation of demultiplexers • 1:2 decoders • 2:4 decoders 33 Sources: TSR, Katz, Boriello & Vahid Demultiplexers as general-purpose logic • A n:2n decoder can implement any function of n variables – with the variables used as control inputs – the enable inputs tied to 1 and – the appropriate minterms summed to form the function “1” 0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) C 34 Sources: TSR, Katz, Boriello & Vahid 17 Demultiplexers as general-purpose logic (cont’d) • F1 = A'BC'D + A'B'CD + ABCD • F2 = ABC'D' + ABC 0 1 • F3 = (A' + B' + C' + D') 2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15 Enable A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD A B C D 35 Sources: TSR, Katz, Boriello & Vahid Mux and demux combination • Uses in multi-point connections A0 Sa A1 B0 B1 MUX MUX A B Sb multiple input sources Sum Ss DEMUX S0 multiple output destinations S1 36 Sources: TSR, Katz, Boriello & Vahid 18 Summary • What we’ve covered so far: – – – – – – – – – Number representations Switches and CMOS transistor gates Boolean algebra SOP and POS Logic minimization using K-maps Two and multi-level implementation Timing and Hazards AOI, PAL, PLA, ROM implementation Mux and Demux • What comes next: – ALU design – Sequential circuits 37 Sources: TSR, Katz, Boriello & Vahid 19