THE. PRODUCTS Rr:FERENCED HERt:IN l\RE NO
LONGER MANUFACTURED BY HONEYWEll 1
THE R~GHTS WITH REGARD THERETO HAVI
BEEN SOLD TO TRACONEX INC. HONEYWaL
INC. IS NOT RESPONSIBLE FOR WARRAN11ES
OR OTHER MAnERS CONCERNING THE
PRODUCTS HEREIN REFERENcm..'
HMC-1000.
TRAFFIC
CONTROLLER
Operation Manual
Honeywell
HMC-1000
TRAFFIC CONTROLLER
OPERATION MANUAL
Honeywell Inc.
TRAFFIC M"ANAGEMENT CENTER
5121 Winnetka Avenue North
New Hope, Minnesota 55428
46099 3/80
To reorder this manual, specify pIN 28022324-002
Printed in U. S. A.
TABLE OF CONTENTS
I
I
[
Section
Page
CONTROLLER FUNCTIONAL DESCRIPTION
Operational Specifications
1.1
Modes
1.2
Man Sync (Stop Timing)
1. 2. 1
Manual
1. 2. 2
On Line
1. 2. 3
Free (Local)
1. 2. 4
Remote (Coordinated)
1. 2. 5
Timing
1.3
Programmi.ng Signal Light and Control Sequences
1.4
1.4. 1
Sample PROM Programming
Display and Front Panel Controls
1.5
Power Up Condition
1.6
External Inputs
1.7
Outputs
1.8
THEORY OF OPERATION
2.0
2. 1
Controller Organization
2. 1. 1
Dial Select Logic
2. 1. 2
Memory Address Logic
2. 1. 3
Programmer Connections
2. 1. 4
Time Display
2. 1. 5
Offset Logic
2. 1. 6
Manual, On Line,
Stop Time Inputs
2. 1. 7
Cycle, Offset, and Interval ;rimers
2. 1. 8
Control Logic
2.1.9
PROM
2. 1. 10 I nte rval Display
2. 1. 11 Power Supply Restart and Countdown Circuit
2. 2
Controller Subassemblies
2. 2. 1
Mother Board and Programmer Input/Output Board
2. 2. 2
Display Card
2. 2. 3
Memory Card
2. 2. 4
Control Card
2. 2. 5
Preempt Card
2. 2. 6
Output Card
2. 2. 7
Power Supply
APPENDIX A - SCHEMATICS, ASSEMBLY DRAWINGS AND
PARTS LISTS
APPENDIX B - NCR 1105 EAROM OPERATION
1-1
1-.3
1-3
1-3
1-5
1-5
1-5
1-6
1-9
1-11
1-14
1-17
1-19
1.0
.
iii
46099
1- 20
1- 23
2-1
2-3
2-6
2-8
2-8
2-9
2-9
2-9
2-10
2-10
2-12
2-13
2-13
2-13
2-13
2-15
2-18
2-24
2-29
2-31
2-34
A-I
B-1
SECTION 1
CONTROLLER FUNCTIONAL DESCRIPTION
I
The Honeywell HMC-I000 Traffic Controller (Figure 1-1) is a pre-timed intersection controller which operates in either an isolated or coordinated mode of
operation.
In the coordinated mode, the HMC-I000 operates as part of a
multi-dial interconnected system, either as a local intersection controller or
as a combined local/master controller.
The HMC-I000 is capable of storing and timing four dials having up to 16 intervals each.
Each interval can be programmed to switch 32 signal outputs into
one of three user selected state conditions (On.. Off.. or Flash). The Controller has five modes of operation: Man Sync (Stop Timing), Manual, On-Line ..
Free and Remote.
The Free, Remote and Man Sync (Stop Timing) modes are
selected from the front panel MODE switch on the HMC-IOOO.
The Manual
and On-Line modes are selected through inputs to the HMC-I000 entered
through the Input /Output cable.
The cycle, interval, dwell and offset times are easily programmed using the
Honeywell HMCP-I000 Programmer.
The use of a non-volatile electrically
alterable read-only memory (EAROM) assures the integrity of these stored
operational parameters.
Power failures or even physical disconnection and
relocation of the controller have no effect on stored data.
A visual display panel indicates the current controller operational status, and
also provides visual verification of parameters entered into the EAROM.
Programmable read-only memories (PROMs) are programmed to meet the
specific signal input and output requirements of the controller application,
and can be "burned-in 11 at the factory or in the field using the HPP-I000 Programmer.
1-1
46099
Figure 1-1.
Honeywell HMC-I000 Solid State Traffic Controller
1-2
46099
~
Figure 1- 2 presents a block diagram of the HMC -1 000 cont roller illustrating
the various inputs, outputs and switch positions described in detail 'on the
following pages.
(
1.1
OPERATIONAL SPECIFICATIONS
Power Requirements: 95 to 135 Vac, 60 Hz, 0.75 amp max.
(1
Environmental:
Temperature: - 30°F to 165°F.
[
Heating and cooling supplied as
part of terminal facilities.
, Humidity: 0 to 950/0, noncondensing. Electronic boards
conformal coated.
Physical: Height, 7. 6 inches; Width, 9.6 inches; Depth, 8 inches.
Weight: 10 pounds.
1.2
MODES
The HMC-lOOO operates in one of five modes as selected by the MODE switch
and/or external inputs.
If there is a conflict in the selection of one or more
modes, the prevailing operational mode will be selected in the following
priority
Man Sync (Stop Timing), Manual, On-Line, Free, Remote
1.2.1
Man Sync (Stop Timing)
In the Man Sync (Stop Timing) mode the HMC-1000 stops timing and holds in
the current interval with the STOP TIMING indicator illuminated and the
i
CLOCK indicator extinguished.
The Man Sync mode is selected by grounding
I
~
the STOP TIME input through· the Input /Output cable or by placing the MODE
switch in the Man Sync position.
1-3
46099
I
DISPLAY
DI SPLAY/PROGRAM
ACTIVE
I
••
0
0
1
2
-
.....
-
1"\,"
3
...
0
0
4
r
OFF
0
INTERVAL 0
CYCLE
0
DWELL
~~
~
OFFSET 1 0
OFFSET 2 0
OFFSET 3
0
ACTIVE DIAL
STOP TIME
MANUAL
MANUAL ADVANCE
ON LINE
I-
=> ADVANCE <ON LINE)
0z
2
I
DIAL
H
0
1
2
_
3
0
..
.......
3 0
4 0
.
.....
..
RESTART
l./)
REMOTE
.....
-
.
", "
r---
----.
.....
.....
.....
..
...
~
..
32..
0
~
OUTPUTS
0-
.......~
LOGIC AND
FOUR DIAL
MEMORY
.. 8
..
..
. 24 VDC
.....
p
....
p
OFFSET
2
I
3
I
.....
.....
POWER
••
MODE
FREE
0-+0 REMOTE
o
o
Figure 1-2.
ON
OFF 0
....
1 AMP
MAN SYNC
HMC-1000 Controller Block Diagram
1-4
46099
......
FLASHING
BUS
1. 2.2
Manual
In the Manual mode, the HMC-I000 stops timing except for intervals that have
been programmed to be guaranteed intervals.
Intervals not programmed as
such may be advanced one interval at a time by grounding the MANUAL
ADVANCE input.
~
Intervals may be programmed as guaranteed automatic
advance or guaranteed manual advance required.
Intervals programmed for
guaranteed automatic advance will advance to the next interval when the pro-
(
grammed time has been reached.
Intervals programmed for guaranteed manual
advance will advance to the next interval only with manual advance.
The
Manual Advance mode is selected by grounding the MANUAL input through the
Input/Output cable.
A MANUAL ADVANCE input before the programmed time
has been reached causes the manual advance to be stored and the advance to
occur at the programmed time. A MANUAL ADVANCE input after the programmed time has been reached causes the HMC-I000 to advance to the
[I
next interval.
1. 2.3
[
On Line
In the On Line mode, the HMC -1000 functions in the same manner as in the
Mar;ual mode except that the active input is the ADVANCE (ON LINE) input.
The HMC-I000 is placed in the ON LINE mode by grounding the ON LINE
input through the Input/Output cable.
Note: The MANUAL and STOP TIME
inputs will override this input.
t
1.2.4
~
In the Free mode, the HMC-IOOO times the intervals and automatically advances
[
Free (Local)
them without regard to external synchronization pulses.
the Free mode when the MODE switch is in the FREE position.
1-5
l
[
The HMC-I000 is in
46099
Synchronization
can be achieved even if the HMC-lOOO is not in an interconnected system.
The controller can be placed in the Stop Timing mode by putting the Mode"
switch in the MAN SYNC position for the appropriate time and then placing
the MODE switch in the FREE position.
The HMC- 100"0 will then operate
in apparent synchronization because timing occurs by division of the 60Hz
power line.
1.2.5
Synchroni.zation is lost when power is interrupted.
Remote (Coordinated)
In the Remote mode, the HMC-IOOO times the intervals and automatically
advances intervals in synchronization with synchronization pulses supplied to
one of the OFFSET inputs.
The HMC-IOOO is ir:t the Remote mode when the
MODE switch is in the REMOTE" position and synchronization pulses are being
received.
Synchronization is achieved by extending the dwell interval (assigned
by PROM programming) for a time up to or equal to the programmed dwell
time.
Each time the dwell interval repeats, the interval is extended until
synchronization is achieved.
The dwell interval will then begin at the synchro-
nization time, which is determined by delaying the incoming synchronization
pulse by the offset time (stored in EAROM).
Ftgure 1-3 illustrates the timing
of an HMC-l 000 in synchronization when four intervals are used and interval 4
is.. the dwell interval.
The offset time is programmable and may be any value
between 0 seconds and the cycle time in one second increments.
illustrates how the HMC-IOOO achieves synchronization.
Figure 1-4
These pulses are
not recognized until the second synchronization pulse after the power and/or
synchronization is turned on, or after the MODE switch is placed in the
REMOTE position.
The dwell interval is then extended by no more than the
programmed dwell time until the controller is synchronized.
1-6
46099
..
"
n__
-...
____---In
. . +GN24D VDC
OFFSET 11NPUT
J.--f.---1
CYCLE TIME
INTERVAL
I
TIME (SEC)
OFFS ET 1 TI ME
-411~
Figure 1-3.
---~~~
2--l3~
Example of Synchronized HMC-1000 Utilizing Four
Intervals (Interval 4 is dwell interval)
FIRST SYNCH PULSE RECEIVED
RECOGNIZES SYNCH PRES ENT
l
OFFSET 1
INPUT
INTERVAL
I
!
MODE
6
'*
l
~~ 2~3~ 4~11- 213~14~1~ 2~3.
FREE
1'41
-1 6
~
HMC-1000 NOW SYNCHRONIZED
REMOTE
------------INTERVAL
DWELL INTERVAL EXTENDED BY FULL DWELL TIME
(3A
(3B
(3B
(3A
1
2
3
DWELL INTERVAL EXTENDED BY LESS THAN FULL DWELL TIME
4
Figure 1-4.
POSSIBLE FUNCTION
CLEARANCE
GREEN
CLEARANCE
GREEN (DWELL INTERVAL)
Example of HMC-1000 Detecting Synch Pulses and Extending Dwell
Interval Until Controller is Synchronized (Note: Offset time is
shown as zero)
+24V
OFFSET 1
INPUT
TIME (SEC) ....
+24V
OFFSET 2
INPUT
---fl_____n"'__----'
GND
+24V
OFFSET 3
INPUT
GND
n
'------
OFFSET 2
*
n-
"'-----
OFFSET 3
OFFSET 2 WILL SWITCH TO OFFSET 3 AT THE TIME INDICATED IF BOTH
OFFSET 2 AND 3 ARE HIGH FOR 100 MILLISECONDS.
Figure 1- 5 .
Offset Se Ie ction
.1-7
46099
Other features in the Remote mode include:
•
If the synchronization should fail either high or low, the HMC-lOOO
will revert to the Free mode without extending the dwell interval.
In interconnected systems, in case the master controller
fails or is temporarily removed from service, the HMC-lOOO will
remain in synchronization as long as the other controllers in the
system accurately track the 60Hz power line.
•
Once the HMC-lOOO is in synchronization, it will remain in synchronization as long as the sync pulse cycle time is equal to the dial cycle
time ±250ms.
This feature is incorporated to allow the use of an
electromechanical master controller which may introduce some jitter
into the incoming pulses.
If the sync pulse does not occur in this time
frame, the HMC-IOOO automatically extends the dwell (up to the maximum time set in the dwell timer) to try to obtain synchronization.
•
The offset time may be selected as illustrated in Figure 1- 5.
Three
offset times per dial may be programmed into the HMC-lOOO and
selected by applying a synchronization pulse to the appropriate input.
When the offset time is changed, the HMC -1000 will have to resynchronize itself.
•
The HMC-lOOO can be used in a system that uses an offset interrupter.
Some electromechanical timers require additional sync
pulses, which often occur at random intervals between the regular
sync pulses.
The HMC-lOOO synchronizes only on pulses having the
same cycle time as the HMC-lOOO is programmed for.
CAUTION:
If the master controller supplying
synchron~zation to
the HMC-lOOO runs "fast" or has a slightly shorter
cycle time, the HMC-lOOO will not synchronize or will
not remain in synchronization.
On the other hand, if
the master runs" slower" or has a slightly longer
1-8
46099
I
I
cycle time than the HMC-IOOO, the HMC-IOOO ,will
dwell in the dwell interval on each cycle and cause its
cycle time to be extended to the master's cycle time.
1.3
TIMING
Timing may be programmed and stored in the EAROM for each dial within the
I
I
I
I
t
limits shown below:
TIME
INTERVAL
QUANTITY
16
MEMORY
RANGE
(SEC)
INCREMENT
(SEC)
0-99.9
0.1
CYCLE
1
0-999
1.0
DWELL
1
0-99.9
O. 1
OFFSET
3
0-999
1.0
The interval times control the amount of time the controller is in the interval.
Intervals having zero time are skipped.
Cycle" dwell, and offset times are
used in the Remote mode as described above.
It should be noted that the sum
of all the interval times used must equal the cycle time and therefore the sum
of all the interval times must be measured in 1 second increments. The
HMCP-I000 Programmer has circuitry that assures this relationship.
Figure
1-6' illustrates a chart format that can be used to program the HMC-I000.
Mark the times for the dwell interval and the last interval, then fill in all the
times for the dials and intervals used.
This chart can be used for programming
and maintaining records.
Timing is derived from the 60 Hz power line by applying threshold detection,
hysterisis" and filtering to the 60 Hz waveform (for noise rejection) and then
dividing the frequency by digital counters to 10 Hz and 1 Hz.
The 10 Hz signal
drives countdown circuitry, and the 1 Hz signal drives flashing displays and
flashing signal circuits.
1-9
46099
INTERVAL
TYPE
I-
....I
....I
«
....I
$
c
(f)
INTERVAL
TIME (SEC)
l1J
1
2
4
9
10
coO
11
-. -
-. _. -
-.
- .-
_. -
- '0_
_. -
-0 _
_._.-
12
-. _.
_. -
13
14
',1
- ._. -
_
- 0_
7
8
co~
DIAL 4
_. _. .-
6
O'
DIAL 3
_.-
5
~
cn~
DIAL 2
_0_0-
3
-'.
DIAL 1
15
_0 _
16
-.
CYCLE
DWELL
OFFSET
1
OFFSET
2
OFFSET
3
1\V
V1\
Figure 1-6.
-
-.-
- 0_
_. _.-
_. _. -
_._0 _
_.-._.-. -
-.-.
- .-
_0-
_. _. -
_. -
_.
-
_. -
-
_._.- ._.-
_.._._.-
-.-
-.- .-
-.-
_.-
_._.-
_.-
_.-. -
-.-
_.-.-
-. -
-.-
-.-
HMC-1000 Controller Programming Chart
1. 4 PROGRAMMING SIGNAL LIGHT AND CONTROL SEQUENCES
The three state conditions (On, Off, Flash) of the 32 outputs and 8 interval
control functions can be programmed for each interval.
Programming is
accomplished by "burning" metal links on fi ve programmable read only
memory (PROM) chips using an HPP-I000 Programmer or equi valent.
The
PROM's are then inserted into sockets on the HMC-I000's Output Card.
PROM controls 8 outputs or internal control functions.
Each
Figure 1-7 illustrates
how the PROM's are organized and is a chart to aid in programming the HMC1000.
It is not necessary to insert all five PROM's in an HMC-I000 but PROM
1 is always required.
The flashing state is one flash per second, with a 50
percent duty cycle.
For ready reference the function of each output can be defined on Figure 1-7
in terms of cabinet wiring, for example: Output 1, controlled by PROM 1, Bit
0, could be Phase-A Red; Output 2, controlled by PROM 1, Bit 1, could be
Phase-A Yellow; etc.
As is evident from the figure, some of the PROM bits
are permanently assigned to interval control functions of the HMC-I000.
These permanently assigned control functions are described below.
None of
the control functions operate in the flash state.
•
LAST INTERVAL - A logic 1 is inserted in the last interval.
For
example, if 13 intervals are required a 1 in interval 13 will cause
the HMC-I000 to skip intervals 14, 15, and 16 jump to interval 1
after interval 13.
If more than one interval is programmed as last
interval, the lowest numbered last interval will be considered the
last interval.
•
DWELL INTERV AL - A logic 1 is inserted in the dwell interval.
example, if interval 10 is to be the dwell interval (possibly main
street green), a 1 is inserted in interval 10.
1-11
46099
For successful
For
>-
o <X:
<X:...J
FUNCTION
ow
...Ja::
LAST INTEVAL
f-
:::>
a.
f-
:2
0
a::
:::>
0
a.
1
1
INTERVAL
!::
co
1
1
3
4
2
3
5
4
6
5
7
6
7
0
DWELL INTERVAL *
2
2
3
11
4
12
5
13
14
6
7
~
3
18
19
~
23
4
24
25
9
10
11
12
0
1
5
6
7
5
0
1
2
II
=
J =
3
GUARANTEED INTERVAL*
WITH MAN ADVANCE *
ALLOW DIAL TRANSFER *
4
SPECIAL 1 *
5
,
0
6
7
= LIGHT
ON
OR BLANK = LIGHT OFF
F = FLASHING
= FLASHING
16
6
7
28
GUARANTEEDINTERVAL*
WITH AUTO ADVANCE *
*
13 14 15
0
1
2
29
32
o
8
3
4
30
1
7
2
26
27
SPECIAL 3 *
6
5
22
SPECIAL 2 *
5
3
4
20
21
31
4
1
8
9
10
15
16
17
3
0
2
*
2
STATE NOT ALLOWED FOR THIS BIT
Figure 1-7.
PROM Program Sheet
1-12
46099
NOT ACTIVE
ACTIVE
coordinated operation, only one interval may be the dwell interval.
•
GUARANTEED INTERVAL WITH AUTOMATIC ADVANCE - This
feature is acti ve only in the Manual or On Line modes and is typically
used to guarantee adequate clearance time in these modes.
During
Manual or On Line modes, the intervals having 0 for this bit will
time out and automatically advance to the next interval wtth or without a manual advance or computer advance input.
Intervals having 1
for this bit and 1 for the Guaranteed Interval With Manual Advance
bit will cause stop timing and require a manual (or computer) advance
to go to the next intervaL
If a PROM is not plugged into the PROM 5
socket, all intervals will require manual advance.
If a new but
unprogrammed PROM is plugged into the PROM 5 socket, all intervals
will time out and automatically advance, if in the Manual or On Line
modes, and the HMC-IOOO will appear to be in the Free mode.
(Unprogrammed PROMs have all bits set to 0.) Intervals programmed
with 0 for this bit and the other guaranteed interval bit will time out
and automatically advance in the Manual and On Line modes.
•
GUARANTEED INTERVAL WITH MANUAL ADVANCE - This feature
is active only in the Manual or On Line modes and is typically used to
extend the length of movements but guarantees a minimum time for
the movement.
In the Manual or On Line mode, the intervals ha ving 0 for this bit
will be timed and held until a manual (or computer) advance is
received.
(During the Manual mode only manual advance commands
are accepted.) If the advance command is received before the programmed time, the advance will be remembered and the interval
advanced when at the end of the programmed time.
If an interval is:.inadvertently programmed for both options it will
require a manual (or computer) advance to go to the next interval.
1-13
46099
•
ALLOW DIAL TRANSFER - When this bit is 1, remote transfer of the
dial is allowed.
inhibited.
When this bit is 0, remote transfer of the dial is
Typically this feature is used to permit dial transfer
during one or more selected intervals.
No PROM in the PROM 5
socket causes all intervals to allow dial transfers.
An unprogrammed
PROM in the PROM 5 socket results in no remote dial transfers
allowed.
•
Special 1, 2, 3 are unused bits reserved for special functions.
1.4. 1 Sample PROM Programming
Figure 1-8 illustrates a PROM Programming Sheet filled out to reflect the
programming sequence required to prepare an HMC-1000 Traffic Controller
for proper operation. The format illustrated is for a 2-phase intersection
with pedestrian signals. In this example, Interval 1 is vehicle clearance,
showing yellow on the main street signal. Interval 2 is an all red clearance.
Interval 3 is the side street movement, with side street green and walk illuminated. Interval 4 is side street pedestrian clearance, with the side
street flashing don't walk. Interval 5 is side street yellow clearance followed by Interval 6, all red clearance. Interval 7 is a main street movem~nt,
with main street showing green and walk, followed by pedestrian
clearance, Interval 8 (flashing don't walk).
Interval 7 is defined by PROM 1 to be the dwell interval that is extended
when the HMC-1000 Controller is synchronizing itself in a coordinated
system. Interval 8 is the last interval, this means that intervals "9 through
16 are skipped.
1-14
46099
>0«
«-l
ow
-l'"
FUNC.ION
hAlt-)
\~
~T. ~eo
\y
"""U ~T.
'IE. L.
"'~1tJ 'ST. 4CW
'G
'Zit
~lD~ 'ST. ttl: D
SlOe ST. 'Ie\.
S,'tl~
I::J
Q.
I::J
0
::;;
0
'"
co
1
0
Q.
1
2·,
1
0
\
3
0
0
1
I
0
0
0
I
0
0
0
4
3
I
5
4
ST.-t;.Rtol "Z.G
6
"
5
0
6
0
DWELL INTERVAL *
7
0
0
0
0
I
I
1
0
0
0
0
0
0
'3~
MAl'" ~T. C.W '3V
... AIW ·!iT. -.,AL.J, 13Ca
9
2
SlOE ST. D.W. 4R
SIOE-ST.O,W. 4Y
~'OE ST. Wit"'" fij(;
10
3
11
4
0
0
0
0 0
2
8
12
5
13
6
14
7
15
3
16
1
2
18
3
19
4
20
5
21
6
22
7
4
24
0
0
0
0
0
I
0
0
4
5
6
I
\
\
0
0
0
0
C)
0
0
0
0
0
0
0
I
0
I
I
,
0
I
0
C
0
0
0
0
, ,
0
0
I
~
~
r.l
~
2
3
27
4
28
5
29
6
30
7
0
t-\
,
~
(;
I."
,.."
-
t.
l"\
I
R
IV
y
"""
G
OW
5
0
"'lJ
"
IA"
(
~
')
LT
C~.J
'\
0 0 0
0 0
0
0 0
0 0
(;) (;)
0
I 0
(;)
0 0
I
3
I I I I I I I I
ALLOW DIAL TRANSFER*
4
0
SPECIAL 1 *
5
SPECIAL 2 *
6
SPECIAL 3*
7
0
0 0 0 0
0 0 0
0 0 0 0 0 0 0 0
0
0
0
0
"
0
ON
0
0
0
0
0
0
0
0 0
0 0
0
0
0
INTERVAL 5
MS
SS
INTERVAL 6
MS
SS
0
0
0
0
0
@
@
@
@
@
@
0
0
0
()
0
INTERVAL 7'
MS
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
@
@
@
INTERVAL 10
MS
SS
INTERVAL 11
MS
SS
INTERVAL 12
MS
SS
INTERVAL 8
MS
SS
@
0
0
@
@
@
0
0
0
0
()
0
0
0
@
@
@
,
INTERVAL 13
MS
SS
INTERVAL 14
MS
SS
INTERVAL 15
MS
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@
0
0
0
0
0
0
0
0
0
0
@
@
@
@
@
@
@
0
0
0
0
0
@
@
@
@
.@ .@
0-
0
INTERVAL 4
MS
SS
0
0
h
GUARANTEED INTERVAL*
WITH MAN. ADVANCE *
0
0
j
0
*
~~
W
.r-
SS
•
•
•
•
•
•
•
•
•
•
a
a
•
•
•
•
•
•
• • • • • • • • •0 • • • • •
0
INTERVAL 9
MS
SS
I .....
0
= LIGHT OFF
= FLASHING
= FLASHING STATE NOT
LT
0
0
F
W
MS
0
1
= LIGHT
DW
INTERVAL 3
I
2
1
G
0
0
GUARANTEED INTERVAL*
WITH AUTO. ADVANCE *
o OR
R
1
26
32
13 14 15 16
y
~
~ I~ ~
...\
\
12
INTERVAL 2
MS
SS
<:>
1
f\ -...
11
~
D~ I\~
y
.I
10
I 0
.
~,
1\'
9
0
0
I
,
,. ~ ~l
,,,"
0
0
0
\.11
;
8
,,
0
0 0
0
I
I
0 0
0 0
0 0
0 0
0
0
~ I
0 0
0 0
0 0
0 0
0
0
.. h ... v.. F.-J'
~
7
0
25
31
,,
0
17
23
I
0
0
0
I
7
~T.
,
2
?y
t).w.
2
3
LAST INTEVAL *
MAl\.!
INTERVAL 1
MS
SS
INTERVAL
- !::
OFF
.
~
0
0
0
0
0
INTERVAL 16
MS
SS
0
0
0
0
0
0
0
0
0
0
@
@
-:
. - ON
() -
}
FLASHING
l ' NOTACT'"
0= ACTIVE
0
" "
BLANK
ALLOWED FOR THIS BIT
Figure 1-8. PROM Programming Sheet
(Sample Program)
f-15
46099
I
r
I
Note that PROM 5 defines Interval 7 as the only interval allowing
dial trans,
fers to occur, and that all intervals except 3 and 7 are Guaranteed Intervals
with Automatic Advance when the HMC-1000 Controller is in the On-line or
Manual Mode. Intervals 3 and 7 require manual advance and they are not
guaranteed since they are not clearance intervals.
I
I
1. 5 DISPLAY AND FRONT PANEL CONTROLS
Referring to Figure 1-1, the Display indicates the active interval on the
selected dial, the selected time for that interval, and the status of the
HMC-1000.
The INTERVAL display is a two digit number (1 through 16) and the TIME !SEC
display is a three digit number with decimal point.
selected by the DISPLAY!PROGRAM switches.
1, 2, 3, 4 selects the dial being displayed.
The time displayed is
The upper switch; ACTIVE,
The ACTIVE position displays
information selected by the ACTIVE DIAL switch.
The ACTIVE DIAL and
DISPLAY!PROGRAM switches do not have to be in the same positions.
-The lower DISPLAY!PROGRAM switch selects the type of data being retrieved
from EAROM and being displayed.
In the OFF position the INTERVAL and
the TIME !SEC displays are extinguished.
To lengthen their life it is re-
commended that the displays be turned off during normal operation and be
turned on only when troubleshooting or when programming is being performed.
In the INTERVAL position, the current interval is displayed arid the stored .
interval time is displayed.
(When programming, the interval being programmed
and its time are displayed independent of the currently operating interval.) In
1-17
46099
the other positions the function times are displayed.
This switch is also used
to select what functions are being programmed when an HMCP-1000 Programmer is used for programming.
The other status displays operate continuously.
1.
The STOP TIMING indicator is illuminated when the HMC-1000 is
not timing.
2.
The CLOCK indicator flashes at one flash per second when the
controlle r is timing.
3.
The OF FSET indicator indicates which one of the three offsets is
being used.
4.
The DIAL indicator indicates which one of the four dials is currently
active.
The ACTIVE DIAL switch, REMOTE, 1, 2, 3, 4, selects the currently active
dial that the controller is operating in.
REMOTE allows the remote input
lines to select the dial, subject to the Allow Dial Transfer bit.
The other
positions select a dial without regard to the Allow Dial Transfer bit.
NOTE: The current interval time being timed does not change immediately
when the ACTIVE DIAL switch is changed.
The timer reads a new time only
when it completes the current interval period.
out of step operation when switching dials.
This procedure prevents any
The display may indicate a time
from one dial while the controller is timing a time from a previously selected
dial.
p.
The MODE switch selects the REMOTE, FREE, or MAN SYNC (stop timing)
modes according to the function description in paragraph 1. 2.
The POWER switch supplies the 115 Vac power to the HMC-1000.
A 1 ampere
slow blow fuse protects the HMC-IOOO.
The INPUT /OUTPUT connector connects the HMC-1000 to the cabinet wiring
and includes all inputs, outputs, and 115 Vac power.
The PROGRAMMER
connector allows connection of the HMCP-1000 Programmer or other suitable
programmers to program the timing functions.
1. 6 POWER UP CONDITION
When power is first applied to the HMC-1000, the following initial conditions
occur:
1.
The interval is set to 1.
2.
The ACTIVE DIAL switch selects the dial.
If the ACTIVE DIAL
switch is in the REMOTE position, the dial is selected by external
input.
3.
Timing begins approximately O. 5 second after power is applied.
This
delay assures that all power supply voltages are within tolerance before starting operation.
4.
The HMC-IOOO powers up in the Free mode unless it is in the
Manual, On Line, or Man Sync modes.
5.
If external offset signals are present the correct offset is selected
before sync is recognized.
1-19
46099
For power interruptions of less than 500 milliseconds, the HMC-1000 will
retain the current interval and, when power is reapplied, operation will commence without resetting.
During the power interruption, the timer will stop
timing since the 60 Hz signal is not present.
In a coordinated system a power
loss may cause synchronization to be lost if the power interruption did not
also occur at the master controller.
For power interruptions of greater than 1 second, the HMC-1000 will reset
to the power up condition when power is reapplied.
For power interruptions
between O. 5 and 1 second, either reset or continued operation may occur.
1. 7 EXTERNAL INPUTS
This paragraph describes the functions of the external inputs (see Figure 1-2).
1.
DIAL 2, DIAL 3, and DIAL 4.
These inputs select the active dial when
the ACTIVE DIAL switch is in the REMOTE position.
these inputs selects the appropriate dial.
grounded, Dial 1 is selected.
Grounding one of
If none of these inputs are
If more than one dial input is grounded,
the highest number dial is selected.
2.
OFFSET 1, OFFSET 2, OFFSET 3.
These inputs provide synchronization
and offset selection as described in paragraph 1. 2. 5.
Grounding more
than one input will result in the controller operating in the Free mode.
If one input is continuously grounded while the other input has a sync
pulse an unknown offset selection will result if more than one input has
"simultaneous11 sync pulses.
3.
RESTART.
Grounding the restart input holds the HMC-1000 in the power
up restart condition described in paragraph 1. 6.
is released, the HMC-1000 will start running.
1-20
46099
When the restart input
4.
STOP TIME (man sync), MANUAL and MANUAL ADVANCE, ON LINE,
ADVANCE, See paragraphs 1. 2. 1, 1. 2.2, and 1. 2. 3, respectively,
for a description of these inputs.
5.
115 VAC, NEUTRAL, and CHASSIS GND.
power connections for the HMC-1000.
These are the 60 Hz 115 Vac
115 Vac input is the "hot" side of
the power line anc should be connected to the" colored, " ungrounded wire
as specified by the National Electrical Code.
The NEUTRAL input is the
grounded side of the power line and should be connected to the white wire
as specified by the National Electrical Code.
The CHASSIS GND connects
to the HMC-1000 chassis and is a safety ground to prevent the unit from
becoming "hot" should there be a failure in the insulation between the 115
115 Vac and chassis.
The CHASSIS GND should be connected to the cabinet
at the terminal facilities.
6.
LOGIC GND.
Several logic ground pins are available on the HMC-1000
INPUT /OUTPUT connector.
The LOGIC GND is the reference for all
inputs and outputs (except 115 Vac power) and is not connected to the
chassis ground.
The electrical requirements for the external inputs are listed in Table 1-1.
..
1-21
46099
Table 1-1.
--
-----
.
FUNCTION
PULL UP
RESISTOR
(K OHMS)
TR DE (ON)
PULL UP CONDI- MAX SINK FALSE (OFF)
TO
TION
CURRENT CONDITION
(VOLTS)
(VOLTS) (MA)
(VOLTS)
,DIAL 2
10
24
DIAL 3
10
24
DIAL 4
10
24
OFFSET 1
10
24
0)'"
OFFSET 2
10
24
col:"
OFFSET 3
10
24
ON LINE
10
24
ADVANCE (on line)
10
24
MANUAL
10
24
MANUAL ADVANCE
10
24
STOP TIME
10
24
RESTART
10
12
~
o'
col:"
,
Electrical Requirements for External Inputs
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 8
o to 3. 2
. APPROXIMATE
DELAY BEFORE
OPERATE
(milliseconds)
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
3
16 to 24
10
12
7. 6 to 12
10 to 100
'.
1.8 OUTPUTS
This paragraph describes the functions of the outputs from the HMC -1000.
1.
OUTPUTS 1 THRU 32.
These outputs are designed to drive solid state
load relays and are the 32 outputs intended to control signal lights, sync
pulse (when HMC-1000 is used as a master), or other control functions.
These outputs are programmable as described in paragraph 1. 4.
2.
FLASHING BUS.
This is a general purpose output that supplies a 24 VDC,
one flash per second, 50 percent duty cycle output.
3.
+24VDC.
This output is regulated 24 VDC for the load relays and for the
conflict monitors.
CAUTION:
THIS OUTPUT SHOULD NOT BE SHORTED TO GROUND.
SERIOUS DAMAGE TO THE HMC-1000 COULD RESULT IF THIS
OUTPUT IS SHORTED TO GROUND.
1-23,
46099
ELECTRICAL CIRCUIT REQUIREMENTS FOR HMC-1000 OUTPUTS
+24 ± 1 VOLTS
OUTPUT 1 THROUGH 32
10K OHMS
10 OHMS
~""t:--....J\rvv'-----+ OUT PU T
. - I SINK
Vee
J
LOGIC GND
=
MAXIMUM SINK CURRENT
40 ma
MAXIMUM VOLTAGE (APPLIED TO OUTPUn 30 VOLTS
0.7 VOLT
MAXIMUM VCE SATURATION VOLTAGE
=
=
OPTIONAL OUTPUT 1 THROUGH 32
10 OHMS
..,,---r-.JV'o,N'---+ OU T PU T
. - I SINK
=
100 ma
MAXIMUM SINK CURRENT
MAXIMUM VOLTAGE (APPLIED TO OUTPUn 24 VOL TS
1.1 VOLTS
MAXIMUM VCE SATURATION VOLTAGE
=
=
FLASHING BUS
10
200 OHMS
OHMS
FLASHING BUS
LOGIC GND
=
MAXIMUM OUTPUT CURRENT
25 ma
APPROXIMATE ON RESISTANCE
220 OHMS
APPROXIMATE OFF RESISTANCE (GREATER THAN 100 K OHMS)
=
+24 VDC
VOL TAGE TOLERANCE: 24 ± 2 VOLTS DC
MAXIMUM CURRENT: 0.18 AMPERES
CAUTION: SERIOUS DAMAGE TO THE HMC-1000 COULD RESULT
IF THE +24 VDC OUTPUT IS SHORTED TO GROUND.
1-24
46099
.
SECTION 2
THEORY OF OPERATION
The high operational reliability of the all solid state HMC-1000 Controller is
achieved through the extensive use of low-noise CMOS circuitry.
The
HMC-1000 meets NEMA specifications fop all defined input and output signal
levels and environmental requirements.
I
I
I
I
Figure 2-1 illustrates the HMC-1000 Controller's organization by function.
An electrically alterable read only memory (EAROM) and support addressing
and timing logic stores the interval, cycle, dwell and offset times while a
programmable read only memory (PROM) stores the state of each output
(On, Off, Flash) for each interval.
Digital countdown timers measure the
cycle time, offset time, interval and dwell time using data stored in the
EAROM and based on the 60Hz line frequency.
Control logic decides when to
dwell in the Remote Mode, when to advance the interval counter, when to skip
back to Interval 1 (after the last interval), etc.
The control logic also con-
trols the advance interval in the On Line, and Manual modes controlled by
I
I
I
appropriate inputs.
Dial select logic selects the active dial from the ACTIVE DIAL switch
or from remote inputs and selects the dial to be displayed or programmed
from the DISPLAY!PROGRAM switch. Offset logic detects synchronization pulses
from the three offset input lines.
Displays indicate INTERVAL, TIME,
active DIAL, active OFFSET, CLOCK, and STOP TIMING.
The power supply distributes power to all HMC-1000 circuits,
external cabinet functions, and the HPP-1000 Programmer.
th~.
24 Vdc to
A power up
reset and clock circuit initiates the interval counter and the flip flops in the
control logic.
I
2-1
46099
I
..... .., . . . . . . . . f
••
~
......... , .......
CONTROL, ADDRESS, DATA TO PROGRAMMER
y t
«
I«
o
OFF
0
INTERVAL-CYCLE
0
0
DWELL
OFFSETl 0
OFFSET20
OFFSET3 0
ACTIVE
-<>
~
2
3
-<>
i.o
-
INTERVAL - - .
2
:i
DIAL
SELECT
LOGIC
Ci
3
4
I
A
DIAL
o.
CO~
co
-
L-t
.---.
DIAL,
OFFSET,
CLOCK
AND STOP
TIME LED
:::>
2
1
ILJ.I
Vl
2
o
3
Ll..
Ll..
OFFSET
LOGIC
OFFSET
...J
«
>
0::
LJ.I
I~
INTERVAL
DISPLAY
0
2
«
<.:l~
2~
-<.:l
::;;;0
t=...J
> ,Vl
o::::;;;Vl
ooLJ.I
::;;;0::0::
LJ.IǤ:
::;;;~«
PROM
<32>
I
I
...J
0
0::
I2
0
u
'...J
Vl«
0::>
LJ.I0::
::;;;LJ.I
-I12
2:;:0
-MODE
--
020::
O«LJ.I
I-Ul2_2
FREE 0
Vl
I-
Cl.
STROBE
.
REMOTE 0
1-<>
2
3-0
4-0
Cl)~
TIME
DISPLAY
ADDRESS
CTIVE DIAL
~
f----t
(CAM)
CONTROL
RESTART
10Hz
OUTPUT
1
PWR UP
RESET
fAND CLOCK
CIRCUIT
:::><.:l:::>
REMOTE
000
U...JU
MAN SYNC 0
SYNC
(
ON LINE
R
ADV.
,
MAN.
24VDC
MAN. ADV.
POWER TO PROG.
STOP TIME
POWER
SUPPLY
/
RESTART
Figure 2-1.
HMC-1000 Controller - Organized by Function
~ 115VAC
Numerous connections to the HPP-1000 Programmer supply control timing
and data flow between the two units.
2.1 CONTROLLER ORGANIZATION
The memory used to store time data in the HMC-1000 Controller is an
EAROM, organized as a 256 word, four bit word device.
A word may be addressed by selecting one of 8 row inputs and any combination on 5 column inputs (the column input address is decoded on the EAROM
chip to select one of 32 columns).
A word may be written or read, one 4 bit
word at a time, by selecting the row and column address and applying proper
timing signals to clock inputs.
The data when read appears at the 4 bit data
input/ output terminals.
When writing data, the data at the input/ output terminal, driven by the programmer, will be stored in memory.
occurred before writing data.
The erase operation must have
This is accomplished by putting a high voltage
(+54 volts) pulse on a selected row line.
The entire row is erased at one
time.
In the HMC-1000, two rows (containing 64 words) are used for one
dial.
Erasing, accomplished only when a programmer is connected to the
HMC-1000, erases two rows at a time which corresponds to erasing one dial
at a time.
A memory chip is capable of storing the timing data for 4 dials.
For more information on the EAROM see Appendix B.
2-3
46099
Each 4 bit word in the memory corresponds to a decimal digit and is. encoded
as a Binary Code decimal number as shown below:
Bit
D3
D2
D1
DO
Decimal
Value
Displayed
Character
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
1
2
3
4
5
6
7
8
9
Valid
Valid
Valid
Valid
Valid
Valid
1
1-
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
Not
Not
Not
Not
Not
Not
1
2
3
4
5
6
7
8
9
A
- (minus sign)
C
(dark or blank)
E
F
Notice that the combinations above decimal value 9 are not valid decimal
numbers but that characters having invalid decimal values may be displayed
by the seven-segment time displays as a alphabetic or other characters.
Dur-
ing normal operation the programmer enters only valid decimal values into
m~mory
but when the memory is erased, some of the data read out of the
erased memory will be invalid decimal numbers.
Three four bit words are used to make up a 3 digit time display.
Each dial
contains; 16 - three digit interval times, 1 - three digit cycle time, 1 - three
digit dwell time and 3 - three digit offset times.
Each dial requires 63 words
to store the above time information.
2-4
46099
"
I
I
I
I
I
I
t
I
I
I
I
I
Timing is done in the HMC-IOOO using presetable counters as
illustrat~d in
Figure 2-2.
4 BIT DATA FROM MEMORY
,
•
0:::
UJ
IZ
r-t DWN
1
COUNTER 1
;:)
o
u
o
<C
o
..J
L
BORROW
2
r
.
COUNTER 2
,....
TIME OUT
p
COUNTER 3
3
CLOCK
Figure 2-2.
Countdown Circuit
At the beginning of the period to be timed, one digit at a time is retrieved
from EAROM and loaded into the counters.
digit 1, then counter 1 is loaded.
First memory is addressed for
Then in a similar manner, the other two
digits are loaded into the counters with data from memory.
approximately 2 ms.
Loading takes
A clock, derived from the 60 Hz power line, then
counts the three counters down.
When all three counters contain zero, a
If the clock fre-
time out pulse is generated terminating the timed period.
quency is 1 Hz, the range of timing is 0 to 999 seconds in 1 second incre-
f
ments.
If the clock frequency is 10Hz, the range of timing is 0 to 99.9
seconds in O. 1 second increments.
I
I
I
2-5
1
J
46099
.
Since tp.ere :are several counters, a display, and a programmer that must
read or write data, the EAROM must be time shared among the several
users.
Timing logic is used to multiplex the EAROM addressing and data
routing to the several users.
Figure 2-3 is a detailed block diagram of the HMC-1000 showing all connections to the programmer
(--7-
~r ~), all inputs ( 0 - - ) and. outputs
( [J-:-). One line on this block diagram may represent several wires,
for example
(4) .
represents four wires.
The block diagram also indi-
cates which card or cards contain the function described in the block diagram.
2.1.1
Dial Select Logic
Starting from the left in Figure 2-3, the dial select logic selects the active
dial (controlling the signal lights) and the dial to be programmed or displayed.
Remote dial inputs are first buffered and filtered and prioritized.
example, if dial 4 and dial 3 inputs are low, dial 4 is selected.
For
The remote
dial input is then buffered by a 4 bit latch that holds the dial until the transfer
allow bit from the PROM is set.
When the ACTIVE DIAL switch (S3) is in
the REMOTE position, the active dial selected is the dial stored in the 4 bit
latch.
When the ACTIVE DIAL switch is in any other position, the active
dial selected is by the switch.
dial.
The DIAL display LED's display the active
The DISPLAY /PROGRAM switch (82) selects the dial to be displayed
which may be the active dial displayed by the dial display LED's or one of
the other three dials.
The output of the dial select logic is multiplexed
depending on whether data is being loaded into counters (active dial) or into
the display (display/program dial).
J':
2-6
46099
-'
«
:;J
~
w
-'
....
C
z
z
o
~ ~
:5
~
Cl
~
u.
u.
o
>Cl
>-
>-
0
INTERVAL
'"o
'"'IT
«
>-
~
u
i
....w
~
-'
w
,. ~,. ~,.
....w
w
<D
~
in
....
«
....
«
;:; §I 21 §I §i 5i
~J+~
v
c:::
::;
'"
::;
0.
'"
'"
0.
§I
:oJ
~
'"
3
U
u
N
S2
0
~.
u
0
,..:
~
V>
0:
<:;
c;
0
~Y
:i:
CYCLE
t---f-------~- DISPLAY OFF
DWELL
+--+
---'-(4;..'.... INTERVAL
OFFSET 1
OFFSET 2
DISPLAY/PROGRAM
SWITCHES
OFFSET 3
V>
.----
S1
~
::;
(32)
~~~
'"w
o
'"ou
-
-J
«
>
~~~
1
«<:;;
>-0
",-,
OUTPUTS
LAST INTERVAL
::;=>o
~~~
DWELL INTERVAL
o
~
ACTI~E
::;
GUAR INTERVALS (2)
f----t
DIAL 2
-:r:::
~
MEMORY
(EAROM>
CONTROL
LOGIC
DIAL 3
1 H, CLOCK
DIAL
*'en"
O·
CO
CO
4
INTERVAL
t\:) I
-.;j
-1
~
OFFSET 1
BUFFERS
o.w
MODE SWITCH
FREE
LOAD DWELL
SYNC PULSE
1-__{,,-3;..'~
L_......:=::..::..~
2
CARD
NO.
NAME
1
DISPLAY
2
3
4
MEMORY
CONTROL
PREEMPT
OUTPUT
115 VAC
00
LINE)
MANUAL
KEY
5
CKT
(2)
--<
er-
-a-
+24VDC
+24
(3)
FROM PROGRAMMER
+ 5
10 Hz CLOCK
1 Hz CLOCK
OUTPUT
COUNT
DOWN CKT
(2)
INDICATES NUMBER OF WIRES
Figure 2-3.
SUPPLY
OFF
~115
ON
VAC
vae
vae
DISPLAY
r
60 Hz
GND
CONNECTION FROM ANOTHER PLACE
(3)
o
POWER
I
4
.......-J
LOGIC [ - - - - ,
CONNECTION TO ANOTHER PLACE ON PAGE
S4
~
vae
+12 VDC
+ 5
INPUT
I
+24 VQG
----;> TO PROGRAMMER
RESTART
(
UNREG. DC
NUMBER, ICARD 3) OR (2), INDICATES
CIRCUIT ON CARD SPECIFIED
(CARD 4>
¢
{CARD 3 AND 4}
CARD
0.
t;:~
ADVANCEi.ON
60 Hz
'---
MAN.S~
ti5
V>
START
o------~ RESTART
I ~~
SS
REMO~
OFFSET
LOGIC
ON LINE
~~
I
RESTART ________
~TART
~ ~b~SHING
uo
'"
--+I gg
I
10 Hz
CLOCK
DRIVER
~~
I
1 Hz CLOCK
I
,
,~
(CARD 21
CHASSIS GND
l"""
J
(
HMC-1000 Controller Detailed Block Diagram
I
,l,
rf7
CHASSIS
OGND
2.1.2
Memory Address Logic
The memory address logic determines what data is being retreived from
memory.
When the multiplexer calls for display data and no programmer is
connected to the HMC-1000, the data address is selected by the DISPLAY / .
PROGRAM switch.
When the switch is in INTERVAL, the interval counter
also helps select the memory address.
If the multiplexer calls for display
data and an HMCP-1000 programmer is connected, the display address is
selected by the DISPLAY /PROGRAM switch, except when this switch is in
the INTERVAL position, in which case the PGM ADR inputs select the interval address.
When a "parallel" programmer is connected, the DISPLAY /
PROGRAM switch is ignored during any programmer read/write functions
and the memory address is determined by the PGM ADR inputs.
During the load cycle part of the multiplex cycle, the cycle time memory
location is addressed by the address logic and during the load offset part of
the multiplex cycle, the offset memory location selected by the offset logic
is addressed.
During the load interval part of the multiplex cycle, the inter-
val counter determines memory address unless the control card commands
a load dwell which changes the address of the dwell time memory location.
Loading the counters only occur when the control logic commands the multiplexer to stop and go through the load counter sequence.
Only one counter at
a time is loaded one digit at a time (3 digits per counter).
2. 1. 3
Programmer Connections
Programming the EAROM is accomplished through the several interconnecting
wires to the programmer.
The data being programmed enters the memory via
the 4 bit DATA bus while the ROW WRITE lines select the EAROM row.
DIGIT STROBE, DISPLAY,
a~d
ROW SELECT outputs coordinate the timing
of the programmer and HMC-1000 while a WRITE command enables the write
2-8
46099
function in the EAROM.
EXTERNAL CLOCK inputs stop the
multipl~x
timing
logic when erasing memory and substitute a slower clock when writing mem0ry.
Writing memory requires more time than reading.
2.1.4
Time Display
When the display is not turned off, the display reads from memory the data
selected by the PROGRAM/DISPLAY switches to indicate the contents of
memory.
The display contains a 4 bit latch for each digit and these 4 bit
latches are loaded one digit at a time just like the counters.
When the display
is turned off, the multiplexer does not read data from memory for the display.
2.1.5
Offset Logic
The offset logic determines which offset time is loaded into the offset timer
when the HMC-1000 is in the remote mode and generates the synchronization
pulse that causes the offset timer to start.
The three offset inputs are first
buffered and filtered and then latched in a memory to store the offset that was
last called.
The last called offset is displayed by the OFFSET display.
A
sync pulse is generated every time all offset inputs are false (pulled up to
24 volts).
2.1.6
Manual, On Line, Stop Time Inputs
Inputs to the HMC-1000 are buffered by CMOS buffers.
The buffers have the
function of converting the 24 volt logic at the input to 12 volt logic for internal
use and the buffers also provide filtering or time delays to reject noise spikes
that may be applied to the inputs.
2-9
46099
"
2.1.7
Cycle, Offset and Interval Timers
The HMC-1000 contains one counter to time intervals and dwell.
has a range of
a to 99.9
seconds in O. 1 second increments.
This counter
Two other
counters, the cycle time and offset time counters are used in the remote mode
to obtain synchronized operation.
The cycle time counter is used to accept
synchronized pulses that occur only at intervals of one cycle.
When offset
interpreters are used in some electromechanical systems, extra synchronized
pulses between the periodic cycle time synchronized pulses are transmitted
on the interconnect system.
These pulses, used to shorten the dwell time
when an electromechanical controller is coming into synchronizat ion, do not
have the same period as the cycle time and hence are ignored by the
HMC-1000.
The offset time counter is used to "delay" the synchronized pulse
to a later time in the cycle.
When a synchronized pulse is received and
accepted, the offset time counter is loaded and started.
When it times out,
its output is used by the control logic to determine if the HMC-1000 should
dwell in the dwell interval or not.
If the offset time counter times out within
O. 5 second of the interval being changed to the dwell interval, the HMC-1000
does not dwell.
If it times out more than O. 5 second before the dwell interval
has started, the HMC-1000 will dwell.
If the counter times out while the
HMC-1000 is dwelling, the HMC-1000 will immediately stop dwelling and
start timing the interval.
range of
a to
The offset time and cycle time counters have a
999 seconds in one second intervals.
This is accomplished by a
fourth stage counter between the 10 Hz clock and the other three counter
stages.
The fourth stage is always preset to zero whenever the counter is
loaded.
2.1.8
Control Logic
The control logic tells the memory multiplexer when to load the three counters,
tells the interval counter to count or reset, operates the CLOCK and STOP
2-10
46099
,.
TIME displays, and determines what mode the HMC-1000 is operating in.
The
mode is selected by the mode switch, manual input, on line input and stop time
input.
2.1.8.1 Stop Time (Man Sync) Mode -- The Stop Time mode, stops the
counters by turning off the 10 Hz clock, illuminates the STOP TIME display,
and turns off the CLOCK display.
The stop time mode is selected by ground-
ing the Stop Time input or by putting the mode switch in the MAN SYNC
position.
2.1. 8.2 Manual Mode -- The Manual mode stops the 10Hz clock, extinguishes
the CLOCK display during intervals that are not programed as guaranteed,
and enables the Manual Advance input.
On intervals that are not guaranteed,
the Interval Counter is advanced once each time the Manual Advance input is
grounded.
On guaranteed intervals the interval/ dwell timer is loaded and the
10Hz clock is enabled to time the interval.
If the interval is guaranteed with
automatic advance, the manual advance input is ignored and the interval
counter is advanced when the interval/ dwell timer times out.
If the interval
is guaranteed with manual advance, the interval counter is advanced when the
interval/ dwell timer times out, and if the manual advance input has been or
is grounded.
The manual mode is entered by grounding the manual input.
2. 1. 8. 3 On Line Mode - - The On Line mode is the same as the Manual mode
except it is enabled by the on line input and the interval counter is advanced
by the advance input.
If the Manual and the On Line inputs are grounded at
the same time, the Manual mode takes priority.
2. 1. 8.4 Free Mode - - In the Free mode, the interval/ dwe 11 timer is loaded
from memory each time the interval counter is advanced.
The interval
counter is advanced every time the interval/ dwell timer times out.
The
interval counter is reset to Interval 1 when the last interval has been timed.
The CLOCK display
flash~s
once per second during this mode.
is enabled by having the MODE switch in the FREE position.
2-11
46099
,
The Free mode
2. 1. 8.5 Remote Mode - - The HMC-1000 is in the Remote mode when the
mode switch is in the REMOTE position and synchronized pulses are being
received by the HMC-1000.
The interval counter is advanced once each time
the interval/ dwell timer times out.. in the Free mode.
When a synchronization pulse is received the cycle time and offset time
counters are loaded with the cycle and offset times respectively.
Loading
occurs only if the cycle time counter has timed out to permit operation with
offset interrupters.
If the interval counter reaches the dwell interval and the
offset time counter has not timed out in the last 0.5 second, the interval/ dwell
timer is loaded with the dwell time, a dwell flip- flop in the control logic is
set and the CLOCK display is extinguished.
The HMC-1000 then" dwells"
until the offset time counter times out or the interval/ dwell timer times out.
At the end of dwell the interval/ dwell timer is loaded with the interval time
and the interval counter is not advanced.
The cycle time is thus extended in
the dwell interval within 0.5 second after the offset time counter has timed
out.
If no synchronization pulses are received, the effective mode is free.
2.1.9
PROM
The programmable read only memory (PROM) stores the state of each output
(On, Off, Flash) and the state of the 8 control functions.
The PROM contains
5 chips capable of storing the state for 8 wires or bits each for all 16 intervals".
The control functions are:
•
Last interval
•
Dwell interval
•
Transfer dial allow
•
Guaranteed interval with manual advance required
2-12
46099
.
•
Guaranteed interval with automatic advance
•
Three special functions (not used)
2. 1. 10
Interval Display
The interval is displayed on a seven segment readout.
Logic changes the
four wire output from the interval counter to two digits.
When a programmer
is connected, the interval displayed can be the interval being programmed.
2.1.11
Power Supply, Restart and Countdown Circuit
The power supply regulates 24 V dc, 12 V dc and 5 V dc for use by the
HMC-1000, the HMCP-1000 programmer and for external cabinet circuitry.
A countdown circuit divides the 60 Hz line frequency by 6 and 60 to generate
10Hz for the timers and 1Hz for the flash indication.
A restart circuit
senses loss of 60 Hz power and resets the interval counter, offset logic, dial
select logic, control logic and timers at the appropriate times.
On external
input it allows the same restart option.
2. 2 CONTROLLER SUBASSEMBLIES
~.
2.1
Mother Board and Programmer Input/ Output Board
All electronic components within the HMC-1000 Controller are mounted on
five printed circuit cards and one subassembly (Figure 2-4), these include:
•
Display card
•
Memory card
•
Control card
2-13
46099
.
OUTPUT CARD
PREEMPT CARD
CONTROL CARD
MEMORY CARD
DISPLAY CARD
MOTH ER BOARD
• PROGRAMMER
I/O BOARD
24V SHUT-OFF.?
BOARD
IBBON
ONNECTORS
POWER SUPPLY
SUBASSEMBLY
Figure 2-4.
HMC-IOOO Controllerl Cover
Removed to show Interior
Elements
2-14
46099
(4)
•
Preempt card
•
Output card
•
Power supply subassembly.
The cards are interconnected to a mother board by card connectors and the
power supply is connected to the mother board with plug-type connectors.
Four Ribbon type cables connect the mother board to the programmer/inputoutput board.
This board has the programmer connector, input-output con-
nector, and three rotary switches mounted on it and the components for the
noise filtering circuits.
The interconnect diagram (see Appendix A, drawing
number 28020881) shows all interconnection wiring between cards, switches
and connectors.
The fuse, power on-off switch and mode switch are con-
nected by wire to the programmer/input-output card.
2.2.2
Display Card (Figure 2-5)
The Display card contains the INTERVAL and TIME 1 SEC seven-segment
readouts; the DIAL, OFFSET, CLOCK and STOP TIMING LED's; a portion of
the memory address logic; and the interval display logic.
Referring to the
schematic (28020681-001) in Appendix A: U7, 11 and 14, the time display
chips, contain a 4 bit latch, seven- segment decoder, segment drivers, sevensegment LED readout and decimal point circuitry needed to display the time.
Data to the time display chips comes from the memory at a CMOS Level
(12 volts high), via the DO, D1, D2, D3 inputs.
level to TTL levels.
Buffers convert the CMOS
The strobes, Sl, S2, S3, coming from the memory card
are also CMOS and are buffered to the TTL leveL
When data is to be entered
into the displays, data is first set up on the data lines and then the appropriate
strobe line is pulled low to enter the data into the display's latch.
U16 pin 3,
.
determines if the decimal point is turned on, based on the DISPLAY /PROGRAM
switch position.
The decimal point is turned on only for interval and dwell
times.
2-15
46099
~;
2-16
46099
U1 and U2 display the interval.
The four interval lines, coded as shown in
Figure 2-6, are converted to decimal number by U15, a binary adder, and
associated logic, U16.
8
INTERVAL BITS
4
2
1
INTERVAL
DISPLAYED
0
1
1
2
0
0
0
0
1
1
0
1
3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
5
6
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
9
I
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
------
4
----
7
8
- - - - ----- ------
--
1
--
10
11
12
--13
14
15
16
=+ 5 VOLTS, 0 = 0 VOLTS <TTL LEVEl)
Figure 2-6.
Interval Coding
The LED displays, CR5 through CR13, are buffered by appropriate buffers.
Data selector chips U6, U12 and U 18 form a portion of the memory address
logic.
When no programmer is connected, U6 selects the interval address to
be displayed.
When the DISPLAY /PROGRAM switch is in the IN1;:ERVAL
position, U 12 and U18 select the display address to be the same as the interval.
In the other switch positions, the display address is coded by diodes
CR1, CR2, CR3, and CR4 and selected by U 12. to an appropriate code for
CYCLE, DWELL,
OFFS~T
1, OFFSET 2, and OFFSET 3.
When a "serial" programmer (such as the HMC P-1 000) is connected, the
interval is switched by U6 to the programmer address inputs.
When the
DISPLAY /PROGRAM. switch is in the INTERVAL position the display address
becomes the same as the programm.er inputs.
When a "parallel" programmer
is connected, the display address becomes the same as the programmer address via U18 when the programmer writes data to memory.
2.2. 3
Memory Card (Figure 2-7)
The Memory card contains the EAROM memory, memory addressing logic,
buffers to and from the memory, the LSI chip, restart circuit, and high frequency clock.
The LSI contains the 60Hz to 10Hz and 1Hz countdown circuit
7
three counter/timers, memory address logic, and multiplex timer logic.
Figure 2-8 shows how the memory is addressed for the various types of data
stored in EAROM.
U4, U11, U12 and logic on the display card addresses the
LSI chip (U15) inputs 14, 13, 12, 11 and lO.
The LSI chip then generates a new
multiplexed address that is presented to the column memory address inputs
A4, A3, A2, A1, A'/J and row select logic input A.
states, one for each digit, as shown in Figure 2-8.
The new address has three
In addition, one row at a
time is selected by U14 depending on which dial is selected by card inputs B
and C and the state of A.
Figure 2-8 indicates that Row 1 (Rl) or Row 2 (R2)
is selected for dial 1 depending on the present state of A.
selected for dial 2, etc.
R3 or R4 is
The D input to Ul4 turns on a row only when the
memory is being accessed.
Transistor buffers between the LSI chip and the
EAROM convert the open drain LSI outputs to the 24 volt level for the EAROM.
In addition transistor buffers between the LSI chip, U15, and the .TTL decoder,
U 14, convert the open drain outputs to TTL logic levels.
U14 is capable of
driving the Row inputs through a resistive divider network.
Note that Figure
2-8 contains a list of the various volt levels at the inputs and outputs to the
LSI and the address and r.ow inputs to the EAROM.
Data from the memory is
buffered to the CMOS logic levels for use by the display and LSI.
2-18
46099
2-19
46099
.
LSI INPUT
14
13
12
11
10
A4
A3
A2
Al
AO
RO=A
a
13
12
11
10
a
13
13
11
10
a
a
1 1 11
,
111
10
1
11
10
1
a
a
1
11
10
1
1
X
X
1
1
1
1 -
1
X
1
1
1
X
1
1
!<
1
X
X
1
X
1
X
DATA TYPE
DIG IT
NOTES
INTERVAL
1 LSD
13, 12, 11, 10 SELECTED
AS DESIRED INTERVAL
2
1
a
11
10
1
1
11
10
1
a
11
10
1
a
1
1
a
a
1
1
1
1
a
1
3 MSD
DEFINED BY
11 AND 10
1
ROW SELECT
D
C
B
A=RO
ACTIVE
ROW PIN
1
X
X
X
NONE
X
a
a
a
a
a
a
a
Rl
R2
1
1
1
1
a
R3
R4
2
2
1
1
a
a
a
R5
R6
3
3
1
1
x=
1
1
1
1
a
1
R7
R8
2
DWELL
2
1
3 MSD
LOGIC 1
+12 VOLTS
+0.5 VOLTS
MEMORY ADDRESS IN
ROW PIN (READ)
ROW PIN (WRITE)
ROW SELECT <TTL>
Figure 2-8.
11
10
DATA TYPE
a
a
a
OFFSET 1
1
OFFSET 2
1
a
OFFSET 3
1
1
CYCLE
LOGIC LEVEL DEFINITIONS
4
4
DON'T CARE
11 AND 10 SELECTED AS
SHOWN BELOW
1 LSD
DIAL
a
a
a
a
a
a
a
a
1
1 LSD
3 MSD
•
~
CDO
0
11
O')r-:l
o·
CCJr-:l
1
a a
a a
a a
1
1
,
LSI OUTPUT
MEMORY ADDRESS
a
a
a VOLTS
a VOLTS
LOGIC
VOLTS
24 VOLTS
+12 VOLTS
24 VOLTS
a
VOLTS
24 VOLTS
+ 5
VOLTS
a VOLTS
HMC-1000 Controller Memory Map
A clock formed by V8 pin 11, V9 pin 10, C6, R12, and R13 drives the multiplexer logic in the LSI chip.
Timing signals TO, and T1, from the chip are
used to coordinate memory addressing, and display functions with the multiplexer.
According to Figure 2-9, when T1=0 and TO=O, the multiplexer
cycle is in the display/program mode.
If MAO input is grounded (DISPLAY I
PROGRAM switch not in OFF position), the LSI will generate three strobe
outputs, one for each digit, and the address logic will address the memory
rows and column to read the data selected by the DISPLAY / PROGRAM
switches.
time mode.
When T1=0 and TO=l, the multiplexer cycle is in the load offset
If MAl is not grounded, the multiplexer goes on to the next part
of the cycle without loading any counters.
If MAl is grounded, the offset
counters is loaded with the selected offset time.
In the same way the other
two counters may be loaded during other parts of the multiplexer cycle.
Address logic on the memory card is used to multiplex the address during the
various portions of the multiplexer cycle.
V13 decodes T1 and TO to four
outputs, one for each part of the multiplexer cycle.
When T1 and TO are 0,
then the 2YO output, pin 9 of V13, is low causing V 12 to select the display
address to address the memory via the LSI chip.
plex cycle, V12 selects the output of V11.
On other parts of the multi-
When T1=1 and TO=O, V13 causes
V 11 to select the interval input from the interval counter or the load dwell
input for loading dwell times into the interval/dwell timer.
On the remaining
tw;,o parts of the multiplex cycle V11 selects the offset/ cycle address logic.
The 14 input to the LSI chip is handled separately by individual gates in a
similar logical combination manner.
Figure 2-10 shows some typical waveforms found on the memory card for the
switch positions and other conditions shown.
Note that when the display is
turned on, the waveform repeats once each multiplexer cycle and an oscilloscope can be triggered on the' display line V13-pin9, or memory card pin 44
(negative going pulse).
the scope.
The waveform will then be displayed repeatedly on
When the display is off or it is desired to look at the waveforms
2-21
46099
Tl
~
(J)t\:)
TO
EAROM DATA LOADED
TO (FROM)
LSI FUNCTION
LOGIC 0 AT
THIS LSI
INPUT ACTIVATES
FUNCTION
MEMORY ADDRESS
DATA TYPE
0
0
DISPLAY (PROGRAMMER)
STROBE Sl, S2, S3
MAO
SELECTED BY DISPLAY/
PROGRAMMER SWITCH
AND/OR PROGRAMMER
DISPLAY/
PROGRAM
SWITCH
~O
1
OFFSET TIME COUNTER
LOAD COUNTER
C10
MAl
SET TO OFFSET SELECTED
BY OFFSET LOGIC
1
0
INTERVAL/DWELL
TIME COUNTER
LOAD COUNTER
C20
MA2
SET TO INTERVAL SELECTED
BY INTERVAL COUNTER OR
TO DWELL DURING LOAD DWELL
ACTIVE
DIAL
SWITCH
(MAY BE
REMOTE
INPUTS)
1
1
CYCLE TIME COUNTER
LOAD COUNTER
C30
MA3
SET TO CYCLE ADDRESS
o •
CO~
COt\:)
LOGIC 0
= 0 VOLTS
LOGIC 1
= 12 VOLTS
TYPICAL WAVEFORM. NO FUNCTIONS ACTIVE (MAO
=MAl::::
MA2
=MA3 = 12 VOLTS =LOGIC 1)
12V
-
TO (LSI PIN 28)
Tl (LSI PIN 27)
,
DIAL (ROWS)
SELECTED
BY
-,
~
I.-
I
25
L-
OV
12V
OV
± 10 MICROSECONDS
Figure 2-9.
Multiplexer Functions
!
CHIP
PIN
rDIGIT 1
I
DIGIT 2
--r
DIGIT 3 - ,
12Y CLOCK
TO
12~
=- -....r- ~
10
ILll.....-
± 5"S
0Tl
5Y DISPLAY
0-
I
I
24V -
U
0-
-U
24V _
Q3
12V -
"
STROBE
DIGIT 1
0-
I
U
U
I
12vS2
0-
U
U
STROBE
DIGIT 2
0-
SV-
DIAL 1
29
2B
12V -
UIS
COt-.:>
CO""
12V-
A
012V-
14
012V -
13
STROBE
DIGIT 3
I
DISPLAY
UI0
20
UI0
21
U1S
35
U1S
34
U
U
--------_o.+I....
012V-
11
0-
24V _
IQ
0_
24V -
A4
,.
CYCLE ADDRESS
0-
DIAL 2--!
024V -
Al
024V -
AQ
0-
l
I
u:I
1~",lg
______---JIL-
24VA2
~
--------,U
I
I
0_
I-- DIGIT 1
I
-+--
DIGIT 2
--I--
0
-
_
I
DIGIT
U
U
,------U
U
'
·1
,3
3--1
Sl
NO STROBES (DISPLAY OFF>
o -
-----------------------------S2
o -
U1S
33
U14
12
U14
13
U14
14
U14
15
o
S3
u
SV
=============~IL~
24VA3
•
012v -
12
2~V
U
U
12V
I
I
------I.
Tl
U13
12V
S:::::l
0) t-.:>
o'
TO
27
0~
o -
12v _
12V
I.
::= t-I.--U
L
I
12v-
S3
~
I
0-
Ql
Sl
IL
12~::::l
U15
UIS
U-
~
_________--In__
o
SV
~V
DIAL 4
o _
:-
I
IL
I
o _----1
_
ULr
1~-
Uls
14
8
o
12V 12V-
_=I
0
12 V=
U
Uls
UIS
U1S
UI0
15
UIO
14
UI0
13
UI0
12
UI0
11
~l:-:=:11
I L
--,u
r-
12
11
"- ill 1-"'"""''' ---lill·111 "
DISPLAY/PROGRAM SWITCHES,
ACTIVE DIAL SWITCH:
OTHER CONDITIONS,
ACTIVE, OFF
DIAL 4
OFFSET 3, INTERVAL 8. LOAO DWELL COMMANOEO
DISPLAY/PROGRAM SWITCHES, DIAL 1, CYCLE
ACTIVE DIAL SWITCH, DIAL 2
OTHER CONDITIONS, OFFSET 1, INTERVAL b
Figure 2-10.
u
----------------------
12V-
Uls
u
Example Waveforms on Memory Card
for loading the counters, the waveform will occur only once per counter load
and therefore it is desirable to have a memory scope and trigger the scope on
MAl, MA2, MA3 inputs (negative going pulse) U15 pin 23, 24, 25 or card pin
26, 28, 30 respectively.
To make these signals occur more often, program
the interval times to be O. 1 sec or program most of the intervals to be 0
seconds.
Also program the cycle time short and the offset times to 0 sec.
Generate offset sync pulses every 0.3 seconds of greater to make the offset
counter load often.
For this type of trouble shooting it is advisable to have a
storage or memory scopes (2 channels desirable),
The clock is derived from the 60 Hz signal.
A 60 Hz output from the power
supply is buffered by a programmable unijunction transistor, Q10, and an RC
network to provide filtering, level detection and hysteresis.
The 60 Hz is
then counted down to 10Hz and 1Hz by the LSI, both of which are available for
use by other circuitry.
The 60Hz signal is also used to generate a restart signal.
If no power is ap-
plied to the HMC-1000, U8 pin 4 goes high upon applying 115 Vac for a period
determined by C8 and R14.
If power fails, the reset pulse will not be initiated
until C8 discharges through R14 and R16 enough to go below the U8 threshold.
A second input to U8, filtered by C7 and R15, is used as an external restart.
2.2.4
Control Card (Figure 2-11)
The Control card contains the dial select logic, the offset select logic, most
of the control logic, and the interval counter.
The buffered remote dial inputs
from the preempt card are applied to the remote dial priority logic, U16 pin
10, U20-11, U17-10, U17-11, U21-4, and U21-12, to select only one dial when
more than one remote input is grounded.
U6 is a 4 bit latch whose 'output is
the same as the input when the transfer allow bit is low and whose output is
the stored dial information when the transfer allow bit is high.
U7 selects
the active dial when the ACTIVE DIAL switch is in position's 1 through 4 and
2-24
46099
,.
o
~
+>
s::
o
U
2-25
46099
"
selects U6 output when the switch is in the REMOTE position.
display cause the active dial to be displayed.
address.
Wires to the
US selects the dial for memory
When the DISPLAY /PROGRAM switch is in the ACTIVE position,
US selects the active dial all the time.
When the switch is in position's 1
through 4, US selects the display dial when the multiplexer is calling for a
display function and the active dial during the rest of the cycle.
U2 pin 6 and
U2 -S encode the 4 wire, one at a time logic, to a 2 wire binary code (B and
C row select lines) for the memory address.
The synchronized and offset inputs from the preempt card are applied to the
synchronization logic, U10, Ul and Ul1.
When a synchronized pulse is gen-
erated flip- flops U 10 sample the offset 2 and 3 lines and store the present
offset condition.
U11 decodes the stored offset to a one at a time 3 wire for-
mat for use by memory address logic and the offset display.
On power up
reset, U 10 is set to offset 1.
The interval counter, U9 (pins 3, 4, 5, 6), is controlled by U11 (pin 12) and
associated U16 gates.
The counter is reset on power up and whenever an
advance signal is generated by the control logic and the last interval input is
low.
If it is not the last interval, a clock pulse advances the counter one
count at a time.
U lS-11, prevents the interval counter from advancing if the
controller is presently dwelling.
Buffers in U5 and U3, convert the CMOS
levels at the U9 outputs to TTL levels to drive the TTL gates that require
interval information.
The control logic outputs the advance interval, load interval timer command,
load offset timer command, load cycle timer command and load dwell command.
The load interval timer and advance interval command is generated
by flip-flop U13-13 based on the advance logic formed by U19, U1S-10,
U15-9, is combined by U14-13, and is synchronized to the multiplexer by the
counter 2 input.
Whenever one of the following conditions occur, a load in-
terval command is generated:
2-26
46099
"
1)
If single step mode is 0 volts (U19-8)
1A) Interval timer times out (U18-8) at 12V)
or 1B) End of dwell (offset timer times out (U18-9 at 12V)
2)
If single step mode is 12 volts (U19-8)
2A) Guaranteed manual advance, automatic manual advance
and single step advance at OV, (U15-8, U15-1, U15-2
at OV).
or 2B) Interval timer times out (U 18 -8 at 12V) and guaranteed
manual advance bit set (U 19-1 at 12V).
or 2C) Interval timer times out (U18-8 at 12V) and single step
advance step (U19-12 at 0 volts).
Figure 2-12 shows the waveforms that occur each time the interval timer
times out.
U13 pin 1 generates a load offset time and load background time every time a
synchronization pulse is received, providing the background timer C30 has
timed out.
The two flip- flops, U22, detect whether synchronization is present by sampling for two consecutive cycles.
U22-13 is set every time a synchronization
pulse is received, and the fact that the synchronization pulse was received
causes U22-2 to shift at the end of the dwell interval.
If synchronization
should fail, the logic directs the HMC-1000 to go to the Free mode.
The out-
put at U17 pin 4 determines whether dwell should be timed when the interval
counter comes around to the dwell interval.
U17-4 is 0 volts, dwell inhibited,
if there is no synchronization (U15-5 at 12V), in the Manual or On Line mode
(U15-4 at 12V), in the Stop Timing (Man Sync) mode (U15-3 at 14V), in the
Free mode (U20-6 at OV), or if the offset timer has timed out in the last 0.5
second (U17-5 at 12V).
If any of these conditions do not exist when the dwell
interval comes around, U12-1 goes to 12V to command a loading of a dwell
time.
When a dwell time is loaded, the dwell flip-flop U12-13 is set so that
2-27
46099
.
CHIP
PIN
U20
1
U13
8
U18
U13
U13
8
9
13
+12V
COUNTER 2
-0
-12V
U
I
U
f\
f\
~
°
12V
C20 COUNTER
0
12V
0_
12V
~NOTE
~
I--- NOT E 1 ---....
LOAD INTERVAL TIMER
0_
I
4
USE 10M, LOW
CAPACI TANCE
PROBE
I
~
I
INTERVAL COUNTER ADVANCES.
DISPLAY/PROGRAM SWITCH: NOT OFF
OTHER CONDITIONS: INTERVAL TIME TIMES OUT
NOTE 1. THE EDGES SHOWN MAY OCCUR ANY TIME BETWEEN THE LIMITS SHOWN.
Figure 2-12.
Typical Control Card Waveforms, Interval Time Out
CHIP
PIN
U20
1
COUNTER 2
0_
U18
8
C20
-+12
U
U
12V-
U13
13
U18
1
U12
5
U12
1
U12
13
I
012V
LOAD INTERVAL TIMER
0_
b
12V
DWELL INTERVAL
0_
12V
ENABLE DWELL
0_
12VLOAD DWELL
0_
I
'-----INTERVAL COUNTER ADVANCES
12VDWELL
0_
DISPLAY/PROGRAM SWITCH: NOT OFF
OTHER CONDITIONS: INTERVAL TIMES OUT, DWELL REQUIRED
(HMC-I000 NOT IN SYNC).
Figure 2-13.
Typical Control Card Waveforms, Dwell Started
1'.
2-28
46099
"
U 12-13 is 12V.
U12 is reset when the dwell time ends, or if the offset timer
times out during dwell.
Figure 2-13 shows the typical waveform when a
dwell time is loaded into the interval counter.
The other half of counter U9 (output pin 13) is used to generate a 0.5 second
output every time the offset timer times out.
When C 10 goes to 12V the out-
put of U 17 goes to 12V for 0.5 second, preventing dwell, should the dwell
interval be started during the 0.5 second window.
This circuit is included to
allow for "jitter" in the synchronization pulse if the master controller is
electromechanical.
2.2.5
Preempt Card (Figure 2-14)
The Preempt card contains the buffers for all inputs and the control logic for
the manual advance and on line modes.
The buffers, made of CMOS non
inverting buffers, are used to provide level shifting from 24 volts to 12 volt
levels.
A pull up resistor pulls the inputs up to 24 volts until an external
switch grounds the point.
A resistor divider brings the voltage level at the
CMOS gate inputs to 12 volts.
A capacitor between the input and output of
the CMOS buffers provide noise filtering and AC hysteresis.
Note that a
synchronization pulse is generated every time an offset input is grounded.
The preempt board generates a stop timing command (U5 pin 6 at 12V) whenev.er one of the following conditions are true:
•
Manual synchronization is grounded
•
The stop time input is grounded
•
The on line input or the manual input is grounded and
both of the
guarante~d
interval inputs are at 0 volts.
2-29
46099
;.;:
2-30
46099
"
A single step mode command is generated (U6-4 at 12V) when the on line or
manual advance input is grounded.
When either the manual advance or on line input are grounded, the single step
advance is enabled.
The flip flop, V1, stores the fact that an advance was
commanded even though a advance has not yet occurred.
This happens when
an advance command is generated before a guaranteed interval has timed out.
The flip flop, U1, clock input is controlled by select logic U4-6, U4-9 and
U7-3.
When the on line input is grounded, grounding the advance input causes
the clock input to go high.
When the manual input is grounded, grounding the
manual advance input causes the clock input to go high.
When both on line and
manual advance are grounded, only the manual advance input causes the
clock input to go high.
Note that the flip flop is reset every time the interval
counter is advanced or power up is reset.
2.2.6
Output Card (Figure 2-15)
The output card contains PROMs and buffers for all outputs.
chip is organized as 32 eight bit words.
a time by a 5 wire binary code.
Each PROM
The 32 words are addressed one at
Four of the wires are connected to the inter-
val counter and one wire is connected to the 1Hz clock.
When the 1Hz clock
is high, one 8 bit word is addressed relating to the interval being addressed.
When the 1Hz clock is low, another 8 bit word is addressed.
ved there are two words programmed.
For each inter-
If a bit in the word is programmed as
a logic 0 or a logic 1 for both words, the output state for that bit will be a
steady off or on, respectively.
If a bit is programmed logic 0 in one word
and logic 1 in the other word, the output will turn on and off at the 1Hz clock
rate causing the flashing state.
2-31
46099
2-32
46099
..
For example. if for interval 5 (binary address 0100) the words are .programmed as follows:
tHz CLOCK
EIGHT BIT WORD
MSB
LSB
High
0001
1001
Low
1001
1001
all of the outputs will be steady on or off except the most significant bit
(MSB). which will flash.
The HPP-1000 Programmer automatically programs
PROMs for the selected state (On. Off. Flash).
There are five PROMs so that the output card can accommodate 40 circuits.
All of the circuits are buffered with open collector high voltage inventors
capable of driving load relays or other circuitry.
Note that 32 signal light
outputs are pulled up tp 24 volts with a pull up resistor and the 8 control outputs are pulled up to 12 volts.
The output card contains an auxiliary flashing bus circuit that supplies a 24
volt square wave at the 1Hz clock rate.
2.2.6.1 High Current Output Card -- The High Current Output card performs
the same function as the Output card except that the output current sink capability is increased.
This card operates in the same manner as the card
described in paragraph 2.2.6 except that no pull up resistors are included.
Note that when using the High Current Output card the 24 VDC supply limitations must be observed.
The 32 outputs available at the connector are the only outputs modified by
plugging the High Current Output card into the HMC-1000 instead of the normal Output card.
Unless otherwise specified. the HMC-1000 Controller is
supplied with the regulav, Output card.
2-33
46099
"
2.2.7
Power Supply
The Power Supply supplies all power to the HMC-1000 electronic circuitry,
24 volts for cabinet functions (including load relay drive) and 11 volts dc
unregulated to the HMCP-1000 Programmer.
Two transformers step the 115-volt ac 60 Hz down to lower voltage levels.
Both transformer outputs are rectified and filtered by a capacitor input filter.
(Before rectifying and filtering 30Vac p-p is supplied to the controllers
restart and clock circuits.) These filtered voltages are regulated by three
terminal integrated circuit regulators into 5 volts dc for the display card,
memory address logic, dial select logic, and output board; 24 volts dc for
the EAROM, and the input/ output circuits; and 12 volts dc for the CMOS control logic functions.
The filter capacitors are sized to store considerable energy.
When 60 Hz
power fails, the capacitors can supply enough energy to allow the power supply voltages to remain regulated for some time after power loss.
The 24 vdc
stays regulated for at least 1.5 seconds after power loss while the 12 vdc
stays regulated for at least 3 seconds after loss.
external load on the 24 volt supply.
Both times depend on the
The 5 volt supply remain regulated for
at least 75 milliseconds after power loss.
The interval counter and timers
ar.:e supplied by the 12 volt power supply, so for momentory power loss of
less than 1 second duration, interval and timing functions continue.
When
power returns the power up reset circuit will restart the controller in Interval
1 if the power failure was at least 0.75 ± 0.25 second long.
2-34
46099
I
I
I
I
A 24-volt shutoff circuit turns on the 24 volts dc to the memory, the, input/
output circuitry, and the external cabinet fun ctions, when either 60 Hz
power is present for at least 50 milliseconds or the restart signal is low.
The 24-volt shutoff circuit turns off the 24 volts dc when power has been
interrupted for O. 75 ± .25 seco:ld and the controller is being restarted in
interval 1. If a controller power failure occurs, the 24-volts the controller
supplies to the cabinet functions will also be interrupted. This causes the
cabinet's voltage monitor to switch the intersection to nashing operation.
This occurs within one second of power failure.
2-35
46099
APPENDIX A
I
SCHEMATICS, ASSEMBLY DRAWINGS AND PARTS LISTS
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REFERENCE
2802.1449
HMC.1000C
2802.08,8
HMC 1000
NEXT ASSY
Al'f'LICATIOH
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APPENDIX B
NCR 1105 EAROM OPERATION
MNOS TECHNOLOGY USED IN THE 1105 EAROM
The structure of a basic MNOS memory device is presented in Figure B-1.
The gate insulator of the alterable portion consists of a thin oxide layer
(approx. 30
A)
and a much thicker overlay of silicon-nitride.
The uniqueness
of the structure is that, with the application of sufficient gate voltage, positive
or negative charges can be made to tunnel through the very thin oxide layer.
When the tunneling voltage is removed, the charge trapped at the oxide-nitride
interface causes alternation of the device's threshold voltage.
Application of
a sufficiently high negative voltage results in the storage of a net positive
charge, shifting the threshold voltage in the negative direction (the "written"
state). Conversely, a sufficient positive voltage shifts the threshold voltage
in the positive direction (the "erased" state).
The split-gate structure, shown in Figure B-1, is used to prevent low drainsubstrate breakdown voltage in the written state and depletion mode operation
\
of the transistor in the erased state.
CIRCUIT OPERATION OF THE 1105 EAROM
The basic circuit configuration of the 1105 EAROM is presented in Figure B-2
and the pin configuration is shown in Figure B-3.
The circuit shown is dupli-
cated for each of the four parallel bits forming one word. Data is stored in
the four arrays of 8 x 64 MNOS memory transistors.
Each uses two transis-
tors per bit to provide a total of 256 words of 4 parallel bits each.
A bit is
stored in an MNOS transistor pair by first raising the threshold of both tranoistors to their positive limit (erasing) and then writing the left- or the right-hand
device negatively, depending on whether a logical 0 or 1 is to be stored.
B-1
46099
Figure B-1.
Cross Section
of a split- gate
MNOS Memory
Transistor
n - Substrate
.....t - - - -
Si
I
Column #1
Column #32
~
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o---:±::+--~:+------- - ---0......-4-_-+-
Figure B-2.
NCR 1105 EAROM
Basic Schematic
(1/ 4 chip, 2 56
bits)
D--+---+--+---+-- - ----- -- - 4 - - + - + - - - + -
o-+--+-+---+-- --- - - - - - 4 - - 4 - 4 - - 4 D--+-.....--+-+-.....--+-- - - - - - - -
-4--0......-4--4_--+-
Voo
Voo
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32
VOO
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1
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Memory FET
VSS
CS
Top View
vSS
Figure B- 3.
Pin Configuration
24 a-----ov Data In/Out 4
Data In/Out 1
Data In/Out 2
cs
23 r - - v
22 r-----'v
o--~
21 r - - - ' J 1/13
20 r - - - v 1>.
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46099
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10
15 r - - v
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11
12
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13 t - - - ( )
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R
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7
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3
A2
•
Column
Addresses
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In both writing and reading, a particular word is accessed by selecting one of
the eight rows and one of the 32 memory array columns.
The row and column
selection is identical and parallel for each of the four bits of a word.
Erasure is accomplished by applying a +30 v. pulse of 100 ms duration to the
eight row lines either simultaneously or selectively.
Writing uses the channel shielding principle. The source of the left- or righthand transistor of a particular location is grounded by a flip-flop that is set
by input data.
A -24 v. pulse of 10 ms duration is applied to the proper row
line, and the threshold voltage of the transistor whose source is grounded is
written negatively.
Reading is accomplished by differentially sensing the threshold voltages of a
pair of MNOS transistors. As shown in Figure B-2, one common sensing
system, made up of the flip-flop and an input/output driver, is used for all
32 columns. A read cycle begins when a column is selected by means of the
column address circuits, and the two data lines are momentarily grounded
by
~
1.
A negative pulse is applied to one of the eight memory row lines.
The
two selected memory transistors, acting as source followers, drive first one
and then the other data line negative.
The flip-flop will set into one of its two
stable states, depending upon which of the two data lines falls negative first.
The sensitivity of the flip-flop detection system to small threshold differences
is. improved by slowing the negative-going edge of the row input pulse to a
O. 5 fJ,s fall time during reading.
The
~3
pulse increases the voltage difference
between the data lines and drives the input /output driver.
switches true or false depending on the stored data.
The data output
Several advantages result
from the sensing method employed: (1) The absolute level of threshold voltage
is relatively unimportant.
Only the difference voltage is sensed; 'variations
in device characteristics and circuit conditions have little effect on data storage.
(2) A difference of a few tenths of a volt is sufficient to set the flip-flop.
(3) The source and channel voltage of the transistor with the more positive
B-3
46099
threshold will follow the row input voltage.
Consequently, the field in the gate
insulator will be small, and degradation of the stored data resulting from application of the row input read pulse will be minimized.
J
B-4
46099
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Honeywell
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