The MOS Transistor
The Devices:
Polysilicon
Aluminum
MOS Transistor
Dynamics
[Adapted from Rabaey’s Digital Integrated Circuits , ©2002, J. Rabaey et al.]
EE415 VLSI Design
EE415 VLSI Design
Dynamic Behavior of MOS Transistor
•MOSFET is a majority carrier device
(unlike pn junction diode)
•Delays depend on the time to (dis)charge
the capacitances between MOS terminals
•Capacitances originate from three sources:
•basic MOS structure (layout)
•charge present in the channel
S
•depletion regions of the reverse-biased
pn-junctions of drain and source
•Capacitances are non-linear and vary with
the applied voltage
MOS Structure Capacitances
Gate Capacitance
•Gate isolated from channel by gate oxide
Cox = ε ox / t ox
G
CGS
CGD
D
CSB
CGB
CDB
•tox small as possible
•Results in gate capacitance Cg
Cg = CoxWL
B
EE415 VLSI Design
EE415 VLSI Design
The Gate Capacitance
Gate Capacitance
Gate Oxide
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Field-Oxide
(SiO 2)
p+ stopper
Bulk Contact
CROSS-SECTION of NMOS Transistor
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EE415 VLSI Design
1
The Gate Capacitance
Gate Capacitance depends on
•channel charge (non-linear)
•topology
The Gate Capacitance
Channel Capacitance
Overlap Capacitance
Capacitance due to topology
•Source and drain extend below the gate oxide by x d
(lateral diffusion)
•Effective length of the channel L eff is shorter than the
drawn length by factor of 2xd
•Cause of parasitic overlap capacitance, CgsO, between
gate and source (drain)
EE415 VLSI Design
EE415 VLSI Design
The Channel Capacitance
Channel Capacitance has three components
•capacitance between gate and source, C gs
•capacitance between gate and drain, Cgd
•capacitance between gate and bulk region, Cg b
The Channel Capacitance
Different distributions of gate capacitance for varying
operating conditions
Channel Capacitance values
•non-linear, depends on operating region
•averaged to simplify analysis
Most important regions in digital design: saturation and cut-off
EE415 VLSI Design
EE415 VLSI Design
Diffusion Capacitance
Capacitive Device Model
Bottom Plate Capacitance
G
Junction Depth
CG S = Cgs + CgsO
CG S
CGD = Cgd + CgdO
CGB = Cgb
CSB = CSdiff
CG D
D
S
CG B
CS B
CDB
CDB = CDdiff
B
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EE415 VLSI Design
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Transistor Capacitance Values
for 0.25µ
Example: For an NMOS with L = 0.24 µ m,
W = 0.36 µ m, LD = LS = 0.625 µ m
Review: Sources of
Capacitance
Vout
Vin
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
Vout2
CL
CGC = Cox WL = 0.52 fF
so Cgate _cap = Cox WL + 2Co W = 0.74 fF
Cbp = Cj LS W = 0.45 fF
so Cdiffusion_cap = 0.90 fF
Vin
Overlap capacitance
Cox
(fF/µm2)
Co
(fF/µm)
Cj
(fF/µm2)
mj
φb
(V)
Cjsw
(fF/µm)
mjsw
φbsw
(V)
NMOS
6
0.31
2
0.5
0.9
0.28
0.44
0.9
PMOS
6
0.27
1.9
0.48
0.9
0.22
0.32
0.9
M1 and M2 are either in cut -off or in saturation.
The floating gate-drain capacitor is replaced by a
capacitance-to-ground (gate-bulk capacitor).
∆V
CGD1
∆V
M3
CG3
Vin
∆V
We can simplify the diffusion capacitance calculations
even further by using a Keq to relate the linearized
capacitor to the value of the junction capacitance under
zero-bias
C eq = Keq C j 0
2C GB1
∆V
M1
M1
high-to-low
A capacitor experiencing identical but opposite voltage
swings at both its terminals can be replaced by a
capacitor to ground whose value is two times the
original value
EE415 VLSI Design
low-to-high
Keqbp
Keqsw
Keqbp
Keqsw
NMOS
0.57
0.61
0.79
0.81
PMOS
0.79
0.86
0.59
0.7
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Extrinsic (Fan-Out)
Capacitance
l
Vout2
Cw
Drain-Bulk Capacitance: Keq’s
(for 2.5 µm)
l
Vout
Vout
Vin
l
Vout
EE415 VLSI Design
Gate-Drain Capacitance: The
Miller Effect
l
M4
pdrain CD B 2
ndrain
CD B 1
M1
intrinsic MOS transistor capacitances
extrinsic MOS transistor ( fanout) capacitances
wiring (interconnect) capacitance
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l
CG4
M2
CGD12
Csw = Cjsw (2LS + W) = 0.45 fF
Layout of Two Chained Inverters
V DD
The extrinsic, or fan-out, capacitance is the total gate
capacitance of the loading gates M3 and M4.
PMOS
1.125/0.25
C fan-out = C gate (NMOS) + C gate (PMOS)
= (C GSOn+ C GDOn+ W nLnC ox) + (C GSOp+ C GDOp+ W pLpC ox )
1.2µm
=2λ
Out
In
Metal1
l
Simplification of the actual situation
» Assumes all the components of C gate are between Vout and
GND
(or VDD)
» Assumes the channel capacitances of the loading gates
are constant
EE415 VLSI Design
Polysilicon
0.125
0.5
NMOS
0.375/0.25
GND
W/L
AD (µ m2 )
PD (µ m)
AS (µ m2 )
PS (µ m)
NMOS
0.375/0.25
0.3
1.875
0.3
1.875
PMOS
1.125/0.25
0.7
2.375
0.7
2.375
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Components of CL (0.25 µm)
Expression
Value (fF) Value (fF)
H→ L
L→ H
0.23
0.23
The Sub-Micron MOS Transistor
•Actual transistor deviates substantially from model
C Term
CGD1
2 Con Wn
CGD2
2 Cop Wp
0.61
0.61
CDB1
KeqbpnAD nCj + KeqswnPD nCjsw
0.66
0.90
CDB2
KeqbppAD pCj + KeqswpPD pCjsw
1.5
1.15
CG3
(2 Con)Wn + Cox WnLn
0.76
0.76
•Influenced heavily by secondary effects
CG4
(2 Cop)Wp + Cox WpLp
2.28
2.28
•Latchup problems
Cw
from extraction
0.12
0.12
CL
∑
6.1
6.0
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•Channel length becomes comparable to other device
parameters. Ex: depth of drain and source junctions
•Referred to as a short-channel device
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The Sub-Micron MOS Transistor
Threshold Variations
Part of the region below gate is depleted by source and
drain fields, which reduce the threshold voltage for short
channel. Similar effect is caused by increase in Vds, so
threshold is smaller with larger Vds
Secondary Effects:
•Threshold Variations
VT
VT
•Parasitic Resistances
•Velocity Saturation and Mobility Degradation
Long-channel threshold
Low VD S threshold
•Sub-threshold Conduction
L
Threshold as a function of
the length (for lowVD S)
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Vds
Drain-induced barrier lowering
(for low L)
EE415 VLSI Design
Variations in I-V Characteristics
Parasitic Resistances
Polysilicon gate
Drain
contact
increase W
G
LD
D
RS
RS ,D
W
VG S ,eff
S
RD
L
= S ,D RS Q + RC
W
RSQ is the resistance per square
RC is the contact resistance
EE415 VLSI Design
Drain
the bulk region
•The velocity of the carriers is proportional to the electric field up to
a point. When electric field reaches a critical value, Esat , the velocity
saturates.
•When the channel length decreases, only a small VDS is needed for
saturation
•Causes a linear dependence of the saturation current wrt the gate
voltage (in contrast to squared dependence of long-channel device)
•Current drive cannot be increased by decreasing L
•Reduced L decreases the mobility of the carriers due to the vert ical
component of the electric field (decreases ID)
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Voltage-Current Relation:
Velocity Saturation
υ n (m/s)
Velocity Saturation
For short channel devices
l Linear: When VDS ≤ VGS – VT
υsat = 10 5
I D = κ (VDS) k’n W/L [(VGS – VT )VDS – VDS2/2]
Constant velocity
where
κ (V) = 1/(1 + (V/ ξcL)) is a measure of the degree of
velocity saturation
Constant mobility (slope = µ)
l
ξc = 1.5
ξ (V/µm)
EE415 VLSI Design
Velocity Saturation Effects
Velocity Saturation
1.5
Long
channel
devices
For short channel devices
and large enough VGS – VT
VDSAT < VGS – VT so
the device enters
saturation before VDS
reaches VGS – VT and
operates more often in
saturation
l
Short
channel
devices
0
VDSAT
VGS-VT
0.5
V GS = 5
1.0
V GS = 4
V GS = 3
0.5
V GS = 2
Linear D ependence
VGS = VDD
I D (mA )
10
V GS = 1
0.0
1.0
2.0
3.0
4.0
I D (mA )
EE415 VLSI Design
Saturation: When VDS = VDSAT ≥ VGS – VT
I DSat = κ (VDSAT) k’n W/L [(VGS – VT )VDSAT – VDSAT2/2]
0
0.0
5.0
VD S (V)
(a) I D as a function of VD S
I DSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control voltage
1.0
2.0
VGS (V)
3.0
(b) I D as a function of V GS
(for VDS = 5 V).
l
Sub-Threshold Conduction
The Slope Factor
Linear
q VGS
-4
ID ~ I0 e
10
-6
Quadratic
nkT
ID(A)
S is ∆V GS for ID2/ID1 =10
10
-10
Exponential
-12
VT
10
0
0.5
2.5
X 10-4
Early Velocity
Saturation
1
1.5
2
2.5
Typical values for S:
60 .. 100 mV/decade
VGS = 2.5V
2
VGS = 2.0V
1.5
Linear
1
V GS(V)
EE415 VLSI Design
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, V T = 0.4V
C
, n =1 + D
Cox
-8
10
Short Channel I-V Plot (NMOS)
ID (A)
-2
10
10
Linear Dependence on VGS
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Saturation
0.5
VGS = 1.5V
VGS = 1.0V
Linear dependence
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0
0
EE415 VLSI Design
0.5
1
1.5
2
2.5
VD S (V)
5
Sub-Threshold ID vs V GS
q VGS
qV

− DS
I D = I 0 e nkT  1 − e kT

Sub-Threshold ID vs VDS
qVGS
qV

− DS
I D = I 0 e nkT  1 − e kT






(1 + λ ⋅V DS )


VGS from 0 to 0.3V
VDS from 0 to 0.5V
EE415 VLSI Design
EE415 VLSI Design
ID versus VGS
-4
-4
x 10
x 10
2.5
-4
5
6
-4
x 10
VGS= 2.5 V
2
4
linear
quadratic
ID (A)
I D (A)
I D (A)
0.5
quadratic
0.5
1
1.5
2
2.5
VGS= 2.0 V
3
2
0
0
2
Resistive Saturation
4
1
1
0
0
0.5
VGS (V)
1
1.5
2
VDS = VGS - VT
2
VGS= 1.5 V
1
VGS= 1.0 V
0
VGS= 2.0 V
1.5
VGS= 1.5 V
1
VGS= 1.0 V
0.5
2.5
VGS(V)
Long Channel
VGS= 2.5 V
5
1.5
3
x 10
2.5
I D(A)
6
ID versus VDS
0
0.5
1
Short Channel
VDS(V)
1.5
2
2.5
0
0
0.5
Long Channel
EE415 VLSI Design
1
VDS(V)
1.5
2
2.5
Short Channel
EE415 VLSI Design
A unified model
for manual analysis
A PMOS Transistor
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
0
x 10
G
-0.2
S
D
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
ID (A)
-0.4
-4
B
-0.6
NMOS
VT0(V)
0.43
γ(V0.5 )
0.4
VDSAT(V)
0.63
k’(A/V2)
115 x 10-6
λ(V-1)
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
EE415 VLSI Design
VGS = -2.5V
-0.8
-1
-2.5
-2
EE415 VLSI Design
-1.5
-1
-0.5
0
VDS(V)
6
The Transistor as a Switch
The Transistor as a Switch
VGS ≥ V T
VGS ≥ VT
7
ID
S
VG S = VDD
D
Req (Ohm)
Ron
5
Resistance inversely
proportional to W/L (doubling W
halves Ron )
4
l
x10 5
6
Rmid
R0
V DS
VDD
EE415 VLSI Design
For VDD >>VT+VDSAT/2, Ron
independent of VDD
Once VDD approaches VT, Ron
increases dramatically
l
2
VDD (V)
0
0.5
1
1.5
2
1
1.5
2
2.5
NMOS(kΩ)
PMOS (kΩ)
35
115
19
55
15
38
13
31
Latchup
VD D
Strong Inversion VGS > VT
VD D
Rnwell
Weak Inversion (Sub-Threshold) VGS ≤ VT
p+
n+
EE415 VLSI Design
+
n
p+
n-well
p+
+
p-source
n
Rnwell
Rpsubs
n-source
p-substrate
» Exponential in V GS with linear VDS dependence
(a) Origin of latchup
Rpsubs
(b) Equivalent circuit
EE415 VLSI Design
Fitting level-1 model
to short channel characteristics
Region of
matching
ID
Ron (for W/L = 1)
For larger devices
divide Req by W/L
EE415 VLSI Design
» Linear (Resistive) VDS < V DSAT
» Saturated (Constant Current) VDS ≥ VDSAT
l
(for VGS = VDD ,
V D S = VDD →VDD /2)
2.5
VDD (V)
Summary of MOSFET
Operating Regions
l
D
3
1
VDD/ 2
l
Ron
S
Short-channel
I-V curve
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
VGS = 5 V
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Long-channel
approximation
VD S = 5 V
VDS
Level 4 (BSIM): Emperical - Simple and Popular
’
Select k and λ such that best matching is obtained @ Vg s= Vd s = VDD
Berkeley Short-Channel IGFET Model
EE415 VLSI Design
EE415 VLSI Design
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MAIN MOS SPICE PARAMETERS
EE415 VLSI Design
SPICE Parameters for Parasitics
EE415 VLSI Design
SPICE Transistors Parameters
Simple Model versus SPICE
-4
x 10
2.5
VDS=V DSAT
2
Velocity
Saturated
I D (A)
1.5
Linear
1
VD S A T=V GT
0.5
VDS=V G T
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
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EE415 VLSI Design
Process Variations
Technology Evolution
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the
impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage.
Variations in the dimensions of the devices, mainly resulting from the
limited resolution of the photolithographic process. This causes (W /L )
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.
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Impact of Device Variations
Future Perspectives
2.10
Del ay (n sec )
2.10
D el ay ( n sec)
1.90
1.90
1.70
1.70
1.50
1.10 1.20
1.30 1.40
1.50 1.60
L eff (in µ m)
1.50
–0.90
–0.80
–0.70
–0.60 –0.50
VTp (V)
25 nm FINFET MOS transistor
Delay of Adder circuit as a function of variations in L and VT
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EE415 VLSI Design
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