eGaN® FET DATASHEET
EPC8004
EPC8004 – Enhancement Mode Power Transistor
VDS , 40 V
RDS(on) , 110 m
ID , 2.7 A
New Product
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device
structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial as
well as those where on-state losses dominate.
Maximum Ratings
VDS
ID
VGS
TJ
TSTG
Drain-to-Source Voltage (Continuous)
40
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 125° C)
48
Continuous (TA = 25˚C, θJA = 87)
2.7
Pulsed (25˚C, TPulse = 300 µs)
7.5
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
Operating Temperature
-40 to 150
Storage Temperature
-40 to 150
PARAMETER
EPC8004 eGaN FETs are supplied only in
passivated die form with solder bars
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (LiDAR)
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
V
A
V
˚C
TEST CONDITIONS
MIN
40
TYP
MAX
UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 125 µA
IDSS
Drain Source Leakage
VGS = 0 V, VDS = 32 V, T = 25˚C
50
Gate-Source Forward Leakage
VGS = 5 V
100
500
Gate-Source Reverse Leakage
VGS = -4 V
50
100
1.4
2.5
V
110
mΩ
IGSS
V
100
VGS(TH)
Gate Threshold Voltage
RDS(ON)
Drain-Source On Resistance
VGS = 5 V, ID = 0.5 A
80
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
2.2
VGS = VGS, ID = 0.25 mA
0.8
µA
µA
V
Specifications are with substrate shorted to source where applicable.
Thermal Characteristics
TYP
UNIT
RθJC
Thermal Resistance, Junction to Case
8.2
˚C/W
RθJB
Thermal Resistance, Junction to Board
16
˚C/W
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
82
˚C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 1
eGaN® FET DATASHEET
EPC8004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45
52
23
34
1.3
UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
0.8
RG
Gate Resistance
0.34
QG
Total Gate Charge
370
QGS
Gate to Source Charge
QGD
Gate to Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
VGS = 0 V, VDS = 20 V
pF
Ω
450
120
VDS = 20 V, ID = 1 A
47
80
pC
95
VGS = 0 V, VDS = 20 V
940
630
0
Specifications are with substrate shorted to source where applicable.
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
8
8
VGS = 5
VGS = 4
VGS = 3
VGS = 2
7
5
4
3
5
4
3
2
2
1
1
0
0
0.5
1
1.5
2
2.5
V DS = 3 V
6
ID– Drain Current (A)
ID– Drain Current (A)
6
25˚C
125˚C
7
0
0.5
3
1
1.5
VDS– Drain-to-Source Voltage (V)
Figure 3: R DS(on) vs VGS for Various Drain Currents
400
350
ID= 0.5 A
300
ID= 1.5 A
ID= 1 A
ID= 2 A
250
200
150
100
50
0
2
2.5
3
3.5
4
2.5
3
3.5
4
4.5
5
VGS– Gate-to-Source Voltage (V)
RDS(on) – Drain-to-Source Resistance (mΩ)
Drain-to-Source Resistance (mΩ)
400
2
4.5
5
Figure 4: R DS(on) vs VGS for Various Temperatures
25˚C
125˚C
350
300
ID = 1 A
250
200
150
100
50
0
2
2.5
VGS– Gate-to-Source Voltage (V)
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
3
3.5
4
4.5
5
VGS– Gate-to-Source Voltage (V)
| PAGE 2
eGaN® FET DATASHEET
EPC8004
Figure 5A: Capacitance (Log Scale)
Figure 5: Capacitance (Linear Scale)
10
2
40
C – Capacitance (pF)
C – Capacitance (pF)
50
COSS = CGD + CSD
CISS = CGD + CGS
30
CRSS = CGD
20
101
100
COSS = CGD + CSD
CISS = CGD + CGS
10
CRSS = CGD
0
0
10
20
10-1
40
30
0
10
40
30
VDS– Drain-to-Source Voltage (V)
VDS– Drain-to-Source Voltage (V)
Figure 6: Gate Charge
Figure 7: Reverse Drain-Source Characteristics
5
8
ID= 1 A
VDS = 20 V
25˚C
125˚C
7
ISD– Source-to-Drain Current (A)
4
VG– Gate Voltage (V)
20
3
2
1
6
5
4
3
2
1
0
0
100
200
0
0
400
300
0.5
1
1.5
QG– Gate Charge (pC)
3
3.5
4
4.5
5
Figure 9: Normalized Threshold Voltage vs Temperature
1.8
ID= 1 A
VGS = 5 V
1.3
Normalized Threshold Voltage (V)
Normalized On-State Resistance – RDS(on)
2.5
VSD– Source-to-Drain Voltage (V)
Figure 8: Normalized On Resistance vs Temperature
1.6
2
1.4
1.2
1
ID = 0.25 mA
1.2
1.1
1
0.9
0.8
0.7
0.8
0
25
50
75
100
125
TJ– Junction Temperature (°C)
150
0.6
0
25
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
50
75
100
125
150
TJ– Junction Temperature (°C)
| PAGE 3
eGaN® FET DATASHEET
EPC8004
Figure 11: Smith Chart
Figure 10: Gate Current
1.4
1.0
1.4
1.2
3.
0.4
0.3
0.6
0
S11 – Gate Reflection
S22 – Drain Reflection
EPC8004
0.5
0.8
2.0
1.8
0.6
1.6
0.7
0.8
1
0.9
1.2
4.0
5.0
0.2
0.4
6.0
3 GHz
GHz
0.1
8.0
10
10
3.0
5.0
4.0
1.8
2.0
1.6
1.2
1.4
0.9
1.0
0.8
0.7
0.6
0.5
0.4
0.3
0
0.2
20
0.1
IG– Gate Current (mA)
S-Parameter Characteristics
VGSQ = 1.38 V, VDSQ = 20 V, IDQ = 0.50 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
25˚C
125˚C
20
0.2
0.1
8.0
10
6.0
0.2
5.0
RF Café
2002
0.3
0
6
3.
5
0.4
200 MHz
200
MHz
1.6
0.7
0.6
1.8
2.0
0.5
VGS– Gate-to-Source Voltage (V)
1.4
4
1.2
3
1.0
2
0.9
1
0.8
0
4.0
0
All measurements were done with substrate shortened to source.
Figure 13: Device Reflection
Figure 12: Gain Chart
45
Amplitude
[dB]
Gmax
1.6
40
1.4
35
1.2
30
1
25
0.8
20
0.6
15
0.4
10
0.2
5
0
0
-0.2
100
1000
Z DS
Z GS
Figure 14: Taper and Reference Plane details – Device Connection
Frequency (MHz)
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
[Ω]
200
2.00 – j8.07
15.27 – j6.36
500
1.74 – j2.18
10.78 – j7.01
1000
1.41 + j1.60
5.98 – j4.42
1200
1.30 + j3.20
4.52 – j3.07
1500
1.11 + j4.75
3.19 – j0.98
2000
0.84 + j8.32
2.14 + j3.07
2400
0.70 + j10.24
1.95 + j5.86
3000
0.65 + j14.17
2.17 + j10.24
S-Parameter Table - Download S-parameter files at www.epc-co.com
All dimensions in µm
914
1621
[Ω]
355
271
[MHz]
914
271
Drain (ZDS)
1621
Gate (ZGS)
1000
Frequency
Device Outline
Gate Circuit
Reference Plane
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149
Drain Circuit
Reference Plane
| PAGE 4
eGaN® FET DATASHEET
EPC8004
ZθJB Normalized Thermal Impedance
Figure 15: Transient Thermal Response Curves
1
0.1
Junction-to-Board
Duty Factors:
0.5
0.2
0.1
0.05
T
0.02
0.01 0.01
P DM
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
0.001
10-5
10-4
tp
10-3
10-2
10-1
1
tp– Rectangular Pulse Duration (s)
10
100
Junction-to-Case
ZθJC Normalized Thermal Impedance
1
Duty Factors:
0.5
0.1
0.2
0.1
0.05
T
P DM
0.02
0.01 0.01
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.001
10-6
10-5
tp
10-4
10-3
10-2
10-1
1
10
tp– Rectangular Pulse Duration (s)
Figure 16: Safe Operating Area
ID - Drain Current (A)
10
1
Pulse Width
100 ms
10 ms
Limited by RDS(on)
1 ms
100 µs
0.1
0.1
1
10
VDS – Drain Voltage (V)
100
TJ = Max Rated, TC = +25°C, Single Pulse
a
e
f
Gate Pad
bump is
under this
edge of die
Loaded Tape Feed Direction
g
c
YYYY
4mm pitch, 8mm wide tape on 7” reel
7” reel
d
b
ZZZZ
TAPE AND REEL CONFIGURATION
8004
Die is placed into pocket
bump side down
(face side down)
EPC8004 (Note 1)
Dimension (mm) target min
a
8
7.9
1.75 1.65
b
c (see note 2)
3.5 3.45
d
4
3.9
e
4
3.9
f (see note 2)
2
1.95
g
1.5
1.5
max
8.3
1.85
3.55
4.1
4.1
2.05
1.6
Die
orientation
dot
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 5
eGaN® FET DATASHEET
EPC8004
DIE MARKINGS
8004
YYYY
ZZZZ
Die orientation dot
Laser Markings
Part
Number
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
8004
YYYY
ZZZZ
EPC8004
Gate Pad bump is
under this edge of die
DIE OUTLINE
Solder Bar View
A
d
e
e
1
i
X2
f
5
2
j
C
B
3
Dim
4
g
x2
6
h
i
All dimensions in µm
815 Max
(685)
RECOMMENDED
LAND PATTERN
600
225
2080
B
820
850
880
C
555
580
605
D
400
400
400
E
600
600
600
F
200
225
250
G
175
200
225
H
425
450
475
I
175
200
225
J
400
400
400
6
2
400
560
850
180
X2
600
4
180
x2
2050
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
2050
1
Max
2020
100 +/- 20
SEATING PLANE
400
Nominal
A
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
Side View
(units in µm)
Micrometers
Min
3
5
430
180
The land pattern is solder mask defined.
Solder mask opening is 10 µm smaller per side than bump.
Additional assembly resources available at:
http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
All dimensions in µm
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
Information subject to
change without notice.
Revised June, 2015
| PAGE 6