UNIVERSITY OF CALIFORNIA
Department of Electrical Engineering and Computer Sciences
CS150 Fall 2001
Prof. Subramanian
Homework #7
Due: Friday, November 16, 2001
1. A comparator with cascaded inputs uses the result of a comparison of lower order bits
along with the higher order bits and determines the result of the whole comparison.
a. Design the logic circuitry for a 2-bit comparator with cascading inputs. The
inputs and outputs are show in the figure below.
b. Design the logic circuitry for a 4-bit comparator with cascading inputs by
cascading the 2-bit comparator you designed in part (a).
Solution
There are three case which we must deal with in the comparator:
• The top 2 bits could be different. In which case, we don’t care about the rest of the
inputs.
• The top 2 bits could be the same but the bottom 2 bits could be differet. In this case, we
still don’t care about the C1-C3 inputs.
• The top 2 bits could be the same and the bottom 2 bits could be the same, meaning that A
= B. Here, we need to look to the result of lower order comparison, the C1-C3 inputs.
Top 2 bits
Different
Top 2 bits
Same,
Bottom 2
Different
A=B
A1
1
0
0
1
0
1
0
0
1
1
B1
0
1
0
1
0
1
0
0
1
1
A0
X
X
B0
X
X
F1
0
1
F2
0
0
F3
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
C1
C2
C3
By observing the above truth table we can get the following equations (not necessarily
minimized):
F 3 = A1B1'+ A0 B0' ( A1 ⊕ B1) + C 3( A1 ⊕ B1 ⊕ A0 ⊕ B0)
F 2 = C 2( A1 ⊕ B1 ⊕ A0 ⊕ B 0)
F 3 = A1' B1 + A0' B 0( A1 ⊕ B1) + C1( A1 ⊕ B1 ⊕ A0 ⊕ B0)
We can cascade a two bit comparator, much
like we cascade other arithmetic circuits.
2. Implement a combinational logic circuit that converts a 4-bit sign and magnitude number
into its corresponding 2’s complement representation. Draw an input/output conversion
truth table, intermediate K-maps, and your minimized two-level logic description.
Solution
Decimal
0
1
2
3
4
5
6
7
-0
-1
-2
-3
-4
-5
-6
-7
Sign Magnitude
X3 X2 X1 X0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
2’s Complement
F3 F2 F1 F0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
By examination we can determine
equations for F3 and F0:
F3 = X3 (X3 X2’ X1’ X0’)’
F0 = X1
K-map analysis yields equations for
F1 and F2”
F1 = X1X3’ + X0’X1 + X0X1’X3
F2 = X2X3’ + X0’X1’X2 +
X0X2’X3 + X1X2’X3
3. Design a combinational circuit with an unsigned 3-bit input (A2:0), an unsigned 2-bit
input (B1:0) and an unsigned 3-bit output (C2:0). Your circuit should compute the
quotient of dividing A by B. For example, if A = 111b (7d) and B = 10b (2d), then C =
011b (3d), since 7/2 is 3.5, so the quotient part is 3. Note:Division byzero will never
occur – take adbvantage of don’t care conditions in this case.
a. Write out the truth table for this circuit.
b. Simplify the logic for C0 using a K-map.
Solution
Write out the truth table (it’s a big one).
A B A2 A1 A0 B1 B0 C C2 C1 C0
0 0 0
0
0
0
0 X X X X
0 1 0
0
0
0
1 0 0
0
0
0 2 0
0
0
1
0 0 0
0
0
0 3 0
0
0
1
1 0 0
0
0
1 0 0
0
1
0
0 X X X X
1 1 0
0
1
0
1 1 0
0
1
1 2 0
0
1
1
0 0 0
0
0
1 3 0
0
1
1
1 0 0
0
0
2 0 0
1
0
0
0 X X X X
2 1 0
1
0
0
1 2 0
1
0
2 2 0
1
0
1
0 1 0
0
1
2 3 0
1
0
1
1 0 0
0
0
3 0 0
1
1
0
0 X X X X
3 1 0
1
1
0
1 3 0
1
1
3 2 0
1
1
1
0 1 0
0
1
3 3 0
1
1
1
1 1 0
0
1
4 0 1
0
0
0
0 X X X X
4 1 1
0
0
0
1 4 1
0
0
4 2 1
0
0
1
0 2 0
1
0
4 3 1
0
0
1
1 1 0
0
1
5 0 1
0
1
0
0 X X X X
5 1 1
0
1
0
1 5 1
0
1
5 2 1
0
1
1
0 2 0
1
0
5 3 1
0
1
1
1 1 0
0
1
6 0 1
1
0
0
0 X X X X
6 1 1
1
0
0
1 6 1
1
0
6 2 1
1
0
1
0 3 0
1
1
6 3 1
1
0
1
1 2 0
1
0
7 0 1
1
1
0
0 X X X X
7 1 1
1
1
0
1 7 1
1
1
7 2 1
1
1
1
0 3 0
1
1
7 3 1
1
1
1
1 2 0
1
0
K-map for C0
From the above K-map we get the
following minimized function for C0:
C0 = A2’A1A0 + A1B1B0’ +
A2’A0B1B0’ + A2A1A0’B1’ +
A2’A1’A0B0 + A2’A1’B1B0
4. The truth table for a 1-bit combinational binary subtractor, analogous to the half adder,
computing D(ifference) = A minus B, with BL (borrow-from-left), is
A
0
0
1
1
B
0
1
0
1
D
0
1
1
0
BL
0
1
0
0
a. Design a 1-bit combinational binary subtractor, comparable to the full adder, with
two data inputs (A, B), a borrow from the right input (BI), a borrow request to the
left output (BL), and a difference output (D)
b. Show how your design can be cascaded to form multibit subtractors.
c. Does the subtractor work correctly for negative two’s complement numbers?
d. How is a subtraction underflow condition indicated?
Solution
First, write out the truth table for the full subtractor:
A
B
BI
BL
D
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
0
0
1
0
1
1
0
0
0
1
1
1
1
1
BL = A’B + A’BI + BBI
D = A ⊕ B ⊕ BI
A full subtractor can be cascaded in the
same manner as a full adder:
Full subtractor K-maps:
5. Given some 4-bit shift registers (74184’s) and some full adders design a circuit that will
take two four bit numbers (A3:0 and B3:0) serially (bit order: A3, A2, A1, A0, B3, B2,
B1, B0) and compute the result their addition.
Solution