Field Programmable Gate Arrays
• Configuration
Memory
• Programmable
Logic Blocks
(PLBs)
• Programmable
Input/Output Cells
• Programmable
Interconnect
Typical Complexity = 5M – 1B transistors
Basic FPGA Operation
Write Configuration Memory
• Defines system function
– Input/Output Cells
– Logic in PLBs
– Connections between
PLBs & I/O cells
Changing configuration
memory data => changes
system function
• Can change at anytime
– Even while system
function is in operation
– Run-time
reconfiguration (RTR)
1110011010001000100101010001011
1000101001010101010010010001000
1010100100100110010010000111100
0110010100010000110010001010001
0010010010001010010101010010010
0101000101001010001010010100100
0100101010111010101010101010101
0101011110111110000000000000011
0100111110000100111000001110010
0101000000001111100100100010100
1110010010100001111000111000100
1010101010101010101001010010101
0100100101010101010101001001001
Basic PLB Architecture
• Look-up Table (LUT) implements truth table
• Memory elements:
– Flip-flop/latch
– Some FPGAs - LUTs can also implement small
RAMs
• Carry & control logic implements fast
adders/subtractors
carry out
Input[1:4]
4
LUT/
RAM
Control
Carry &
Control
Logic
clock, enable, set/reset
3
carry in
Flip-flop/
Latch
Output
Q output
A Simple PLB
• Two 3-input LUTs
– Can implement any
4-input combinational
logic function
• 1 flip-flop
C7
C3
C2
C1
C0
Cout
LUT C
8x1
3
Smux
SOmux
0 Sout
1
0
1
LUT S
8x1
• 22 configuration
memory bits D3
0
1
CB5
CEmux
CB3
Clock Enable
SRmux
0
1
CB4
FF
Set/Reset
Clock
– 6 controls
• CB0-7
C4
111 110 101 100 011 010 001 000
LUT
out
• Active levels
• Clock edge
D2-0
• Set/reset
• C0-7
• S0-7
C5
D2-0
– Programmable:
– 8 per LUT
C6
CB
CB0
CB1
CB2
= Configuration
Memory Bit
Combinational Logic Fucntions
• Gates are combined to
create complex circuits
• Multiplexer example
– If S = 0, Z = A
– If S = 1, Z = B
– Very common digital
circuit
– Heavily used in FPGAs
• S input controlled by
configuration memory bit
• We’ll see it again
A
S
Z
B
Truth table
SAB Z
000 0
001 0
010 1
011 1
100 0
101 1
110 0
111 1
Logic symbol
A
B
0
S1
0
1
Z
Look-up Tables
• Recall multiplexer
example
• Configuration
memory holds
outputs for truth
table
• Internal signals
connect to control
signals of
multiplexers to
select value of
truth table for any
given input value
Multiplexer
0
0
A
0
1
B
0
1
1
1
0
0
0
1
Z
1
0
1
1
0
0
1
1
1
B
0
A
Z
1
S
0
1
1
0
1
S
Truth table
SAB Z
000 0
001 0
010 1
011 1
100 0
101 1
110 0
111 1
Look-up Table Based RAMs
Address Decoder
• Normal LUT mode Data In ck0
performs read
ck1
operations
ck2
• Address decoder In0
ck3
In1
with write enable
In2
ck4
generates clock
ck5
signals to latches
for write operations
ck6
ck7
• Small RAMs but Write
can be combined Enable
for larger RAMs
0
0
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
In0
In1
In2
Z
Example PLB
• ¼ of a PLB (called a slice)
from Xilinx Spartan 3
– Two 4-input Look-Up Tables
(LUTs)
• Can perform any
combinational logic function
of up to 4 inputs
• Can function as small RAM
(16x1-bit) or shift register (up
to 16-bit)
– Two D-type flip-flops
• Programmable as level
sensitive latches
• Programmable clock edge,
clock enable, set/reset
– Extra logic
• Fast carry for adders
• MUXs for Shannon
expansion
• And more
Spartan 3 PLB Slices
Slice L
Slice M
Interconnect Network
• Wire segments of varying length
– xN = N PLBs in length
• 1, 2, 4, 6, and 8 are most common
– xH = half the array in length
– xL = length of full array
• Programmable Interconnect Points (PIPs)
• Also known as Configurable Interconnect Points (CIPs)
– Transmission gate connects to 2 wire segments
– Controlled by configuration memory bit
Wire A
• 0 = wires disconnected
• 1 = wires connected
config
bit
Wire B
PIPs
• Break-point PIP
– Connect or isolate 2 wire segments
• Cross-point PIP
– Turn corners
• Compound cross-point PIP
– Collection of 6 break-point PIPs
• Can route to two isolated signal nets
• Multiplexer PIP
– Directional and buffered
– Select 1-of-N inputs for output
• Decoded MUX PIP – N config bits select from 2N inputs
• Non-decoded MUX PIP – 1 config bit per input
Spartan 3 Routing Resources
switch matrix
over 2,400 PIPs
mostly MUX PIPs
PLB consists
of 4 slices
x6 wire
segments
x2 wire
segments
xH & xL wire
segments
over 450
total wire
segments
in PLB
Input/Output Cells
• Bi-directional buffers
– Programmable for input or output
– Tri-state control for bi-directional operation
– Flip-flops/latches for improved timing
• Set-up and hold times
• Clock-to-output delay
– Pull-up/down resistors
• Routing resources
Tri-state Control
to/from
internal
routing
resources
Output Data
Pad
Input Data
– Connections to core of array
• Programmable I/O voltage & current levels
Spartan 3 I/O Cell
FPGAs
• Recent trend - incorporate specialized cores
– RAMs – single-port, dual-port, FIFOs
• 128 bits to 36K bits per RAM
• 4 to 575 per FPGA
– DSPs – 18x18-bit multiplier, 48-bit accumulator,
etc.
• up to 512 per FPGA
– Microprocessors and/or microcontrollers
• up to 2 per FPGA
– Hard core processor
• Support soft core processors
– Synthesized from HDL into programmable resources
200
2S15
2S30
2S50
2S100
2S150
2S200
V50
V100
V150
V200
V300
V400
V600
V800
V1000
3S50
3S200
3S400
3S1000
3S1500
3S2000
3S4000
3S5000
2V40
2V80
2V250
2V500
2V1000
2V1500
2V2000
2V3000
2V4000
2V6000
2V8000
2VP2
2VP4
2VP7
2VP20
2VPX20
2VP30
2VP40
2VP50
2VP70
2VPX70
2VP100
RAMs/multipliers
Specialized Cores
450
400
350
300
250
Virtex and Spartan II
4K-bit RAMs
Virtex II and Spartan 3
18K-bit RAMs and 18×18-bit multipliers
150
100
50
0
Spartan 3 Programmable RAMs
• 18 Kbit dual-port RAM
• Each port independently configurable as
– 512 words x 36 bits
• 32 data bits + 4 parity bits
– 1K words x 18 bits
• 16 data bits + 2 parity bits
– 2K words x 9 bits
• 8 data bits + 1 parity bit
– 4K words x 4 bits (no parity)
– 8K words x 2 bits (no parity)
– 16K words x 1 bit (no parity)
• Each port has independently programmable
– clock edge
– active levels for write enable, RAM enable, reset
Spartan 3 (XC3S200)
• PLBs = 24 rows
x 20 columns =
480
– 4 slices/PLB
• 2 L slices
– L= logic
• 2 M slices
– M= memory
• RAMs = 12
18Kbit dual port
RAMs
• Multipliers = 12
18x18-bit signed
Ranges of Resources
FPGA Resource
Logic
Routing
Specialized
Cores
Other
Small FPGA Large FPGA
PLBs per FPGA
256
25,920
LUTs and flip-flops per PLB
1
8
Wire segments per PLB
45
406
PIPs per PLB
139
3,462
Bits per memory core
128
36,864
Memory cores per FPGA
16
576
DSP cores
0
512
Input/output cells
62
1,200
Configuration memory bits
42,104
79,704,832
Xilinx FPGAs
•
Virtex and Spartan 2
– Array of 96 to 6,144 PLBs
• 4 LUTs/RAMs (4-input)
• 4 FF/latches
– 4 to 32 4K-bit dual-port RAMs
•
Virtex II, Virtex II Pro
– Array of 352 to 11,204 PLBs
• 8 LUTs/RAMs (4-input)
• 8 FF/latches
– 12 to 444 18K-bit dual-port RAMs
– 12 to 444 18×18-bit multipliers
– 0 to 2 PowerPC processor cores
•
PC
PC
Virtex 4
– Array of 1,536 to 22,272 PLBs
• 4 LUTs/RAMs (4-input)
• 4 LUTs (4-input)
• 8 FF/latches
– 48 to 552 18K-bit dual-port RAMs
• Also operate as FIFOs
– 32 to 512 DSP cores include:
– 0 to 2 PowerPC processor cores
•
Spartan 3
480 – Array of 192 to 8,320 PLBs
• 4 LUTs/RAMs (4-input)
3S200
• 4 LUTs (4-input)
• 8 FF/latches
12 – 4 to 104 18K-bit dual-port RAMs
12 – 4 to 104 18×18-bit multipliers