Vol. 34, No. 9
Journal of Semiconductors
September 2013
A wideband CMOS inductorless low noise amplifier employing noise cancellation
for digital TV tuner applications
Zhang Jihong(张继红), Bai Xuefei(白雪飞)Ž , and Huang Lu(黄鲁)
Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China
Abstract: A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed
LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise
generated by the input transistors. The chip is implemented in SMIC 0.18 m CMOS technology. Measurement
shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below
3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is –
17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5
0.35 mm2 .
Key words: LNA; noise cancellation; CMOS; wideband
DOI: 10.1088/1674-4926/34/9/095011
EEACC: 1205; 1220
1. Introduction
Low noise figure (NF) RF front-end receivers are in high
demand in terrestrial digital video broadcasting. The low noise
amplifier (LNA), as the first block of a receiver, plays the
most important role in the overall NFŒ1; 2 . Inductorless topologies have been proposed to reduce the chip areaŒ3 7 . These
LNAs usually rely on resistive feedback techniques for wideband input matching, which leads to poor noise figure, and
hence, poor sensitivityŒ8 . Therefore, noise cancellation techniques have been proposed in Refs. [3, 4] to overcome the poor
noise figure of these inductorless wideband LNAs.
In this paper, a fully integrated inductorless wideband
CMOS LNA employing noise cancellation in 0.18 m CMOS
process is presented. The LNA achieves a low noise figure by
using a composite NMOS/PMOS transistor pair connected in
a cross-coupled configuration to provide partial noise cancellation of the main transistors. Also, analytical expressions for
the performance parameters are derived.
Fig. 1. (a) Noise and (b) signal voltage at nodes X and Y.
2. Basic noise cancellation principle
To understand how to cancel the noise generated by the
MOSFET, the schematic of a common source (CS) stage with
resistive feedback is shown in Fig. 1(a). The noise current In
of M1 flows through RF and RS , producing voltages at the gate
and drain of M1 with the same polarity. On the other hand, the
signal voltages at nodes X and Y have opposite signs as shown
in Fig. 1(b). This difference for noise and signal makes it possible to cancel the noise of M1, while simultaneously adding the
signal contributions constructively. This is done by creating a
new output, where the voltage at node Y is added to a scaled
negative replica of the voltage at node X. A proper value for
this scaling factor renders noise canceling at the output node,
for the thermal noise originating from M1. Figure 2 shows a
Fig. 2. Noise cancellation of feedback CS stage.
straightforward implementation. If VX is amplified by –Av and
added to VY , the noise of M1 can be removedŒ9 .
* Project supported by the National Science and Technology Major Project, China (No. 2011ZX03004-002-01).
† Corresponding author. Email: baixf@ustc.edu.cn
Received 4 February 2013, revised manuscript received 25 March 2013
© 2013 Chinese Institute of Electronics
095011-1
J. Semicond. 2013, 34(9)
Zhang Jihong et al.
Fig. 3. Complete schematic of the proposed wideband inductorless LNA.
3. Proposed LNA Architecture
The proposed wideband inductorless LNA is shown in
Fig. 3, and all components in the figure are integrated on-chip.
Transistor M1 is placed in deep N-well (DNW) region, so the
source and bulk terminal can be connected together to eliminate the noise currents generating from body effect. Devices
in DNW also show a better isolation from substrate noise couplingŒ10 . Transistor M0 is incorporated into the gate of transistor M1 in a cross-coupled configuration.
This composite configuration reduces the output noise of
the two transistors, thus, the overall noise figure is reduced. The
input matching is adjusted through the feedback resistance RF
and the effective transconductance of the overall LNA. Transistor M2 and parasitic capacitor Cout form the push-pull architecture to achieve a high gain. Increasing the overall gain helps
to reduce the noise contribution of the load and feedback resistances, and therefore lowering the overall noise figure. Also,
the DC current biasing is provided by M2. The source follower
composed by M3 and M4 is added as the output buffer for the
measurement.
4. Circuit design and analysis
Fig. 4. Composite NMOS/PMOS transistor architecture.
Fig. 5. Half-circuit small-signal model of the proposed LNA.
gm; eff , is given by the series combination of the NMOS and
PMOS transistors.
4.1. Wideband and high gain
The basic cell of the proposed LNA is the composite
NMOS/PMOS transistor pair as shown in Fig. 4. Ideally, if the
two inputs have the same amplitude and phase, then the source
voltage of the two transistors, VS , is the same as the input, leading to a zero output current. On the other hand, if the two inputs
have the same amplitude but differ in phase, then VS becomes
an AC ground, resulting in a finite output current. That is to
say, this configuration amplifies the differential voltage and rejects the common-mode one. The effective transconductance,
iO D gm; eff .Vin
gm; eff D
VinC /;
gm0 gm1
:
gm0 C gm1
(1)
(2)
The gain of the proposed LNA in Fig. 3 is calculated by
using the half-circuit small-signal analysis shown in Fig. 5.
095011-2
J. Semicond. 2013, 34(9)
Av .s/ D
D
VoutC
VinC
Zhang Jihong et al.
Vout
Vin
Av;mid .1 C s=!z /
Av;mid
;
.1 C s=!po /.1 C s=!ps /
1 C s=!po
Av;mid D .2gm;eff C gm2 /.RF jjrO2 /;
!z D
!ps D
2gm0
;
2Cgs0 C CS
!po D
1
;
Cout .RF jjrO2 /
gm0 C gm1
;
Cgs0 C Cgs1 C CS
(3)
where Av;mid is the mid-band gain, !po is the pole at the output,
!ps and !z are due to the parasitic capacitances Cgs1 , Cgs0 , and
CS .
Increasing the gain requires a higher value of RF jjrO2 ,
which reduces the upper cut-off frequency of the LNA. This
is indicative of the design trade-offs between gain and bandwidth.
4.2. Wideband input matching
Using the half-circuit small-signal model in Fig. 5, the
half-circuit input impedance of the proposed LNA is analytically given by
Zin; half
1
sCgd1
1
jj
D
1 C Av .s/ s.Cgs1 C Cgs0 /
RF jj
jj
gm1 C gm0 C sCS
;
s.gm1 gm0 /.Cgs1 C Cgs0 /
Fig. 6. Equivalent circuits showing the effect of noise current.
Changing either of these quantities helps to improve the matching. As an example, to reduce the value of Rin; mid either the
value of 2gm; eff C gm2 has to increase or the value of RF =rO2
has to decrease. Increasing 2gm; eff C gm2 leads to a lower noise
figure, however, the input capacitance increases leading to a
poor matching at higher frequencies, that is to say, lower bandwidth. On the other hand, reducing the value of RF =rO2 lowers
the gain and hence increases the noise figure. This is the tradeoff between increasing the bandwidth of the input impedance
versus having a lower noise figure at higher frequencies.
(4)
where Av .s/ is the gain of the LNA and Cgd is the gate–drain
capacitance of the NMOS transistor. The input impedance
is composed of three parallel impedances as follows: (1)
RF jj(1/sCgd1 /=.1 C Av / which is responsible for the input
matching; (2) 1=s.Cgs1 C Cgs0 / which is due to the finite input
capacitance; and (3) .gm1 C gm0 C sCS //s.gm1 gm0 /(Cgs1 C
Cgs0 / which appears due to non-equal values of gm1 and gm0 .
For gm1 D gm0 , the input impedance is the parallel combination of the first two terms in Eq. (4). Actually, it is hard to
guarantee similar gm1 and gm0 , because of the design or process
mismatches, therefore the third term in Eq. (4) is effective.
The differential input impedance, Zin .s/ D 2Zin; half .s/,
could be further simplified as follows.
Rin; mid .1 C s=!po /
;
Cgs1 C Cgs0
RF .Cgs1 C Cgs0 /
1 C sRF Cgd1 C
C s2
Av; mid
Av; mid !po
2
RF
RF
1C
:
Rin; mid D 2 1 C Av;mid
2gm; eff C gm2
rO2
(5)
Zin D
The mid-band value of the input impedance Rin; mid , depends on the value of 2gm; eff C gm2 and the ratio of RF =rO2 .
4.3. Noise figure
Considering the noise generated by NMOS and PMOS
transistors, the cross connection leads to partial noise cancellation of the generated noise. The partial noise cancellation is
clarified qualitatively for the proposed architectures, as shown
in Fig. 6. In this figure, the noise current due to the right NMOS
transistor, in; M1 , is considered. The left section is replaced by
its input impedance, which is analytically derived using the
small signal model. The noise current in; M1 produces an output
noise voltage, Vout; n . Then, Vout; n generates a noise voltage at
nodes VinC and Vin . These two voltages drive the left section
and produce an output noise voltage, Vout; p , which is a fraction
of Vout; n (Vout; p D ˇVout; n , ˇ < 1). Due to the cross connection,
Vout; p carries the same polarity as Vout; n , thereby the differential
output noise voltage is reduced. Similarly the noise generated
by M0 is partially canceled. In the conventional case, Vout; p and
Vout; n carry different polarities, so that the conventional LNA
with resistive feedback has higher noise figure.
The different noise sources affecting the overall noise figure are shown in Fig. 7, where only the noise contributors of
half of the circuit are shown.
Assuming RS RF and RS rO2 , the resultant output
differential noise voltage due to M1is given by
095011-3
J. Semicond. 2013, 34(9)
Zhang Jihong et al.
Fig. 8. Chip microphotograph.
Fig. 7. Noise sources in the proposed LNA.
2
vin;
M0 D
2
vn;
outd; M1
0
B gm; eff
2B
@ gm1 rO2 jjRF
12
1
rO2 RS
1 C gm; eff
rO2 C RF
C 2
C i
A n; M1 :
2
vin;
M2 D
(6)
2
vn;
outd; M1 D
1
2
gm; eff
rO2 jjRF
gm1
2
in;2 M1 :
(7)
2
vin;
M1 D
1
i2 :
2
2 gm1
.2gm; eff C gm2 /2 n; M1
(8)
The noise current of M1 is given by
in;2 M1 D 4kT n gm1 f C
KF;n IDC
f;
f Cox L2n
gm1 .2gm; eff C gm2 /2
2
vin;
RF D
2
2f Cox L2n gm1
.2gm; eff C gm2 /2
f;
(11)
2
KF; p IDC gm;
eff
2
4f Cox L2p gm2
.2gm; eff C gm2 /2
f;
(12)
2 2
RS
2
1
1C
kTf:
2
.2gm; eff C gm2 /RS
RF
(13)
Finally, the total noise figure is obtained by summing the
quantities of Eqs. (10)–(13) and then dividing by kTRS f ,
which is the noise generated by the source resistance at the input of the LNA. Hence, the total noise figure is as follows.
NFtot D 1 C
C
C
f
2
KF; n IDC gm;
eff
2
2f Cox L2p gm0
.2gm; eff C gm2 /2
(9)
where is the Boltzmann constant, vn and KF; n are the thermal
and flicker noise factors respectively, IDC is the DC current,
Cox is the oxide capacitance per unit area, and Ln is the channel
length of M1. Substituting Eq. (9) in Eq. (8), the input-referred
noise voltage is as follows.
2
2kT n gm;
eff
2
KF; p IDC gm;
eff
The input-referred voltages’ noise due to the thermal noise
of RF is as follows.
Dividing Eq. (7) by Av;mid defined in Eq. (3), the inputreferred noise due to M1 is obtained.
2
gm;
eff
f
kT p gm2
f
.2gm; eff C gm2 /2
C
Assuming perfect matching, Equation (6) reduces to
C
gm0 .2gm; eff C gm2 /2
C
D
2
vin;
M1 D
2
2kT p gm;
eff
f:
(10)
Similar analysis is applied to M0 and M2, the inputreferred noise voltage is as follows.
095011-4
C
2
2n gm;
eff
gm1 RS .2gm; eff C gm2 /2
2
2p gm;
eff
gm0 RS .2gm; eff C gm2 /2
p gm2
RS .2gm; eff C gm2 /2
KF;p
KF;p
KF;n
C 2 2 C
2
2
2
Ln gm1
Lp gm0
2L2p gm2
!
2
IDC gm;
eff
2kTf Cox RS .2gm; eff C gm2 /2
2
2
1
RS
1C
:
C
2
.2gm; eff C gm2 /RS RF
(14)
J. Semicond. 2013, 34(9)
Zhang Jihong et al.
Fig. 10. Measured NF.
Fig. 9. Measured S parameters.
Fig. 11. Measured input 1 dB compression point.
The above analysis shows that the noise contribution of
the NMOS/PMOS transistor is reduced compared to the conventional LNA. Increasing the transistor width helps to reduce
the flicker noise and width per finger is minimized to reduce
the effective series gate resistance resulting in higher gain and
lower noise figure. The composite NMOS/PMOS transistors
are sized in a way to maximize the bandwidth.
5. Experiment results
This proposed LNA is fabricated in SMIC 0.18 m CMOS
technology and the microphotograph is shown in Fig. 8; it occupies a core area of 0.5 0.35 mm2 . The proposed chip is
mounted on FR-4 PCB test board (COB) for measurements.
Within the frequency band of interest, there has been a 2.2–
2.8 dB loss due to the SMAs, passive baluns and transmission
line. The minimum insertion loss 2.2 dB at the center frequency
is used for calibration.
Agilent E8364C PNA network analyzer was used to measure S parameters. From Fig. 9, the measured S21 achieves a
maximum of 13 dB at 200 MHz. S21 is 10–13 dB from 50
to 900 MHz. The power gain should be updated to 12.2–15.2
dB by adding 2.2 dB, due to the insertion loss. The measured
S11 stays below –9.5 dB and S22 keeps below –10 dB over
300 MHz to 1 GHz. Reverse isolation S12 < –50 dB from 10
MHz to 1.5 GHz which indicates good stability performance.
Noise Figure is measured by Agilent N8974A NFA series
noise analyzer. After calibration, the NF is shown in Fig. 10.
The measured NF has a minimum value of 2.3 dB at 900 MHz
and bellows 3.1 dB from 300 MHz to 1.2 GHz.
Figure 11 shows the measured input referred 1 dB compression point of –17 dBm at 900 MHz. The linearity is inversely proportional to the overdrive voltage. Due to the higher
supply voltage requirement, the linearity is not very good.
Also, the proposed LNA does not have an inherent nonlinearity cancellation similar to the noise. Increasing the linearity requires increasing the supply voltage, which results in higher
power consumption.
The LNA consumes 7 mA from 1.8 V supply voltage, and
the buffer occupies 4 mA. Table 1 summarizes the performance
of the proposed LNA, with comparison to previously published
LNAs. Single-to-differential topology is used in Ref. [1] to
save power and improve NF. Reference [2] exploited feedforward noise-canceling technique to minimize the noise without
suffering from instability issues. A differential CG LNA with
a positive-negative feedback technique is described in Ref. [5]
to achieve high gain and low noise figure. Reference [7] presented an efficient compensation scheme to improve gain and
phase balance. Noise cancellation technique is used in Ref. [8]
and this paper to reduce NF. Competitive performance is obtained with the trade-off design consideration and the proposed
LNA can be used in digital TV tuner applications.
095011-5
J. Semicond. 2013, 34(9)
Parameter
Process (m)
Supply voltage (V)
Bandwidth (GHz)
NF (dB)
Gain (dB)
P1dB (dBm)
S11 (dB)
Power (mW)
Core area (mm2 /
Ref. [1]
0.18 CMOS
1.8
0.05–0.86
< 4.5
16
> 10
< 8
10.8
0.04
Zhang Jihong et al.
Table 1. Performance summary and comparison.
Ref. [2]
Ref. [5]
Ref. [7]
0.18 CMOS
0.18 CMOS
0.13 CMOS
2.5
1.8
1.2
0.2–2
0.3–0.92
0.1–2
< 2.4
< 2.8
< 4.8
14
21
7.6
9:6
12:8
9:1
< 8
< 10
< 10
35
3.6
3
0.075
0.33*
0.075
Ref. [8]
0.09 CMOS
1.8
0.002–1.1
< 1.9
20
11:1
< 10
18
0.06
This work
0.18 CMOS
1.8
0.3–0.9
< 3.1
15.2
17
< 9:5
12.6
0.175
* Including pads. ** Graphically estimated.
6. Conclusion
A 300–900 MHz wideband inductorless LNA employing
noise cancellation is designed and measured. The theory and
measurement shows that the proposed approach reduces the
noise figure of the conventional LNA with resistive feedback.
Measurements of a fabricated prototype using SMIC 0.18 m
CMOS technology show a voltage gain of 15.2 dB and the minimum noise figure is 2.3 dB. The circuit shows an input matching with the measured S11 below 9:5 dB. The input referred
1 dB compression point (IP1dB) is 17 dBm at 900 MHz. The
core circuit consumes 7 mA current from a supply of 1.8 V.
[4]
References
[8]
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