Improvement in WL-CSP Reliability by Wafer Thinning
Li Wetz, Jerry White, Beth Keser
Motorola SPS
2100 E. Elliot Road, MD EL 619
Tempe, AZ, USA 85284
Li.Wetz@motorola.com
Phone: (480) 413-5670
Abstract
WL-CSP is a low profile, true chip size package that is
entirely built on a wafer using front-end and back end
processing. The wafers can be batch-processed in a fab,
which reduces the number of materials and packaging steps,
reduces inventory, and allows for wafer level burn in and test.
This technology is driven by cost, size, and ease of testing and
is ideal for low to mid I/O devices. Peripheral bondpads from
the die are redistributed into an area array using a
photodielectric and a redistribution metal, eliminating the
need for a substrate or interposer. Solder balls are placed onto
the redistributed metal bondpads and reflowed, creating a
large standoff which improves reliability. The bump structure
and pad geometry of the test vehicle was optimized using
simulation and validated by experimentation. This WL-CSP
technology was evaluated using a 5 x 5 mm2 die with a 0.5
mm pitch 8 x 8 array of solder bumps. Board level reliability
was performed using 1.2 mm thick, 2-layer FR-4 boards with
0.25 mm non-soldermask defined copper pads coated with
OSP. Standard thickness WL-CSP wafers are 27-mils. An
evaluation was performed to evaluate the potential reliability
improvement of WL-CSPs by thinning the wafers. Wafers
were thinned down to 4-mils thickness using two techniques.
The first method is standard wafer backgrinding. The second
is the novel approach of plasma etching, which results in a
damage-free surface and improves wafer and die strength.
Board level reliability will be presented comparing standard
WL-CSPs to those thinned using the aforementioned
techniques.
Introduction
As electronic components continue to shrink in size, the
semiconductor industry is moving toward IC miniaturization.
Wafer level chip scale packaging (WL-CSP) is becoming a
popular method of packaging low to mid-I/O devices. WLCSP is cost effective, easy to test, and has a small footprint
and low profile.
Cost is a major factor driving WL-CSP technology.
Wafer level packages are built entirely using fab-type batch
processing at the wafer level, decreasing cost. Packaging
steps are reduced because WL-CSP does not require materials
and processes such as underfill, substrates, or interposers,
which are typically found in chip scale packages (CSP) or ball
grid array (BGA) packages. Packaging time and inventory
can be subsequently reduced because WL-CSPs do not need
to be sent to assembly houses.
Wafer level burn-in and test (WLBT) is another driving
force behind WL-CSP technologies. Test will no longer need
to be performed prior to packaging. Once the wafer has
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completed the final packaging step, it can be burned-in and
tested for known good packages (KGP). Testing at the wafer
level reduces the number of test steps and requires less test
capital thereby reducing costs by as much as 50%.
Size is the third major driving force for wafer-level
packaging. The footprint and profile of a WL-CSP is the same
as the die.
Motorola’s approach to WL-CSP technology uses
redistribution at the wafer level, which replaces use of an
interposer. Solder balls are placed at the wafer level to form
first and second level interconnects. Package and board level
reliability results for this WL-CSP structure have been
reported previously [1].
Wafer Thinning
There are several benefits to thinning wafer level
packages. Thinning the die can benefit IC components in
several ways: by reducing thermal resistance, improving
device performance, increasing reliability, and lowering
overall package height so end application such as cell phones
can be thinner. The focus of this paper is to evaluate the
improvement in reliability by wafer thinning. Thinning the
wafer helps to minimize die stress, which occurs due to
mismatches in the coefficient of thermal expansion (CTE)
between the silicon die and the board materials. The thinner
die has less shear forces acting on it. The solder joint
reliability is thus improved since the reduction in die stress
allows it to flex with the board [2]. WL-CSPs thinned via
mechanical back grinding and plasma etching are evaluated
here.
In typical mechanical grinding, unwanted silicon is
removed from the backside of the wafer using a two-step
process – coarse grinding followed by fine grinding. This is
performed using a grinding tool that contains diamond
particles of specific dimensions held by a bonding material
such as epoxy, wax, or ceramic. During coarse grinding,
typically 90% of the back grind is completed, significantly
reducing the thickness of the wafer. Coarse grinding will
cause microcracks and damage the silicon lattice. Fine
grinding completes the back grind process and removes part
of this damage, but still leaves some silicon flaws behind [3].
Plasma etching is a dry etching technology that uses
atmospheric downstream plasma (ADP). Using this method, a
wafer can be uniformly thinned without generating
microcracks or damage to the silicon lattice. Plasma etching
may be used after mechanical grinding to help remove surface
defects created during the process. In ADP etching, an inert
thermal plasma is generated by DC discharge at atmospheric
pressure. The wafer is suspended in a chuck with the
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backside facing down (in which there is no contact between
the wafer and holder). Two electrodes directed upwards, at a
90° angle to each other, sit below the wafer. A plasma arc is
formed when a DC field is applied between the two
electrodes. Reactant is injected to the plasma stream, which
uniformly etches the backside of the wafer [4,5].
time so as to guide the development team towards the most
optimum design in a time effective manner. Keeping this in
mind the most optimum approach was chosen as the 2-D
plane strain approach.
Test Vehicle
The test vehicle evaluated by Motorola is a 5 × 5 mm die
with a 0.5mm pitch 8 x 8 array of solder bumps. Each six-inch
wafer yields 496 packaged die. Photographs of the diced WLCSP are shown in Figures 1 and 2. Peripheral bondpads from
the die are redistributed into an area array using sputtered
aluminum redistribution metal with 300-um redistributed
bond pads. The BCB redistribution photodielectric was 5 µm
thick with 250 µm diameter openings to the bondpads. This
redistribution process has been described previously [6]. The
preformed solder balls were eutectic Sn-36Pb-2Ag with 300
mm diameter to give maximum bump height for the 0.5 mm
pitch array. Figure 3 shows a cross-section of a WL-CSP.
Figure 3: Cross-section of the SnPbAg WL-CSP.
Inputs include:
• Board is 5.8 × 5.8 × 0.54 mm, 2-layer FR-4
• Solder joint stand off is 168 µm
• Package performance is compared for temperature
cycling between –55°C and 125°C, using 10-minute ramp
and 10-minute dwell times.
Figure 4 shows a comparison between the predicted lives
of full thickness WL-CSPs and those of thinned WL-CSPs. In
this figure, the predicted lifetimes have been normalized with
the baseline (full thickness) WL-CSP equal to one. As die
thickness decreases, the solder joint reliability increases.
Figure 1: Tilt view of Motorola's WL-CSP.
Life Comparison with Thinned Die
Normalized Predicted Life
4
3
2
1
0
0
0.2
0.4
0.6
0.8
Die Thickness (mm)
Figure 2: Top view of Motorola's WL-CSP.
Figure 4: Die thickness reliability
Simulations
A non-linear finite element method (FEM) was used for
analyzing and comparing the various designs.
This
methodology was extremely effective in capturing the impact
of complicated shapes, multiple components, non-linear
material behavior and complex loading situations. However,
depending on the approach chosen, this methodology can also
be very time consuming and tedious. The emphasis here is on
quick result generation to enable evaluation of a number of
different design options and parametric studies in the shortest
Board Level Reliability
WL-CSPs were attached to boards and subjected to
accelerated life tests to determine their reliability. Board
attach was performed on a full thickness wafer (27-mils, or
690 microns), one wafer thinned by standard back grind
techniques (2000 Angstroms surface finish) and one wafer
thinned by an atmospheric plasma operation. Both of the
thinned wafers had a final thickness of 95-microns. All
wafers utilized SnPbAg solder spheres. The WL-CSPs were
assembled to 1.2-mm thick 2-layer FR-4, single-sided boards
using SnPbAg solder paste. The boards had conventional
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copper laminated core construction with OSP and nonsoldermask defined pad openings that were 100 micron
greater than the 250-micron test pads. A cross-section of the
WL-CSP attached to the board is shown in Figure 5.
Board level reliability for LLTS (-55°C to +125°C) and
AATC (-40°C to +125°C) were performed. The boards were
tested for failures every 100 cycles. Resistance levels
determined failure criteria. When the resistance of a package
increased to 50% above its initial value, the part was
considered a failure. Where applicable, Weibull plots were
generated to determine the characteristic reliability for each
package thickness.
The characteristic life is defined as the age at which
63.2% of the units have failed. The Weibull plot assumes a
single failure mode for all samples. Characteristic life for all
tests are shown in Table 2.
Figure 6: Weibull of LLTS reliability results.
a)
b)
c)
Figure 7: Cross-sections of WL-CSPs after LLTS
reliability testing: (a) full thickness wafer after 1300
cycles, (b) mechanically back ground wafer after 1300
cycles, (c) plasma etched after 1200 cycles. Failure mode
was solder cracking.
Figure 8 is a Weibull plot of –40/125°C AATC. Full
wafer thickness packages had time to first failure at 1500
cycles with a characteristic life of 3928 cycles. Mechanically
ground wafers had first failure at 2000 cycles with a
characteristic life of 2676 cycles. The characteristic life for
the plasma etched wafers was 7650 cycles with the first
failure occurring at 900 cycles. The dominant failure mode
for all wafers was solder cracking. Cross-sections can be seen
in Figure 9. Again, solder cracking was shifted from the die
side to the board side after wafer thinning.
Figure 5: Typical cross-section of the WLCSP attached to board.
Table 2: Board level reliability results.
Characteristic Life
Full Thickness
Grind
LLTS
5695
7921
-40/125°C AATC
3928
2676
Plasma
>20,000
(< 50% failure)
7650
Figure 6 is a Weibull plot for LLTS results of each
package thickness. For LLTS (-55°C to +125°C) full
thickness WL-CSPs had time to first failure at 1300 cycles
and a characteristic life of 5965 cycles. Mechanically ground
wafers had first time to failure at 1000 cycles with a
characteristic life of 7921 cycles. Plasma thinned wafers had
first failure at 900 cycles with a characteristic life of over
20,000 cycles (based on less than 50% failure rate). The
dominant failure mode for all alloys was solder cracking.
Cross-sections can be seen in Figure 7. For the thicker
package in Figure 7a, the solder cracks at the die side. By
thinning the package, we have successfully moved the failure
in the solder to the board side.
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Figure 8: Weibull of -40/125°C AATC reliability results.
2003 Electronic Components and Technology Conference
thank Vasile Romega-Thompson, Steve Post, and Jim Drye of
the test and reliability lab. We are also very grateful to all the
members of the WL-CSP team for their support.
Figure 9: Cross-sections of WL-CSPs after –40/125°C
AATC reliability testing: (a) full thickness after 1500
cycles, (b) mechanically back ground after 2000 cycles,
and (c) plasma etched after 900 cycles. Failure mode was
solder cracking for all cases.
Summary
Wafer level packaging technology simplifies processing
and reduces cost by eliminating substrate and underfill. Using
preformed balls results in a large overall collapse height,
which meets solder joint reliability requirements for
commercial applications. Improved reliability was shown by
the addition of using thinned wafers. By comparison of the
two thinning methods, using a small sample size in each case,
the use of plasma thinning appears to impart additional
reliability as compared to standard grind techniques. Also,
thinning the wafers shifts the failure mode from solder
cracking at the die side to solder cracking at the board side.
Acknowledgments
We would like to thank Dr. Vijay Sarihan for the
simulation results, Raj Bajaj, Kevin Lish, and Justin Poarch
for wafer processing and die attach. We would also like to
References
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