Application Report
SLAA296 – May 2006
Using ADS8410/13 in Daisy-Chain Mode
Bhaskar Goswami, Vikash Sethia ....................................................................................... DAP Nyquist
ABSTRACT
Many applications require multiple analog-to-digital converters (ADC) in a system.
Daisy chaining multiple ADCs enables the use of a single data receiver or a small
FPGA. It offers easy and minimal digital routing. This application report describes how
multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a
high-speed (200 Mbps) LVDS serial interface. This application report also suggests a
way to de-serialize high-speed serial data. It discusses the board design aspects and
test guidelines. It also presents reference schematics and layouts for the boards.
Finally, the reference board results are presented.
Contents
1
Introduction .......................................................................................... 2
2
Description of the Device .......................................................................... 2
3
Digital Interface ..................................................................................... 2
4
Definition of Daisy Chain .......................................................................... 3
5
Block Diagram ...................................................................................... 3
6
Timing ................................................................................................ 4
7
Board Design Aspects ............................................................................ 12
8
System Block Diagram ........................................................................... 17
9
De-Serialization.................................................................................... 19
10
Limitation on Number of Devices in the Chain ................................................ 20
11
Results .............................................................................................. 20
12
Conclusion ......................................................................................... 24
Appendix A
ADS8413EVM Daisy Chain Schematics, Layout, and Photograph ............... 25
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Three Devices in Daisy Chain .................................................................... 3
Four Devices in Daisy-Chain Mode .............................................................. 4
Sample and Convert With Wait (Less Than 2-MSPS Throughput) .......................... 6
Sample and Convert With No Wait or Back to Back (2-MSPS Throughput)................ 6
Data Read With CS Low and BYTE = 0 ......................................................... 7
Start of Data Read Cycle With RD and CS Low and Device in Wait or Sample Phase .. 8
Start of Data Read Cycle With End of Conversion ............................................. 9
Data Read Cycle End With MODE C/D = 0 ..................................................... 9
Data Read Operation for Devices in Daisy-Chain Mode ..................................... 10
Data Propagation From Device n to Device n+1 in Daisy-Chain Mode .................... 11
Four Devices Placed in Straight Line Fashion ................................................ 12
Four Devices Placed in Circular Fashion ...................................................... 12
LVDS Driver/ Receiver in Point-to-Point Connection ......................................... 12
CLK_O and SYNC_O Connection Between Last Device and the Deserializers.......... 13
Terminating at Both Receivers .................................................................. 13
Terminating at One Receiver .................................................................... 13
Terminating at Source End ...................................................................... 14
Analog and Digital Circuitry Are Separated in the Layout With a Virtual Boundary ..... 15
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Introduction
19
20
21
22
23
24
25
26
27
Devices Are Rotated and Placed to Reduce LVDS Trace Length..........................
LVDS Routing .....................................................................................
First and Second Device in the Chain ..........................................................
Third and Forth Device in the Chain ............................................................
Last ADC in the Chain and the Deserializers .................................................
CLK_I and CLK_O of Device 1 ..................................................................
CLK_I and CLK_O of Device 2 .................................................................
CLK_I and CLK_O of Device 3 ..................................................................
CLK_I and CLK_O of Device 4 ..................................................................
16
17
18
19
20
21
22
22
23
List of Tables
1
2
3
4
1
CONVST and CSTART Timing Control.......................................................... 6
Clock Duty Cycle .................................................................................. 21
Linearity of Four Devices in the Chain ......................................................... 23
SNR and THD of Four Devices in the Chain .................................................. 23
Introduction
In many applications, multiple ADCs are used to convert several analog channels. For stand-alone ADCs
(i.e., ADCs without an option for daisy chain or cascade) multiple digital outputs are sometimes
multiplexed with a digital multiplexer. In other cases, a high pin-count FPGA or DSP is used to receive
multiple digital outputs. To avoid this complexity, the ADS8410/13 offers a daisy-chain mode (explained in
detail later) in which data from multiple devices are transmitted through the chain and is received from
only the last device. Layout is simpler because of point-to-point connection. The serial LVDS (low voltage
differential signaling) interface offers high- speed (200 Mbps) data transmission to enable the use of more
devices for a given throughput. The low differential swing in LVDS mode causes lower ground bounce in
the system and less crosstalk among the digital signals. This helps to achieve a better signal-to-noise ratio
in a system.
2
Description of the Device
The ADS8410 and ADS8413 are 16-bit 2-MSPS A/D converters with 4-V internal reference. The devices
include a capacitor-based SAR A/D converter with inherent sample and hold.
These devices offer a 200-Mbps serial LVDS interface. The interface is designed to support cascading
and daisy chaining of multiple devices. There is a mode to select 16/8-bit data frame to interface with shift
registers for converting the data to parallel format.
ADS8410 has pseudo-differential input stage. The –IN swing of ±200 mV is useful for compensating the
ground voltage mismatch between the ADC and the sensor and also for canceling the common-mode
noise.
The ADS8413 has unipolar differential input range, which supports differential input swing of –VREF to
+VREF with a common mode of +VREF/2.
The devices operate at a lower power when used at lower conversion rates, because of the nap feature.
Nap mode shuts down the device partially when the device is not converting.
These devices are available in a 48-pin QFN package.
3
Digital Interface
The ADS8410/13 offers 200 Mbps LVDS interface. LVDS is current output which terminates at the
receiver with a 100-Ω resistor which converts it to voltage. The high speed offers more device integration
in a system at a given ADC sampling rate. LVDS has a typical differential swing of ±680 mV (+680 mV for
logic 1 and –680 mV for logic 0) which is better in a low-noise system. The differential nature of this
signaling filters any common-mode noise.
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Definition of Daisy Chain
4
Definition of Daisy Chain
In daisy-chain mode, multiple devices are connected such that each device receives the previous devices’
data and transfers it along with its own data. Consider a situation where N devices are in the chain. The
second device receives the first device’s data and passes this data along with its own data to the third
device. The third device sends its own data along with first and second devices’ data. The Nth device
sends its own data with all N - 1 devices' data. Finally, one receiver is connected to the Nth device, which
collects all the data from the Nth device. Figure 1 shows how three (N = 3) devices work in a daisy chain.
st
1
Device
nd
D1
2
Device
rd
D2
D1
3
Device
D3
D2
D1
Receiver
Figure 1. Three Devices in Daisy Chain
5
Block Diagram
Figure 2 shows how four devices are connected in a daisy chain using the ADS8410/13. MODE C/D
(cascade or daisy-chain mode) has to be logic zero to operate in daisy-chain mode. The first device in
the chain is identified by LAT Y/N = 0. For all other devices, LAT Y/N = 1. LAT Y/N signifies that the
first device sends out data without latency and the other devices send out data with latency. Either
CSTART (LVDS) or CONVST(CMOS) is used as a conversion start signal. Depending on the CLK I/E
signal, the first device either takes in an external clock or generates an internal clock. This clock is
used as the master clock for all the devices in the daisy chain, and the interface is synchronized with
this clock. Other devices can only accept CLK_O from the previous device as an external clock. SDI
(Serial Data Input) and SYNC_I (Frame Sync Input) of the first device should be logic 0 (+ve terminal
to GND and –ve terminal to +VBD). BUS_BUSY = 1 signifies that the device is busy sending out data
in the bus. RD is Data Read Request to the Device and also acts as a handshake signal for
daisy-chain and cascade operation. RD = 1 brings about a 3-state device output. BUS_BUSY of the
last device can be connected to RD of the first device. Otherwise, BUS_BUSY of the last device should
be kept floating. RD of the first device should be connected to GND in this case.
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CLK_I
Separate CS , CONVST , CSTART
VDD
VDD
CLK I/E
LAT Y/N
SDO
SYNC_I SYNC_O
CLK_O
CLK_O
CLK_I
BUS_BUSY
RD
CSZ
CONVST
RD
CSTART
CSZ
CONVST
BUS_BUSY
CSTART
RD
CS
CONVST
CSTART
BUS_BUSY
CLK_O
SDI
BUS_BUSY
CSZ
SYNC_I SYNC_O
CLK_I
GND
GND
CLK I/E
SYNC_I SYNC_O
RD
IN4
VDD
LAT Y/N
SDO
CLK_I
MODE C/D
GND
SDI
Device #4
CONVST
SDO
SYNC_I SYNC_O
CLK_O
ANALOG IN
IN3
MODE C/D
GND
CLK I/E
SDI
Device #3
CSTART
SDO
ANALOG IN
VDD
LAT Y/N
VDD/GND
CLK I/E
GND
Device #2
Device #1
SDI
MODE C/D
GND
LAT Y/N
IN2
GND
MODE C/D
ANALOG IN
IN1
ANALOG IN
Timing
for each IC
Figure 2. Four Devices in Daisy-Chain Mode
6
Timing
6.1
Timing Requirements
in the following timing table, all specifications are typical at –40°C to 85°C, +VA= +5 V, +VBD = +5 V and
3.3 V (unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
REF
ns
Figure 3,
Figure 4
ns
Figure 3,
Figure 4
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
100
tconv Conversion time
tw1
4
391
Pulse duration, CONVST high
tw2
Pulse duration, CONVST low
td1
Delay time, CONVST rising edge to sample start
td2
Delay time, CONVST falling edge to conversion start
td3
Delay time, CONVST falling edge to busy high
td4
Delay time, conversion end to busy low
tw3
Pulse duration, CSTART high
Using ADS8410/13 in Daisy-Chain Mode
100
40
5
5
+VBD = 5 V
13
+VBD = 3.3 V
14
+VBD = 5 V
7
+VBD = 3.3 V
8
100
ns
Figure 3
ns
Figure 3,
Figure 4
ns
Figure 3
ns
Figure 3,
Figure 4
ns
Figure 3,
Figure 4
ns
Figure 3,
Figure 4
ns
Figure 3 ,
Table 1
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Timing
PARAMETER
MIN
TYP
MAX
45
UNIT
REF
ns
Figure 3,
Figure 4 ,
Table 1
tw4
Pulse duration, CSTART low
td5
Delay time, CSTART rising edge to sample start
7.5
ns
Figure 3,
Figure 4
Table 1
td6
Delay time, CSTART falling edge to conversion start
7.5
ns
Figure 3,
Figure 4
Table 1
td7
Delay time, CSTART falling edge to busy high
ns
Figure 3,
Figure 4
Table 1
ns
Figure 6
ns
Figure 6
ns
Figure 7
ns
Figure 7
ns
Figure 7
ns
Figure 6
+VBD = 5 V
15.5
+VBD = 3.3 V
16.5
I/O RELATED
6.2
td8
Delay time, RD falling edge while CS low to BUS_BUSY high
td9
Delay time, RD falling edge while CS low to SYNC_O and
SDO out of 3-state condition (for device with LAT_Y/N pulled
low)
td10
Delay time, pre_conversion end (point A) to SYNC_O and SDO out of
3-state condition
td11
Delay time, pre_conversion end (point A) to BUS_BUSY
high
td12
Delay time, conversion phase end to SYNC_O high
td13
Delay time, RD falling edge while CS low to SYNC_O high
tw5
Pulse duration, RD low for device in no latency mode
16
+VBD = 5 V
28
+VBD = 3.3 V
29
22
+VBD = 5 V
7
+VBD = 3.3 V
8
+VBD = 5 V
+VBD = 3.3 V
6
9 + tCLK
5 + 4*tCLK
8 + 5*tCLK
5.5 + 4*tCLK
8.5 + 5*tCLK
5
ns
Figure 9
ns
Figure 6,
Figure 7
ns
Figure 8,
Figure 10
4
ns
Figure 8,
Figure 10
11 + 0.5*tCLK
ns
Figure 10
ns
Figure 9
ns
Figure 7
+VBD = 5 V
1.3
+VBD = 3.3 V
1.4
td14
Delay time, CLK_O rising edge to data valid
td15
Delay time, BUS_BUSY low to SYNC_O high in daisy-chain
mode indicating receiving device to output data
td16
Delay time, CLK_O to SDO and SYNC_O 3-state
tpd1
Propagation delay time, SYNC_I to SYNC_O in daisy-chain mode
+VBD = 5 V
+VBD = 3.3 V
td18
Delay time, RD rising edge to BUS_BUSY high for device
with LAT_Y/N = 1
+VBD = 5 V
td19
Delay time, point A indicating clear for bus 3-state release to
BUSY falling edge
+VBD = 5 V
tclk
CLK frequency (serial data rate)
4*tCLK– 6
4*tCLK– 2.5
4*tCLK– 6.5
4*tCLK– 3
7
+VBD = 3.3 V
8
40
+VBD = 3.3 V
40.5
190
200
210
MHz
Sample and Convert
The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal.
Both signals are functionally identical. The following diagrams show control with CONVST. The rising edge
of CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in
the wait state. Figure 4 shows the case when the device is in the conversion phase at the rising edge of
CONVST. In this case, the sample phase starts immediately at the end of the conversion phase, and there
is no wait state.
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Timing
Figure 3. Sample and Convert With Wait (Less Than 2-MSPS Throughput)
Figure 4. Sample and Convert With No Wait or Back to Back (2-MSPS Throughput)
The device ends the sample phase and enters the conversion phase on the falling edge of CONVST
(CSTART). A high level on the BUSY output indicates an ongoing conversion. The device conversion time
is fixed. The falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing
conversion. A data read after a conversion abort fetches invalid data. Valid data is only available after a
sample phase and a conversion phase has completed. The timing diagram for control with CSTART is
similar to Figure 3 and Figure 4. Table 1 shows the equivalent timing for control with CONVST and
CSTART.
Table 1. CONVST and CSTART Timing Control
6.3
TIMING FOR CONTROL WITH
CONVST
TIMING FOR CONTROL WITH
CSTART
tw1
tw3
tw2
tw4
t1
t5
t2
t6
t3
t7
Data Read Operation
The ADS8413 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS
interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a
single device or multiple devices can be implemented with a daisy-chain or cascade configuration. The
following sections discuss data read timing when a single device is used.
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Timing
6.3.1
Data Read for a Single Device (See Table 1 for Device Configuration)
For a single device, the two possible read cycle starts are: a data read cycle start during a wait or sample
phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change
depending on MODE C/D selection. Figure 5 explains the data read cycle. The details of a read frame
start with the two previous listed conditions and a read cycle end with MODE C/D selection are explained
in Figure 6, Figure 7, and Figure 8, respectively.
See Figure 6
See Figures 7 and 8
RD
SYNC_O
CLK_O
1F
1R
18F 18R
2R
SDO
D15
D0
D14
BUS BUSY
Figure 5. Data Read With CS Low and BYTE = 0
As shown in Figure 5, a new data read cycle is initiated with the falling edge of RD, if CS is low and the
device is in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and
sets BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to
rising edge) if the BYTE input is held low and can be used to synchronize a data frame. The clock count
begins with the first CLK_O falling edge after a SYNC_O rising edge. The MSB is latched out on the
second rising edge (2R) and each subsequent data bit is latched out on the rising edge of the clock. The
receiver can shift data bits on the falling edges of the clock. The next rising edge of SYNC_O coincides
with the 16th rising edge of the clock. D0 is latched out on the 17th rising edge of the clock. The receiver
can latch the de-serialized 16-bit word on the 18th rising edge (18R, or the second rising edge after a
SYNC_O rising edge).
CS high during a data read results in a 3-state SYNC_O and SDO condition. These signals remain in the
3-state condition until the start of the next data read cycle.
6.3.2
Data Read Cycle Start During Wait or Sample Phase
As shown in Figure 6, the falling edge of RD, with CS low and when the device is in a wait or sample
phase, triggers the start of a read cycle. The cycle starts when BUS_BUSY goes high and SYNC_O, SDO
are released from the 3-state condition. SYNC_O is low at the start and rises to a high level td13 ns after
the falling edge of RD. As shown in Figure 6, the MSB is shifted on the 2nd rising edge of the clock (2R).
Other details about the data read cycle are discussed in the previous section (see Figure 5).
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Timing
td9
RD
td13
td8
BUSY
BUS_BUSY
0R
1F
1R
3R
CLK_O
SYNC_O
td14
SDO_O
MSB
MSB - 1
Figure 6. Start of Data Read Cycle With RD and CS Low and Device in Wait or Sample Phase
6.3.3
Data Read Cycle Start at End of Conversion Phase (Read Without Latency, Back-to-Back)
This mode is optimized for a data read immediately after the end of a conversion phase and ensures that
the data read is complete before the sample end while running at 2 MSPS. Point A in Figure 7 indicates
pre_conversion_end; it occurs td19 ns before the falling edge of BUSY or [(td2 + tcnv + td4) – td19] ns after
the falling edge of CONVST. A read cycle is initiated at point A if RD is issued before point A while CS is
low. Alternately, RD and CS can be held low. At the start of the read cycle, BUS_BUSY rises to a high
level and the LVDS outputs are released from the 3-state condition. The rising edge of SYNC_O, occurs
td12 ns after the conversion end. As shown in Figure 7, the MSB is shifted on the 2nd rising edge of the
clock (2R). Other details about the data read cycle are discussed in the previous section (see Figure 5).
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Timing
Conversion Phase
Conversion End
A
td19
RD_REQ (Int)
td11
td4
BUSY
td10
BUS_BUSY O/P
0R
1F
1R
2R
3R
CLK_O
td12
SYNC_O
td14
SDO_O
MSB
MSB − 1
Figure 7. Start of Data Read Cycle With End of Conversion
6.3.4
Data Read Cycle End (With MODE C/D = 0)
A data read cycle ends after all 16 bits have been serially latched out. Figure 8 shows the timing of the
falling edge of BUS_BUSY and the rising edge of SYNC_O with respect to SDO. SYNC_O rises on the
16th rising edge of CLK_O. As shown in Figure 6 and Figure 7, the MSB is shifted out on the 2nd rising
edge of CLK_O. Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST
CS = 0
BUS_BUSY
td15
SYNC_O
15R
16R
17R
18R
CLK_O
td16
SDO
LSB − 1
LSB
Figure 8. Data Read Cycle End With MODE C/D = 0
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Timing
The next two rising edges of CLK_O are shown as 17R and 18R in Figure 8. On 17R, the LSB is latched
out, and on 18R, SDO and SYNC-O go to a 3-state condition. Note that BUS_BUSY falls td15 ns before
the rising edge of SYNC_O when MODE C/D = 0. Care must be taken not to allow LVDS bus usage by
any other device until the end of the read cycle or (td15 + 2/fclk + td16) ns after the falling edge of
BUS_BUSY.
6.4
Timing Diagrams for Daisy-Chain Operation
The conversion speed for n devices in the chain must be selected such that:
• 1/conversion speed > read startup delay + n× (data frame duration) + td16
• Read startup delay = 10 ns + (td19– td4) + td12 + 2/fCLK
• Data frame duration = 16/fCLK
Note that it is unnecessary for all devices in the chain to sample the data simultaneously. But, all of the
devices must operate with the same exact conversion speed.
nth CONV
n + 1 Tracking
n + 1 Conversion
CONVST #1
See Figure 6 for details
CS
tw5
RD #1
BUS_BUSY #n
(Last device)
BUS_BUSY #1
RD #2
SDO #1
SDI #2
16−Bit Data
nth conversion
See Figure 12 for details
SYNC_O #1
SYNC_I #2
td18
BUS_BUSY #2
RD #3
#1 16−Bits
nth conversion
SDO #2
SDI #3
#2 16−Bits
nth conversion
SYNC_O #2
SYNC_I #3
Figure 9. Data Read Operation for Devices in Daisy-Chain Mode
6.5
Data Read Operation
On power up, BUS_BUSY of all of the devices is low. The devices receive CONVST or CSTART to
sample and start the conversion. The first device in the chain starts the data read cycle at the end of its
conversion. BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start.
Device 2 BUS_BUSY goes high on the rising edge of RD #1. This propagates until the last device in the
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Timing
chain. Device 2 receives CLK_I, SDI, and SYNC_I from device 1, and it passes all of these signals to the
next device. Device 2 (and every subsequent device in the chain) passes the received signals to its output
until it sees the falling edge of RD #1 (same as BUS_BUSY of the previous device). In daisy-chain mode,
BUS_BUSY for any device falls when it has passed all of the previous device data followed by its own
data. The falling edge of BUS_BUSY occurs before the rising edge of SYNC_O. This indicates to the
receiving device that the previous data chain is over, and it is now the receiving device's turn to output the
data. The device outputs the data from the last completed conversion. BUS_BUSY of the last device in the
chain is fed back to RD of the first device (or device 1 RD tied to 0). This makes sure that RD of device 1
is low before its conversion is over. The chain continues with only one external signal (CONVST or
CSTART) when CS is held low. Every device LVDS output goes to a 3-state condition once all data
transfer through the device has been completed. CS going high during the data read cycle of any device
places its SYNC_O and SDO in a 3-state condition. This halts the propagation of data through the chain.
To reset this condition, it is necessary to assert CS high for all devices. The new read sequence starts
only after CS for all devices is low before point A as shown in Figure 7. The high pulse on CS must be at
least 20 ns wide. It is better to connect CS of all of the devices together to avoid undesired halting of the
daisy chain.
CS = 0
BUS_BUSY #1
RD #2
td15
SYNC_O #1
SYNC_I #2
td16
15R
16R
17R
18R
CLK_O #1
CLK_I #2
SDO #1
SDO #2
LSB − 1
#1
LSB #1
BUSY_BUS #2 = 1
18R
17F 17R
CLK_O #2
tpd1
SYNC_O #2
#1 DATA
LSB − 1
#1
LSB #1
MSB
MSB − 1
#2 DATA
Figure 10. Data Propagation From Device n to Device n+1 in Daisy-Chain Mode
As shown in Figure 10, a propagation delay of tpd1 occurs from SYNC_I to SYNC_O or SDI to SDO. Note
that the data frames of all devices in the chain appear seamless at the last device output. The rising edge
of SYNC_O occurs at an interval of 16 clocks (or 8 clocks in BYTE mode); this can be used as data frame
sync. The deserializer at the output of the last device can shift the data on every falling edge of the clock
and it can latch the parallel 16-bit word on the second rising edge of CLK_O (shown as 18R) after every
rising edge of SYNC_O.
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Board Design Aspects
7
Board Design Aspects
7.1
Placement
Consider an application where four devices are operated in daisy-chain mode. There aretwo ways to do
this layout. The chain can be in a straight line fashion (as in Figure 11) or in a circular fashion (as in
Figure 12).
st
1
Device
nd
2
Device
rd
3
Device
th
4
Device
Receiver
Figure 11. Four Devices Placed in Straight Line Fashion
rd
3
Device
nd
2
Device
th
4
Device
Receiver
st
1
Device
Figure 12. Four Devices Placed in Circular Fashion
Any one of the layouts can be chosen depending on the area and shape of the printed-circuit board.
7.2
Signal Integrity
The device offers high speed LVDS CLK_O (Clock Output), SDO (Serial Data Output) and SYNC_O
(Frame Sync Output) signals which have a typical rise time of only 700 ps. According to LVDS standards,
the receiver termination needs to be 100 Ω (shunt resistance between +ve and –ve terminal of each LVDS
signals) to have proper voltage swing. To avoid reflection, the differential characteristic impedance needs
to match with the 100-Ω termination. So, CLK_O, SDO, and SYNC_O differential traces need to have
100-Ω differential characteristic impedance.
7.3
Termination Strategy
For point-to-point connection, LVDS signals are terminated with a 100-Ω resistor at the receiver end as
shown in Figure 13.
ADC
100 W
ADC
Figure 13. LVDS Driver/ Receiver in Point-to-Point Connection
The differential characteristic impedance of the line should be maintained close to 100 Ω. This strategy is
followed for signals which connect one ADC to another ADC. As an example, this is followed for the traces
between CLK_O of the first device and CLK_I (Clock Input) of the second device.
This method is not valid for the signals which connect the last device in the chain to two deserializers
which are in cascade (as shown in Figure 14).
12
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Board Design Aspects
ADC
SN65LVDS152
SN65LVDS152
Figure 14. CLK_O and SYNC_O Connection Between Last Device and the Deserializers
One way to terminate this structure is to have two 100-Ω resistor termination at both receiver ends (see
Figure 15). But because LVDS is a current source, two parallel resistors drive the voltage swing to half. If
your receiver has lower threshold than one half of LVDS differential swing and you have enough noise
margin for your system, you can use this termination strategy.
ADC
100 W
SN65LVDS152
100 W
SN65LVDS152
Figure 15. Terminating at Both Receivers
Another way to terminate is to put the termination at any one of the receiver ends. In this case, the signal
is reflected from the receiver which is not terminated. Make sure that the trace length of the unterminated
end from the common point is smaller than 0.6 inch (see Figure 16). This is valid for an FR4 printed-circuit
board.
Smaller Than 0.6 inch
ADC
SN65LVDS152
100 W
SN65LVDS152
Figure 16. Terminating at One Receiver
One more way to terminate in this case is to terminate at the driver end. The signal gets reflected from the
receiver ends once and gets absorbed at the driver end fully. Ensure that the trace length of the
unterminated trace from the common point (see Figure 17, in this case point A to B, C to D, A to E, or C to
F) is less than 0.6 inch.
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Board Design Aspects
A
ADC
100 W
C
B
D
SN65LVDS152
E
F
SN65LVDS152
Figure 17. Terminating at Source End
7.4
Layout Guidelines
ADS8410/13 offers high-speed digital interface. Analog and digital layout should not be mixed up. Analog
placement and routing should be separated from the digital placement and routing as far as possible. The
black line in Figure 18 is a virtual boundary for the analog and digital placement. Analog circuitry
(operational amplifiers and reference input) is on the left side of the boundary. The digital circuitry
(deserializer, clock multiplier, and digital buffers) is on the right side of the boundary.
14
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Board Design Aspects
Figure 18. Analog and Digital Circuitry Are Separated in the Layout With a Virtual Boundary
Each device (ADS8410/13) is rotated appropriately and placed such that LVDS outputs from the previous
device and LVDS inputs of the device connects in the shortest path. In Figure 19, the arrows indicate pin
number 1 for each device. Note that a device is rotated by 90 degrees with respect to the previous device
to make the LVDS lines short.
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Board Design Aspects
Figure 19. Devices Are Rotated and Placed to Reduce LVDS Trace Length
ADS8410/13 offers high-speed (200 Mbps) LVDS interface. Therefore, it is important to meet setup and
hold time requirements for LVDS signals. To achieve this, the length of CLK_O to CLK_I, SDO to SDI, and
SYNC_O to SYNC_I (Figure 20) should be equal. This is valid for LVDS signals between two devices and
also the LVDS signals between last device and the deserializers. Any length mismatch should be less
than 100 mils (1 mil = 1/1000 inch). Sometimes, traces are made serpentine in nature to match the length.
Figure 20 shows routing of LVDS signals between device 1 and 2. Also note that LVDS pairs are routed
differentially to make the differential characteristic impedance constant.
16
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System Block Diagram
CLK_I
CLK_O
SDI
SDO
SYNC_I
SYNC_O
Dev 2
Dev 1
Figure 20. LVDS Routing
8
System Block Diagram
Figure 21 and Figure 22 show how four devices in a daisy chain are tested. Figure 21 shows how first and
second devices are connected. A pattern generator is used to generate necessary control signals and
clock. A 25-MHz clock is generated from the pattern generator and is multiplied by a clock multiplier
(CDCF5801) to get a 200-MHz LVDS clock. CMOS to LVDS drivers (SN75LVDS389) are used to convert
from CMOS/ TTL to LVDS.
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System Block Diagram
DUT #2
CS
BUS_BUSY
CLK_O CONVST
CSTART
SDO
DUT#3
SYNC_O CLK_I
SDI
SYNC_I
RD
CMOS
LVDS
BUS_ BUSY
BUSY
VDD/GND
Through
Jumper
Settings
LAT Y/N
CLK I/E
BYTE,
MODE C/D
NAP, PD
CLK_O
SDO
SYNC_O
SDI
SYNC_I
CSTART
CS, RD
CLK_I
200 MHz
CLK
CONVST
Pattern
Generator
CMOS
to
LVDS
Driver
Clock
multiplier
(has PLL
inside)
25 MHz
CLK
DUT #1
Figure 21. First and Second Device in the Chain
Figure 22 shows how third and forth devices are connected. Serial data from the forth device is converted
to parallel by two cascaded SN65LVDS152
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De-Serialization
Last DUT #4
BUS_BUSY
To capture card
CLK_O
SDO
SYNC_O
D0-D15
RD
Deserialiser
BUS_BUSY#2
CLK_I
SDI
SYNC_I
CMOS
LVDS
BUS_ BUSY
BUSY
VDD/GND
Through
Jumper
Settings
CS
SYNC_O
LAT Y/N
CLK I/E
BYTE,
MODE C/D
NAP, PD
RD
CS,
CONVST
CLK_O
SDO
Pattern
Generator
DUT #2
CLK_I
SDI
SYNC_I
CSTART
Diff Driver
DUT #3
Figure 22. Third and Forth Device in the Chain
9
De-Serialization
The interface is compatible with the TI deserializer SN65LVDS152. SN65LVDS152 is a 10-bit deserializer.
Two such devices are cascaded to get 16-bit parallel data output. The following diagram shows the
connection of the deserializer with the ADC (this is the last ADC in the chain). Figure 23 shows this
connection with the necessary terminations.
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Limitation on Number of Devices in the Chain
DI+
DILCI+
LCICLK_O+
CLK_O-
MCIMCI+
COCO+
SDO+
SDOSYNC_O+
SYNC_OADS8410/13
100 W Resistor
SN65LVDS152
DI+
DILCI+
LCI-
MCIMCI+
COCO+
SN65LVDS152
Figure 23. Last ADC in the Chain and the Deserializers
10
Limitation on Number of Devices in the Chain
Theoretically, the number of devices that can be in daisy chained are unlimited. If more than four devices
are used, the sampling rate needs to be reduced. Seethe Timing Diagrams for Daisy Chain Operation
section of the ADS8410/13 data sheet for the relation between sampling rate and the number of devices in
a daisy chain. However, the duty cycle of the clock output (CLK_O) can be degraded to 40%–60% with
the internal clock mode operation or with the external clock mode operation (provided external input clock
(CLK_I) duty cycle is 50%) at 200 MHz. CLK_O of device 1 is CLK_I of device 2. So, device 2 sees a
clock with 40%–60% duty cycle as the external input clock. CLK_O of device 2 is further degraded.
Therefore, as the number of devices increases in a chain, the clock duty cycle of the last device can
degrade further which may cause setup and hold-time violation. But typically, four devices can be
operated in a daisy chain with a 200-MHz external or internal clock. If the clock frequency is reduced,
more devices can be integrated in the chain.
11
Results
11.1 Clock Duty Cycle
One important parameter when multiple devices are daisy chained is the clock duty cycle. An external
clock is used as an input to the first device, or the internal clock from the first device is used for the master
clock. This clock then travels through four devices and finally comes out from the fourth device as CLK_O.
SDO and SYNC_O are generated from the positive edge of CLK_O, but they are latched at the
deserializer at the negative edge of CLK_O. Any degradation in the duty cycle shifts the negative edge of
CLK_O with respect to the positive edge of CLK_O. This may violate setup and hold time. Careful design
of transmitters and receivers of ADS8410/13 ensures that the duty cycle degradation is within the limit.
Table 2 lists the measured duty cycle with both external and internal clock.
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Results
Table 2. Clock Duty Cycle
DUTY CYCLE
INPUT CLOCK
CLK_O #1
CLK_O #2
CLK_O #3
CLK_O #4
External clock
49%
56%
47%
58%
43%
Internal clock
–
52%
54%
51%
54%
The following Figure 24 through Figure 27 show CLK_I and CLK_O for four devices in a daisy chain. Blue
color denotes CLK_I, and pink color denotes CLK_O. An external clock of 49% duty cycle is used in these
examples.
Figure 24. CLK_I and CLK_O of Device 1
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Results
Figure 25. CLK_I and CLK_O of Device 2
Figure 26. CLK_I and CLK_O of Device 3
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Results
Figure 27. CLK_I and CLK_O of Device 4
11.2 Linearity Across Devices
Table 3 shows DNL and INL of ADS8413 versus the device number in the daisy chain. The data has been
captured for four devices in the chain at 200-MHz external clock, and 2-MSPS throughput.
Table 3. Linearity of Four Devices in the Chain
DEVICE
DNL
INL
MAX
MIN
MAX
MIN
1
0.88
–0.68
1.13
–1.62
2
0.87
–0.77
1.59
–1.15
3
0.88
–0.70
1.14
–1.30
4
0.79
–0.73
1.36
–1.21
11.3 SNR and THD Across Devices
Table 4 shows the ac performance of ADS8413 in the daisy chain. The data has been collected for four
devices with the input-signal frequency of 20 kHz at a sampling rate of 2 MSPS and an external clock of
200 MHz.
Table 4. SNR and THD of Four Devices in the Chain
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DEVICE
SNR
THD
1
91.07
–103.66
2
90.54
–105.74
3
91.38
–101.08
Using ADS8410/13 in Daisy-Chain Mode
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Conclusion
Table 4. SNR and THD of Four Devices in the
Chain (continued)
DEVICE
SNR
THD
4
91.39
–101.12
11.4 Overdrive Test
The ADS8410/13 works in daisy-chain mode excellently even if one or more devices are overdriven with
input voltage more than device power supply. This was tested with a power supply of 5 V. The inputs (IN+,
and IN–) were overdriven by 5.3 V (+0.3 V for IN– in case of ADS8410) and –0.3V (absolute maximum
rating). The overdriven device outputs SDO, SYNC_O, and CLK_O normally. The data from the
overdriven device may not be correct because absolute input voltage range is lower than this (–0.2 to Vref
+ 0.2). All other devices (without overdrive) function normally in the chain.
12
Conclusion
Daisy-chain mode offers a free-running clock which helps to synchronize digital circuitry easily. The
free-running nature of the clock offers the flexibility to use a PLL in the digital system. This system can run
with its own internal clock (clock is generated from the first device) or an external clock. The external clock
should be a free-running clock. The full frame (conversion and acquisition) of the sampling time of the
ADC is available for data transfer. This allows using four devices with a throughput of 2 MSPS. No
performance degradation was seen with four devices in a daisy-chain configuration.
24
Using ADS8410/13 in Daisy-Chain Mode
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Appendix A
Appendix A ADS8413EVM Daisy Chain Schematics, Layout, and Photograph
A.1
Schematics
The daisy chain schematics are affixed to this page.
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25
4
2
1
JUMPERX3P
LAT Y/N_A
LVDD
3
PD
J35
A
A
A
VA
1pF 100ohms
1%
JUMPERX3P
C330
NAP
J36
1
R58
100ohms
1pF
1%
2
C328 R61
VCC3.3
1pF
JUMPERX3P
3
J30
1
MODE C/D
TP105
TP8
2
A
VA
C28 C32
0.022uF
A
0.022uF
VA
A
C31
1pF
TP105
TP115
TP105
TP116
TP105
TP117
TP105
TP118
TP105
TP121
TP105
TP122
CLK_I-
TP105
TP33
A
CLK_I+
SDI-
B
A
SDI+
SYNC_I-
TP105
TP31
A
SYNC_I+
CSTART1-
TP105
TP29
A
CSTART1+
A
BVDD
0.001uF
C7 C22
0.1uF
this value has to be changed to 4.7u
A
A
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 01 07
SCALE
H=4ND; V=4LA
LVSS
CLK_I-
CLK_I+
SDI-(HIGH/LO)
CS
CONVST
BUS_BUSY
REFOUT
RD
NC
BUSY
AVDD
BVSS
AVSS
BVDD
48PIN,QFP,OZTEK
INP
SYNC_O+
DUT9
INM
SYNC_O-
AVSS(IN)
SDO+
AVDD(IN)
SDO-
AVDD(COMP)
CLK_O+
AVSS(COMP)
CLK_O-
PBKG(ANA)
LVDD
36
35
34
33
32
31
30
29
28
27
26
25
37 38 39 40 41 42 43 44 45 46 47 48
CS
BYTE
CONVST
PD
NAP
MODE C/D
CLK I/E
LAT Y/N
AVDD(REF)
AVSS(REF)
DUT8
PD
REFM
REFM
13 14 15 16 17 18 19 20 21 22 23 24
TP105
TP30
0.0039uF
0.001uF
A
100ohms
1%
TP105
TP113
TP105
TP114
LVDD
25
26
27
28
29
30
31
32
33
34
35
36
R27
C30 C25
0.001uF
A
C5
CLK_O1+
VA
VA
C26 C23
SDO1-
0.0022uF
0.0039uF
0.0022uF
C27 C24
0.0039uF
0.0039uF
VA
100ohms
1%
C329 R57
A
VA
100ohms
1%
100ohms
CLK_O11%
C335 R62
3
SDO1+
R29
VA
1
2
3
4
5
6
7
8
9
10
11
12
LVSS
PBKG(ANA)
CLK_O-
100ohms
1%SYNC_O1-
CLK_I-
AVSS(COMP)
CLK_O+
37 38 39 40 41 42 43 44 45 46 47 48
AVDD(COMP)
BVDD
CLK_O-
48 47 46 45 44 43 42 41 40 39 38 37
R28
BYTE
CS
CONVST
BYTE
PD
NAP
CLK I/E
MODE C/D
LAT Y/N
AVDD(REF)
SDO-
AVDD(IN)
2
VCC3.3
SDO+
A
A
C
TP105SYNC_O1+
CLK_I+
JUMPERX3P
1
AVSS(IN)
SYNC_O-
R18
RD
TP2
PBKG(DIG)
VCC3.3
INM
R17
49.9ohms BUSY1
CLK_O+
TP105
49.9ohms TP1 TP105
25
26
27
28
29
30
31
32
33
34
35
36
A
7X7 48RGZ SINGLE
GND
DUT10
CLK_I-
2
SYNC_O+
LVSS
VA
VA
BYTE
J34
1
A
INP
BVDD
CLK_I+
3
AVSS
SDI-(HIGH/LO)
JUMPERX3P
BUSY
BVSS
SDI+(HIGH/LO)
VCC3.3
A
RD
DUT12
INP1
INM1
BUS_BUSY
NC
SYNC_I-(M/S)
A
TP7
BUS_BUSY1
AVDD
SYNC_I+(M/S)
VA0F
REFOUT
CSTART-
C93
2
REFIN
AVSS(REF)
1%
0ohms
1%
LAT Y/N_A
CSTART+
J41
1
DVSS
3
10uF
DVDD
REFIN
PBKG(DIG)
JUMPERX3P
24 23 22 21 20 19 18 17 16 15 14 13
VCC3.3
REFM
1uF
C1 C3 C4
R1
+
R2
0ohms
0.01uF
REFM
12
11
10
9
8
7
6
5
4
3
2
1
A
REFM
PBKG(ANA)
2
SDI-(HIGH/LO)
A
AVDD(COMP)
AVSS(COMP)
SDI+(HIGH/LO)
CONVST1
SDOSYNC_I-(M/S)
CS1
CLK I/E_B
SDO+
AVDD(IN)
NAP
A
SYNC_O-
A
SDI+(HIGH/LO)
J33
BYTE
VA
AVSS(IN)
CSTART-
0ohms
BVDD
SYNC_O+
7X7 48RGZ SINGLE
GND
DUT8
INM
SYNC_I+(M/S)
J197
J190
R307
A
3
1
R211
1
1
INM1
INP
CLK I/E
JUMPERX3P
20ohms
1 0ohms
AVSS
MODE C/D
J76
GND
R204
BVSS
SYNC_I-(M/S)
VCC3.3
INMA
AVDD
SYNC_I+(M/S)
2
PD
RD
BUSY
CSTART+
CLK I/E_A
BUS_BUSY
NC
DVSS
J40
J2041
J2071
REFOUT
LAT Y/N
1
A
D
NAP
AVSS(REF)
3
1
1
CSTART-
J75
GND
JUMPERX3P
J199
J188
REFIN
CSTART+
VCC3.3
R209
1 0ohms
INP1
AVDD(REF)
INPA
DVSS
R210
20ohms
DVDD
CLK I/E_A
MODE C/D
PBKG(DIG)
2
REFM
12
11
10
9
8
7
6
5
4
3
2
1
LAT Y/N_B
REFM
J32
1
DVDD
3
24 23 22 21 20 19 18 17 16 15 14 13
VCC3.3
3
4
U10
1
2
3
4
REF_5V
C86 C80
0.1uF 0.001uF
3
NC
NC
+Vin
NC
EN
8
7
6
5
VREF
GND
NC
R60
1%
C85
R67
C91
C84 C89
0.1uF
D
10uF 1uF
1Kohms
1%
A
A
A
A
C59
0.1uF
0.1uF
+
R59
OPV+
C60
REF_DC
1Kohms
1uF
A
OPV-
1
1Kohms
VRE4141K
A
2
C35
0F
A
R43
R23
49.9ohms
OPV+
C341
+
V-
4
0ohms
Ccomp
3
R176
DC
+
C230 C228 C229
0.1uF
1 5
A
A
49.9ohms
A
10uF 1uF
C37
R173
0ohms
OPV+ 7
R186
0ohms
A
0F
R190
J53
GND
OPV-
R192
1 0ohms
0ohms
0ohms
A
A
2
+
R175
6
INMB
1 5
4
49.9ohms
DC
J59 1
U124
AD8021AR
3
J60 1
R184
8
DIS
6
AD8021AR
0F
R82
Ccomp
-
V+
U4
DIS
V+
2
REF_DC
8
LOG REF
7
A
V-
0ohms
LOG REF
A
C344
C
0F
OPV-
R181
A
0ohms
C33
A
J52
GND
0F
R21
OPV+ 7
0ohms
J27 1
REF_5V
DIS
1 5
C46 C6
C38
0.1uF 0.001uF
0F
OPV-
0ohms
R73
OPV-
0ohms
J18 1
0.1uF
R74
0ohms
A
A
J26 1
R69
NC
EN
GND
VREF
DIS
B
NC
REF_REFIN
1Kohms
1uF
VRE4141K
R75
0ohms
R66
C45
A
+
OPV+
REFIN
C92 C83 C90
0.1uF
10uF 1uF
R64
1Kohms
1%
A
A
A
A
C88
0F
A
R56
49.9ohms
OPV+
7
2
INPA
REF_REFIN
3
8
+
4
U9
6
AD8021AR
V-
+
Ccomp
J19 1
R50
3
+Vin
U5
6
AD8021AR
+
49.9ohms 4 1 5
C343
DC
0F
J57 1
8
7
6
5
A
8
LOG REF
J7
GND
R35
0ohms
-
V-
R48
1 0ohms
V+
OPV+ 7
2
NC
0ohms
49.9ohms
R39
0ohms
NC
R65
R22
A
C87
A
0F
0ohms
3
INPB
6
C81
C34
R38
1
2
3
4
A
J25 1
U123
AD8021AR
R174
DIS
4
49.9ohms
DC
-
REFIN
1 5
C82
49.9ohms 4 1 5
C36
DC
0F
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
0F
OPV-
OPV-
H=4ND; V=4LA
A
R72
0ohms
Ccomp
R70
2
U7
INMA
Ccomp
+
U6
6
AD8021AR
3
A
8
OPV-
0.1uF
A
-
LOG REF
J24 1
2
V-
R34
0ohms
A
R182
8
V+
R42
0ohms
J67 1
A
0ohms
R49
0ohms
49.9ohms
A
J6
GND
1 0ohms
LOG REF
0ohms
R191
V+
R41
R47
OPV+ 7
R177
C63
1 0ohms
49.9ohms
A
R189
A
R172
0ohms
DIS
0.1uF
C64
A
0F
C347
Ccomp
OPV+
0.1uF
OPV-
C348
C342
V+
A
OPV+
V-
A
OPV-
R180
0ohms
J66 1
A
0.1uF
C61
J61 1
R185
0ohms
A
0.1uF
0.1uF
C62
C345
0.1uF
0.1uF
C346
OPV+
0.1uF
OPV-
OPV+
LOG REF
OPV-
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 02 07
SCALE
4
3
C326
1pF
A
R165
C340
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
100ohms
SDO- 1%
SYNC_O+
TP105
TP129
TP105
TP131
A
R160
100ohmsSYNC_O1pF
VCC3.3
1%
A
TP105
TP48
A
VCC3.3
A
VCC3.3
C9
VCC3.3
CLK_I
VCC3.3
SDO+
TP105
TP124
TP105
TP123
TP105
TP49
2
C8 C11 C10
0.001uF 0.001uF
0.001uF
0.001uF
VCC3.3
A
CO-
A
R63
CO+
U3
DI+
Vcc
DI-
LVI
GND
MCI-
LCI+
MCI+
LCI-
GND
GND
DCO
CO_EN
DO-9
Vcc
DO-8
GND
DO-7
Vcc
DO-6
Vcc
DO-5
GND
DO-4
GND
DO-3
EN
DO-2
CO-
DO-1
CO+
DO-0
100ohms
VCC3.3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R162
CLK_O+
CLK_OA
R20
R19
R3
R4
R5
R6
R7
R8
R9
R10
100ohms
1%
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
C323
1pF
TP105
TP128
TP105
TP126
A
A
VCC3.3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
VCC3.3
C17
C16 C19 C18 C21 C20
CLK_I
CO+
C365C357
COSYNC_O+
A
SYNC_O-
R161
C322
100ohms
1%
1pF
VCC3.3
VCC3.3
A
A
VCC3.3
C13
C12 C15 C14
VCC3.3
0.001uF 0.001uF
0.001uF
0.001uF
A
A
DI-
LVI
GND
MCI-
LCI+
MCI+
LCI-
GND
GND
DCO
CO_EN
DO-9
Vcc
DO-8
GND
DO-7
Vcc
DO-6
Vcc
DO-5
GND
DO-4
GND
DO-3
EN
DO-2
CO-
DO-1
CO+
DO-0
VDDP
VDDO
GNDP
GNDO
GND
CLKOUT
NC
LEADLAG
DLYCTRL CLKOUTB
GNDPA
GNDO
VDDPA
VDDO
VDDPD
MULT0
STOPB
MULT1
PWRDNB
P2
1uF
J187
CLK_IB
JUMPERX3P VCC3.3
A VCC3.3
3
J2
1
JUMPERX3P VCC3.3
3
2
VCC3.3
OE 19
A
J4
1
D
G3
3EN1[BA]
3EN2[AB]
A
U127
DIR 1
A2
A3
A4
A5
A6
A7
A8
49.9ohms
RD
1
A1 2
R200
49.9ohms
CS3 R198
CSTART249.9ohms
R194
CS2 49.9ohms
R197
49.9ohms
CSTART1 R195
CS1 49.9ohms
R199
1pF 100ohms
1%
CLK_O49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
49.9ohms
R30
35.7ohms
U126
A
CSTART349.9ohms
CLK_O+
R11
R12
R13
R14
R15
R16
A
A
R193
CLK_IA
C339R163
A
VCC3.3
VCC3.3
2
20
Vcc
0.1uF GND
10
CLK_IB
VCC3.3
P1
VCC3.3
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
REFCLK
24
23
22
21
20
19
18
17
16
15
14
13
A
1
Vcc
P0
CDCF5801DBQ
3
DI+
VDDREF
A
JUMPERX3P
U2
A
0.001uF 0.001uF
0.001uF
0.001uF
0.001uF
0.001uF
SN65LVDS152DA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
U1
1
2
3
4
5
6
7
8
9
10
11
12
TP105
TP42
1
D10
D11
D12
D13
D14
D15
2
3
4
5
6
7
8
9
A
1uF
B2 CS_IN3
B3 CSTART_IN2
B4 CS_IN2
B5 CSTART_IN1
B6 CS_IN1
B7 RD_IN
C
B8
U127
OE 19
20
Vcc
0.1uF GND
10
G3
3EN1[BA]
3EN2[AB]
A
U126
DIR 1
R196
A
17
16
15
14
13
12
11
CSTART_IN3
SN74AHC245DW
VCC3.3
C366C358
18 B1
CSTART449.9ohms
1
A1 2
CS4 49.9ohms
A2
A3
A4
A5
A6
A7
A8
R201
SN65LVDS152DA
2
3
4
5
6
7
8
9
A
18 B1
CSTART_IN4
17
16
15
14
13
12
11
CS_IN4
B2
B3
B4
B5
B6
B7
B8
B
SN74AHC245DW
CSTART1+
R166
A
VCC3.3
CSTART1
SYNC_I
SDI
CLK_IA
A
0.0022uF
0.0039uF
VCC3.3
C79 C78 C462
VCC3.3
0.001uF
CSTART2
CSTART3
CSTART4
A
VCC3.3
0.0022uF
0.0039uF
VCC3.3
VCC3.3
C321C320 C461
0.001uF
A
A
22
21
20
SN75LVDS389DBT
CSTART1SYNC_I-
R167
R215
100ohms
1%
SDI+
1Kohms
R168
CLK_I+
100ohms
1%CLK_I-
R171
1
2
1Kohms
CSTART1
1Kohms
R296
R299
VCC3.3
R295
49.9ohms
1%
H=4ND; V=4LA
1Kohms
JUMPERX3P
3
0
2
R225
0
1Kohms
VCC3.3 49.9ohms
1%
1
CSTART2
100ohms
1%CSTART4-
CSTART4
J84
R226
CONVST2
100ohms
1%CSTART3CSTART4+
1
R297
R228
1Kohms
CSTART3+
3
CSTART4
49.9ohms
1%
CSTART2+
JUMPERX3P
CONVST4
J68
R214
0
VCC3.3
100ohms
1%CSTART2-
R170
R224
3
CSTART1
100ohms
1%SDI-
R169
JUMPERX3P
CONVST1
J220
0.001uF
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
R229
1Kohms
J83
A
JUMPERX3P
3
CONVST3
CSTART2
1
CSTART3
J221
VCC3.3
U125
J219
C311C310C460
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
J222
0.0022uF
0.0039uF
VCC3.3
100ohms
1%
SYNC_I+
VCC3.3
J85
CSTART3
2
0
R227
1Kohms
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
R298
49.9ohms
1%
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 03 07
SCALE
4
3
2
1
D0 1
J5
D1 3
J5
D2 5
J5
D3 7
J5
D4 9
J5
D5 11
J5
D6 13
J5
D7 15
J5
D8 17
J5
D9 19
J5
D10 21
J5
D11 23
J5
D12 25
J5
D13 27
J5
D14 29
J5
D15 31
P5
2
1
2
+
R53
CR1
348ohms
+
10uF
C56
10uF
A
LED3
P2PIN
MC 1,5/2-G-5,08
L2
700H
C53
VA
1
2
A
L5
700H
1
C70
1uF
A
REF_5V
+
C54
10uF
A
C69
1uF
CLK_I
A
P4
BVDD
1
2
+
C55 C67
348ohms
10uF
SYNC_I
RD_IN
1uF
LED5
CR2
P2PIN
MC 1,5/2-G-5,08
R55
SDI
A
1
3
5
7
9
11
13
15
17
19
2
4
A
6
8
10
A
12 P8
14
16
18
A
20
TSS-110-02-G-D
P6
VCC3.3
1
2
+
C58 C73
348ohms
10uF
1uF
LED1
CR5
P2PIN
MC 1,5/2-G-5,08
R52
+
LED2
CR4
C75
C76
C74
C77
10uF
+
MC 1,5/3-G-50
1
3
5
7
9
11
13
15
17
19
D
C
A
2
4
6
8
10
12 P9
14
16
18
20
A
OPV+
R51
2.87Kohms
P7
CS_IN1
CSTART_IN1
CS_IN2
CSTART_IN2
CS_IN3
CSTART_IN3
CS_IN4
CSTART_IN4
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
J5
33
J5
35
J5
37
J5
39
TSS-110-02-G-D
A
1
2
3
J5
J5
J5
J5
J5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J5
10uF
B
1uF
A
1uF
OPV-
A
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 04 07
SCALE
H=4ND; V=4LA
4
3
2
1
D
LAT Y/N_B
CLK I/E_B
MODE C/D
NAP
C
PD
VA
BYTE
CS2
CONVST2
A
CS
INM
GND
SYNC_O+
SYNC_O-
A
AVSS(IN)
SDO+
AVDD(IN)
SDO-
AVSS(COMP)
PBKG(ANA)
CLK_OLVDD
R242
49.9ohms
BUSY2
R240
A
TP105
TP105
BVDD
VCC3.3
3
TP77
J180
R248
1
BUS_BUSY1
4
2
TP105
SYNC_O2+
JUMPER4P,THRU
100ohms
SYNC_O21%
R250
100ohms
1%
VA
R252
SDO2+
B
SDO2CLK_O2+
100ohms
CLK_O21%
25
26
27
28
29
30
31
32
33
34
35
36
A
CLK_O+
LVSS
AVDD(COMP)
37 38 39 40 41 42 43 44 45 46 47 48
BYTE
CONVST
PD
NAP
MODE C/D
CLK I/E
LAT Y/N
AVSS(REF)
AVDD(REF)
DUT13
CLK_I-
A
INP
BVDD
CLK_I+
A
7X7 48RGZ SINGLE
AVSS
SDI-(HIGH/LO)
0ohms
A
BVSS
SYNC_I-(M/S)
VA
VA
R306
A
A
A
C441
R262
VA
C411C404
A
VA
C410C394
0.022uF
A
VA
C420
A
C382
C400
C406
0.0039uF
0.001uF
C437 R261
A
TP105
TP112
TP105
TP111
1pF 100ohms
1%
C443
R264
C384C390
1pF
0.1uF
this value has to be changed to 4.7u
0.001uF
A
TP105
TP55
BVDD
0.001uF
TP105
TP108
TP105
TP107
1pF 100ohms
1%
A
VA
C398C392
A
VA
0.0022uF
VA
0.0039uF
VA
TP105
TP109
TP105
TP110
1pF 100ohms
1%
C442
R263
0.022uF
J202
J192
1
1
0.0022uF
1 0ohms
INM2
0.0039uF
J141
GND
R275
0.0039uF
INMB
A
AVDD
SDI+(HIGH/LO)
INP2
INM2
R276
20ohms
VA
A
J2081
J211 1
A
0F
RD
DUT11
C424
CSTART-
1
1
49.9ohmsTP79
BUS_BUSY
BUSY
SYNC_I+(M/S)
R278
J200
J189
BUS_BUSY2
NC
CSTART+
1 0ohms
INP2
DVSS
J142
GND
20ohms
REFOUT
DVDD
INPB
REFIN
PBKG(DIG)
1%
0ohms
1%
R277
24 23 22 21 20 19 18 17 16 15 14 13
10uF
REFM
C373C376
C379
R230
+
R233
0.01uF 0ohms
REFM
1uF
REFIN
TP53
12
11
10
9
8
7
6
5
4
3
2
1
A
100ohms
1%
TP105
TP120
TP105
TP119
CLK_O1-
TP105
TP57
A
CLK_O1+
SDO1-
TP105
TP56
SDO1+
SYNC_O1-
TP105
TP59
SYNC_O1+
CSTART2-
A
A
TP105
TP58
A
A
CSTART2+
A
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 05 07
SCALE
H=4ND; V=4LA
4
3
2
1
D
LAT Y/N_B
CLK I/E_B
MODE C/D
NAP
PD
VA
CS3
BYTE
CONVST3
TP61
A
J196
J194
CS
DUT10
CLK_I-
CLK_OLVSS
PBKG(ANA)
CLK_I+
AVSS(COMP)
CLK_O+
SDI-(HIGH/LO)
AVDD(COMP)
LVDD
37 38 39 40 41 42 43 44 45 46 47 48
CONVST
BYTE
PD
NAP
CLK I/E
MODE C/D
LAT Y/N
AVDD(REF)
SDOSDI+(HIGH/LO)
A
R305
A
R244
3
49.9ohms
BUSY3
R238
A
A
A
R251
C438
TP105
TP63
1pF 100ohms
1%
A
R249
C447
1pF 100ohms
1%
VA
VA
C413C405
A
VA
C412C396
0.022uF
A
VA
A
R265
C444
BVDD
0.001uF
C386C389
0.1uF
this value has to be changed to 4.7u
0.001uF
A
1pF 100ohms
1%
0.0039uF
A
C383
R247
C446
C402C408
0.001uF
VA
C399C393
A
VA
C419
1pF
TP75
TP105
BVDD
J181
SYNC_O3+
1
BUS_BUSY2
4
2
JUMPER4P,THRU
R254
100ohms
SYNC_O31%
SDO3+
R256
100ohms
1%SDO3VA
CLK_O3+
R258
100ohms
CLK_O31%
A
A
C
TP105
TP78
0ohms
0.022uF
1 0ohms
1
1
SDO+
AVDD(IN)
INM3
0.0022uF
R270
0.0039uF
J146
GND
20ohms
0.0039uF
INMA
SYNC_O-
A
SYNC_I-(M/S)
R271
AVSS(IN)
SYNC_I+(M/S)
J2051
J2061
A
A
INM
CSTART-
1
1
VA
VA
SYNC_O+
7X7 48RGZ SINGLE
GND
DUT12
49.9ohms
25
26
27
28
29
30
31
32
33
34
35
36
J198
J191
INP3
INP
BVDD
VA
R268
1 0ohms
A
BVSS
0.0022uF
J145
GND
20ohms
0.0039uF
INPA
INP3
INM3
RD
AVDD
CSTART+
R269
BUS_BUSY
BUSY
AVSS
TP105
VCC3.3
NC
DVSS
A
AVSS(REF)
REFM
C425
VA 0F
REFOUT
DVDD
1%
0ohms
1%
REFIN
PBKG(DIG)
24 23 22 21 20 19 18 17 16 15 14 13
10uF
C374C378C381
R231
+
R234
0ohms
0.01uF
REFM
1uF
REFIN
BUS_BUSY3
12
11
10
9
8
7
6
5
4
3
2
1
A
100ohms
1%
TP105
TP93
TP105
TP94
CLK_O2-
TP105
TP67
B
A
TP105
TP85
TP105
TP86
TP105
TP89
TP105
TP90
CLK_O2+
SDO2-
TP105
TP64
A
SDO2+
SYNC_O2-
TP105
TP65
A
TP105
TP99
TP105
TP100
SYNC_O2+
CSTART3-
TP105
TP62
A
CSTART3+
A
A
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 06 07
SCALE
H=4ND; V=4LA
4
3
2
1
D
VA
C414C397
A
C403C409
0.001uF
A
0.022uF
PD
BVDD
C385
0.001uF
C388C391
0.1uF
this value has to be changed to 4.7u
0.001uF
A
MODE C/D
NAP
A
A
VA
C401C395
TP105
TP68
0.0039uF
A
VA
0.0039uF
C421
0.022uF
LAT Y/N_B
CLK I/E_B
VA
0.0022uF
C415C407
0.0039uF
VA
0.0022uF
0.0039uF
VA
A
A
BYTE
VA
A
CONVST4
CS4
INMB
J143
GND
20ohms
1 0ohms
R280
J203
J195
INM4
1
1
CS
37 38 39 40 41 42 43 44 45 46 47 48
CONVST
BYTE
PD
NAP
CLK I/E
MODE C/D
LAT Y/N
AVDD(REF)
AVSS(REF)
REFM
DUT13
SDO+
A
SDO-
AVDD(IN)
AVSS(COMP)
PBKG(ANA)
CLK_O+
CLK_OCLK_I-
AVDD(COMP)
LVDD
R236
3
49.9ohms BUSY4 TP76
TP105
R239
SYNC_O+
A
BVDD
A
A
A
C440
R257
1pF 100ohms
1%
2
JUMPER4P,THRU
100ohms
1%SYNC_O-
R266
100ohms
1%SDOVA
CLK_O+
R260
TP105
TP83
TP105
TP84
C439
R255
TP105
TP87
TP105
TP88
C448
R253
TP105
TP91
TP105
TP92
1pF 100ohms
1%
1pF 100ohms
1%
C445
R246
1pF
BUS_BUSY3
4
1
100ohms
CLK_O1%
CLK_O3A
A
R259
J182
SDO+
R304
0ohms
VCC3.3
TP74 TP105
49.9ohms
25
26
27
28
29
30
31
32
33
34
35
36
R274
A
AVSS(IN)
SYNC_O-
LVSS
A
J2091
J2101
INM
CLK_I+
R272
J201
J193
1
1
SYNC_O+
7X7 48RGZ SINGLE
GND
DUT11
SDI-(HIGH/LO)
J144
GND
1 0ohms
INP4
A
INP
BVDD
VA
INPB
VA
VA
AVSS
SDI+(HIGH/LO)
R273
20ohms
A
BVSS
SYNC_I-(M/S)
INP4
INM4
RD
AVDD
SYNC_I+(M/S)
A
BUS_BUSY
BUSY
CSTART-
0F
TP105
NC
CSTART+
C426
REFOUT
DVSS
VA
REFIN
DVDD
1%
0ohms
1%
PBKG(DIG)
10uF
24 23 22 21 20 19 18 17 16 15 14 13
REFIN
C375C377C380
R232
+
R235
0ohms
0.01uF
REFM
1uF
C
TP66
12
11
10
9
8
7
6
5
4
3
2
1
A
100ohms
1%
TP105
TP98
TP105
TP97
TP105
TP70
B
A
CLK_O3+
SDO3-
TP105
TP71
A
SDO3+
SYNC_O3-
TP105
TP72
A
SYNC_O3+
CSTART4TP105
TP73
CSTART4+
A
A
EXAS INSTRUMENTS
TSEMICONDUCTOR
OPERATIONS
CODE IDENTITY
NUMBER
01295
SHEET
@REV
C
N SIZE @EDGE_NUMBER REV 07 07
SCALE
H=4ND; V=4LA
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Daisy Chain Board Layout
A.2
Daisy Chain Board Layout
The daisy chain board layout is affixed to this page.
26
Using ADS8410/13 in Daisy-Chain Mode
SLAA296 – May 2006
Submit Documentation Feedback
1
2
3
1
GND
1
1
1
1
2
2
2
2
1
1
1
1
2
2
1
2
2
6
7
8
5
2
1
1
1
2
2
2
1
2
2
2
1
2
2
1
1
1
GND
GND
2
2
GND
1
1
1
GND
GND
1
2
2
2
2
GND
GND
GND
GND
1
1
1
1
1
1
2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
2
1
2
2
2
1
1
1
2
2
1
2
1
2
1
1
1
1
1
2
2
2
1
2
2
2
1
1
1
1
2
2
2
9
8
7
6
5
4
3
2
1
20
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
2
2
1
2
13
14
15
16
17
18
19
20
21
22
23
24
2
1
1
2
1
1
2
1
2
1
3
1
1
1
2
1
1
2
1
2
1
2
1
1
2
1
1
1
1
3
2
4
1
2
1
1
2
1
1
1
2
1
1
1
2
2
1
2
1
1
1
4
2
1
2
1
2
1
1
1
1
2
1
2
1
1
1
1
2
1
2
1
2
2
1
1
2
1
2
1
1
2
1
1
1
2
2
2
1
1
1
1
2
1
2
2
1
2
2
1
2
1
1
1
1
2
1
1
2
1
2
1
1
2
2
1
1
1
2
2
1
2
1
2
1
1
2
2
1
1
1
2
1
10
1
19
1
1
1
1
1
11
3
3
1
2
2
1
1
2
12
1
1
1
2
1
13
5
2
2
1
2
2
1
14
2
1
2
2
1
7
2
2
1
1
1
2
1
1
2
15
8
4
GND
1
2
17
16
2
2
2
1
2
2
2
1
1
1
1
1
2
1
1
1
2
2
1
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
19
18
9
1
2
1
1
2
2
1
2
GND
2
20
11
10
1
4
3
2
2
1
1
2
1
1
1
2
1
1
1
1
1
2
1
2
2
13
12
2
2
6
5
15
14
2
1
2
1
1
3
4
17
16
6
1
1
8
7
19
18
1
1
1
2
20
GND
1
1
1
GND
1
1
GND
1
2
GND
1
GND
1
2
2
1
1
1
2
1
GND
1
2
2
1
1
2
2
1
1
1
2
2
1
1
6
7
8
5
5
6
7
8
1
GND
2
2
2
1
2
2
5
6
7
8
1
1
2
1
2
1
2
2
1
5
6
7
8
2
1
1
2
2
1
1
1
1
2
1
2
1
1
1
2
1
1
1
2
1
1
2
2
2
2
2
1
2
2
2
2
1
1
1
1
2
1
2
1
3
2
1
4
3
2
1
1
2
1
1
4
2
1
1
2
2
1
2
1
2
1
1
1
1
2
2
2
2
2
1
2
1
2
1
1
1
1
1
1
2
1
2
2
1
2
2
1
1
2
2
1
2
1
GND
1
1
2
GND
1
4
3
2
1
1
2
2
1
1
2
2
2
1
4
1
1
1
2
2
1
1
1
2
1
1
1
2
1
1
1
2
3
2
1
1
1
2
1
8
2
1
2
1
2
2
1
3
7
1
2
2
4
6
2
1
5
2
2
3
1
2
2
1
1
2
GND
2
2
1
1
1
GND
1
1
1
2
GND
1
2
GND
1
GND
GND
4
3
2
1
GND
1
GND
GND
GND
2
GND
1
GND
2
GND
1
2
3
4
3
2
1
1
1
1
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
1
3
1
2
1
1
1
1
2
1
2
2
1
2
1
2
2
1
2
1
2
GND
1
2
1
2
1
2
1
1
2
1
1
2
2
2
1
1
2
2
2
1
1
1
2
2
2
1
2
3
1
2
3
1
3
2
1
1
1
2
1
1
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
1
2
2
2
2
1
2
1
2
1
1
1
3
1
1
2
1
1
2
2
2
1
1
1
1
2
1
1
1
2
2
1
2
2
12
11
10
9
8
7
6
5
4
3
2
1
2
2
1
2
1
1
1
1
1
3
1
2
3
2
1
1
2
1
1
2
2
2
1
1
2
1
2
2
2
2
1
2
1
2
1
2
1
1
2
1
2
2
1
1
1
1
2
2
1
2
2
1
3
2
1
3
2
GND
3
1
2
1
1
2
2
3
1
1
1
1
2
2
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
1
2
1
2
1
2
1
1
3
2
2
2
1
1
1
1
1
2
1
3
2
2
1
1
1
2
2
1
5
6
7
8
2
1
2
2
1
2
1
2
1
1
1
2
3
1
1
1
1
1
1
2
1
1
3
1
1
1
1
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
1
1
1
2
1
1
1
1
1
2
1
GND
GND
1
GND
D
GND
2
2
2
2
1
1
1
1
GND
GND
GND
1
GND
GND
1
GND
GND
GND
2
2
2
2
1
1
1
1
GND
GND
1
GND
GND
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Daisy Chain Board Photograph
A.3
Daisy Chain Board Photograph
SLAA296 – May 2006
Submit Documentation Feedback
Using ADS8410/13 in Daisy-Chain Mode
27
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