Subtractors
Half subtractors
Half subtractors represent the smallest block for subtraction in digital computers. What
they do is very simple: they subtract two bits, producing a difference and a borrow.
The logic is straightforward. Subtracting two 0s or two 1s results in 0. Subtracting 0 from
1 results in 1. Subtracting 1 from 0 results in a borrow where 1 is the borrow bit and 0 is
the difference bit.
0
0
1
1
-
0
1
0
1
= 0
= -1
= 1
= 0
The operation can be tabulated as follows:
Inputs
A
B
0
0
0
1
1
0
1
1
Outputs
Bout D
0
0
1
1
0
1
0
0
Truth table for a half subtractor
The expressions for the borrow and difference bits are B  A  B and D  A  B .
The circuit for the half subtractor is the following:
OFFTIME = .5uS B
ONTIME = .5uS CLK
DELAY = 5nS
STARTVAL = 1
OPPVAL = 0
U1A
U3A
V
1
B
1
3
2
2
74LS08
74LS04
V
U2A
D
1
OFFTIME = 1uS A
ONTIME = 1uS CLK
DELAY = 5nS
STARTVAL = 1
OPPVAL = 0
3
2
V
74LS386A
V
Circuit for a half subtractor
1
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The half subtractor consists of an AND gate that provides the carry bit and an XOR gate
that provides the difference bit. An additional NOT gate is used to invert A and provide
the correct logic for the borrow bit.
In high-level schematics, the half subtractor is often shown as a block:
Half subtractor block
The waveforms for the half subtractor reflect the logic previously outlined:
A:1
B:1
U1A:Y
U2A:Y
0s
0.5us
1.0us
1.5us
2.0us
Time
Waveforms for a half subtractor
The half subtractor produces a borrow bit only when A is 0 and B is 1 and it produces a
difference bit only if one of the input bits is 1.
2
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Full subtractors
Full subtractors are the next step after half subtractors. What they do is very simple:
they subtract three bits and they produce a difference and a borrow.
The logic is not so straightforward.
The operation can be tabulated as follows:
A
0
0
0
0
1
1
1
1
Inputs
B
Bin
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Outputs
Bout D
0
0
1
1
1
1
1
0
0
1
0
0
0
0
1
1
Truth table for a full subtractor
One of the bits is a borrow-in bit that comes from a previous stage. That bit is shown in
the third column. The borrow-out bit that results from the operation is passed on to a
higher level within the subtractor.
The expressions for the borrow and difference bits are:


Bout  A  B Bin  A  B
3
D  A  B  Bin
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The circuit for the full subtractor is the following:
U1A
OFFTIME = .5uS C
ONTIME = .5uS CLK
DELAY = 5nS
STARTVAL = 1
OPPVAL = 0
U2A
1
3
D
1
2
V
3
2
74LS386A
OFFTIME = 1uS B
ONTIME = 1uS CLK
DELAY = 5nS
STARTVAL = 1
OPPVAL = 0
V
74LS386A
V
OFFTIME = 2uS A
ONTIME = 2uS CLK
DELAY = 5nS
STARTVAL = 1
OPPVAL = 0
VCC
V
U3A
U6A
2
1
3
3
VCC
3
1
U7A
1
2
74LS08
U4A
R1
1k
B
1
74LS266
V1
U5A
1
2
V
74LS32
3
2
2
74LS08
74LS04
5Vdc
0
Circuit for a full subtractor
The full subtractor is a little more complex than the previous circuits. It consists of 7
gates: 2 XOR, 1 XNOR, 2 AND, 1 NOT and 1 OR. The XOR gates provide the
difference bit while the rest of the gates provides the borrow bit. The 74LS266 XNOR
gate requires a pull-up resistor because it has an open collector.
In high-level schematics, the full subtractor is often shown as a block:
Block for a full subtractor
The waveforms for the full subtractor reflect the logic previously outlined:
A:1
B:1
C:1
U2A:Y
U5A:Y
0s
0.5us
1.0us
1.5us
2.0us
2.5us
3.0us
3.5us
4.0us
Time
Waveforms for a full subtractor
4
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