Lecture 12
Digital Circuits (II)
MOS INVERTER CIRCUITS
Outline
• NMOS inverter with resistor pull-up
–The inverter
• NMOS inverter with current-source pull-up
• Complementary MOS (CMOS) inverter
• Static analysis of CMOS inverter
Reading Assignment:
Howe and Sodini; Chapter 5, Section 5.4
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1. NMOS inverter with resistor pull-up:
Dynamics
•
CL pull-down limited by current through transistor
– [shall study this issue in detail with CMOS]
•
•
CL pull-up limited by resistor (tPLH ≈ RCL)
Pull-up slowest
VDD
VDD
R
R
VOUT:
LO HI
VOUT:
HI LO
VIN:
LO HI
CL
VIN:
HI LO
pull-up
pull-down
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CL
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1. NMOS inverter with resistor pull-up:
Inverter design issues
Noise margins ↑ ⇒ |Av| ↑⇒
•
•
R ↑ ⇒ |RCL| ↑⇒ slow switching
gm ↑ ⇒ |W| ↑⇒ big transistor
– (slow switching at input)
Trade-off between speed and noise margin.
During pull-up we need:
•
•
High current for fast switching
But also high incremental resistance for high noise
margin.
⇒ use current source as pull-up
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2. NMOS inverter with current-source pull-up
I—V characteristics of current source:
iSUP
+
vSUP
1
roc
ISUP
iSUP
_
vSUP
Equivalent circuit models :
iSUP
+
vSUP
ISUP
roc
roc
_
large-signal model
•
•
•
•
small-signal model
High current throughout voltage range vSUP > 0
iSUP = 0 for vSUP ≤ 0
iSUP = ISUP + vSUP/ roc for vSUP > 0
High small-signal resistance roc.
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NMOS inverter with current-source pull-up
VDD
Static Characteristics
iSUP
VOUT
VIN
CL
Inverter characteristics :
iD
V
ISUP + rDD
oc
4
VIN = VGS
3
2
1
VDD
vOUT = vDS
(a)
VOUT
1
2
3
4
VIN
(b)
High roc ⇒ high noise margins
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PMOS as current-source pull-up
I—V characteristics of PMOS:
+ S+
VSG
_
VSD
G
VG
B
−IDp
+
−
+
−
_
D
5V
+ V
D
−
−ID(VSG ,VSD)
(a)
VSG = 3.5 V
300
250
−IDp
(µA)
VSD = VSG + VTp = VSG − 1 V
(triode
region)
VSG = 3 V
200
(saturation region)
150
VSG = 25
100
VSG = 0, 0.5, 1 V
(cutoff region)
VSG = 2 V
50
VSG = 1.5 V
1
2
3
4
VSD (V)
5
(b)
Note: enhancement-mode PMOS has VTp <0.
In saturation:
(
− IDp ∝ VSG + VTp
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PMOS as current-source pull-up:
Circuit and load-line diagram of inverter with PMOS
current source pull-up:
VDD
PMOS load line for VSG=VDD-VB
-IDp=IDn
VDD
VB
VOUT
VIN
VIN
CL
0
0
VDD
VOUT
Inverter characteristics:
NMOS cutoff
PMOS triode
VOUT
NMOS saturation
PMOS triode
VDD
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
0
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0
VTn
VDD
Lecture 12
VIN
7
PMOS as current-source pull-up:
NMOS inverter with current-source pull-up allows high
noise margin with fast switching
• High Incremental resistance
• Constant charging current of load capacitance
But…
When VIN = VDD, there is a direct current path between
supply and ground
⇒ power is consumed even if the inverter is idle.
VDD
PMOS load line for VSG=VDD-VB
-IDp=IDn
VDD
VB
VOUT:LO
VIN
VIN:HI
CL
0
0
VDD
VOUT
Ideally, we would like to have a current source that is
itself switchable, i.e it shuts off when input is high
⇒ CMOS!
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3. Complementary MOS (CMOS) Inverter
Circuit schematic:
VDD
VIN
VOUT
CL
Basic Operation:
•
VIN = 0 ⇒ VOUT = VDD
VGSn = 0 < VTn
⇒
VSGp = VDD > - VTp ⇒
•
NMOS OFF
PMOS ON
VIN = VDD ⇒ VOUT = 0
VGSn = VDD > VTn
VSGp = 0 < - VTp
⇒
⇒
NMOS ON
PMOS OFF
No power consumption while idle in any logic state!
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VOUT
VDD 1
2
CMOS Inverter (Contd.):
3
Output characteristics of both transistors:
4
5
VDD
VIN
−IDp = IDn
IDn = −IDp
VIN
3
3
4
1
5
VDD
n-channel
(a)
2
4
2
VOUT
1
VDD
5
VOUT
p-channel
(b)
Note:
VIN = VGSn = VDD -VSGp ⇒ VSGp=VDD - VIN
VOUT = VDSn = VDD -VSDp ⇒ VSDp=VDD - VOUT
IDn = -IDp
Combine into single diagram of ID vs. VOUT with VIN as
parameter
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CMOS Inverter (Contd.):
ID
VDD-VIN
VIN
0
0
VOUT
• No current while idle in any logic state
Inverter Characteristics:
NMOS cutoff
PMOS triode
VOUT
NMOS saturation
PMOS triode
VDD
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
NMOS triode
PMOS cutoff
0
0
VTn
VDD+VTp VDD VIN
• “rail-to-rail” logic: logic levels are 0 and VDD
• High |Av| around logic threshold
⇒ good noise margins
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2. CMOS inverter: noise margins
VOUT
NML
VDD
Av(VM)
VM
0
0
VILVM VIH
VDD VIN
NMH
•
•
•
Calculate VM
Calculate Av(VM)
Calculate NML and NMH
Calculate VM (VM = VIN = VOUT)
At VM both transistors are saturated:
I Dn
Wn
2
=
µ nCox (VM − VTn )
2Ln
− IDp =
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Wp
2Lp
µ pCox (VDD − VM + VTp )
2
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CMOS inverter: noise margins (contd.)
Define:
kn =
Wn
µn Cox ;
Ln
kp =
Wp
µp Cox
Lp
Since :
I Dn = −IDp
Then:
(
1
1
2
kn (VM − VTn ) = kp VDD − VM + VTp
2
2
)
2
Solve for VM:
VTn +
VM =
kp
kn
1+
(VDD + VTp )
kp
kn
Usually, VTn and VTp fixed and VTn = - VTp
⇒ VM engineered through kp/kn ratio.
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CMOS inverter: noise margins (contd..)
• Symmetric case: kn = kp
VDD
VM =
2
This implies:
Wp
Wp
µ pCox
kp
L
= 1 = Wp
kn
n µ C
n ox
Ln
≈
µp
Lp
Wn
2µ p
Ln
⇒
Wp
W
≈2 n
Lp
Ln
Since usually Lp ≈ Ln = Lmin ⇒ Wp ≈ 2Wn
• Asymmetric case:
kn >> kp , or
Wp
Wn
>>
Ln
Lp
VM ≈ VTn
NMOS turns on as soon as VIN goes above VTn.
• Asymmetric case:
kn << kp , or
Wp
Wn
<<
Ln
Lp
VM ≈ VDD + VTp
PMOS turns on as soon as VIN goes below VDD + VTp.
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CMOS inverter: noise margins (contd…)
Calculate Av(VM)
• Small signal model:
S2
+
vsg2=-vin
-
+
vin
-
+
gmpvsg2
rop
G2
D2
G1
D1
+
vgs1
gmnvgs1
vout
ron
-
-
S1
G1=G2
D1=D2
+
+
vin
gmnvin
gmpvin
ron//rop
-
vout
-
S1=S2
(
)(
A v = − g mn + gmp ron // rop
)
This can be rather large.
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CMOS inverter: calculate noise margins
(contd.)
VOUT
NML
VDD
Av(VM)
VM
0
VILVM VIH
0
VDD VIN
NMH
• Noise-margin low, NML:
VIL = VM −
VDD − VM
Av
NM L = VIL − VOL = VIL = VM −
VDD − VM
Av
• Noise-margin high, NMH:
VIH
⎛
1 ⎞
⎟
= VM ⎜1 +
Av ⎠
⎝
NM H = VOH − VIH
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⎛
1 ⎞
⎜
⎟
= VDD − VM 1+
Av ⎠
⎝
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What did we learn today?
Summary of Key Concepts
• In NMOS inverter with resistor pull-up, there is a
trade-off between noise margin and speed
• Trade-off resolved using current source pull-up
– Use PMOS as current source.
• In NMOS inverter with current-source pull-up: if
VIN = High, there is power consumption even if
inverter is idling.
• Complementary MOS: NMOS and PMOS switchon alternatively.
– No current path between power supply and ground
– No power consumption while idling
• Calculation of CMOS
– VM
– Noise Margin
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