台灣新竹‧交通大學‧前瞻電力電子中心 808實驗室 (電力電子系統與晶片實驗室)
PWM DC-AC Converters (Inverters)
脈寬調變DC-AC轉換器 (變流器)
鄒應嶼 教 授
國立交通大學
電機控制工程研究所
2016年5月25日
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Advanced Power Electronics Center, NCTU, Taiwan
Power Electronic Systems & Chips Lab., NCTU, Taiwan
8. PWM DC-AC Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機與控制工程研究所‧電力電子實驗室~鄒應嶼 教授
1/136
PWM DC-AC Inverters
 Introduction
 Inverter Topologies
 PWM Techniques for Single-Phase Inverters
 PWM Techniques for Three-Phase Inverters
 Dead-Time Protection and Distortion
 Filter Design
 Modeling in dq-Frame
 Closed-Loop Control Techniques
2/136
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Introduction
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
Chapter 8 Switch-Mode DC-AC Inverters: DC  Sinusoidal AC
Power Electronics: Converters, Applications and Design,
N. Mohan, T. M. Undeland, and W. P. Robbins, John Wiley & Sons, 3rd Ed., 2002.
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
3/136
Introduction
What is an Inverter ?
 AC/DC: Rectifier
 Applications
 DC/DC: Chopper
 Topologies
 DC/AC: Inverter
 Characteristics & Dynamics
 AC/AC: Cycloconverter
 Pulse-width Modulation
(PWM)
 Control Techniques
 Implementation Issues
Inverter
DC INPUT
Reference
Commands
AC OUTPUT
An inherent bi-directional
DC/AC converter!
4/136
Applications of DC/AC Inverters








PWM Inverters for AC Motor Drives
PWM Inverters for AC Power Source
Ballast Fluorescent Lamps
UPS & AVR
Induction Heating
Atmospheric Pressure Plasma
PV Inverters, Grid Converters
Distributed Generators
Single-Channel 150W, Philips
IEEE Spectrum 2003.
5/136
Applications of Inverters
 Grid Inverter: Battery-Based Energy Storage System
DC/AC
Battery
Filter
P
Grid
Lo
vg  Vg sin(2 f g t )
Vbat
 220 2 1  10%  sin(2  60  t )
N
 Regenerative Motor Drive
VDC = 300~380~420 VDC
Q1
Q3
R
Q2
Q4
S
Vdc
S5
S3
S1
a
S2
b
S4
S6
c
Application in a Grid-Connected PV System
PV Inverter
DC Side isolation
switch
DC
AC
AC
DC
inverter
Electrical
Distribution
System
PV Array
(usually building mounted)
Meter
AC mains supply
To high
efficiency AC
appliances
PV Panel
Full-Bridge Inverter
Main fuse box
Relay
Gate Drive
Inverter
Gate Drive
Feedback
Sensing Circuit
Microcontroller
7/136
Applications of Inverters in AC Motor Drives
 Single-Phase (One Winding)
(a) Single-phase bipolar
ia
vab
Vdc
 Three-Phase (Three Windings)
T1
T3
T2
T4
a
(b) Three-phase bipolar
S
N
S
Vdc
T1
T3
T5
T2
T4
T6
a
b
c
N
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
8/136
Single-Phase Half-Bridge Inverter
1
Vdc
2
iA
Q1
D1 v A
D2 v B
iB
v0
1
Vdc
2
D ( t )  0.5  Dm sin(t )
L
Q2
1
Vdc
2
Sinusoidal modulation to produce ac
output:
vg
iL
C
R
For the linear RLC load, the resulting
inductor current variation is also sinusoidal.
v0
When the converter is connected with grid
and the current is controlled to be linear
proportional to the grid voltage, the load is
equivalent to a resistor R and the inductor
current is:
1
v0 (t )   2 D  1 Vdc
2
0
vo ( t )
1 Vdc
 (2 D  1)
R
2 R
Hence, current-bidirectional twoquadrant switches are required.
iL ( t ) 
1 D
0.5
1
 Vdc
2
9/136
Single-Phase Half-Bridge Inverter
1
Vdc
2
vref
D
Amp
1
Vdc
2
Carrier
Gate Driver
1
Vdc
2
D(t )  0.5  Dm sin(t )
Q1
Q2
vo
Vo
1
v0 (t )   2 D  1 Vdc
2
0.5
1.0
D
1
 Vdc
2
 The simplest single-phase inverter topology.
 The half-bridge inverter is a buck-derived bidirectional converter with a
differential output relative to the neutral point of the source.
 Output voltage is limited with 0.5Vdc.
 Unbalance issues of the upper and lower voltage sources under fast and large
external disturbances.
10/136
Single-Phase Half-Bridge Inverter: Current Paths
 MOSFET is a bi-directional switch
S1
Vdc1
o
Vdc
1
i
a
Load
C
S2
Vdc 2
i
N-channel MOSFET
on
off
on
(reverse conduction)
0
Symbol
Q1
Vdc1
o
Vdc 2
Load
D1 V
dc1
Q2
Instantaneous i-v characteristic
Q1
D1 V
dc1
Symbol
o
a
Load
D2 Vdc 2
o
a
Q2
Q1
D1
a
Load
D2 Vdc 2
Q2
D2
Q1 OFF, Q2 ON
Q1 OFF, Q2 OFF, D2 ON
Q1 ON, Q2 OFF
v
v
11/136
Single-Phase Half-Bridge Inverter: Load
Characteristics
Q1
Vdc1
o
Vdc 2
D1
o
a
Q2
(a) Grid Inverter
Q1
Vdc1
D2
Vdc 2
D1
(b) AC power supply
Q1
D1
o
a
Q2
motor
Vdc1
D2
a
Q2
Vdc 2
D2
(c) motor
 Grid inverter: an inductor is used as a current filter and is connected with the utility.
 AC power supply: An LC filter is used as a voltage filter to generate a regulated ac
voltage source.
 The motor load can be a PM dc motor or a single-phase ac motor. c
12/136
Characteristics & Dynamics of a Buck Converter
io
IL
I L (max) 
L
C
Vdc
Vd Ts
4L
R
vo
0
D
1.0
0.5
vo
M=0.50
Vdc
1
2
M=0.75
vo
io
io
3
4
0
One-quadrant operation.
t
Output voltage and current waveforms
13/136
Characteristics & Dynamics
io
vo
L
C
Vdc
R
vo
D  1.0
0.9
CCM
0.7
vo
2
0.5
1
io
3
0.3
4
0.1
One-quadrant operation.
io
14/136
AC Source Voltage Regulation Problems
idc
iinv
ic
vdc
Vdc
S1
S3
L
Load
A
Cdc
vo
C
S2
S4
B
iL
(a) Testing Load
Rectifier load
200
v
vo
50
40
150
PWM
Controller
30
100
20
50
Vo(V)
Current
Controller
iL
10
0
0
Io(A), IL(A)
*
o
-10
-50
-20
-100
-30
-150
 Variations in dc-link
 Regenerative loads
 Voltage drop of battery
 Utility RMS variations
-2000
-40
2
4
6
8
t,(ms)
10
12
14
16
-50
(b) Output voltage and current
 Load uncertainties
 Parameter variations
 Load variations
 Nonlinear load
 Permissible load power factor
 Regenerative load
 Nonlinearity due to switching
 Dead-time of the gate drive circuit
 Non-ideal switching characteristics
 Nonlinearity due to DCM/CCM
Techniques in Closed-Loop Control of DC/AC Power
Converter
 Control Loop Design
 Topology
 Filter Design
 Simulation
 Power Devices and Gate Drives
 Harmonic Analysis
 Implementation Issues
 Protection and Compensation
 HF Magnetic Components
 Controller Implementation
 Power Devices and Gate Drives
 Snubber Circuit Design
 Nonlinear Power Load
 Grounding and Noise Reduction
 Regenerative Motor Load
Controller
command
Control
 Load Characteristics
Vdc
PWM
Modulator
Gate
Driver
=
 Load Dynamics
output
~
Filter
Load
Inverter
Processor
Signal
Conditioning
 PWM Modulation Strategy
 Harmonic and THD Analysis
 Dead-Time Protection
 Dead-Time Compensation
 Over-modulation Control
 Loss Analysis
 Implementation of PWM modulator
Sensors
feedback
 Current Sensor
 Sampling Techniques
 Voltage Sensors
 Signal Filtering
 Placement of Sensors
 Signal Conditioning
 A/D & D/A Converters
 Analog Circuit Design
16/136
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Inverter Topologies
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
02【硬體設計】02：Power Converters for Motor Drives.ppt
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
17/136
Basic Inverter Topologies
S1
Vdc1
a
o
Vdc
Vdc 2
S2
S2
S5
S3
a
a
Vdc
Vdc
(a) Half-bridge




S1
S3
S1
S4
b
(b) Full-bridge
b
S2
S4
S6
c
(c) Three-phase
The DC source can be a voltage source or a current source.
Most inverters are voltage source inverters (VSI).
Inverters are inherent bi-directional DC-AC converters.
Half-bridge inverter compared with the full-bridge inverter with a same dc-link
voltage will produce only one-half output voltage.
18/136
Classifications of Inverters
Variable Voltage Inverter
Voltage Source Inverter (VCI)
PWM Inverter (VVVF Inverter)
Single-Phase/Three-Phase
Current-Controlled PWM Inverter
Current Source Inverter (CCI)
Square Wave CSI
PWM CSI
 Processed Energy Source and Load (Voltage Source, Current Source)
 Topology (Single-Phase, Three-Phase, etc.)
 PWM Strategy (Square, PWM, Sine PWM, Regular PWM, Space Vector PWM, etc.)
 Switching Devices (SCR, Power Transistor, Power MOSFET, IGBT, etc.)
 Switching Schemes (PWM, Resonant, Quasi-Resonant, Soft PWM, etc)
 Control Schemes (Hysteresis, PID, Dead-beat, Variable Structure, Fuzzy, etc.)
 Controller Implementation (Analog, Microprocessor, DSP, etc.)
19/136
Voltage Source Inverter & Current Source Inverter
VSI: Voltage Source Inverter
S1
S3
S5
Vdc
S1
S3
S5
S2
S4
S6
I dc
S2




CSI: Current Source Inverter
S4
S6
Most conventional inverters are voltage source inverters (VSI).
The output of a VSI must be connected with an inductor!
The output of a CSI must be connected with a capacitor!
CSI with a quasi-Z network (ZCSI) are getting interest in recnt years.
2005.Comparison of Three Phase CSI and VSI Linked with DC to DC Boost Converters for Fuel Cell Generation Systems (epe).pdf
【投影片】Inverter Using Current Source Topology (ape2010).pdf
20/136
Three-Phase Inverter Motor Drives
VSI: Voltage Source Inverter
S5
S3
S1
3-Phase
Power
Supply
Voltage (Line to Neutral)
S
N
S
S6
S4
S2
Current (Line)
N
A DC-link capacitor provides a voltage source!
CSI: Current Source Inverter
S3
S1
3-Phase
Power
Supply
Voltage (Line to
Neutral)
S5
S
N
S4
S2
Current (Line)
S
S6
N
A DC-link indutor provides a voltage source!
21/136
Inverter Topologies
p
p
S1
Vdc
2
Vdc
Load
io
Vdc
2
D1
a
a
o
o
Vdc
2
vAN S 2
Vdc
2
D2
Vdc
S2
D1
ia i Load
b
c
D2 S 2
ic
D2
Three-Phase Half-Bridge
p
A
D1 S1
n
Single-Phase Half-Bridge
D1
io
b
S2
n
S1
S1
S3
Load
D2 vAN
p
B
S4
n
S1
D3
a
Vdc
D4
S2
D1 S 3
b
D2 S 4
D3 S 5
D5
c
D4 S 6
D6
ia
ib Load
ic
n
Single-Phase Full-Bridge
Three-Phase Full-Bridge
22/136
Derivation of Full-Bridge Converter
Differentialconnectionofloadtoobtainbipolaroutputvoltage
load
converter 1
Differential load voltage is:
V  V1  V2
V1
V1  M (D)Vg
DC source
V
D
Vg
The outputs V1 and V2 may both be
positive, but the differential output
voltage V can be positive or
negative.
converter 2
V2
V2  M (D' )Vg
D’
23/136
Differential Connection Using Two Buck Converters
Buck converter 1
Converter #1 transistor driven with duty
cycle D
1
2
Converter #2 transistor driven with duty
cycle complement D’
V1
Differential load voltage is
V
V  DVg  D'Vg
V  ( 2 D  1)Vg
Vg
M ( D)
1
2
1
V2
0
0.5
1 D
Buck converter 2
1
24/136
Simplification of filter circuit, differentially-connected
buck converters
Original circuit
Bypass load directly with capacitor
Buck converter 1
1
1
2
2
V1
V
V
Vg
Vg
2
2
1
1
V2
Buck converter 2
25/136
Simplification of filter circuit, differentially-connected
buck converters
Combine series-connected
inductors
Re-draw for clarity
1
2
C
1
Vg
2
2
iL
V
1
R
V
Vg
2
1
H-bridge, or bridge inverter
Commonly used in single-phase
Inverter applications and in servo
Amplifier applications
26/136
Derivation of Full-Bridge DC-DC Converter
io
2
1
2
vo
4
3
0
3
io
vo
4
0
(a)
1
(b)
io
2
0
3
io
2
1
vo
4
0
3
1
vo
4
(d)
(c)
Characteristics of a Full-Bridge Converter
io
S3
S1
L
A
Vdc
vg
vo
B
S2
 Its output can be DC or AC, depend on the
selected PWM strategy.
S4
4Q Operation!
io
2
0
3
rL
 An inverter is a differential mode 4-quadrant
DC-DC converter.
 Power can be transferred back and forth
between source and load.
1
vo
4
 A buck type converter.
 Input and output voltage do not have a
common ground.
 A lot of inverter topologies have been
developed.
 PWM modulation strategy is required to reduce
harmonic distortion as well as switching loss
reduction.
 Control is required to maintain stable, robust,
and fast response.
28/136
Dynamics of a Full-Bridge Inverter with Unipolar PWM
vo

OPx

vo,1
D 1.0
0.9
io ,1
0.7
0.5
3
1
0.3
0.1
Small signal perturbation
at operating point OPx
io
vo,1


2
1
io ,1
3
4
29/136
From Single-Phase Inverter to Three-Phase Inverter
S3
S1
L
a
Vdc
iL
S3
S1
rL
Vdc
b
c
b
S2
S4
S2
S4
La
ea
Rb
Lb
eb
Rc
Lc
ec
S5
a
vg
Ra
S6
n
 The basic inverter cell for bi-directional three-phase AC/DC
converters!
 Singe-Phase  Three-Phase
 Two-Level Switching  Three-Level Switching
 The basis for the understanding of major control issues and
performance indices for the grid converters.
 The basis for learning and developing more sophisticated control
schemes.
30/136
From Single-Phase Inverter to Three-Phase Inverter
S1
Vdc1
L
a
o
L
a
vg
iL
Vdc
S2
Vdc 2
S3
S1
rL
S2
S1
S4
b
rL
vg
iL
S5
S3
a
Vdc
b
S2
S6
S4
c
Ra
La
ea
Rb
Lb
eb
Rc
Lc
ec
n
31/136
Full-Bridge Converter: Load Characteristics
ia
S3
S1
iL
A
Vdc
Ra
A
vg
B
S2
S3
S1
rL
L
va
Vdc
(a) A grid inverter
vemf
B
S2
S4
La
S4
(c) A dc servo motor drive
ia
S3
S1
A
iL
Vdc
Ra
A
C
B
S2
S3
S1
L
S4
(b) An ac voltage regulator.
vo
va
Vdc
B
S2
La
vemf
S4
(d) A single-phase BLDC motor drive
32/136
Split Phase 6-Switch Inverter with Battery Bank at HV DC-Link
5 kW solid oxide fuel cell (SOFC)
Vin: 22~41 VDC
DC-link Voltage = 400 VDC
5 kW Battery Bank at HV DC-Link
Peak Output Power = 10 kW
Load: Two split-phase 60 Hz, 120-VAC






Jin Wang, F.Z. Peng, J. Anderson, A. Joseph, and R. Buffenbarger, “Low cost fuel cell converter system for residential power
generation,” IEEE Transactions on Power Electronics, vol. 19, no. 5, pp. 1315-1322, Sept. 2004.
Development of Single-Phase Non-Isolated Grid Inverters
PV Array Filter
Basic FB inverter
S1
Vrv
D1
S3
Filter
D3
Vv
L2
S2
D2
S4
PV Array Filter
S5
D5
L1
VAB  0
Crv
Grid
Vrv
FB inverter
S1
D1
S3
Filter
D3
Grid
PV Array Filter HERIC FB inverter
L
Vv
Crv
L2
N
D4
S2
D2
S4
Full-bridge
(Bipolar/ Unipolar/ Hybrid)
PV
Array
DC Link L
Boost
DC Link H HB
AC Bypass Filter
Boost Bypass
Grid
Crv
S2
S4
D2
PV Array Filter
Grid
D
H5 Topology (SMA)
PV Array
Filter
Vrv
L
S1
D
B
Crv 2
S2
D1
D2
Grid
S  L2
D
S3
S4
D3
Crv 2
S4
S2
D6
PV
Array
L2
B
【投影片】Latest in PV Inverter & Trends (2012)
T. Hauser et. al, Sunways, EUPVConf Valencia 2008, 4DO.8.2
D4
S6
H6Topology (FBDC Bypass)
Filter Clamping Switch HB inverter
C rv 1
V rv / 2
S1
D1
Filter Gri
d
V AB  V rv / 2
L1
V rv
D
Vv
N
D2
C rv 2
V rv / 2
S2
D2
V rs
NPC (Danfoss)
L1
L
D
D4
D4
Vrs
D3
A
D
L1
S3
Grid
Vv
N
VAB  0
A
Vrv / 2
D1
Filter
Vv
HERIC Topology (Sunway)
Filter
S1
Crv1 D 
Vrs
NPC inverter
DC Bypass
S5
FB inverter
D5
L1
Vrs
Vrv
REFU UltraEta
D
N
D4
Vrv / 2
C rv1
Vrs
D3
S
Vrv
Vrs
Vrs
S3
D1
S1
L1
L
Filter
Conergy Topology
Vv
Selection of Single-phase Three-wire Transformerless
Inverter Topologies
Cdc1
S1
S3
Lo2
Lo1
Cdc 2
S2
S4
Co1
Vac1
Cdc 1
Vac 2
Co 2
S1
Lo1
120V
120V
Cdc 2
Vac1
S2
(a) Single DC Bus with Split Capacitor
Co1
120V
Co 2
Vac 2
120V
Lo1
S1
S3
S5
Co1
Cdc
Cdc 3
Vac1
S3
Lo 2
120V
Vac 240
S2
S4
Co 2
S6
Vac 2
Cdc 4
120V
S4
Lo2
(c) Dual DC bus with central tap ground
(b) Single-phase three-wire inverter
[1] T. A. Nergaard, J. F. Ferrell, L. G. Leslie, and J. S. Lai, “Design considerations for a 48 V fuel cell to split single phase inverter system with ultracapacitor energy storage,”
Proc. IEEE Power Electronics Specialist Conference, 2002.
[2] S. J. Chiang and C. M. Liaw, “Single-phase three-wire transformerless inverter,” IEE Electric Power Applications, vol. 141, pp. 197-205, July 1994.
[3] M. Martino, C. Citro, K.Rouzbehi, P. Rodriguez, “Efficiency analysis of single-phase photovoltaic transformer-less inverters,” International Conference on Renewable
Energies and Power Quality (ICREPQ) Santiago de Compostela (Spain), 28th to 30th March, 2012.
35/136
Interleaved Bi-Directional DC-DC Charger/Discharger
with Single-Phase Three-Wire Inverter
Battery
DC/DC
DC-Link
DC/AC
Filter
Grid
Lo1
P
S1
S3
S5
Co1
Vac1
120V
Co 2
S2
N
S4
Vac 2
120V
Vac 240
S6
Lo2
36/136
Three-Phase Four-Wire Inverter with a Split DC Bus
Min Dai, Mohammad Nanda Marwali, Jin-Woo Jung, and Ali Keyhani, “A three-phase four-wire inverter control technique for a
single distributed generation unit in island mode,” IEEE Trans. on Power Electronics, vol. 23, no. 1, pp. 322-332, Jan. 2008.
37/136
Three-Phase Four-Wire Inverter: Control Block Diagram
38/136
Three-Phase Four-Leg Inverter
Gyeong-Hun Kim, Chulsang Hwang, Jin-Hong Jeon, Jong-Bo Ahn, and Eung-Sang Kim, "A novel three-phase four-leg inverter
based load unbalance compensator for stand-alone microgrid," Electrical Power and Energy Systems, vol. 65, pp. 70–75, 2015.
39/136
Topology and Control of a Three-phase Four-wire Grid
Inverter
40/136
Pioneer on NPC PWM Inverter
Neutral-Point-Clamped (NPC) 3-Phase PWM Inverter
DCL
S11
S21
C1
S12
D21
S13
U
S22
S31
D31
S32
ib(S11)
S33
ib(S13)
D11
Ed
D22
S23
V
D32
D12
C2
S14
S24
ib(S14)
S34
ib(S12)
Neutral Point Clamped PWM Inverter
PWM Gating Waveforms for the
NPC-PWM Inverter
A. Nabae, T. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE IAS Annu. Meeting, Cincinnati, OH,
Sep. 28–Oct. 3 1980, pp. 761–776.
A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA17, pp. 518-523, 1981.
41/136
The Multilevel Converter Concept
Vdc
Vdc
Vdc
a
N
a
N
vaN
a
Vdc
vaN
vaN
Vdc
N
Vdc
Vdc
vaN
Vdc
vaN
0
-Vdc
Vdc
4Vdc
0
0
-Vdc
0
0.005
0.01 0.015
0.02
Time [s]
(a)
0.025 0.03
0
vaN
m
-4Vdc
0.005
0.01 0.015
Time [s]
(b)
0.02
0.025 0.03
0
0.005
0.01 0.015
0.02
0.025 0.03
Time [s]
(c)
Converter output voltage waveform: a) two level, b) three level, c) nine level.
42/136
Comparison of phase voltage of 2- and 3-levelinverters
Vdc
Vdc / 2
S+
S-
Vdc / 2
Vdc / 2
Vdc / 2
Sn S+
S-
Vdc / 2
vo
vo
Passive NPC inverter
vo
vo
t
t
Vdc / 2
43/136
Neutral-Point-Clamped (NPC) Converter
Vdc1
Q1
D1
Vdc1
a
Q1
D1
a
o
o
Vdc 2
Q2
D2
Vdc 2
Q2
D2
 Three Ways to Realize a Four-Quadrant Switch
1
1
i
1
i
1
i
i
v
v
v
v
0
0
0
0
[1] A. Nabae, T. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE IAS Annu. Meeting, Cincinnati, OH, Sep.
28–Oct. 3 1980, pp. 761–776. [A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind.
Appl., vol. IA-17, pp. 518-523, 1981.]
[2] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on neutral-point-clamped inverters,” IEEE Transactions on
Industrial Electronics, vol. 57, no. 7, pp. 2219-2230, July 2010.
Different Types of Switching Devices
Filter
S3
S1
L
a
rL
ig
vg
Vdc
b
S2
S4
IGBT
Si FRD
Si IGBT
MOSFET
SiC SBD
Si
SiC MOSFET
Si FRD
Si
SiC SBD
SiC
MOSFET
IGBT
GaN
MOSFET
GaN HEMT
SBD: Schottky Barrier Diode
FRD: Fast Recovery Diode
Neutral-Point-Clamped (NPC) Grid Inverter
Q1
Vdc1
D1
o
Q2
D1
o
a
Vdc 2
Q1
Vdc1
D2
(a) Half-bridge grid inverter
a
Q2
Vdc 2
D2
(b) Three-level NPC grid inverter
NPC inverter module
Q1
Vdc1
Q2
Q1
Vdc1
D2
Vdc 2
D1
a
o
a
o
Vdc 2
D1
Q2
D2
46/136
2-Level vs. 3-Level Inverters
P
Circuit
P
a
b
c
Vdc
Vdc
N
N
Phase
Voltage
A
VPN
VPN
v AN
Voltage
C
v AO
0
VPN
0
Line
B
VPN
v AB
VPN
0
0
VPN
1
 VPN
2
v AB
VPN
(a) 2-Level PWM
(b) 3-Level PWM
Development of Multi-Level Inverter Topologies
Cd 1
Cd 1
a
b
c
a
b
o
c
Cd 2
Cd 2
(a) 3-level NPC VSC
T 1U
(b) T-type 3-level VSC with BB-IGBT
T 1V
T 1W
T 3U
Cd 1
a
T 3V
T 4U
T 3W
T 4V
Cd 2
T 4W
T 2U
T 2V
T 2W
b
c
(c) T-type 3-level NPC VSC with RB-IGBT (Fuji)
(d) 5L-MLC2 Converter
H5 & H10 Converter
Power Electronics Systems & Chips Lab., NCTU, Taiwan
PWM Techniques for Single-Phase
Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
50/136
Single-Phase (One-Leg) Switch-Mode Inverter
Resistive Load
P
T A
Vd
2
Vdc
o
Vd
2
D A
io
Incandescent
light bulb
LCR Load
A
Filter
T A
D A
v AN
vAo
N
L
O
A
D
Regenerative Load
Middle point of the DC-link source
ia
Ra
va
Speaker
La
vemf
DC Motor
The middle point is important for both definition and thinking!
vAo is the inverter output voltage!
A Simple First-Quadrant Chopper
io
Input-Output Relationships:
Vdc
vo
M is the modulation index and assume
the chopper is operating in CCM.
Vo  MVdc
R
L
Vo 
E
1
Ts

Ts
0
vo (t )dt
I 0,ac ( RMS ) 
vo
M (1  M )
2 3Lf sw
M=0.50
2
f s 
R
L
fs 
1
Ts
Vdc
M=0.75
Vdc
1
vo
io
io
3
4
0
One-quadrant operation.
t
Output voltage and current waveforms
52/136
Pulse-Width Modulator
Modulating signal
v o* (desired)
vcontrol
Amp
v o (actual)
comparator
repetitive
waveform
Carrier signal
vst saw-tooth voltage
vcontrol (amplified error)
V̂st
vcontrol  v st
switch
control
signal
on
Ts
D
ton vcontrol

Ts
Vˆst
The carrier signal may be a nonlinear
function to produce nonlinear PWM
control signal.
on
off
ton
switch control
signal
toff
off
vcontrol  v st
(switch frequency fs = 1/Ts)
53/136
Three Types of PWM Modulation Schemes
Trailing-Edge PWM
Usually used in DC-DC & PFC Boost Converters
Leading-Edge PWM
Double-Edge PWM (Central PWM, usually used in sine-wave inverters )
Analog PWM Implementation
 Trailing-edge modulation is most common in DC–DC converters.
 Double-edge modulation eliminates certain harmonics when the reference is a sine
wave, and is a preferred method for AC–DC and DC–AC converters where the PWM
reference contains a sinusoidal component.
 A combination of synchronized leading-edge and trailing-edge modulation has also
been used to control a boost single-phase power factor correction (PFC) converter
and a buck DC–DC converter to reduce ripple in the intermediate DC bus capacitor
[1].
 Analog PWM is also called natural-sampling PWM in contrast to the regularsampling PWM fir its digital implementation.
v carrier
v control
v control
comparator
0
v control
v carrier
t
uAo
v carrier
(
1
)
fs
v Ao , fundamenta
l
 ( v Ao ) 1
t
0
0
Vdc
2

Vdc
2
t
[1] UCC38501 BiCMOS PFC/PWM Combination Controller datasheet. Texas Instruments, Dallas, Texas, USA (1999)
Pulsewidth Modulator for a Half-Bridge Converter
Switching States
56/136
Conduction Modes and PWM Strategies
Load
Vdc
2
vemf
Vdc
io
D1
S1
A
o
Vdc
2
S2
v AN
N
D2
IGBT
IGBT + DIODE
DIODE
ICE
Ir
IFQ
IRD
Loss
L oss
VFD Vr
VFQ VC E
Loss=VFQIFQ +VFDIRD
VFQIFQ =(VCE +I F Q rQ )IFQ
MOSFET
MOSFET + DIODE
IDS
DIODE
R ON
Ir
IF
IRD
Loss
Loss
VFD Vr
VF VD S
 The inductor current must
keep its continuity!
 The current path defines its
conduction mode.
 IGBT is a 1Q switch.
 MOSFET is a 2Q switch.
 MOSFET converter can
provide extra conduction
paths and its PWM strategy
can be more complicated.
 The converter is a 4Q bidirectional converter.
 DC/DC, DC/AC, AC/DC,
AC/AC are all possible!
 For a regenerative load, such
as a motor, the power flow
can flow back to the source.
 Current loop area must be
kept in minimum for practical
implementation to reduce
EMI.
Loss=IF2R ON +VFDIRD
Conduction Modes
Load
Vdc
2
Vdc
vemf
io
D1
S1
A
o
Vdc
2
S2
vAN
D2
S1 ON & S2 OFF
N
Current path during these time periods.
Load
Vdc
2
Vdc
vemf
io
D1
S1
S1 OFF & S2 OFF, D2 ON
A
o
Vdc
2
vAN
S2
D2
The inductor current must
keep its continuity!
N
Current path during these time periods.
58/136
Conduction Modes
Load
Vdc
2
Vdc
vemf
io
D1
S1
A
o
V dc
2
S2
vAN
D2
S1 OFF & S2 ON
N
Current path during these time periods.
Load
Vdc
2
Vdc
vemf
io
D1
S1
S1 OFF & S2 OFF, D1 ON
A
o
V dc
2
vAN
S2
Current path during these time periods.
D2
The inductor current must
keep its continuity!
N
59/136
PWM Waveforms and Inductor Current
Load
Vdc
2
Vdc
vemf
io
D1
S1
U (t f )
A
o
Vdc
2
vAN S2
t
D2
N
tk  2
tk  3
Average output voltage
t
Ts
Ts
Double edged PWM strategy with half-bridge converter
The Voltage Reference Command
 The modulation signal can be updated in every
half-cycle of the switching period, and achieve a
double switching effect as compared with the
single-edge PWM strategy.
61/136
Single-Phase (One-Leg) Switch-Mode Inverter
P
T A
Vdc
2
Vdc
o
Vdc
2
v Ao
Vdc
2
D A
io
0
t
V
 dc
2
A
T A
D A
v AN
N
Spectrum of Square-Wave Inverter
4 Vdc
V
(VˆAo )1 
 1.273( dc )
 2
2
(Vˆ )
(VˆAo)n  Ao 1
n
1
f1
V
(VˆAo )1 /( dc )
2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0

0
1
3
4 Vdc
V
 1.273( dc )
 2
2
5
7
9
11
13
15
N-th: harmonics of VAo
No dc component and even harmonics, if output
waveform is symmetric!
62/136
Half-Bridge Singe-Phase PWM Inverter
P
T A
Vdc
2
Vdc
o
Vdc
2
Vdc
2
D A
0
io
A

T A
v AN
D A
fs
v Ao
t
Vdc
2
1
f1
V
(VˆAo )1 /( dc )
2
N
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Spectrum of PWM Inverter
4 Vdc
V
(VˆAo )1 
 1.273( dc ) D
2
 2
(Vˆ )
(VˆAo)n  Ao 1 D
n

4 Vdc
V
 1.273( dc )
 2
2
fs
D
0
1
3
5
7
9
11
13
15
N-th: harmonics of VAo
In general, f s  f1
fs
f1
63/136
Half-Bridge Singe-Phase Sine Wave PWM Inverter
o: middle point of the DC source
P
Vdc
2
Vdc
S1
Load
io
P: DC source positive
D1
N: DC source negative
vao: voltage applied to the load
a
o
Vdc
2
D2
vAN S 2
N
v control
Comparator
s1
v control
v carrier
v carrier
0
t
s2
Natural-Sampling Sinusoidal PWM
64/136
Half-Bridge Inverter
Vcontrol
V tri
t
0
(
uAo
1
)
fs
vAo,fundamenta
l (vAo)1
Vd
2
t
0

Vd
2
t=0
vcontrol
vcontrol
vcarrier

vcontrol  vtri


TA : on, TA : off 
v control  v tri



TA : on, TA : off 
This is what we
need!
vcarrier
t
0
同一種電路拓撲，其表現行為
主要決定於PWM的控制方式！
Harmonics distribution
PWM Techniques
Vref
1
V
2 dc
D
Carrier
vm(t) vc (t)
Q1
Gate Driver
1
V
2 dc
Q2
vo
0
t
(
Harmonic Spectrum of Output Voltage
x
x
x
x
x
x
x
x
x
vAB
vAB,1
0
x
x
1
V
2 dc
1
)
fs
x
x
x
x
x
x
x
t
1
 Vdc
2
x
1
V
2 dc
THD of Output Current
THD (%)
0
1
 Vdc
2
1.0
Modulation index
iL
iL,avg
t
Natural Sampling Sinusoidal PWM for Half-Bridge
Inverter
V tri
Vcontrol
Amplitude Modulation Ratio
0
t
(
uAo
1
)
fs
ma 
v Ao , fundamenta l  ( v Ao ) 1
Frequency Modulation Ratio
Vdc
2
0

vcontrol  v tri



TA : on, TA : off 
t
Vdc
2
mf 
t=0
vcontrol  v tri



TA : on, TA : off 
T A
Vdc
2
V dc
2
A
T A
fs
f1
1
Vdc
2
vcontrol  vtri
TA is on,
v Ao 
vcontrol  v tri
TA is on,
1
v Ao   Vdc
2
D A
iA
o
Vdc
Vˆcontrol
Vˆtri
D A v
AN
1
v AN  v Ao  vnN  v Ao  Vdc
2
N
(VˆAN ) h  (VˆAo ) h
67/136
Single-Phase PWM Inverter: Waveform and Spectrum
V control
TA+
Vdc
2
Vdc
o
Vdc
2
DA+
V tri
t
0
iA
A
(
u Ao
TA-
DA-
1
)
fs
v Ao , fundamental  ( vAo )1
Vdc
2
v AN
t
0
N
One-leg switch-mode PWM inverter
vcontrol  v tri



T
:
on
,
T
:
off
A
 A


t=0
V dc
2
 vcontrol  vtri



T
:
o
n
,
T
:
off
 A
A

Harmonics distribution
(VˆAo ) h
V dc / 2
1.2
ma  0.8, m f  15
1.0
0.8
x
x
0.6
0.4
1
x
x
x
0.0
x
x
x
0.2
mf
(mf 2)
x
x
x
x
2mf
(2mf 1)
Harmonics of f 1 
x
x
x
x
3m f
x
x
x
(3mf  2)
68/136
Natural Sampling PWM
Advantages:
 Simple
 Easy to be implemented by analog circuit
Disadvantages:
 Beat effect phenomenon
 Not easy to be implemented with MCU-based software
 Asynchronous (modulating and carrier signal)
 Limited linear voltage control range
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
69/136
Waveforms under Overmodulation
Vcontrol
V
(VˆAo )1 /( dc )
2
V tri
t
0
4

(
u Ao
1
)
fs
v Ao, fundamental  (v Ao )1
Square-wave
 1.273
1.0
Vd
2
Linear modulation range
t
0
overmodulation
V
 d
2
0
0
1.0
3.24
ma
70/136
Bipolar and Unipolar PWM
Unipolar PWM
Bipolar PWM
Q1
Q3
71/136
Current Ripple Analysis of Bipolar PWM
Q1
iAB
Vdc
A
Q2
vAB
Vdc
-
Q3
I AB 
io
(Vdc  Vemf ) DTs
iAB
If the IR drop is neglected,
vAB
B
Q4
Vemf  (2D  1)Vdc
V 2(1  D ) DTs
I AB  dc
L
I AB VdcTs

(1  D ) D
2
L
V
iABd
0
M (D)
1
0
c

L
vAB
v AB
VAB  (2D  1)Vdc
0.5
1 D
I AB
I AB(max) 
Bipolar PWM (a) voltage and (b) current.
1 VdcTs
2 L
1
72/136
Current Ripple Analysis of Unipolar PWM
Q1
Q3
iAB
Vdc
B
Q4
Q2
vAB
Vdc
-
io
(Vdc  Vemf ) DTs

L
iAB
If the IR drop is neglected,
vAB
A
I AB 
Vemf  DVdc
0
V (1  D ) DTs
I AB  dc
L
I AB VdcTs

(1  D ) D
2
2L
vAB
v AB
M ( D)
1
VAB  DVdc
V
iABd
0
c
I AB
I AB(max) 
Bipolar PWM (a) voltage and (b) current.
1 VdcTs
4 L
1 D
The negative voltage is
controlled by another
control signal DIR.
73/136
Voltage Ripple Analysis: Bipolar and Unipolar PWM
V r ,rm s

Vd
1
Vr
I r
3

Vd
I M AX
For a same output voltage, the PWM duty
ratios are different using different PWM
control schemes.
For a 50% VDC output, Dbipolar  0.75
1.0
(a) bipolar
0.75
Dunipolar  0.5
(b) unipolar
0.50
The current ripple ratio is:
0.25
-1.0
0
-0.5
0
0.5
0
0.5
1.0
1.0
1.0
Vo
Vd
Dbipolar
Dbipolar
Bipolar PWM
V T 3
I AB VdcTs
(1  D ) D  dc s

2
L
L 16
V T 2
I AB VdcTs
(1  D ) D  dc s

2
2L
L 16
3
2
Unipolar PWM
Vr,rms in a full-bridge converter using PWM: (a) with bipolar
voltage switching; (b) with unipolar voltage switching.
 For DC-DC converter, the current ripple profile can be plotted as a function of the
modulation index. While for DC-AC inverter, the current ripple profile can be
plotted as a function electrical angle and modulation index.
74/136
Hybrid PWM
Modulation waveform, m =de
PWM
carrier, c
Effective duty ratio de(t)
0
1 / fo
S11 ON / S12 OFF
S11 OFF / S12 ON
S11 OFF / S12 ON
S11 ON / S12 OFF
S21 OFF / S22 ON
S21 ON / S22 OFF
Modulation waveform
Carrier waveform
(a)
S11
S 21
iL t 
A
L
Vg
C
v AB
io  t 
vo  t 
0
R
B
S12
(b) V
v o  t   V m sin  o t 
S 22
g
0
 S11 and S12: High Frequency Switching Leg
 S21 and S22: Line Frequency Switching Leg
[1]
1 / fs
Vg
v AB
1 / fo
R. S. Lai and K. D. T. Ngo, “A PWM method for reduction of switching loss in a full-bridge inverter,” IEEE APEC Conf. Proc., 1994.
Unipolar PWM: Current Ripple Profile
Vr1
Vr2
Vr3
Vr4
Vr5
Vr6
I max 
1.01
ma  0.6
VdcTs
8L
I ( )  (1  ma sin  )ma sin 
ma  0.7
0.8
0.8
VdcTs
2L
When ma = 0.707, the maximum
ripple occurs at max=45º.
ma  0.8
0.6
0.6
ma  0.5
S3
S1
L
A
iL
Vdc
0.4
0.4
S2
0.2
0.2
00
0
0.002
ma  1.0
 /2
0.004
Time (s)
S4
Calculate the RMS value of
ripple current with a specified
modulation index?

4
vg
B
ma  0.9

rL
0.006
0.008

[1] P.A. Dahono, A. Purwadi, and Qamaruzzaman, “An LC filter design method for single-phase PWM inverters,” International Conference on
Power Electronics and Drive Systems (PEDS), pp. 571-576, 21-24 Feb 1995.
[2] Hyosung Kim and Kyoung-Hwan Kim, “Filter design for grid connected PV inverters,” IEEE International Conference on Sustainable Energy
Technologies (ICSET). pp. 1070-1075, 24-27 Nov. 2008.
Power Electronics Systems & Chips Lab., NCTU, Taiwan
PWM Techniques for Three-Phase
Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
77/136
PWM Strategies for Motor Drives & Grid Converters
Power
source
Digital link
Controller
PWM
Modulator
Converter
Motor
Load
Speed
Torque
Sensor signals
 The main purpose of the modulation techniques is to attain the maximum voltage
with the lowest Total Harmonic Distortion (THD) in the output voltages.
 PWM strategy plays a most important role for the improvement of voltage control
range and linearity and reduction of current harmonics, leakage current, and
switching loss for a motor drive.
78/136
PWM Strategies for Power Converters
D. G. Holmes and T. A. Lipo,
Pulse Width Modulation for Power Converters: Principles and Practice,
M. E. El-Hawary, Ed. New Jersey: IEEE Press, Wiley-Interscience, 2003.
79/136
Classification of PWM Techniques
 Two-Level Inverter
PWM Techniques
 Multilevel Inverter
 Continuous PWM






SPWM
Regular-Sampled SPWM
SVPWM
Trapezoidal PWM
Harmonic Injection
…
 Discontinuous PWM
 DPWMMIN
 DPWMMAX
 ….
 Programmed PWM
 SHE
 Optimal PWM
80/136
Two-Level Natural Sampling Sine PWM
van
ias
S1
1
Vdc
2
Vdc
S3
S5
a
o
S4
La
a
vbn
ibs
S2
ra
rb
Lb
1
Vdc
2
c
ics
rc
Lc
n
ec
c
vao
vcn
vbo
sinewave
Modulation signal
vco
carrier wave
1
Vdc
2
b
eb
b
S6
Pole Commutation Sequence Rule
ea
n
1
Vdc
2
upper transistor on
1
Vdc
2
1
Vdc
2
per phase output voltage (with
respect to dc center tap)
lower diode on
carrier int.
Commut int. 1
0
Switching
0
pattern
0
volt. vector 0
J
2
1
0
0
4
3
1
0
1
5
4
1
1
1
7
J+1
5
1
0
1
5
6
1
0
0
4
7
0
0
0
0
81/136
Three-Phase Inverter for AC Power Source
3-Phase
Motor
3-Phase
Power
Supply
Vdc
3-phase
load
SVPWM Generator
82/136
Representation of Stator Voltage Vector
The motor stator voltage vector (or current vector) can be expressed as a combination of the
inverter output phase voltage va , vb and vc which can be expressed in the vector form as
2
vs  va   2 vb   v c ,   exp( j
)
3
where
v a  Vm sin  t ,
vb  Vm sin( t  120  ) ,
v c  Vm sin( t  120  ) ,
and Vm is the amplitude of the fundamental component.
83/136
Space Vector Representation of 3-Phase Systems
Space vector based analysis method can also used for the analysis if three-phase inverter.
The inverter output voltage vector (or current vector) can be expressed as a combination of
the inverter output phase voltage va , vb and vc which can be expressed in the vector form as
2
)
v s  v a   2 vb   vc ,   exp( j
3
where
va  Vm sin  t ,
v b  Vm sin( t  120 ) ,
v c  Vm sin( t  120 ) ,
and Vm is the amplitude of the fundamental component. Note: The va is sometimes denoted as vas
with a subscript s meaning to apply to the stator.
bs
Vm
vas (t)
vbs (t )
vcs (t )
vs (t) output voltage vector
vs (t)
vqss ( t )
vas(t )
vbs (t )
t
(a)
cs
(b)
v dss ( t )
vcs (t)
as
84/136
Vector Representation of 3-Phase Quantities
2
( v as  vbs e j  vcs e j 2 )
3
 vdss  jv qss
vs 
v as ( t )
v bs (t )
vcs ( t )
bs
stator voltage vector

s
vs (t )
v qs
(t )

2
3
as
vas (t )
vdss (t )
vbs (t)
vcs (t )
cs
t
(a)
(b)
85/136
Space Vector Representation of 3-Phase Inverter
S1
Vdc
S3
S5
A i
as
o
S2
S4
S6
B
ibs
vas
vbs n
462315
v2
v6
vcs
C ics
II
III
I
v3
v4
IV
V7 (1 1 1)
V4 (1 0 0)
V6 (1 1 0)
V2 (0 1 0)
VI
V
v5
v1
V3 (0 1 1)
V1 (0 0 1)
(a)
V5 (1 0 1)
V0 (0 0 0)
v 0 , v7
: zero voltage vector
(b)
86/136
Vector Decomposition Using Basic Switching Vectors
v2

v6
v6
II
V7 (1 1 1)
V4 (1 0 0)
V6 (1 1 0)
V2 (0 1 0)
v3
III
I
IV
VI
v4
V
V3 (0 1 1)
V1 (0 0 1)
V5 (1 0 1)
V0 (0 0 0)
(a)
v1

vref
v5
v0 , v7 : zero voltage vector
(b)
T6 
v6
Ts

T4 
v
Ts 4

v4
(c)
Fig. (a) The switching configurations of a 3-phase PWM inverter, (b) the corresponding
vectors, and (c) the decomposition of the voltage vector.
The 8 basic switching vectors:
vn 
2
 ( n  1) 
Vd exp  j
3
3 

where n = 1, 2, .., 6, and v0 = v7 = 0.
87/136
Representation of 8 Basic PWM Switching Vectors
There are eight basic switching configurations of the 3-phase PWM inverter as shown in
Fig. 2(a) and their corresponding voltage vectors are shown in Fig. 2(b) which can be
expressed as
vn 
2
 ( n  1) 
Vd exp  j
3
3 

where n = 1, 2, .., 6, and v0 = v7 = 0.
The stator voltage vector can be decomposed to two orthogonal components in a two-axis
coordinate or as a combination of the two basic vectors of Fig. 2(b). An example of the
voltage vector decomposition is shown in Fig. 2(c). The SVPWM strategy aims to
minimize the voltage/current harmonic distortion by proper selection of the switching
vectors and determination of their corresponding dwelling widths.
88/136
Flux Trajectories
Vector Decomposition
v2
v6
IV
V4T2
V3T1
trajector of the flux
linkage
v3t
v4t
I

v3
V4T2
R
II
III
V3T1

v3t

R
v4
VI
V

v1
v5
V3T1
v7, v8 : zero voltage vector
120 *

V4T2
89/136
Synthesis of Flux Trajectory by Integration of Voltage
Vectors
The flux produced by the reference voltage vector in a PWM switching period is a
combination of each individual flux resulted by its corresponding voltage vector. Their
relationships can be expressed as
 T0 s v ref dt   T01 v1dt   TT10 v1dt   TT02 v 2 dt   TT70 v 7 dt .
Because the voltage vector v1 and v2 are constant vector, and v0 and v7 are zero vector,
we can obtain
T
T
v ref  v1 1  v2 2
Ts
Ts
where Ts is the switching period, T1 and T2 are the dwelling time for v1 and v2 ,
respectively.
Note: The voltage vectors v1 and v2 are used for illustration purpose only.
90/136
Decomposition of a Voltage Vector
The voltage space vector can be described in rectangular coordinates as follows
T1 
cos 60   Ts
1 
2
2
Vd     T2 
Vd  

 
3
3
0 
sin 60  2
where a  vref
cos  
2
Vd  a  

3
sin  
2 3Vd , 0    60 , and Vd is the dc-link voltage.

v2

vref
T2 
v
Ts 2

T1 
v1
Ts

v1
T1 
sin( 60   )
Ts
a 
2
sin 60
T2 
sin 
Ts
a 
2
sin 60
T7  T0 
Ts
 T2  T1
2
The equivalent PWM waveforms, which produce same average flux, may have
various combinations of the basic vectors.
91/136
Possible Voltage Compositions of a Stator Voltage
Vector
Ts
Ts
va 1
0.5Vd
vb
0.5Vd
1
va
0.5Vd
t
-1
1
vb
0.5Vd
t
t
-1
-1
vc 1
0.5Vd
vc
1
t 0.5Vd
-1
T0
T2
Ts
2
va
0.5Vd
T1
-1
T7
(a)
t
T0
2
T1
T2
(b)
T0
2
Ts
va 1
0.5Vd
1
t
t
-1
-1
vb 1
0.5Vd
t
vb 1
0.5Vd
t
-1
-1
vc 1
0.5
Vd
t
vc 1
0.5Vd
-1
t
-1
1
T7
2
T1
2
T2
2
T0
2
(c)
-1
t
T0
2
T1
T2
T0
2
(d)
92/136
Symmetric vs. Asymmetric SVPWM
Ts
2
1
va
0.5Vd
1
va
0.5Vd
-1
1
vb
0.5Vd
-1
1
t
-1
1
vb
0.5Vd
t
-1
1
vc
0.5Vd
-1
T1
2
T2
2
t
t
vc
0.5Vd
-1
t
T7
2
Ts
2
T0
2
t
T7
T1
T0
T2
(a)
T0
T2
T7
T1
(b)
93/136
Generation of Optimum PWM Patterns for SVPWM
Ts
2
Ts
va
0.5Vd
1
1
t
-1
1
vb
0.5Vd
vc
0.5Vd
t
-1
1
vb
0.5Vd
t
T0
T2
T1
(a)
T7
vc
0.5Vd
t
-1
t
vb
0.5Vd
t
-1
1
-1
1
t
va
0.5Vd
-1
1
-1
1
t
-1
1
va
0.5Vd
Ts
2
T7 T1
2 2
T2
2
T0
2
(b)
vc
0.5Vd
-1
t
T1
2
T2
2
(c)
94/136
PWM Gating Signals of SVPWM at Each Operation
Section
VI
I
II
III
IV
V
SA
SA
SB
SB
SC
SC
VI
I
II
III
IV
V
SA
SA
SB
SB
SC
SC
95/136
Flux Trajectories
Output Frequency from 0,094 Hz to 1500 Hz
150
100
50
0
-50
-100
-150
-150
(a) 94mHz
3
10
2
5
1
0
0
-5
-1
-10
-2
-10
-5
0
5
(d) 300Hz
10
-3
15
(e) 1000Hz
-50
0
50
100
150
2
3
(c) 60Hz
(b) 5Hz
15
-15
-15
-100
-3
-2
-1
0
1
(f) 1.5kHz
96/136
General Form of Harmonic Injection Scheme
ma  va*
1
1
 va*
 va*  kdc
Vdc
Vnom  Vdc
ma
ma*
mb
mb*
mc
mc*
Zero
Sequence
Signal
Calculator
Gate Driver
Switching
logic
e0
 Dead time protection
 Dead-time compensation
 Protection latch
1999.Simple analytical and graphical methods for carrier-based PWM-VSI drives (pe).pdf
Power Electronics Systems & Chips Lab., NCTU, Taiwan
Dead-Time Protection and Distortion
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
98/136
Dead-Time Protection & Distortion
Current with Correction Disabled
TA
Vdc
2
o
Vdc
Vdc
2
DA
ia
A
DA v AN
TA
N
To prevent shoot-through!
Dead-Time
Top transistor
ON
Example of output current due to
dead-time distortion.
ON
Bottom transistor
ON
ON
ON
The turn off of one transistor trig the delay (dead time) of its
complementary turn on.
99/136
PWM Dead-Time Distortion Caused by Inductive Loads
1
V DC
2
1
 V DC
2
 Causes poor low-speed
motor performance
 Torque ripple
 Distorts current
 Produces noise in audible
region
tdead
*
vGE
1
S1
1
V DC
2
tON 1
*
vGE
2
G1
es
Ls
o
D1
Rs
vL
tON 2
vGE1
1
V DC
2
G2
S2
E1
a
ia
D1
E2
vGE 2
vao
Output voltage error due to the
dead-time:
1
V DC
2
Load Voltage
Applied gate signals
Logic gate signals
Analysis of Dead-time Effect
1
 V DC
2
 v ao  
TS t
V DC t dead
sign ( io )
2 TS
Dead-times effect: when a positive current IO flows through the load, the actual on time for switch S1 is shorter
than the desired one. Consequently, the average voltage across the load is different from the desired one.
101/136
Effect of Blanking Time t
1
V DC
2
D1
G1
E1
a
o
1
VDC
2
ia
Ls
Rs
0
es
vL
G2
v control
vtri
S1
(c)
S2
D2
E2
(a)
vao
(d)
ia  0
Ideal condition (no dead time)
vGE1
0
t
vGE 2
0
t
t
vGE1
0
vref
t
vGE 2
0
t
loss
(e)
vao
iA  0
0
ideal
iA  0
actual
t
Ts
gain
(f)
(b)
Ideal condition (no dead time)
t
ia  0
V
V
t
actual
0
ideal
t
Outputs Distortion Due to Dead-time Effect
No dead time
D1
G1
E1
es
(a)
Vao ,1  t 
S1
1
V DC
2
Ls
o
Rs
with dead time
0
a
vL
1
V DC
2
V
t
ia
S2
G2
D2
I a ,1  t 
E2
0
vao
t
ia  0
V
(b)
(c)
ia  0
vref
V
V  
Due to the current
sign change
V DC t dead
sign ( ia )
2 TS
103/136
Voltage Drop Vo Induced by the Blanking Time
TA
A
Vdc
TB 
iB
D A
iA
io
D A
TA
0
vo
DB 
B
DB 
TB 
t
iA  0
v AN
0
vBN
ideal
actual
Ts
t
0
Ts
v  (v AN ) ideal  (v AN ) actual
t
VAN
VBN
 t
  T Vdc
 s

  t Vdc
 Ts
 t
  T Vdc
 s

  t Vdc
 Ts
iA  0
iA  0
iA  0
iA  0
2 t

V
V
Vdc





AN
BN

Ts

Vo  
  2t Vdc
 Ts
iA  0
iA  0
Effect of t on Vo
vo
T A
A
Vdc
TB 
iB
D A
iA
io
D A
T A
vo
TB 
io  0
No blanking time
(independent of io)
Vo
DB 
B
0
DB 
Vo
io  0
vcontrol
(b)
(a)
Effect of t on Vo, where Vo is defined as a voltage drop if positive.
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
105/136
Effect of t on the Sinusoidal Output
vo (t )
ideal
actual
0
t
Measured current of a PWM inverter
with dead-time distortion.
io
0
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
t
106/136
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Filter Design for Grid Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
107/136
Control Architecture of a Single-Phase NPC Grid
Inverter
GRID
P
ia
Source
or
Load
L1
ig
L2
ic
O
v
Cf
vc
vg
Lg
ve
N
ia
Modulator
vc
v*
Controller
vdc1
vdc1
ig
vg

PLL
108/136
LCL Ripple Filter & EMI Filter of a Grid Inverter
PWM Inverter
DC-link
S1
S3
Ripple Filter
L1
a
L2
C
Vdc
ig
F1
Cx
Ty C
y
Tx
Cx
Cy
RV1
Lg
L
G
vg
ve
F2
b
N
S4
S2
GRID
Protection
EMI Filter
DC-link
Return
L
L
L1
C
1st-order L Filter
2nd-order LC Filter
Current Fed
Voltage Fed
L2
C
L1 L
o
L2
Co
3rd-order LCL Filter
4st-order LLCL Filter
Current Fed
Current Fed
Frequency Response of the LCL Filter
H f (s)
S3
S1
L1
a
Vdc
Cdc
S2
H f 1 ( s) 
H f (s) 

Cf
iL1
Rd
S4
ic
iL 2
0dB
vg
g 0
dB60Hz
1
sL0
b
ig ( s )
vab ( s) v
20dB / dec
L2 ig
vc
1

sL0
60dB / dec
70dB
ig ( s )
vab ( s ) v
60 Hz
1
L1  L2
1
C ( L1 P L2 )
2 f s
g 0
sC f Rd  1
s 3 L1 L2C f  s 2C f Rd ( L1  L2 )  s ( L1  L2 )
Inductance reduction with LCL filter: 20 log
L0
 dB
L1  L2
2011.A Single Phase Grid Connected DC-AC Inverter with Reactive Power Control for Residential PV Application (Xiangdong Zong).pdf

Frequency Response of LCL Ripple-Rejection Filter
H f ( s)
20
1
s ( L1  L2 )
dB60Hz
0
-20dB/dec
20 log Q
Gain [dB]
-20
1
sL
-40
dB fs
-60
-80
1
s 3 L1 L2C f
-60dB/dec
-100
10
10 2
1
2 L0
60 Hz
10 3
1
2 ( L1  L2 )
10 4
1
2 L1L2C
fr 
10 5
fs
Hz
1
2 (L1 P L2 )Cf
Single Inductor Filter Design: Design Guide Lines
 單電感濾波器的設計較為簡單，也可提供濾波器與控制迴路設計的參考。
 併網電流在額定輸出的總諧波失真(≤5%)是濾波器設計的主要規格。假設其中
2%來自電流漣波，另外3%來則其他非線性導致的失真，則來自電流漣波所導致
的總諧波失真THD=2%可作為一階單電感濾波器的設計規格。
 濾波器與控制器頻率響應所構成的控制迴路，應使其閉路之頻寬介於電網頻率
與開關頻率之間，同時維持足夠之相位邊界(phase margin > 60)。
H f ( s)
0dB
 20 d B / de c
 d B 60 H z
 60 d B / de c
1
s L0
 7 0d B
60 Hz
1
L1  L 2
1
C ( L1 P L 2 )
2 f s

112/136
References: LCL Filter Design
[1] Chapter 11: Grid Filter Design, Grid Converters for Photovoltaic and Wind Power Systems, Remus Teodorescu, Marco Liserre, and Pedro
Rodriguez, Wiley; 1 Ed., IEEE Press, April 12, 2011.
[2] P.A. Dahono, A. Purwadi, Qamaruzzaman, “An LC filter design method for single-phase PWM inverters,” IEEE Power Electronics and
Drive Systems (PEDS) Conf. Proc., pp. 571-576, 21-24 Feb 1995.
[3] Michael Lindgren and Jan Svensson, “Control of a voltage-source converter connected to the grid through an LCL-filter-application to
active filtering,” IEEE IAS Annual Meeting, pp. 229-235, 1998.
[4] M. Liserre, F. Blaabjerg, and S. Hansen, “Design and control of an LCL-filter based three-phase active rectifier,” IEEE IAS Annual Meeting,
pp. 299-307, 2001. [see also: M. Liserre, F. Blaabjerg, and S. Hansen, “Design and control of an LCL-filter-based three-phase active
rectifier,” IEEE Trans. Ind. Appl. vol. 41, no. 5, pp. 1281-1291, October 2005.]
[5] M. Liserre, F. Blaabjerg, and A. Dell’Aquila, “Step-by-step design procedure for a grid-connected three-phase PWM voltage source
converter,” International Journal of Electronics, vol. 91, no. 8, pp. 445–460. August 2004.
[5] F.A. Magueed and J. Svensson, “Control of VSC connected to the grid through LCL -filter to achieve balanced currents,” IEEE IAS Annual
Meeting, pp. 572-578, 2005.
[6] R. Hamid and Hadi Saghafi, “Basic criteria in designing LCL filter for grid connected converters,” IEEE ISIE Conf. Proc., pp. 1996-2000,
July 2006.
[7] Fei Liu, Shanxu Duan, Pengwei Xu, Guoqiang Chen, and Fangrui Liu, “Design and control of three-Phase PV grid connected converter with
LCL filter,” IEEE IECON Conf. Proc., pp. 1656-1661, Nov. 2007.
[8] A. Papavasiliou, S.A. Papathanassiou, S.N. Manias, and G. Demetriadis, “Current control of a voltage source inverter connected to the grid
via LCL filter,” IEEE PESC Conf. Proc., pp. 2379-2384, June 2007.
[9] S. Saridakis, E. Koutroulis, and F. Blaabjerg, “Filter optimization of Si and SiC semiconductor-based H5 and Conergy-NPC transformerless
PV inverters,” 15th European Conference on Power Electronics and Applications (EPE), pp. 1-10, 2-6 Sept. 2013.
[10] A. Reznik, M.G. Simoes, A. Al-Durra, and S.M. Muyeen, “LCL filter design and performance analysis for grid-interconnected systems,”
IEEE Transactions on Industry Applications, vol. 50, no. 2, pp. 1225-1232, March-April 2014.
[12] S. Sen, K. Yenduri, and P. Sensarma, “Step-by-step design and control of LCL filter based three phase grid-connected inverter,” IEEE
International Conference on Industrial Technology (ICIT), pp. 503-508, 2014.
[10] Y. Zhang, M. Xue, M. Li, Y. Kang, and J. M. Guerrero, “Co-design of the LCL filter and control for grid-connected inverters,” Journal of
Power Electronics, vol. 14, no. 5, pp. 1047-1056, 2014.
113/136
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Modeling of Grid Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
114/136
A Hybrid DC & AC Microgrid System
i pv
i1 1  d1 
i1
L1
PV
Temperature
v pv
C pv
ST
ib
D
ic
idc
vT vdc
Cd
ST7
iac
D7
ib
DC Load
Solar irradiation
R1
L3
R3
vbat
D
ST8
D8 vD
Battery
Boost Converter
Battery Converter
DFIG
ST1
Wind
Gear
Speed
AC Load
AC/DC/AC
C2
iC
iB
iA
Utility
Grid
L2
ST5
D3
ST3
D1
R2
D5
C
B
A
ST4
ST6
D4
Breaker
ST2
D6
D2
Main Converter
115/136
Modeling of a Single-Phase Grid Inverter
(a) Full-bridge grid inverter
(b) Hybrid NPC Full-bridge grid inverter
REF: Bradford Christopher Trento, Modeling and Control of Single Phase Grid-Tie Converters, Master Thesis, University of Tennessee,
Knoxville, 2012.
Single-Phase Half-Bridge Grid Inverter
Summary of dq-Transformation

abc
Vm

va (t)
vb ( t )
vc ( t)
dq
fa  fb  fc  0
t1
1
1  f 



1
  a
 f  2 
2
2
   fb 
f  
3
3
3

 
0
   fc 

2
2
q
1.0
 f d   cos  sin    f 
f 
 f 
sin

cos






q
  
  
 f d  2  cos  cos   
f  
 q  3  sin   sin   

2
3
1.5
b
2
3

va (t) v (t)
b
 fa 
cos      
 fb



 sin      
 f c 
 = angle between d-q and  reference frames
vs (t1)
0.5
c
vc (t)
d

a
Summary of dq-Transformation ..
dq
 f    cos  
f 
    sin  

abc
 sin    f d 
 
cos     f q 
 sin   
 f a   cos  
 f    cos      sin       f d 
 b 
  fq 
 f c   cos      sin      

 1
 fa  
 f    1
 b  2
 f c  
 1
 2

0 

3   f 
 
2   f 

3

2 
fa  fb  fc  0
119/136
Modeling of a Full-Bridge Grid Inverter in Natural
Reference Frame
120/136
Modeling of a Full-Bridge Grid Inverter in dq-Model
Synchronous Reference Frame
Simulation Model for a Three-Phase Grid-Connected PV Inverter System
PV Solar Array
Np +Vpv /2
Three-Phase Three-Level
Voltage Source Inverter
Boost DC/DC
Converter
Lb
Db
Line Filter
Step-Up
Coupling
Transformer
Electric Utility Grid
PCC
+Vd /2
LF1
PV
Cd1
PV
PV
PV
PV
PV
Ns
LF2
Tbst
Cb
0
Dfd
NP
a
b
LF3
c
CF1
-Vpv /2
Cd2
-Vd /2
CF2
CF3
REF: Marcelo G. Molina, and Luis E. Juanico, “Dynamic modelling and control design of advanced photovoltaic solar system for
distributed generation applications,” Journal of Electrical Engineering: Theory and Application, vol. 1, pp. 141-150, 2010.
1:N(  : Yg)
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Control of Grid Inverters
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機控制工程研究所
台灣新竹‧交通大學‧電機控制工程研究所‧電力電子實驗室~鄒應嶼 教授
123/136
Generic Control Structure for a PV Inverter with Boost
Stage
L
PV
Panels
String
dc-ac
PWMVSI
dc-dc
boost
C
PWM
IPV
VPV
Vdc
Control
Vdc
LCL
filter
N
X’form
&
Grid
PWM
Grid
Synchronization
Current
Control
Ig
Vg
Basic Functions (grid connected converter)
MPPT
Anti-Islanding
Protections
Grid /PV plant
Monitoring
PV specific functions
Active Filter
Control
Micro Grid
Control
Grid Support
(V,f,Q)
Ancillary functions
124/136
Block Diagram of a Single-Phase Grid Inverter
DC
DC
Battery
DC
Cdc
Vdc
Islanding
Protection
PLL
igrid
iref
Current
Control
MPPT
Current
Controller
*
iCHG
vgrid
AC
idc
vdc
Grid
*
vdc
Load Power Control
sin(grid t )
VDC ctrl
PLL Controller
S3
S1
 ff
L
A
Loop Filter
VCO
va *
Vdc
iL

vg
PD

1
s
PI
B
S2
S4
vˆa
Line Voltage
Detector
va
Current Control of Single-Phase VSI Inverters
vs
iPV
iinv
is*
ic S1
vdc
Cdc
Current
Controller
B
is*
is
vab
1
rL  sLs
is
PI Control
IP Control
Proportional Resonant (PR) Control
Feed-Forward PR Control
vm
Ki
s
PWM
Bridge
vab
1
rL  sLs
is
KP
PWM
Controller
is




PWM
Bridge
vs
vs
S4
vm
Ki
s
Ls
A
S2
is*
vs
S3
Kp 
KP
is*
vm
Kr
1 (
r
s
)2
vab
vs
1
rL  sLs
PWM
Bridge
is
vs
KP
is*
vm
Kr
1 (
r
s
)2
PWM
Bridge
1
rL  sLs
Fen Li, Yunping Zou, Wei Chen, and Jie Zhang, “Comparison of current control techniques for single-phase voltage-source PWM rectifiers,”
IEEE International Conference on Industrial Technology (ICIT), pp.1-4, 21-24 April 2008.
is
Current Control Architectures
is
is
Sa

*
Sb
Sb
Sc
abc
is
Sc
abc
is
3
3
Adaptive
Controller
(b) Adaptive hysteresis control.
(a) Hysteresis control.
is
Sa

*
*
vs
*
Sa

i*k 
Sb
Sa
Minimization
Sb
of
ik 1 g function
Sc
Predictive
model
Sc
abc
is
3
vs
ik 
3
sk 
(c) PWM ramp control.
ik 
(d) Predictive control.
127/136
Current Control Architectures of 3-Phase VSI
V dc
Carrier
i
*
a
i
*
b
uAc
ic*
Feedforward
Disturbance
SA
uBc
SB
uCc
SC
Kf
i *s
Kd
usc
Ki
ia
ib
Integral part
is
ic
Kp
PWM
modulator
State
feedback
Three-phase
Load
Three-phase
Load
(a) Stationary PI in three-axis coordinates
i c
i
(b) State feedback controller in three-axis
K1
K2
V dc
uc
Current
regulator
isdc
PI

PWM
modulator
c
K2
i
PI
isqc
ABC
i c
u c
isd
i
K1

i
ia
ib
ic
isq
V dc
Coordinate
transformation
dq


PWM
modulator
ABC
sin  s
cos  s
dq


ABC
ia
ib
ic
Three-phase
Load
ABC
(c) PI in stationary coordinates
Vdc
Three-phase
Load
(b) PI in synchronous coordinates
Current Control Techniques
idc
idc
iinv
ic S1
vdc
v dc
S3
S4
Current
Controller
vdc
vdc
vs
S2
is*
vs
ic S1
Ls
A
Cdc
iinv
S3
A
Cdc
B
vs
S2
is
id*
PWM
Controller
Current
Controller
iq*
is
vq
Ls
S4
B
is
PWM
Controller
CT
iq
id
is
(a) Control in stationary frame with control of signals in ac
quantities.
Coordinate
Transform
vs

PLL
(b) Control in synchronous rotating frame with control of
signals in dc quantities.
129/136
Control in Stationary Reference Frame
Vdc
V
*
dc
DC-link
controller
i*
*
d
i
i
dq
Q*
Q
controller
Q
PR
controller
*
q
i

v*
HC
HC

PR
controller
*
i
i
v *
Modulation
And
PWM
Inverter
ia ib ic
abc

va vb vc
Grid
PLL

General structure for stationary reference frame control strategy using resonant controllers and
harmonic compensators.
Ki s

 K p  s2   2
0
(  )
GPR
( s)  

0





Kis 
Kp  2
s  02 
0
130/136
Control in Synchronous Reference Frame
vd
Vdc
*
d
i
DC-link
controller
Vdc*
*
d
v
PI
controller
id
Modulation
and
PWM
Inverter
 L
L
Q*
Q
controller
Q
*
q
i
vq*
PI
controller
ia ib ic
abc
iq
id
vq
va
vb
vc


PLL
dq
iq
Grid
abc
dq
vd vq
General structure for synchronous rotating frame control using cross-coupling and voltage
feedforward terms.
K

Kp  i

s
( dq )
GPR
(s)  
 0

 Control in the synchronous reference frame transforms the reference signals
and the feedback signals to dc quantities from a fixed reference frequency.

  In this control scheme, the accuracy of this reference angle () of the

reference frame is the key for the elimination of the steady-state error. The
Ki 
Kp 
design of the PLL plays an important role for both transient and steady-state
s 
0
responses.
131/136
Synchronous Reference Frame Current Control for
Single-Phase PV Inverters
 ff
Vd  0
Grid Current
A
V̂d
V
d,q
V̂q
PWM
Modulator
Current
Controller
I d*
PI
I 0
*
q
PI
vd
vq
, 
V
ˆ
PV
String
1
s
s
Grid
Voltage
PLL
sk p  ki
Delay
I g*
d q
to
 
v
TV
ˆ
PLL
Id
-1
Iq
i
 
to
d q
i

2
2008.Synchronous Reference Frame Grid Current Control for Single-Phase Photovoltaic Converters (ias).pdf
ˆ
ˆ
Control of Three-Phase Three-Level Grid Inverter
va vb vc
MPPT Voltage Control
∆v
vr
iqr min
APCM
Vpv
Pg
vq
idr*
D
iq
vd
θs
L‘s
i d1
Vd
dq0
PID
controller
x2
vinv a vinv b vinv
c
vinv d
1
Three-Phase
Three-Level
VSI SPWM
PI2
Lmin
Lmin
id
abc
Three-phase
dq-PLL
dq0
L‘s
-1
abc
Threephase
VSI
IGBTs
Control
Pulses
∆Vdr
DC-DC
Converter
PWM
Vd
D
LPF
4
4
Lmax
Vd max
4
1
∆Vd
PID
controller
i q1
LPF
dq0
∆idr1
idr1
PI3
LPF
1
θs
Lmax
idr1
MPPT
Algorithm
vinv q
abc
idr mix
Pr1
vd 1
x1
Lmin
i d1
vm
vq 1
PID
controller
idr max
LPF
Mag(v)
∆iqr1
i q1
vm
Ttrack
Dini
C1
Lmax
PI1
iqr 1
Lag
compensator
Kv
vm
Ipv
iqr man
LC1
VCM
s
1
1
DC-DC
Converter
IGBTs
Control
Pulses
0
Vd min
va
vb
vc
θs
ia
ib
ic
Current Control
PWM Control
133/136
Evaluations of Current
Controllers
(a) General structure for synchronous rotating frame control
using cross-coupling and voltage feedforward terms.
(b) General structure for stationary reference frame control
strategy using resonant controllers and harmonic compensators.
A. Timbus, M. Liserre, R. Teodorescu, P. Rodriguez, and F. Blaabjerg,
“Evaluation of current controllers for distributed power generation systems,”
IEEE Transactions on Power Electronics, vol. 24, no. 3, pp. 654-664, March
2009.
134/136
Control Algorithms for the Grid Inverters
vdc
vm
v dc
is*











d
PWM
Modulator
vab
1
sL1  rL1
is
vs
Hysteresis Control, Variable Hysteresis Control
PI Control, IP Control, Adaptive PI Control
Dead-Beat Control, Soft Dead-Beat Control
Predictive Control, Adaptive Predictive Control
Proportional Resonant (PR) Control
Repetitive Control, Adaptive Repetitive Control
Repetitive Control with Limited BW Constraint
H∞ Repetitive Control
Fuzzy Control
Phase-Locked Loop Control
Control Loop Design with LCL, LCCL, and LLCL Filter
References: Control of Inverters
Review of Control Architectures
[1]
J. R. Michael, E. B. William, and D. L. Robert, “Control topology options for single-phase UPS inverters,” IEEE Trans. on. Ind. Appli.,
vol. 33, no. 2, pp. 493-502, March/April 1997.
[2] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review of single-phase grid-connected inverters for photovoltaic modules,” IEEE Trans.
Ind. Appl., vol. 41, no. 5, pp. 1292–1306, Sep./Oct. 2005.
[3] David M. Brod and Donald W. Novotny, “Current control of VSI-PWM inverters,” IEEE Transactions on Industry Applications, vol. 21,
no. 3, pp. 562-570, May 1985.
[4] A. Kawamura and T. Yokoyama, “Comparison of five different approaches for real time digital feedback control of PWM inverter,” in
IEEE IAS Annu. Meet. Conf. Rec., 1990, pp. 1005–1011.
[5] L. Malesani and P. Tomasin, “PWM current control techniques of voltage source converters-a survey,” IEEE IECON Conf. Proc., 1993.
[6] M. P. Kazmierkowaski and L. Malesani, “PWM current control techniques for three-phase voltage source converters - a survey,” IEEE.
Trans., on Ind. Electron., vol. 45, no. 5, pp. 691-703, Oct.1998.
[7] Leonardo Augusto Serpa, Current Control Strategies for Multilevel Grid Connected Inverters, PhD Thesis, SWISS FEDERAL
INSTITUTE OF TECHNOLOGY, ZURICH, 2007.
[8] Yaow-Ming Chen, Hsu-Chin Wu, Yung-Chu Chen, Kung-Yen Lee, and Shian-Shing Shyu, “The AC line current regulation strategy for the
grid-connected PV system,” IEEE Transactions on Power Electronics, vol. 25, no. 1, pp. 209-218, 2010.
[9] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overview of control and grid synchronization for distributed power
generation systems,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1398–1409, Oct. 2006.
[10] A. Timbus, M. Liserre, R. Teodorescu, P. Rodriguez, and F. Blaabjerg, “Evaluation of current controllers for distributed power generation
systems,” IEEE Transactions on Power Electronics, vol. 24, no. 3, pp. 654-664, March 2009.
136/136
Power Electronics: Devices, Drivers, Applications, and
Passive Components
Prof Barry Wayne Williams , Mcgraw-Hill; 2 Sub Ed., September 1992.
14
Power Inverters
Inversion is the conversion of dc power to ac power at a desired output voltage or current and
frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation.
The terms voltage-fed and current-fed are used in connection with the output from inverter circuits.
A voltage-source inverter (VSI) is one in which the dc input voltage is essentially constant and
independent of the load current drawn. The inverter specifies the load voltage while the drawn current
shape is dictated by the load.
A current-source inverter (CSI) is one in which the source, hence the load current is predetermined and
the load impedance determines the output voltage. The supply current cannot change quickly. This
current is controlled by series dc supply inductance which prevents sudden changes in current. The load
current magnitude is controlled by varying the input dc voltage to the large inductance, hence inverter
response to load changes is slow. Being a current source, the inverter can survive an output short circuit
thereby offering fault ride-through properties.
Voltage control may be required to maintain a fixed output voltage when the dc input voltage regulation
is poor, or to control power to a load. The inverter and its output can be single-phase, three-phase or
multi-phase. Variable output frequency may be required for ac motor speed control where, in conjunction with voltage or current control, constant motor flux can be maintained.
Inverter output waveforms (either voltage or current) are usually rectilinear in nature and as such contain
harmonics which may lead to reduced load efficiency and performance. Load harmonic reduction can be
achieved by either filtering, selected harmonic-reduction chopping or pulse-width modulation.
The quality of an inverter output is normally evaluated in terms of its harmonic factor, ρ, distortion factor,
µ, and total harmonic distortion, thd. In section 12.6.2 these first two factors were defined in terms of the
supply current. For VSI inverters the factors are redefined in terms of the output voltage harmonics as
follows
V
n >1
ρ n = n = nµn
(14.1)
V1
The distortion factor for an individual harmonic is
ρ
V
µn = n = n
nV1
n
14.1
∑
∑
424
14.1.1i - Square-wave (bipolar) output
Figure 14.1b shows waveforms for a square-wave output (2t1 = t2) where each device is turned on as
appropriate for 180°, (that is π) of the output voltage cycle (state sequence 10, 01, 10, ..).
The load current iL grows exponentially through T1 and T2 (state 10) according to
di
(V)
(14.4)
Vs = L L + iL R
dt
When T1 and T2 are turned off, T3 and T4 are turned on (state 01), thereby reversing the load voltage
polarity. Because of the inductive nature of the load, the load current cannot reverse instantaneously
and load reactive energy flows back into the supply via diodes D3 and D4 (which are in parallel with T3
and T4 respectively) according to
di
−Vs = L L + iL R
(V)
(14.5)
dt
The load current falls exponentially and at zero, T3 and T4 become forward-biased and conduct load
current, thereby feeding power to the load.
The output voltage is a square wave of magnitude ± Vs, figure 14.1b, and has an rms value of Vs.
For a simple R-L load, with time constant τ = L /R, during the first cycle with no initial load current,
solving equation (14.4) yields a load current
−t
V 

(A)
(14.6)
iL (t ) = s  1 − e τ 
R

∨
Under steady-state load conditions, the initial current is I as shown in figure 14.1b, and equation (14.4)
yields
iL (t ) =
Vs  Vs ∨  −τt
−
− I e
(A)
R  R

0 ≤ t ≤ t1 = ½T
(14.7)
(s)
Vab
a
b
VL
o
+Vs
δ
½
1
-Vs
(14.2)
α
α
2
∞
∞
 ∞  Vn  2 
 ρn 
µn2 =
(14.3)
    / V1 =


n≥2
n≥2  n 
 n ≥ 2  n  
The factor Vn /n is used since the harmonic currents produced in an inductive load attenuate with
frequency. The harmonic currents produce unwanted heating and torque oscillations in ac motors,
although such harmonic currents are not a drawback to the power delivered to a resistive heating load or
incandescent lighting load.
thd =
Power Inverters
∑
∧
∧
I
∨
I
T
½T
I
I1
T
½T
dc-to-ac voltage-source inverter bridge topologies
14.1.1 Single-phase voltage-source inverter bridge
Figure 14.1a shows an H-bridge inverter (VSI) for producing an ac voltage and employing switches
which may be transistors (MOSFET or IGBT), or at high powers, thyristors (GTO or GCT). Device
conduction patterns are also shown in figures 14.1b and c. With inductive loads (not purely resistive),
stored energy at turn-off is fed through the bridge reactive feedback or freewheel diodes D1 to D4. These
four diodes clamp the load voltage to within the dc supply voltage rails (0 to Vs).
BWW
Figure 14.1. GCT thyristor single-phase bridge inverter:
(a) circuit diagram; (b) square-wave output voltage; and (c) quasi-square-wave output voltage.
Power Electronics
425
for vL = Vs
Power Inverters
(V)
∨
I ≤0
(A)
During the second half-cycle (t1 ≤ t ≤ t2) when the supply is effectively reversed across the load, equation
(14.5) yields
V  V ∧  −t
V  
 t   −t 
iL (t ) = − s +  s + I  e τ = − s  1 −  1 + tanh  1   e τ 
(A)

R R
R
(14.8)
 2τ   

 
0 ≤ t ≤ t2 − t1 = ½T
(V)
for vL = − Vs
(s)
∧
I ≥0
(A)
A new time axis
has
been used in equation (14.8) starting
at t = t1 in figure 14.1b. Since in steady-state
∧
∨
∧
by symmetry,
I = - I , the initial steady-state current I can be found from equation (14.7) when, at t = t1,
∧
iL = I yielding
− t1
Vs 1 − e τ
V
 t 
= s tanh  1 
(14.9)
(A)
− t1
R
R
 2τ 
1+ e τ
The zero current cross-over point tx, shown on figure 14.1b, can be found by solving equation (14.7) for t
= tx when iL = 0, which yields
 I∨ R 

t x = τ An  1 −

Vs 


(14.10)

 IR
= τ An  1 +
(s)
 Vs 


The average thyristor current, I T , average diode current, I D , and mean source current, I s can be found
by integration of the load current over the appropriated bounds.
1 t1
IT =
iL ( t ) dt
t2 tx
(14.11)
− to
1 V
V
  − t1

=  s ( t1 − to ) + τ  s + I   e τ − e τ  
t2  R

R

where iL is given by equation (14.7) and
1 tx
ID =
−iL ( t ) dt
t2 0
(14.12)
1 V
V
 − tx

=  − s t x − τ  s + I  e τ − 1 
t2  R
R



where iL is given by equation (14.8).
Inspection of the source current waveform in figure 14.1b shows that the average dc voltage source
current is related to the average semiconductor device currents by
∧
∨
I = -I =
∫
∫
(
Is = 2 I T − I D
=
1
t2
)
(14.13)
 Vs
 Vs   −τt

 t1 + τ  + I   e − 1 
R
R




1
The steady-state mean power delivered by the dc supply and absorbed by the resistive load component
R is given by
1 t
2
PL = ∫ Vs iL( t ) dt = Vs I s ( = I Lrms
R)
(14.14)
(W)
t1 0
where iL(t) is given by equation (14.7). Rather than integration involving equations (14.7) and (14.8), the
mean load power can be used to determine the rms load current:
1
VI
= s s
(A)
R
R
The rms output voltage is Vs and the output fundamental frequency fo is f o = 1 T =
iLrms =
PL
(14.15)
1
2t1 =
1
t2 .
426
The instantaneous output voltage expressed as a Fourier series is given by
∞
1
4
VL = Vs ∑ sin nωo t
(V)
π n odd n
where ωo = 2π f o = 2π / t2 and for n = 1 the magnitude of the fundament frequency fo is
output rms fundamental voltage vo1 of
vo1 =
2 2
π Vs = 0.90Vs
(14.16)
4
π Vs which is an
(14.17)
(V)
The load current can be expressed in terms of the Fourier voltage waveform series, that is
∞
4
1
sin ( nωo t − φn )
iL (ωt ) = Vs ∑
π n =1, 3, 5 nZ n
∞
=
∑
=
I n sin ( nωo t − φn )
(14.18)
n 1, 3, 5
where I n =
I
4 Vs
whence I n rms = n
π nZ n
2
φn = tan −1 nωo L R
Z n = R 2 + (nωo L) 2
such that
cos φ1 = R
Z1
The fundamental output power is
2
2
v o1 
V s2  2 2 
2

 cos φ1
 R =
Z
R  π 
 1
The load power is given by the sum of each harmonic i2R power component, that is
P1 = I 12R = 
2
∞
∞
(
)
 In
 R=
I n2 R
= Vs I s


rms
2
n=1, 3, 5 
n=1, 3, 5
Alternately, after integrating equation (14.14), with the load current from equation (14.8)
t

− 1 
V2
 t 
2τ 1 − e τ  V s2 
2τ
=
tanh  1  
PL = s 1 −
1 −
t
− 1 
R 
t1
R 
t1
 2τ  
τ 
1+e 

PL =
∑
∑
(14.19)
(14.20)
(14.21)
2
R the rms loads current is
From PL = i rms
i L rms =
Vs
R
1−
2τ
t1
t 
tanh  1 
 2τ 
(14.22)
The load power factor is given by
i L rsm R
t 
P
2τ
tanh  1 
=
= 1−
S i L rmsv rms
t1
 2τ 
2
pf =
(14.23)
14.1.1ii - Quasi-square-wave (multilevel) output
The rms output voltage form a H-bridge can be varied by producing a quasi-square output voltage (2t1 =
t2, t0 < t1) as shown in figure 14.1c. After T1 and T2 have been turned on (state 10), at the angle α one
device is turned off. If T1 is turned off (and T4 is turned on after a short delay), the load current slowly
freewheels through T2 and D4 (state 00) in a zero voltage loop according to
di
(14.24)
0 = L L + iL R
(V)
dt
When T2 is turned off and T3 turned on (state 01), the remaining load current rapidly reduces to zero
back into the dc supply Vs, through diodes D3 and D4. When the load current reaches zero, T3 and T4
become forward biased and the output current reverses, through T3 and T4.
The output voltage shown in figure 14.1c consists of a sequence of non-zero voltages ±Vs, alternated
with zero output voltage periods. During the zero output voltage period a diode and switch conduct,
firstly T1 and D3 in the first period, and T3 and D1 in the second zero output period. In each case, a zero
voltage loop is formed by a switch, diode, and the load. The next two zero output sequences would be
T2 and D4 then T4 and D2, forming alternating zero voltage loops (sequence 10, 00, 01, 11, 10, ..) rather
than repeating a continuous T1 and D3 then T3 and D1 sequence of zero voltage loops (sequence 10, 11,
01, 11, 10, .. or sequence 10, 00, 01, 00, 10, ..). By alternating the zero voltage loops (between states
00 and 11), losses are uniformly distributed between the semiconductors, device switching frequency is
half that experienced by the load, and a finer output voltage resolution is achievable.
Power Electronics
427
Power Inverters
With reference to figure 14.1c, the load current iL for an applied quasi square-wave voltage is defined as
follows.
(i) vL > 0
V V
 −t
iL (t ) = s −  s − I o  e τ
0 ≤ t ≤ to
(14.25)
R R

I
for I o ≤ 0
(ii) vL = 0
∧
−t
0 ≤ t ≤ t1 − to
II
∧
for I ≥ 0
(iii) vL < 0
(14.26)
(A)
V V
 −t
iL (t ) = − s +  s + I1  e τ = −iL (t )
R R

for I1 ≥ 0
(A)
0 ≤ t ≤ to
I
the n harmonic can be eliminated when cos½nα = 0 , that is for α = π / n . In so eliminating the nth
harmonic, from equation (14.38), the magnitude of the fundamental is reduced to 4 π Vs cos π n .
The output voltage VL in its Fourier coefficient series form is given by
∞
4
cos ½ nα
sin nωo t
(V)
VL = Vs ∑
(14.38)
π
(14.27)
−e τ
t
−o
Vs 1 − e τ
(A)
(14.29)
t
−1
R
1+ e τ
I1 = − I o
(A)
(14.30)
The zero current cross-over instant, tx, shown in figure 14.1c, is found by solving equation (14.25) for t
when iL equals zero current.
 I R
 I R
t x = τ An  1 − o  = τ An  1 + 1 
(14.31)
Vs 
Vs 


I =
The average thyristor current, I T , average diode current, I D , and mean source current, I s can be found
by integration of the load current over the appropriated bounds (assuming alternating zero volt loops).
1 t
1 t −t
I T = ∫ iL ( t ) dt +
iL ( t ) dt
(14.32)
2t2 ∫ 0
t2 t
where iL is given by equations (14.25) and (14.26) for the respective integrals, and
1 t
1 t −t
I D = ∫ −iL ( t ) dt +
iL ( t ) dt
(14.33)
2t2 ∫ 0
t2 0
where iL is given by equations (14.25) and (14.26) for the respective integrals.
1
x
1
o
I
II
1
x
o
I
II
Inspection of the source current waveform in figure 14.1c shows that the average source current is
related to the average semiconductor device currents by
1 to
I s = ∫ iL (t )dt = 2 I T − I D
(14.34)
t1 0
The steady-state mean load and dc source powers are
1 t
2
(W)
PL = ∫ Vs iL( t ) dt = Vs I s
R)
(14.35)
( = I Lrms
t1 0
where iL(t) is given by equation (14.25). The mean load power can be used to determine the rms load
current:
(
I
)
o
I Lrms =
PL
R
=
Vs I s
The output fundamental frequency fo is f o =
(14.36)
(A)
R
1
2t1 =
1
t2
The variable rms output voltage, for 0 ≤ α ≤ π, is
1 t 2
vrms =
Vs dt = 1 − α π Vs
t1 ∫ 0
o
and the output fundamental frequency fo is f o =
1
t2
.
(14.37)
. This equation for rms output voltage shows that only
(14.40)
In
2
φn = tan −1 nωo L R
(14.28)
(A)
− t1
1+ e τ
∧
cos½ nα whence I n rms =
The load power is given by the sum of each harmonic i2R power component, that is
2
∞
∞
I
 R=
PL = ∑  n
I n2 R
= Vs I s

∑
rms
2
n = 1, 3, 5 
n =1, 3, 5,...
(
)
(14.41)
1
Vrms
0.9
V1
0.8
per unit
τ
4 Vs
π nZ n
Z n = R 2 + (nωo L) 2
− t1
1−α
squarewave
α=0
0.6
Output Voltage
Vs e
R
(14.39)
The load current can be expressed in terms of the Fourier voltage waveform series, that is
∞
∞
V
4
cos½ nα
sin ( nωo t − φn ) = ∑ I n sin ( nωo t − φn )
iL (ωt ) = L = Vs ∑
Z L π n =1,3,.. nZ n
n =1, 3, 5,..
The currents I o , I , and I1 are given by
Io = −
n
π
The characteristics of these load voltage harmonics are shown in figure 14.2.
where I n =
∧
− t1 +to
n odd
and for n = 1, the rms fundamental of the output voltage vo1 is given by
2 2
vo1 =
Vs cos½α = 0.90 × Vs × cos½α
(V)
(A)
iL (t ) = I e τ
428
th
π
Vrms
V1
0.4
0.9 × cos½nα
V3
V3
V5
0.2
V5
V7
V7
0
0
0
20°
40°
60°
80°
100°
120°
½π
delay angle
140°
160°
180°
π
α
Figure 14.2. Full bridge inverter output voltage harmonics
normalised with respect to square wave rms output voltage, Vrms=Vs.
The load power and rms current can be evaluated from equations (14.21) and (14.22) provided the rms
voltage given by equation (14.37) replaces Vs. That is

V2
 t 
2τ
tanh  1  
PL = s 1 − α 1 −
(14.42)
π
R
t1
 2τ  

(
)
Power Electronics
429
i L rms =
Vs
R
1−α
π
1−
2τ
t1
t 
tanh  1 
 2τ 
Power Inverters
(14.43)
The load power factor is independent of α and is given by equation (14.23), that is
pf =
i L2rsm R
t 
P
2τ
tanh  1 
=
= 1−
S i L rmsv rms
t1
 2τ 
(14.44)
A variation of the basic four-switch dc to ac single-phase H-bridge is the half-bridge version where two
series switches (one pole or leg) and diodes are replaced by a split two-capacitor voltage source, as
shown in figure 14.3. This reduces the number of semiconductors and gate circuit requirements, but at
the expense of halving the maximum output voltage. Example 14.3 illustrates the half-bridge and its
essential features. Behaviour characteristics are as for the full-bridge, square-wave, single-phase
inverter but Vs is replaced by ½Vs in the appropriate equations. Only a rectangular-wave bipolar output
voltage can be obtained. Since zero volt loops cannot be created, no rms voltage control is possible.
The rms output voltage is ½Vs, while the output power is a quarter that of the full H-bridge.
Example 14.1a:
Single-phase H-bridge with an L-R load
A single-phase H-bridge inverter, as shown in figure 14.1a, supplies a 10 ohm resistance with
inductance 50 mH, from a 340 V dc source. If the bridge is operating at 50 Hz (output), determine the
average supply current and the load rms voltage and current and steady-state current waveforms with
i.
a square-wave output
ii.
a symmetrical quasi-square-wave output with a 50 per cent on-time.
Solution
The time constant of the load, τ = 0.05mH/10Ω = 5 ms, t1 = 10ms and t2 = 20ms.
i. The output voltage rms value is 340 V ac.
Equation (14.9) gives the load current at the time when the supply polarity is reversed across the load,
as shown in figure 14.1b, that is
− to
∧
∨
I = −I =
Vs 1 − e τ
−t
R
1+ e τ
1
(A)
where t1 = 10 ms. Therefore
340V 1 − e −2
×
(A)
10Ω 1 + e −2
= 25.9A
When vL = +340 V, from equation (14.7) the load current is given by
iL = 34 - (34 + 25.9) × e -200 t = 34 - 59.9e-200 t
0 ≤ t ≤ 10 ms
∧
∨
I = −I =
From equation (14.10) the zero current cross-over time, tx, occurs 5ms × An (1 + 25.9A×10Ω/340V ) =
2.83ms after load voltage reversal.
When vL = -340 V, from equation (14.8) the load current is given by
iL = -34 + (34 + 25.9) × e-200 t = -34 + 59.9e-200 t
0 ≤ t ≤ 10 ms
The mean power delivered to the load is given by equation (14.14), that is
10 ms
1
340V × {34 - 59.9 × e-200t } dt
PL =
10ms ∫ 0
= 2755 W
From P = i 2 R , the load rms current is
P
P
= 16.60A and I s = L = 2755W
= 8.1A
iLrms = L = 2755W
10Ω
340V
R
Vs
These power and rms current results can be confirmed with equations (14.21) and (14.22).
ii. The quasi-square output voltage has a 5 ms on-time, to, and a 5 ms period of zero volts.
From equation (14.37) the rms output voltage is
Vs 1 − 5ms /10ms = Vs 2 = 240V rms .
The current during the different intervals is specified by equations (14.25) to (14.30). Alternately, the
steady-state load current equations can be specified by determining the load current equations for the
430
first few cycles at start-up until steady-state conditions are attained.
First 5 ms on-period when vL = 340 V and initially iL = 0 A
iL = 34 - 34 e-200 t
and at 5ms, iL = 21.5A
First 5 ms zero-period when vL = 0 V
iL = 21.5 e-200 t
and at 5ms, iL =7.9A
Second 5 ms on-period when vL = -340 V
iL = -34 + (34+7.9) × e-200 t
with iL = 0 at 1 ms and ending with iL = -18.6 A
Second 5 ms zero-period when vL = 0 V
iL = -18.6 e-200 t
ending with iL = -6.8A
Third 5 ms on-period when vL = 340 V
iL = 34 - (34+6.8) × e-200 t
with iL = 0 at 0.9 ms and ending with iL = 19.0 A
Third 5 ms zero-period when vL = 0 V
iL = 19.0 e-200 t
ending with iL = 7.0A
Fourth 5 ms on-period when vL = -340 V
iL = -34 + (34+7.0) × e-200 t
with iL = 0 at 0.93 ms and ending with iL = -18.9 A
Fourth 5 ms zero-period when vL = 0 V
iL = -18.9 e-200 t
ending with iL = -7.0A
Steady-state load current conditions have been reached and the load current waveform is as shown in
figure 14.1c. Convergence of an iterative solution is more rapid if the periods considered are much
longer than the load time constant (and vice versa).
The mean load power for the quasi-square wave is given by
5ms
1
340V × {34 - 41× e-200 t } dt
PL =
10ms ∫ 0
= 1378 W
The load rms and supply currents are
P
P
= 11.74A
= 4.05A
iLrms = L = 1378W
I s = L = 1378W
10Ω
340V
R
Vs
♣
Example 14.1b:
H-bridge inverter ac output factors
In each waveform case (square and quasi-square) of example 14.1a calculate
i.
the average and peak current in the switches
ii.
the average and peak current in the diodes
iii.
the peak blocking voltage of each semiconductor type
iv.
the average source current
v.
the harmonic factor and distortion factor of the lowest order harmonic
vi.
the total harmonic distortion
Solution
Square-wave
∧
i. The peak current in the switch is I = 25.9 A and the current zero cross-over occurs at tx =2.83ms. The
average switch current, from equation (14.11) is
10ms
1
(34 - 59.9 e −200 t ) dt
IT =
20ms ∫ 2.83ms
= 5.71 A
Power Electronics
431
ii. The peak diode current is 25.9 A. The average diode current from equation (14.12) is
2.83ms
1
(34 - 59.9 e −200 t ) dt
ID =
20ms ∫ 0
= 1.66 A
iii. The maximum blocking voltage of each device is 340 V dc.
iv. The average supply current is
(
)
Is = 2 I T − I D = 2 × ( 5.71A - 1.66A ) = 8.10A
This results in the supply delivery power of 340Vdc × 8.10A = 2754W
v. From equation (14.16), with the third as the lowest harmonic, the distortion factors are
V
hf = ρ3 = 3 = 1 , that is, 33 1 3 per cent
3
V1
df = µ3 =
V3
3V1
= 1 , that is, 11.11 per cent
9
vi. From equation (14.16)
 Vn 
∑  n 
thd =
2
/ V1
( ) +( ) +( )
=
1
3
2
1
5
2
1
7
2
Quasi-square-wave, α = ½π (5 ms) and from equation (14.31) tx = 0.93ms
i. The peak switch current is 18.9 A.
From equation (14.32) the average switch current, using alternating zero volt loops, is
5ms
5ms
1
1
IT =
(34 - 41e-200 t ) dt +
19e-200 t dt
20ms ∫ 0.93ms
40ms ∫ 0
= 2.18 + 1.50 = 3.68 A
ii. The peak diode current (and peak switch current) is 18.9 A. The average diode current, from
equation (14.33), when using alternating zero volt loops, is given by
0.93ms
5ms
1
1
ID =
( −34 + 41e−200t ) dt + 40ms ∫ 0 19e-200t dt
20ms ∫ 0
= 0.16 + 1.50 = 1.66 A
iii. The maximum blocking voltage of each device type is 340 V.
)
I s = 2 I T − I D = 2 × ( 3.68A - 1.66A ) = 4.04A
This results in the supply delivery power of 340Vdc × 4.04A = 1374W
v. The harmonics are given by equations (14.1) to (14.3)
V
hf = ρ3 = 3 = 1
= 1 , that is, 33 1 3 per cent
/ 1
3
3 2
2
V1
V3
nV1
=
ρ3
n
=
1
9
, that is, 11.11 per cent
vi.
thd =
For each delay case (α = 0° and α = 90°) in example 14.1, using Fourier voltage analysis, determine
(ignore harmonics above the 10th):
i.
the magnitude of the fundamental and first four harmonics
ii.
the load rms voltage and current
iii.
load power
iv.
load power factor
Solution
The appropriate harmonic analysis is outline in the following table, for α = 0° and α = 90°.
n
Zn
harmonic
Vn (α=0)
R + ( 2π 50nL )
1
Ω
18.62
3
48.17
102
2.12
-72.12
-1.50
5
79.17
61.2
0.77
-43.28
-0.55
7
110.41
43.71
0.40
30.91
0.28
9
141.72
34
0.24
24.04
0.17
332.95V
16.59A
235.43V
11.73A
2
2
0.9Vs
n
V
306
In (α=0)
Vn
Zn
A
16.43
Vn (α=90°)
0.9Vs
cos (½ nα )
n
V
216.37
In (α=90°)
Vn
Zn
A
11.62
i. The magnitude of the fundamental voltage is 306V for the square wave and is reduced to 216V when
a phase delay angle of 90° is introduced. The table shows that the harmonics magnitudes reduce ( 1 n ) as
the harmonic order increases.
ii. The rms load current and voltage can be derived by the square root of the sum of the squares of the
fundamental and harmonic components, that is, for the current
irms = I12 + I 32 + I 52 + .....
The load rms currents, from the table, are 16.59A and 11.73A, which agree with the values obtained in
example 14.1a. Notice that the predicted rms voltages of 333V and 235V differ significantly from the
values in example 14.1a, given by Vs 1 − α π , namely 340V and 240.4V respectively. This is because
the magnitude of the harmonics higher in order than 10 are not insignificant. The error introduced into
the rms current value by ignoring these higher order voltages is insignificant because the impedance
increases approximately proportionally with harmonic number, hence the resultant current becomes
much smaller (insignificant) as the order increases.
iii. The load power is the load i2R loss, that is
2
PL = irms
R = 16.592 × 10Ω = 2752W for α = 0
iv. The load power factor is the ratio of real power dissipated to apparent power, that is
i2 R
2752W
P
= 0.488 for α = 0
pf = = rms =
S irms vrms 16.59A × 340V
i2 R
1376W
P
= rms =
= 0.486 for α = 90°
S irms vrms 11.79A × 240.4V
Equations (14.23) and (14.44) confirm the load power factor is 0.488, independent of α.
♣
pf =
Example 14.3: Single-phase half-bridge inverter with an L-R load
 ∞  Vn  2 
   
 n≥2  n  
∑
2
=
Example 14.2: Harmonic analysis of H-bridge inverter with an L-R load
2
PL = irms
R = 11.732 × 10Ω = 1376W for α = 90°
iv. The average supply current is
df = µ3 =
432
+ ......
= 46.2 per cent
(
Power Inverters
/ V1
2
2
2
 1   −1   1   1 
 3  +  5  +  7  +  9  + ...
       
♣
= 46.2 per cent
A single-phase half-bridge inverter as shown in the figure 14.3, supplies a 10 ohm resistance with
inductance 50 mH from a 340 V dc source. If the bridge is operating at 50 Hz, determine for the squarewave output
i.
steady-state current waveforms
ii.
the load rms voltage
iii.
the peak load current and its time domain solution, iL(t)
Power Electronics
433
Cl
Cl
Cl
Cu
Cupper
vi. When a switch or diode of a parallel pair conduct, the complementary pair of devices experience a
voltage Vs, 340V dc. Thus although the load experiences half the supply voltage, the semiconductors
experience twice that voltage, the same voltage experienced by the switches in the full bridge inverter.
Cu
VL
½Vs
+½Vs
½Vs
170V
δ
½
½Vs
+
∧
½Vs
I
tx
Clower
-170V
t1
12.95A
(a)
vii. The load power (whence various currents) is found by averaging the instantaneous load power
10 ms
1
P
P
170V × (17 - 29.95 × e-200t ) dt
PL =
irms = L
Is = L
R
Vs
10ms ∫ 0
= 638.5W
= 638.5 W
-12.95A
(b)
(c)
Figure 14.3. GCT thyristor single-phase half-bridge inverter:
(a) circuit diagram; (b) square-wave output voltage; and (c) output voltage transfer function.
Solution
From examples 14.1 and 14.2, τ = 5ms.
i. Figure 14.3 shows the output voltage and current waveforms, with various circuit component current
waveforms superimposed. Note that no zero voltage loops can be created with the half-bridge. Only
load voltages ±½Vs , that is ±170V dc, are possible.
ii. The output voltage swing is ±½Vs, ±170V, thus the rms output voltage is ½Vs, 170V. This is, half that
of the full-bridge inverter using the same magnitude source voltage Vs, 340V dc.
iii. The peak load current is half that given by equation (14.9), that is
10Ω
= 638.5W
= 8A
340V
= 1.88A
♣
-½Vs
∨
I
1
t2
2.83ms
434
The average diode current is given by
−t
2.83ms 
1

5ms
ID =
 17 − 29.95e  dt
20ms ∫ 0


= 0.83 A
the average and peak current in the switches
the average and peak current in the diodes
the peak blocking voltage of each semiconductor type
the power delivered to the load, rms load current, and average supply current
iv.
v.
vi.
vii.
+
Power Inverters
14.1.1iii - PWM-wave output
The output voltage and frequency of a single-phase voltage- source inverter bridge can be control using
one of two forms of pulse-width modulation, termed:
• bipolar
• multi-level, usually called unipolar
Both pwm techniques have been analysed extensively for dc voltage outputs when applied to the two
quadrant and four quadrant dc choppers considered in Chapter 13, sections 13.5 and 13.6. It will be
seen that the same triangular modulation principles can be applied and extended, when producing lowharmonic single-phase ac output voltages and currents. The main voltage output difference between the
two methods is the harmonic content near the carrier frequency and its harmonics. Three-phase pwm is
a naturally extension to the single-phase case, except single-phase pwm offers more degrees of
flexibility than its application to three phase inverters, although three-phase pwm does have the attribute
of triplen harmonic cancellation, due to the use of one (co-phasal) triangular carrier.
− t1
½Vs 1 − e τ
½Vs
 t 
=
tanh  1 
−t
R
R
 2τ 
1+ e τ
½×340V
 10ms 
=
× tanh 
 = 12.95A
10Ω
 2×5ms 
The load current waveform is defined by equations (14.7) and (14.8), specifically
½Vs  ½Vs ∨  −τt
iL (t ) =
−
− I ×e
R  R

−t
½ × 340V  ½ × 340V

=
−
+ 12.95A  × e 5ms
10Ω
 10Ω

∧
I =
+1
M
1
-1
I
= 17 − 29.95 e
−t
5ms
for
V∆
Vref
(a)
0 ≤ t ≤ 10ms
and
½Vs  ½Vs ∧  −τt
+
+ I ×e
R  R

−t
½×340V  ½×340V

=−
+
+ 12.95  × e 5ms
10Ω
 10Ω

iL (t ) = −
II
Vs
T1
T2
ON
VL
iv. The peak switch current is I = 12.95A .
The average switch current is given by
−t
10ms
1
(17 − 29.95e 5ms ) dt
IT =
20ms ∫ 2.83ms
= 2.86 A
v. The peak diode current is I = 12.95A .
T1
T2
ON
T1
T2
ON
T1
T2
ON
T3
T4
ON
−t
5ms
= −17 + 29.95 e
for
0 ≤ t ≤ 10ms
By halving the effective supply voltage, the current swing is also halved.
T1
T2
ON
T3
T4
ON
T3
T4
ON
T3
T4
ON
T3
T4
ON
(b)
-Vs
Figure 14.4. Bipolar pulse width modulation:
(a) carrier and modulation waveforms and (b) resultant load pwm waveform.
Bipolar pulse width modulation
Bipolar modulation is the simplest pwm method and involves comparing a fixed frequency and
magnitude triangular carrier with the ac waveform desired, called the modulation waveform. The
modulation is usually a sinusoid of magnitude (modulation index) M such that 0 ≤ M ≤ 1.
Power Electronics
435
Power Inverters
The waveforms in figure 14.4 shown that the load voltage VL swings between the two voltage levels, +Vs
and -Vs, (hence the term bipolar output voltage), according to
• T1 and T2 are on when vref > v∆ (T3 and T4 are off ) such that VL = +Vs
• T3 and T4 are on when vref < v∆ (T1 and T2 are off ) such that VL = -Vs
Multi-level pulse width modulation
Two multilevel output voltage techniques can be use with single-phase voltage fed ac bridges. In both
case, two triangular carries displaced by 180° give the same output for the same switching frequency.
i. The waveforms in figure 14.5 show that the load voltage VL swings between the two voltage levels,
+Vs and -Vs, with interspaced zero periods (hence the term multilevel, specifically three-level in this
case, 0V and ±Vs ), according to
• T1 is on when vref > v∆ such that Vao = +Vs
• T4 is on when vref < v∆ such that Vao = 0V
•
•
T3 is on when vref < -v∆ such that Vbo = Vs
T2 is on when vref > -v∆ such that Vbo = 0V
The multilevel load output voltage is the difference between the two leg voltage waveforms and can be
defines as follows:
• T1 and T2 are on such that Vao = +Vs, Vbo = 0V, Vab = +Vs
• T2 and T3 are on such that Vao = 0V, Vbo = +Vs, Vab = -Vs
• T1 and T3 are on such that Vao = +Vs, Vbo = +Vs, Vab = 0V
• T2 and T4 are on such that Vao = 0V, Vbo = 0V, Vab = 0V
The two zero output states are interleaved to balance switching losses between all four bridge switches.
Device switching is at the carrier frequency, but the bridge load voltage (hence load current)
experiences twice the leg switching frequency since the two carriers are displaced by 180°.
ii. A second multilevel output voltage approach is shown in figure 14.15, where the triangular carriers
are not only displaced by 180° in time, but are vertically displaced, as for multilevel inverter pwm
generation, which is considered in section 14.4. The upper triangle modulates reference values
greater than zero, while the lower triangle modulates when the reference is less than zero.
+1
436
Spectral comparison between bipolar and multilevel pwm waveforms
The key features of the H-bridge inverter output voltage with bipolar pwm are (fig 14.6a):
• a triangular carrier has only odd Fourier components, so the output spectrum only has carrier
components at odd harmonics of the carrier frequency
• the first carrier components occur at the carrier frequency, fc
• side-band components occur spaced by 2fo from other components, around all multiples of the
carrier frequency fc
From figure 14.6b, the key features of the H-bridge inverter output voltage with multilevel pwm are:
• the output switching frequency is double 2fc each leg switching frequency fc, since the switching
of each leg is time shifted (by 180°), hence the first carrier related components in the output
occur at 2fc and then at multiples of 2fc
• no triangular carrier Fourier components exist in the output voltage since the two carriers are in
anti-phase (180° apart), effectively cancelling one another in spectrum terms
• side-band components occur spaced by 2fo from other components, around each multiple of the
carrier frequency 2fc
M-
fc- 2fo
fc- 4fo
fc
fc+ 2fo
fc+ 4fo
with single-phase bipolar pwm
nfc = 0 for n even
2fc-3fo
fo
2fc- fo
1×fc
2fc+ fo
2fc+3fo
2×fc
2 fo
3×fc
4×fc
(a)
Mwith single-phase multilevel pwm
nfc = 0 for all n
2fc-3fo
M
fo
2fc- fo
1×fc
(suppressed carrier)
2fc+ fo
2fc+3fo
2×fc
2 fo
3×fc
4×fc
(b)
-1
V∆
-V∆
Vref
Vs
(a)
Figure 14.6. Typical phase output frequency spectrum, at a give switch commutation frequency, for:
(a) bipolar pwm and (b) multilevel pwm.
T1 on (T4 off)
14.1.2 Three-phase voltage-source inverter bridge
Vao
T4 on (T1 off)
T3 on (T2 off)
Vs
Vbo
T2 on (T3 off)
The basic dc to three-phase voltage-source inverter (VSI) bridge is shown in figure 14.7. It comprises
six power switches together with six associated reactive energy feedback diodes. Each of the three
inverter legs operates at a relative time displacement (phase) of ⅔π, 120°.
Table 14.1. Quasi-square-wave six conduction states - 180° conduction.
(b)
Three conducting switches
Interval
Vs
Vab
VL
Vab=Vao-Vbo
1
2
3
4
-Vs
Figure 14.5. Multilevel (3 level) pulse width modulation:
(a) carriers and modulation waveforms and (b) resultant load pwm waveforms.
5
6
T1
T2
T3
T2
T3
T4
T3
T4
T5
T4
T5
T6
T5
T6
T1
T6
T1
leg state
T2
voltage vector
101
v5
001
v1
011
v3
010
v2
110
v6
100
v4
Power Electronics
437
Power Inverters
14.1.2i - 180° (π) conduction
Figure 14.8 shows inverter bridge quasi-square output voltage waveforms for a 180° switch conduction
pattern. Each switch conducts for 180°, such that no two series connected (leg or arm) semiconductor
switches across the voltage rail conduct simultaneously. Six patterns exist for one output cycle and the
rate of sequencing these patterns, 6fo, specifies the bridge output frequency, fo. The conducting switches
during the six distinct intervals are shown and can be summarised as in Table 14.1.
T1
T5
T4
438
T3
T2
T6
0V
VRo
VBo
VYo
110
100
101
001
011
010
VRB
VBY
Figure 14.7. Three-phase VSI inverter circuit:
(a) GCT thyristor bridge inverter; (b) star-type load; and (c) delta-type load.
VYR
The three output voltage waveforms can be derived by analysing a balanced resistive star load and
considering each of the six connection patterns, as shown in figure 14.9, using the maxtrix in figure
14.8c. Effectively the resistors representing the three-phase load are sequentially cycled anticlockwise
one at a time, being alternately connected to each supply rail. The output voltage is independent of the
load, as it is for all voltage source inverters.
Alternatively, the generation of the three-phase voltages can be analysed analytically by using the
rotating voltage space vector technique. With this approach, the output voltage state from each of the
three inverter legs (or poles) is encoded as summarised in table 14.1, where a ‘1’ signifies the upper
switch in the leg is on, while a ‘0’ means the lower switch is on in that leg. The resultant binary number
(one bit for each of the three inverter legs), represents the output voltage vector number (when
converted to decimal). The six voltage vectors are shown in figure 14.10 forming sextant boundaries,
where the quasi-square output waveform in figure 14.8b is generated by stepping instantaneously from
one vector position to another in an anticlockwise direction. Note that the rotational stepping sequence
is arranged such that when rotating in either direction, only one leg changes state, that is, one device
turns off and then the complementary switch of that leg turns on, at each step. This minimises the
inverter switching losses. The dwell time of the created rotating vector at each of the six vector
positions, is ⅓π (T) of the cycle period (T). Note that the line-to-line zero voltage states 000 and 111
are not used. These represent the condition when either all the upper switches (T1, T3, T5) are on or all
the lower switches (T2, T4, T5) are switched on. Phase reversal can be obtained by interchanging two
phase outputs, or as is the preferred method, the direction of the rotating vector sequence is reversed.
Reversing is therefore effectively achieved by back-tracking along each output waveform.
VRN
With reference to figure 14.8b, the line-to-load neutral voltage Fourier coefficients are given by

nπ −
2nπ 
cos
 2 + cos

2
3
3 
(14.45)
Vn =
Vs 
n
3π
The line-to-load neutral voltage is therefore
∞
2
sin n ωt
Vn = Vs ∑
r = 1, 2, 3, ..
(14.46)
π n =1, 6 r ±1 n
L− N
L− N
that is
vRN =
2
π
v RB

v BY

v YR
1

=0
 -1

(iR)
VBN
(V)
similarly for vYN and vBN, where ωt is substituted by ωt+⅔π and ωt-⅔π respectively.
(14.47)
-1
1
0





 v RN

 v BN

1
 v YN
0
-1





(iB)
(c)
VYN
(iY)
v6
v4
v5
v1
v3
v2
(b)
Figure 14.8. A three-phase bridge inverter employing 180° switch conduction with a resistive load:
(a) the bridge circuit showing T1, T5, and T6 conducting (leg state v6 :– 110); (b) circuit voltage and
current waveforms with each of six sequential output voltage vectors identified; and
(c) phase voltage to line voltage conversion matrix.
The line-to-line voltage, from equation (14.38) with α = ⅓π, gives Fourier coefficients defined by

nπ 
cos
6 
4 
(14.48)
Vn = Vs 
n
π
The line-to-line voltage is thus
∞
2 3
sin n ωt
Vn =
Vs ∑ cos nπ
r = 1, 2, 3, .
(14.49)
n
6
π
n=1, 6 r ±1
L− L
.
L− L
(the
symbol provides the sign), that is
2 3
(14.50)
V [sin ωt - 15 sin 5ωt - 17 sin 7ωt + 111 sin11ωt + . . .] (V)
π s
and similarly for vBY and vYR. Figure 14.8b shows that vRB is shifted π with respect to vRN, hence to
obtain the three line voltages while maintaining a vRN reference, ωt should be substituted with ωt + π,
ωt- ½π and ωt+π, respectively.
vRB =
Vs [sin ωt + 15 sin 5ωt + 71 sin 7ωt + 111 sin11ωt + . . .]
 v RN − v BN
 
 = v BN − v YN
 
 v YN − v RN
Power Electronics
439
Power Inverters
Since the interphase voltages consist of two square waves displaced by ⅔π, no triplen harmonics (3, 6,
9, . . .) exist. The outputs comprise harmonics given by the series n = 6r ± 1 where r ≥ 0 and is an
integer. The nth harmonic has a magnitude of 1/n relative to the fundamental.
By examination of the interphase output voltages in figure 14.8 it can be established that the mean halfcycle voltage is ⅔Vs and the rms value is √⅔ Vs, namely 0.816 Vs. From equation (14.50) the rms value
of the fundamental is √6 Vs /π, namely 0.78 Vs, that is 3/π times the total rms voltage value.
The three-phase inverter output voltage properties are summarised in Table 14.2.
#
Interval 3
T 3 T 4 T 5 on
leg state 011
v 3 = V s e π j
Interval 4
T 4 T 5 T 6 on
leg state 010
v 2 = V s e π j
Interval # 5
T 1 T 5 T 6 on
leg state 110
v6 = V s e π j
T1 / T4
Interval # 2
T 2 T 3 T 4 on
leg state 001
v1 = V s e 0 j
Interval # 6
T 1 T 2 T 6 on
leg state 100
v 4 = V s e π j
T5 / T2
Y
440
#
Interval # 1
T 1 T 2 T 3 on
leg state 101
v 5 = V s e -π j
T3 / T6
R
T5
T1
T1
VRN = Vs /3
VBN = -2Vs /3
VYN = Vs /3
VRN = 2Vs /3
VBN = -Vs /3
VYN = -Vs /3
T2
T6
B
010
v2
110
v6
100
v4
101
v5
B
B
B
T1
011
v3
T6
Y
R
001
v1
T3
T3
VRN = -Vs /3
VBN = 2Vs /3
VYN = -Vs /3
VRN = Vs /3
VBN = Vs /3
VYN = -2Vs /3
T4
T2
B
Table 14.2. Quasi-squarewave voltage properties for a resistive load
Y
Conduction
period
Y
Y
T5
T5
T3
T2
R
Y
Figure 14.10. Generation and arrangement of the six quasi-square inverter output voltage states.
VRN = -2Vs/3
VBN = Vs/3
VYN = Vs/3
VRN = -Vs /3
VBN = -Vs /3
VYN = 2Vs /3
T6
T4
B
3
180°
Phase
Voltage
V L- N
T4
R
3
2π
Figure 14.9. Determination of the line-to-neutral voltage waveforms for a balanced resistive load
and 180° conduction as illustrated in figure 14.8.
14.1.2ii - 120° (⅔π) conduction
The basic three-phase inverter bridge in figure 14.7 can be controlled with each switch conducting for
120°. As a result, at any instant only two switches (one upper and one non-complementary lower)
conduct and the resultant quasi-square output voltage waveforms are shown in figure 14.11. A 60°
(⅓π), dead time exists between two series switches conducting, thereby providing a safety margin
against simultaneous conduction of the two series devices (for example T1 and T4) across the dc supply
rail. This safety margin is obtained at the expense of a lower semi-conductor device utilisation and rms
output voltage than with 180° device conduction. The device conduction pattern is summarised in Table
14.3. A feature with ⅔π conduction is that the phase currents can be measured from the dc link current.
Fundamental voltage
peak
rms
Total rms
Characteristic
Distortion Factor
THD
µ
thd
3
π2
Vl1
V1
Vrms
(V)
(V)
(V)
π Vs
2
2
V
3 s
π
= 0.450 Vs
= 0.471Vs
= 0.955
2
π
Vs
= 0.637Vs
2 3
6
2
V
3 s
Line
Voltage
V L- L
= 1.10 Vs
= 0.78 Vs
= 0.816Vs
120°
(V)
(V)
(V)
3
6
V
2π s
Phase
Voltage
V L- N
Line
Voltage
V L- L
π
π
Vs
Vs
= 0.551 Vs
3
π
Vs
= 0.955Vs
π Vs
= 0.390 Vs
3
V
2π s
= 0.673 Vs
1
Vs
6
= 0.408Vs
1
2
Vs
= 0.707 Vs
3
π
= 0.955
3
π
= 0.955
3
π
= 0.955
−1
9
= 0.311
π2
9
−1
= 0.311
π2
9
−1
= 0.311
π2
−1
9
= 0.311
Power Electronics
441
Power Inverters
442
Figure 14.8b for 180° conduction and 14.11b for 120° conduction show that the line to neutral voltage of
one conduction pattern is proportional to the line-to-line voltage of the other. That is, from equation
(14.38) with α = ⅓π
∞
2
nπ
vRN ( 2 3 π ) = ½ vRY (π ) = ∑
Vs cos
sin nωt
6
n =1,3,5 π n
(14.51)
3
Vs [sin ωt - 15 sin 5ωt - 17 sin 7ωt + 111 sin11ωt + . . .]
(V)
=
π
and
vRY ( 2 3 π ) = 3 2 vRN (π ) =
∞
∑
n=1,3,5
=
3
π
2 3
nπ
Vs cos
sin nω t
πn
6
Vs [sin ωt + 15 sin 5ωt + 17 sin 7ωt +
1
11
(14.52)
sin11ωt + . . .]
(V)
Also vRY = √3 vRN and the phase relationship between these line and phase voltages, of π, has not
been retained. That is, with respect to figure 14.11b, substitute ωt with ωt + π in equation (14.51) and
ωt + ⅓π in equation (14.52).
The output voltage properties for both 120° and 180° conduction are summarised in the Table 14.2.
Table 14.3. Quasi-squarewave conduction states - 120° conduction.
Two conducting devices
Interval
1
T1
2
T2
T2
3
4
5
6
T3
T3
T4
T4
T5
T5
T6
T6
T1
v RB

v BY

v YR
Independent of the conduction angle (120°, 180° or even 150°), quasi-square 180° conduction occurs
with inductive loads, producing the six hexagon states shown in the upper part of figure 14.10. The
resistive load assumptions made in this section for explanation purposes can be misleading.
1

=0
 -1

14.1.3 Inverter ac output voltage and frequency control techniques
It is a common requirement that the output voltage and/or frequency of an inverter be varied in order to
control the load power or, in the case of an induction motor, to control the shaft speed and torque by
maintaining a constant V / f ratio. The six VSI modulation control techniques to be considered are:
•
•
•
•
•
•
Variable voltage dc link
Single-pulse width modulation
Multi-pulse width modulation
Multi-pulse, selected notching modulation
Sinusoidal pulse width modulation
Triplen injection
ƒ Triplens injected into the modulation waveform
ƒ Voltage space vector modulation
14.1.3i - Variable voltage dc link
The rms voltage of a square-wave can be changed and controlled by varying the dc link source voltage.
A variable dc link voltage can be achieved with a dc chopper as considered in chapter 13 or an ac
phase-controlled thyristor bridge as considered in sections 11.2 and 11.5. A dc link L-C smoothing filter
may be necessary.
14.1.3ii - Single-pulse width modulation
Simple pulse-width control can be employed as considered in section 14.1.1b, where a single-phase
bridge is used to produce a quasi-square-wave output voltage as shown in figure 14.1c.
An alternative method of producing a quasi-square wave of controllable pulse width is to transformeradd the square-wave outputs from two push-pull bridge inverters as shown in figure 14.12a. By phaseshifting the output by α, a quasi-square sum results as shown in figure 14.12b.
 v RN − v BN
 
 = v BN − v YN
 
 v YN − v RN
-1
1
0





 v RN

 v BN

1
 v YN
0
-1





(c)
Figure 14.11. A three-phase bridge inverter employing 120° switch conduction with a resistive star
load: (a) the bridge circuit showing T1 and T2 conducting; (b) circuit voltage and current waveforms;
and (c) phase voltage to line voltage conversion matrix.
The output voltage can be described by
Vo =
∞
∑v
an
sin nωt
(14.53)
(V)
n odd
where
van = 2
π
∫
½π
−½ π
Vs cos nα dα =
4
V cos(½ nα )
nπ s
(V)
(14.54)
The rms output voltage is
Vr = Vs 1- α
π
(V)
(14.55)
Power Electronics
443
and the rms value of the fundamental is
2 2
V1 =
Vs cos½α
π
(V)
Power Inverters
(14.56)
As α increases, the magnitude of the harmonics, particularly the third, becomes significant compared
with the fundamental magnitude. This type of control may be used in high power applications.
444
ii. The rms output voltage is given by equation (14.55), that is
V = V 1- α = 340V 1- 1.34 = 257.5V
rms
π
s
π
iii. The peak values of the first four harmonics are given in the table below.
harmonic
n
van =
4
V cos(½ nα )
nπ s
van2
3
-61.4
3765.0
5
-84.7
7175.3
7
-1.4
1.9
9
46.6
2168.5
.
∑v
2
an
=
114.50
The rms value of the ac of the first four harmonics is 114.5/√2 = 81.0V.
iv. The ac component of the harmonics above the 9th is given by
2
2
Vrms n>9 = Vrms
− Vrms
n≤9
= 257.5V 2 − ( 240V 2 + 81.0V 2 ) = 46.3V
v. The total harmonic voltage distortion is given by
THDv =
V 2 −V 2
rms
a1
Va1
2
× 100 =
 Vrms 

 − 1 × 100
 Va1 
2
=
 257.5V 
 240V  − 1 × 100 = 38.9%


♣
14.1.3iii - Multi-pulse width modulation
Figure 14.12. Voltage control by combining phase-shifted push-pull inverters:
(a) two inverters with two transformers for summing and (b) circuit voltage waveforms for a phase
displacement of α.
An extension of the single-pulse modulation technique is multiple-notching as shown in figure 14.13. The
bridge switches are controlled so as to vary the on to off time of each notch, δ, thereby varying the
output rms voltage which is given by Vrms = δ Vs . Alternatively, the number of notches can be varied.
+Vs
fo
Example 14.4: Single-pulse width modulation
Two single-phase H-bridge inverter outputs are transformer added, as shown in figure 14.12. Each
inverter operates at 50Hz but phase shifted so as to produce 240V rms fundamental output when the rail
voltage of each inverter is 340V dc and the transformers turns ratios are 2:2:1.
Determine
i.
the phase shift between the two single phase inverters
ii.
the rms output voltage
iii.
the frequency and magnitude of the first 4 harmonics of 50Hz and their rms ac
contribution to the rms output
iv.
rms voltage of higher order harmonics (higher frequencies than those in part iii.)
v.
the total harmonic distortion of the output voltage.
Solution
i. The output is a quasi-square waveform of magnitude ±340V dc. The magnitude of the
50Hz fundamental is given by equation (14.54), for n =1:
4
va1 = Vs cos(½α )
π
2 240V =
4
π
× 340V × cos(½α )
from which the phase shift is 76.7°, 1.34 radians.
δ1
-Vs
δ1 < δ2
Carrier frequency
+Vs
fc
fo
δ2
-Vs
Figure 14.13. Inverter control giving variable duty cycle of five notches per half cycle:
(a) low duty cycle, δ1, hence low fundamental magnitude and
(b) higher duty cycle, δ2, for a high fundamental voltage output.
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Power Inverters
The harmonic content at lower output voltages is significantly lower than that obtained with single-pulse
modulation. The increased switching frequency does increase the magnitude of higher order harmonics
and the switching losses. The Fourier coefficients of the output voltage in figure 14.13 are given by
fc
fo


fo
fo
4
Vn =
(14.57)
cos 2π n ( 2 j − 1 + δ ) − cos 2π n ( 2 j − 1 − δ ) 
∑
n π j =1,2,3,.. 
fc
fc

where fo is the fundamental frequency, fc the triangular carrier frequency and 0 ≤ δ ≤ 1 is the duty cycle.
In figure 14.14b two notches per half cycle are introduced; hence any two selected harmonics can be
eliminated. The more notches, the lower is the output fundamental. For example, with two notches, the
third and fifth harmonics are eliminated. From
445
14.1.3iv - Multi-pulse, selected notching modulation
If a multi-level waveform (±Vs, 0) is used with quarter wave symmetry, as shown in figure 14.14a, then
both the harmonics and total rms output voltage can be controlled. With one pulse per quarter wave, the
kth harmonic is eliminated from the output voltage if the centre of the pulse is located such that
sin k λ = 0
(14.58)
that is λ = π
k
Independent of the pulse width δ, the kth harmonic is eliminated and the other Fourier components are
given by
8
π
sin n δ
Vn =
V s sin n
(14.59)
nπ
k
The output voltage total rms is solely dependent on the pulse width δ and is given by
2
Vo rms = V s
δ
(14.60)
π
On the other hand, the bipolar waveform (±Vs) in figure 14.14b has an rms value of Vs, independent of
the harmonics eliminated.
Selected elimination of lower-order harmonics can be achieved by producing an output voltage
waveform as shown in figure 14.14b. The exact switching points are calculated off-line so as to eliminate
the required harmonics. For n switchings per half cycle, n selected harmonics can be eliminated.
4
bn = π
∫
½π
0
f (θ ) sin nθ dθ
for
n = 1, 2, 3, ....
446
(14.61)
b3 = 4 Vs (1 − 2 cos 3α + 2 cos 3β ) = 0
3π
and
b5 = 4 Vs (1 − 2 cos 5α + 2 cos 5β ) = 0
5π
Solving yields α1 = 23.6° and β1 = 33.3°. The total rms output voltage is Vs, independent of the
harmonics eliminated. The magnitude (whence rms) of each harmonic component is
4
Vn =
V s (1 − 4 × sin n λ × sin n δ )
(14.62)
nπ
The maximum fundamental rms component of the output voltage waveform is 0.84 of a square wave,
which is (2√2/π)Vs when δ = ½π which produces a square wave.
Ten switching intervals exist compared with two per cycle for a squarewave, hence switching losses and
control circuit complexity are increased.
In the case of a three-phase inverter bridge, the third harmonic does not exist, hence the fifth and
seventh (b5 and b7) can be eliminated with α1 = 16.3° and β1 = 22.1. The 5th, 7th, 11th, and 13th can be
eliminated with the angles 10.55°, 16.09°, 30.91°, and 32.87° respectively. Because the waveforms
have quarter wave symmetry, only angles for 90° need be stored.
The output rms voltage magnitude can be varied by controlling the dc link voltage or by transformeradding two phase-displaced bridge outputs as demonstrated in figure 14.12. The output voltage Fourier
components in equation (14.62) are modified by equation(14.54) given
4
Vn =
V s (1 − 4 × sin n λ × sin n δ ) cos ½n α
(14.63)
nπ
vL
And the total rms output voltage is reduced from Vs , as given by equation (14.55), that is
Vo rms = Vs 1 - α
δ
Vs
π
½π
λ
λ
π
(V)
(14.64)
Thus the fundamental rms magnitude can be changed by introducing an extra constraint to be satisfied,
along with the harmonic eliminating constraints (as a result of the extra constraint, one fewer harmonic
can now be eliminated for a given number of switchings per quarter cycle).
2π
ωt
(a)
-Vs
δ
(b)
The multi-pulse selected notching modulation technique can be extended to the optimal pulse-width
modulation method, where harmonics may not be eliminated, but minimised according to a specific
criterion. In this method, the quarter wave output is considered to have a number of switching angles.
These angles are selected so as, for example, to eliminate certain harmonics, minimise the rms of the
ripple current, or any other desired performance index. The resultant non-linear equations are solved
using numerical methods off-line. The computed angles are then stored in a ROM look-up table for use.
A set of angles must be computed and stored for each desired level of the voltage fundamental and
output frequency.
The optimal pwm approach is particularly useful for high-power, high-voltage GCT thyristor inverters,
which tend to be limited in switching frequency by device switching losses.
14.1.3v - Sinusoidal pulse-width modulation (pwm)
1
1
1
1
λ
Figure 14.14. Output voltage harmonic reduction for a single-phase bridge using selected notching:
(a) multilevel output voltage and (b) bipolar output voltage.
1 - Natural sampling
(a) Synchronous carrier
The output voltage waveform and method of generation for synchronous carrier, natural sampling
sinusoidal pwm, suitable for the single-phase bridge of figure 14.1, are illustrated in figure 14.15. The
switching points are determined by the intersection of the triangular carrier wave fc and the reference
modulation sine wave, fo. The output frequency is at the sine-wave frequency fo and the output voltage is
proportional to the magnitude of the sine wave. The amplitude M (0 ≤ M ≤ 1) is called the modulation
index. For example, figure 14.15a shows maximum voltage output (M = 1), while in figure 14.15b where
the sine-wave magnitude is halved (M = 0.5), the output voltage is halved.
If the frequency of the modulation sinewave, fo, is an integer multiple of the triangular wave carrierfrequency, fc that is, fc = nfo where n is integer, then the modulation is synchronous, as shown in figure
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Power Inverters
14.15. If n is odd then the positive and negative output half cycles are symmetrical and the output
voltage contains no even harmonics. In a three-phase system if n is a multiple of 3 (and odd), the carrier
is a triplen of the modulating frequency and the spectrum does not contain the carrier or its harmonics.
f c = (6q + 3) f o = nf o
(14.65)
for q = 1, 2, 3.
The Fourier harmonic magnitudes of the line to line voltages are given by
 nπ 
 nπ 
a n = V A cos 
 cos 

 2 
 3 
(14.66)
 nπ   nπ 
bn = V A sin 
 sin 

 2   3 
where Vℓ is proportional to the dc supply voltage Vs and the modulation index M.
Rather than using two offset triangular carriers, as shown in figure 14.15, a triangular carrier without an
offset can be used. Now the output only approximates the ideal. Figure 14.16 shows this pwm
generation technique and voltage bipolar output waveform, when applied to the three-phase VSI
inverter in figure 14.7. Two offset carriers are not applicable to six-switch, three-phase pwm generation
since complementary switch action is required. That is, one switch in the inverter leg must always be on.
It will be noticed that, unlike the output in figure 14.15, no zero voltage output periods exist. This has the
effect that, in the case of GCT thyristor bridges, a large number of commutation cycles is required. When
zero output periods exist, as in figure 14.11, one GCT thyristor is commutated and the complementary
device in that leg is not turned on. The previously commutated device can be turned back on without the
need to commutate the complementary device, as would be required with the pwm technique illustrated
in figure 14.16. Commutation losses are reduced, control circuitry simplified and the likelihood of
simultaneous conduction of two series leg devices is reduced.
The alternating zero voltage loop concept can be used, where in figure 14.16b, rather than T1 being on
continuously during the first half of the output cycle, T2 is turned off leaving T1 on, then when either T1 or
T2 must be turned off, T1 is turned off leaving T2 on.
447
448
upper triangular carrier wave
fc
lower triangular carrier wave
fc
reference modulation sinewave fo
Figure 14.15. Derivation of trigger signals for multi-level naturally sampled pulse-width modulation
waveforms: (a) for a high fundamental output voltage (M = 1) and
(b) for a lower output voltage (M = 0.5), with conducting devices shown.
Sinusoidal pwm requires a carrier of much higher frequency than the modulation frequency. The
generated rectilinear output voltage pulses are modulated such that their duration is proportional to the
instantaneous value of the sinusoidal waveform at the centre of the pulse; that is, the pulse area is
proportional to the corresponding value of the modulating sine wave.
If the carrier frequency is very high, an averaging effect occurs, resulting in a sinusoidal fundamental
output with high-frequency harmonics, but minimal low-frequency harmonics.
Figure 14.16. Naturally sampled pulse-width modulation waveforms suitable for a three-phase
bridge inverter: (a) reference signals; (b) conducting devices and fundamental sine waves; and (c)
one output line-to-line voltage waveform.
(b) Asynchronous carrier
When the carrier is not an integer multiple of the modulation waveform, asynchronous modulation
results. Because the output frequency, fo, is usually variable over a wide range, it is difficult to ensure fc
= nfo. To achieve synchronism, the carrier frequency must vary with frequency fo. Simpler generating
systems result if a fixed carrier frequency is used, resulting in asynchronism between fo and fc at most
Power Electronics
Power Inverters
output frequencies. Left over, incomplete carrier cycles create slowly varying output voltages, called
subharmonics, which may be troublesome with low carrier frequencies, as found in high-power drives.
Natural sampling, asynchronous sinusoidal pwm is usually restricted to analogue or ASIC
implementation. The harmonic consequences of asynchronous-carrier natural-sampling are similar to
asynchronous-carrier regular-sampling in 2 to follow.
2 - Regular sampling
(a) Asynchronous carrier
When a fixed carrier frequency is used, usually no attempt is made to synchronise the modulation
frequency. The output waveforms do not have quarter-wave symmetry which produces subharmonics.
These subharmonics are insignificant if fc >> fo, usually, fc > 20 fo.
The implementation of sinusoidal pwm with microprocessors or digital signal processors is common
because of flexibility and the elimination of analogue circuitry associated problems. The digital pwm
generation process involves scaling, by multiplication, of the per unit sine-wave samples stored in ROM.
• Symmetrical modulation
Figure 14.17a illustrates the process of symmetrical modulation, where sampling is at the carrier
frequency. The quantised sine-wave is stepped and held at each sample point. The triangular carrier is
then compared with the step sine-wave sample. The modulation process is termed symmetrical
modulation because the intersection of adjacent sides of the triangular carrier with the stepped sinewave, about the non-sampled carrier peak, are equidistant about the carrier peak. The pulse width,
independent of the modulation index M, is symmetrical about the triangular carrier peak not associated
with sampling, as illustrated by the upper pulse in figure 14.18. The pulse width is given by
1
t ps =
(14.67)
(1- M sin 2π fo t1 )
2 fc
where t1 is the time of sampling.
449
450
• Asymmetrical modulation
Asymmetrical modulation is produced when the carrier is compared with a stepped sine wave produced
by sampling and holding at twice the carrier frequency, as shown in figure 14.17b. Each side of the
triangular carrier about a sampling point intersects the stepped waveform at different step levels. The
resultant pulse width is asymmetrical about the sampling point, as illustrated by the lower pulse in figure
14.18 for two modulation waveform magnitudes. The pulse width is given by
1
t pa =
(14.68)
(1-½ M ( sin 2π fo t1 + sin 2π fo t2 ) )
2 fc
where t1 and t2 are the times at sampling such that t2 = t1 + 1/2fc.
Figure 14.18 shows that a change in the modulation index M varies the pulse width on each edge,
termed double edge modulation. A triangular carrier produces double edge modulation, while a sawtooth
carrier produces single edge modulation, independent of the sampling technique.
t p 2s
t p1s
M2
M1
t1
Triangular carrier
fc
Reference f o2
Reference f o1
t2
M2
Line of
sym m etry
M1
t p1a
t p2a
Figure 14.17. Regular sampling, asynchronous, sinusoidal pulse-width-modulation:
(a) symmetrical modulation and (b) asymmetrical modulation.
The multiplication process is time-consuming, hence natural sampling is not possible. In order to
minimise the multiplication rate, the sinusoidal sine-wave reference is replaced by a quantised stepped
representation of the sine-wave. Figure 14.17 shows two methods used. Sampling is synchronised to
the carrier frequency and the multiplication process is performed at twice the sampling rate for threephase pwm generation (the third phase can be expressed in terms of two phases, since v1 + v2 + v3 = 0).
Figure 14.18. Regular sampling, asynchronous, sinusoidal pulse-width-modulation, showing double
edge: (upper) asymmetrical modulation and (lower) symmetrical modulation.
Power Electronics
451
Power Inverters
452
3 - Frequency spectra of pwm waveforms
The most common form of sinusoidal modulation for three-phase inverters is regular sampling,
asynchronous, fixed frequency carrier, pwm. If fc > 20fo, low frequency subharmonics can be ignored.
The output spectra consists of the modulation frequency fo with magnitude M. Also present are the
spectra components associated with the triangular carrier, fc. For any sampling, these are fc and the odd
harmonics of fc. (The triangular carrier fc contains only odd harmonics). These decrease in magnitude
with increasing frequency. About the frequency nfc are components of fo spaced at ± 2fo, which generally
decrease in magnitude when further away from nfc. That is, at fc the harmonics present are fc, fc ± 2fo, fc
± 4fo, … while about 2fc, the harmonics present are 2fc ± f0, 2fc ± 3fo,..., but 2fc is not present. The typical
output spectrum is shown in figure 14.19. The relative magnitudes of the sidebands vary with modulation
depth and the carrier related frequencies present, fh, are given by
(
f h = ½ 1 + ( −1)
n+1
) n f ± ( 2k − ½ (1 + ( −1) )) f
n
c
where k = 1, 2, 3,.... (sidebands) and
o
m = 0
m = ¼
m = ½
(14.69)
n = 1, 2, 3,.... (carrier )
m = ¾
Mwith single-phase unipolar pwm
fh = 0 for n odd
2fo
(suppressed carrier and n - odd side bands)
m = 1
2fo
ωt
o
fo
1 fc
2 fc
3 fc
4 fc
Figure 14.19. Location of carrier harmonics and modulation frequency sidebands,
showing all sideband separated by 2fm.
Although the various pwm techniques produce other less predominate spectra components, the main
difference is seen in the magnitude of the carrier harmonics and sidebands. The magnitudes increase as
the pwm type changes from naturally sampling to regular sampling, then from asymmetrical to symmetrical modulation, and finally from double edge to single edge. With a three-phase inverter, the
carrier fc and its harmonics do not appear in the line-to-line voltages since the carrier fc and in particular
its harmonics, are co-phase to the three modulation waveforms.
14.1.3vi - Phase dead-banding
Dead banding is when one phase (leg) is in a fixed on state, and the remaining phases are appropriately
modulated so that the phase currents remain sinusoidal. The dead banding occurs for 60° periods of
each cycle with the phase with the largest magnitude voltage being permanently turned on. Sequentially
each switch is clamped to the appropriate link rail. The leg output is in a high state if it is associated with
the largest positive phase voltage magnitude, while the phase output is zero if it is associated with the
largest negative phase magnitude. Thus the phase outputs are cycled, being alternately clamped high
and low for 60° every 180° as shown in figure 14.20. A consequence of dead banding is reduced
switching losses since each leg is not switched at the carrier frequency for 120° (two 60° periods 180°
apart). A consequence of dead banding is increased ripple current. Dead banding is achieved with
discontinuous modulating reference signals. Dead banding for a continuous 120° per phase leg is also
possible but the switching loss savings are not uniformly distributed amongst the six inverter switches.
The magnitude of the fundamental when using standard PWM can be increased from 0.827pu to
0.955pu without introducing output voltage distortion, by the injection of triplen components, which are
co-phasal in a three-phase system, and therefore do not appear in the line currents. Two basic
approaches can be used to affect this undistorted output voltage magnitude increase.
ƒ Triplen injection into the modulation waveform or
ƒ Voltage space vector modulation
1
π
3
2 π
3
π
4
π
3
5 π
3
2π
Figure 14.20. Modulation reference waveform for phase dead banding.
14.1.3vii - Triplen Injection modulation
1 - Triplens injected into the modulation waveform
An inverter reconstitutes three-phase voltages with a maximum magnitude of 0.827 (3√3/2π) of the fixed
three-phase input ac supply. A motor designed for the fixed mains supply is therefore under-fluxed at
rated frequency and not fully utilised on an inverter. As will be shown, by using third harmonic voltage
injection, the flux level can be increased to 0.955 (3/π) of that produced on the three-phase ac mains
supply.
If overmodulation (M > 1) is not allowed, then the modulation wave M sin ωt is restricted in magnitude to
M = 1, as shown in figure 14.21a.
If VRN = M sinωt ≤ 1pu
and
VYN = M sin(ωt + ⅔π) ≤ 1 pu
then
VRY = √3 M sin(ωt - π)
where 0 ≤ M ≤ 1
In a three-phase pwm generator, the fact that harmonics at 3fo (and odd multiplies of 3fo) vectorally
cancel can be utilised effectively to increase M beyond 1, yet still ensure modulation occurs for every
carrier frequency cycle.
Let
VRN = M′ sinωt+ sin3ωt) ≤ 1 pu
and
VYN = M′ ( sin(ωt +⅔π) +  sin 3(ωt + ⅔π)) ≤ 1 pu
then
VRY = √3 M′ sin(ωt - π)
VRN has a maximum instantaneous value of 1 pu at ωt = ±⅓π, as shown in figure 14.21b. Therefore
3
VRN (ωt = 13 π ) =
M ' =1
2
that is
m'= 2 M
m = 1.155M
m
M
(14.70)
3
Thus the fundamental of the phase voltage is M′ sin ωt = 1.155 M sin ωt. That is, if the modulation
reference sin ωt +  sin 3ωt is used, the fundamental output voltage is 15.5 per cent larger than when
sin ωt is used as a reference. The increased fundamental is shown in figure 14.21b.
453
Power Electronics
Power Inverters
454
rotation, determines the inverter output frequency. The sequence of voltage vectors {v1, v3, v2, v6, v4, v5}
is arranged such that stepping from one state to the next involves only one of the three poles changing
state. Thus the number of inverter devices needing to change states (switch) at each transition, is
minimised.
×1.155
[If the inverter switches are relabelled, upper switches T1, T2, T3 - right to left; and lower switches T4, T5,
T6 - right to left: then the rotating voltage sequence becomes {v1, v2, v3, v4, v5, v6}]
Rather than stepping ⅓π radians per step, from one voltage space vector position to the next, thereby
producing a six-step quasi-square fixed magnitude voltage output, the rotating vector is rotated in
smaller steps based on the position being updated at a constant rate (carrier frequency). Furthermore,
the vector length can be varied, modulated, to a magnitude less than Vs.
2 V sin 1 π − θ
(3
)
o/ p
Va
ta
3
=
=
Tc
v1
Vs
Vb
tb
=
=
Tc
v3
2
Vo / p sin θ
3
Vs
where v1 = v3
#
(14.73)
#
Interval 4
T4 T5 T6 on
leg state 010
πj
v2 = V s e 
Interval 3
T3 T4 T5 on
leg state 011
πj
v3 = V s e 
SECTOR
II
SECTOR
SECTOR
III
#
Interval 5
T1 T5 T6 on
leg state 110
πj
v6 = V s e
I
#
Interval 2
T2 T3 T4 on
leg state 001
0j
v1 = V s e
000
111
SECTOR
SECTOR
IV
VI
SECTOR
Figure 14.21. Modulation reference waveforms: (a) sinusoidal reference, sin ωt; (b) third harmonic
injection reference, sin ωt +  sin 3ωt; and (c) triplen injection reference, sin ωt + (1/√3π){9/8 sin3ωt 80/81 sin9ωt + . ..} where the near triangular waveform b is half the magnitude of the shaded area.
The spatial voltage vector technique injects the triplens according to
r
1 ∞
( −1)


VRN = M ' sin ωt +
(14.71)
 sin  ( 2r + 1) 3ωt 
∑
1
3π r =0 ( 2r + 1) − 3   ( 2r + 1) + 13   

The Fourier triplen series represents half the magnitude of the shaded area in figure 14.21c (the
waveform marked ‘b’), which is formed by the three-phase sinusoidal waveforms. The spatial voltage
vector waveform is defined by
3
sin(ωt )
0 ≤ ωt ≤ 16 π
2
(14.72)
3
1
sin(ωt + 16 π )
6 π ≤ ωt ≤ ½π
2
The use of this reference increases the duration of the zero volt loops, thereby decreasing inverter
output current ripple. The maximum modulation index is 1.155. Third harmonic injection, yielding M =
1.155, is a satisfactory approximation to spatial voltage vector injection.
V
#
#
Interval 6
T1 T2 T6 on
leg state 100
πj
v4 = V s e 
Interval 1
T1 T2 T3 on
leg state 101
- πj
v5 = V s e 
001
v1
011
v3
010
v2
110
v6
100
v4
101
v5
2 - Voltage space vector pwm
When generating three-phase quasi-square output voltages, the inverter switches step progressively to
each of the six switch output possibilities (states). In figure 14.10, when producing the quasi-square
output, each of these six states is represented by an output voltage space vector. Each vector has a ⅓π
displacement from its two adjacent states, and each has a length Vs which is the pole output voltage
relative to the inverter 0V rail. Effectively, the quasi-square three-phase output is generated by a
rotating vector of length Vs, jumping successively from one output state to the next in the sequence, and
in so doing creating six voltage output sectors. The speed of rotation, in particular the time for one
111
v7
000
v0
Figure 14.22. Instantaneous output voltage states for the three legs of an inverter.
455
Power Electronics
Power Inverters
V 3 =V s e
To incorporate a variable rotating vector length (modulation depth), it is necessary to vary the average
voltage in each carrier period. Hence pulse width modulation is used in the period between each finite
step of the rotating vector. Pulse width modulation requires the introduction of zero voltage output
states, namely all the top switches on (state 111, v7) or all the lower switches on (state 000, v0). These
two extra states are shown in figure 14.22, at the centre of the hexagon. Now the pole-to-pole output
voltage can be zero, which allows duty cycle variation to achieve variable average output voltage for
each phase, within each carrier period, proportional to the magnitude of the position vector.
To facilitate vector positions (angles) that do not lie on one of the six quasi-square output vectors, an
intermediate vector Vo/p e jθ is resolved into the vector sum of the two quasi-square vectors adjacent to
the rotating vector. This process is shown in figure 14.23 for a voltage vector Vo/p that lies in sector I,
between output states v1 (001) and v3 (011). The voltage vector has been resolved into the two
components Va and Vb as shown.
The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in each case. Therefore
the portion of Tc associated with va and vb is scaled proportionally to v1 and v3, giving ta and tb.
j?π
011
j?π
Tc
011
SECTOR I
SECTOR I
Tc
ωt
∧
Vo / p
tb
Vb = 2 VO / P sin θ
3
V s cos30°
VoV/ pO/P
e jθ
½v 3 = ½V s
θ
000
111
ta
Va = 2 VO / P sin ( 13 π − θ )
3
v 1 =V s e
Tc
30°
000
111
½v 1 = ½V s
j0
v 1 =V s e
j0
001
001
(a)
(b)
V 3 =V s e
The two sine terms in equation (14.73) generate two sine waves displaced by 120°, identical to that
generated with standard carrier based sinusoidal pwm.
The sum of ta and tb cannot be greater than the carrier period Tc, thus
ta + tb ≤ Tc
(14.74)
ta + tb + to = Tc
where the slack variable to has been included to form an equality. The equality dictates that vector v1 is
used for a period ta, v3 is used for a period tb, and during period to, the null vector, v0 or v7, at the centre
of the hexagon is used, which do not affect the average voltage during the carrier interval Tc.
A further constraint is imposed in the time domain. The rotating voltage vector is a fixed length for all
rotating angles, for a given inverter output voltage. Its length is restricted in both time and space.
Obviously the resolved component lengths cannot exceed the pole vector length, Vs. Additionally, the
two vector magnitudes are each a portion of the carrier period, where ta and tb could be both equal to Tc,
that is, they both have a maximum length Vs. The anomaly is that voltages va and vb are added
vectorially but their scalar durations (times ta and tb) are added linearly. The longest time ta + tb possible
is when to is zero, as shown in figures 14.23a and 14.22a, by the hexagon boundary. The shortest
vector to the boundary is where both resolving vectors have a length ½Vs, as shown in figure 14.23b.
For such a condition, ta = tb = ½Tc, that is ta + tb = Tc. Thus for a constant inverter output voltage, when
the rotating voltage vector has a constant length, Vlo /p , the locus of allowable rotating reference voltage
vectors must be within the circle scribed by the maximum length vector shown in figure 14.23b. As
shown, this vector has a length v1 cos30°, specifically 0.866Vs. Thus the full quasi-square vectors v1, v2,
etc., which have a magnitude of 1×Vs, cannot be used for generating a sinusoidal output voltage. The
excess length of each quasi-square voltage (which represents time) is accounted for by using zero state
voltage vectors for a period corresponding to that extra length (1- cos 30° at maximum output voltage).
Having calculated the necessary periods for the inverter poles (ta, tb, and to), the carrier period switching
pattern can be assigned in two ways.
• Minimised current ripple
• Minimised switching losses, using dead banding
456
V 3 =V s e
j?π
tb + ta < T c
reduced to
Tc
011
60°-α
tb + ta > T c
no to
V o /p > Vo /p
TTcc
Vlo / p
α
000
111
Tc
v 1 =V s e
tb + ta < T c
reduced to
j0
001
(c)
Figure 14.23. First sector of inverter operational area involving pole outputs 001 and 011:
(a) general rotating voltage vector; (b) maximum allowable voltage vector length for undistorted
output voltages; and (c) over modulation.
v0
v1
v3
v7
v7
v3
v1
v0
0 00
0 01
011
111
1 11
01 1
001
0 00
¼ to
½ ta
½ tb
¼ to ¼ to
½ tb
¼ ta
¼ to
ΦR
ΦY
ΦB
Tc
Each approach is shown in figure 14.24, using single edged modulation. The waveforms are based on
the equivalent of symmetrical modulation where the pulses are symmetrical about the carrier trough. By
minimising the current ripple, seven switching states are used per carrier cycle, while for loss
minimisation (dead banding) only five switching states occur, but at the expense of increased ripple
current in the output current. When dead banding, the zero voltage state v0 is used in even numbered
sextants and v7 is used in odd numbered sextants.
Sideband and harmonic component magnitudes can be decreased if double-edged modulation
placement of the states is used, which requires recalculation of ta, tb, and to at the carrier crest, as well
as at the trough.
Over-modulation is when the magnitude of the demanded rotating vector is greater than Vlo /p such that
the zero voltage time reduces to zero, to = 0, during a portion of the time of one rotation of the output
vector. Initially this occurs at 30° ( 16 π ( 2 N sector − 1) ) when the output vector length reaches Vlo /p , as shown in
figure 14.23b. As the demand voltage magnitude increases further, the region around the 30° vector
position where to ceases to occur, increases as shown in figure 14.23c. When the output rotational
vector magnitude increases to Vs, the maximum possible, angle α reduces to zero, and to ceases to
occur at any rotational angle. The values of ta, tb, and to (if greater than zero), are calculated as usual,
but pulse times are assigned pro rata to fit within the carrier period Tc.
(a )
v1
v3
v7
v7
v3
v1
001
01 1
111
111
011
001
½ ta
½ tb
¼ to
¼ to
½ tb
¼ ta
ΦR
ΦY
ΦB
Tc
(b )
Figure 14.24. Assignment of pole periods ta and tb based on:
(a) minimum current ripple and (b) minimum switching transitions per carrier cycle, Tc.
Power Electronics
457
14.2
Power Inverters
dc-to-ac controlled current-source inverters
In the current source inverter, CSI, the dc supply is of high reactance, being inductive so as to maintain
the required inverter output bidirectional current independent of the inverter load.
458
• Phase II
When both capacitors are discharged, the load current transfers from D1 to D2 and from D3 to D4, which
connects the capacitors in parallel with the load via diodes D1 to D2. The plates X and Y now charge
negative, ready for the next commutation cycle, as shown in figure 14.26b. Thyristors T1 and T2 are
now forward biased and must have attained forward blocking ability before the start of phase 2.
14.2.1 Single-phase current source inverter
A single-phase, controlled current-sourced bridge is shown in figure 14.25a and its near square-wave
output current is shown in figure 14.25b. No freewheel diodes are required and the thyristors required
forced commutation and have to withstand reverse voltages. An inverter current path must be
maintained at all times for the source controlled current.
Consider thyristors T1 and T2 on and conducting the constant load current. The capacitors are charged
with plates X and Y positive as a result of the previous commutation cycle.
• Phase I
Thyristors T1 and T2 are commutated by triggering thyristors T3 and T4. The capacitors impress
negative voltages across the respective thyristors to be commutated off, as shown in figure 14.26a.
The load current is displaced from T1 and T2 via the path T3-C1-D1, the load and D2-C2-T4. The two
capacitors discharge in series with the load, each capacitor reverse biasing the thyristor to be
commutated, T1 and T2 as well as diodes D3 to D4. The capacitors discharge linearly (due to the
constant current source).
The on-going thyristor automatically commutates the outgoing thyristor. This repeated commutation
sequencing is a processed termed auto-sequential thyristor commutation. The load voltage is load
dependent and usually has controlled voltage spikes during commutation.
Since the GTO and GCT both can be commutated from the gate, the two commutation capacitors C1 and
C2 are not necessary. Commutation overlap is still essential. Also, if the thyristors have reverse
blocking capability, the four diodes D1 to D4 are not necessary. IGBTs require series blocking diodes,
which increases on-state losses. In practice, the current source inverter is only used in very high-power
applications (>1MVA), and the ratings of the self-commutating thyristor devices can be greatly extended
if the simple external capacitive commutation circuits shown in figure 14.25 are used to reduce thyristor
turn-off stresses.
14.2.2 Three-phase current source inverter
A three-phase controlled current-source inverter is shown in figure 14.27a. Only two thyristors can be on
at any instant, that is, the 120° thyristor conduction principle shown in figure 14.11 is used. A quasisquare line current results, as illustrated in figure 14.27b. There is a 60° phase displacement between
commutation of an upper device followed by commutation of a lower device. An upper device (T1, T3, T5)
is turned on to commutate another upper device, and a lower device (T2, T4, T6) commutates another
lower device. The three upper capacitors are all involved with each upper device commutation, whilst
the same constraint applies to the lower capacitors. Thyristor commutation occurs in two distinct phases.
Figure 14.25. Single-phase controlled-current sourced bridge inverter:
(a) bridge circuit with a current source input and (b) load current waveform.
-
+
+
-
-
+
-
+
+
+
(a)
-
+
+
-
(b)
Figure 14.26. Controlled-current sourced bridge inverter showing commutation of T1 and T2 by T3 and
T4: (a) capacitors C1 and C2 discharging and T1, T2, D3, and D4 reversed biased and
(b) C1, C2, and the load in parallel with C1 and C2 charging.
Figure 14.27. Three-phase controlled-current sourced bridge inverter:
(a) bridge circuit with a current source input and (b) load current waveform for one phase
showing 120° conduction.
• Phase I
In figure 14.28a the capacitors C13, C35, C51 are charged with the shown polarities as a result of the
earlier commutation of T5. T1 is commutated by turning on T3. During commutation, the capacitor
Power Electronics
459
Power Inverters
between the two commutating switches is in parallel with the two remaining capacitors which are
effectively connected in series. Capacitor C13 provides displacement current whilst in parallel, C35
and C151 in series also provide thyristor T1 displacement current, thereby reverse biasing T1.
• Phase II
When the capacitors have discharged, T1 becomes forward biased, as shown in figure 14.28b, and
must have regained forward blocking capability before the applied positive dv/dt. The capacitor
voltages reverse as shown in figure 14.28b and when fully charged, diode D1 ceases to conduct.
Independent of this commutation, lower thyristor T2 is commutated by turning on T4, 60° later.
As with the single-phase current sourced inverter, assisted capacitor commutation can greatly improve
the capabilities of self-commutating thyristors, such as the GTO thyristor and GCT. The output capacitors
stiffen the output ac voltage.
A typical application for a three-phase current-sourced inverter would be to feed and control a threephase induction motor. Varying load requirements are met by changing the source current level over a
number of cycles by varying the link inductor input voltage.
An important advantage of the controlled current source concept, as opposed to the constant voltage
link, is good fault tolerance and protection. An output short circuit or simultaneous conduction in an
inverter leg is controlled by the current source. Its time constant is usually longer than that of the input
converter, hence converter shut-down can be initiated before the link current can rise to a catastrophic
level.
-
Io
+
+
-
-
+
+
-
C35
D1
+
+
-
C51
•
•
•
•
•
Commutation capability is load current dependent and a minimum load is required. This limits
the operating frequency and precludes use in UPS systems. The limited operating
frequency can result in torque pulsations.
The inverter can recover from an output short circuit hence the system is rugged and reliable –
fault tolerant.
The converter-inverter configuration has inherent four quadrant capability without extra power
components. Power inversion is achieved by reversing the converter average voltage output
with a delay angle of α > ½π, as in the three-phase fully controlled converter shown in figure
11.18 (or 14.5.3). In the event of a power supply failure, mechanical braking is necessary.
Dynamic braking is possible with voltage source systems.
Current source inverter systems have sluggish performance and stability problems on light loads
and at high frequency. On the other hand, voltage source systems have minimal stability
problems and can operate open loop.
Each machine must have its own controlled rectifier and inverter. The dc link of the voltage
source scheme can be used by many inverters or many machines can utilise one inverter. A
dc link offers limited ride-through.
Current feed inverters tend to be larger in size and weight, because of the link inductor and
filtering requirements.
T1
T5
T3
T4
T2
T6
Tupper
Io
-
+
D1
-
+
CR
C35
C13
C13
•
460
CY
D3
-
+
C51
CB
Io
Tlower
Io
Io
Io
(a)
IR
Io
(a)
+Io
ωt
Io
(b)
Figure 14.28. Controlled-current sourced bridge three-phase inverter showing commutation of T1
and T3: (a) capacitors C13 discharging in parallel with C35 and C51 discharging in series, with T1 and D3
reversed biased (b) C13, C35, and C51 charging in series with the load , with T1 forward biased.
PWM techniques are applicable to current source inverters in order to reduce current harmonics,
thereby reducing load losses and pulsating motor shaft torques. Since current source inverters are most
attractive in very high-power applications, inverter switching is minimised by using optimal pwm. The
central 60° portion about the maximums of each phase cannot be modulated, since link current must
flow and during such periods both the other phases require the opposite current direction. Attempts to
over come such pwm restrictions include using a current sourced inverter with additional parallel current
displacement paths as shown in figure 14.29. The auxiliary thyristors, Tupper and Tlower, and capacitors,
CR, CY, and CB, provide alternative current paths (extra control states) and temporary energy storage.
The auxiliary thyristor can be commutated by the extra capacitors.
Characteristics and features of current source inverters
• The inverter is simple and can utilise rectifier grade thyristors. The switching devices must have
reverse blocking capability and experience high voltages (both forward and reverse) during
commutation.
-Io
(b)
Figure 14.29. Three-phase controlled-current sourced bridge inverter with alternative commutation
current paths: (a) bridge circuit with a current source input and two extra thyristors and
(b) load current waveform for one phase showing 180° conduction involving pwm switching.
14.3
Resonant dc-ac inverters
The voltage source inverters considered in 14.1 involve inductive loads and the use of switches that are
hard switched. That is, the switches experience simultaneous maximum voltage and current during
turn-on and turn-off with an inductive load. The current source inverters considered in 14.2 required
capacitive circuits to commutate the bridge switches. When self-commutatable devices are used in
current source inverters, hard switching occurs. In resonant inverters, the load enables commutation of
the bridge switches with near zero voltage or current switch conditions, resulting in low switching losses.
A characteristic of L-C-R resonant circuits is that at regular, definable instants
ƒ for a step load voltage, the series L-C-R load current sinusoidally reverses or
ƒ for a step load current, the parallel L-C-R load voltage sinusoidally reverses.
If the load can be resonated, as considered in chapter 6.2.3, then switching stresses can be significantly
reduced for a given power through put, provided switching is synchronised to the V or I zero crossing.
Power Electronics
Power Inverters
Three types of resonant converters utilise zero voltage or zero current switching.
ƒ load-resonant converters
ƒ resonant-switch dc-to-dc converters
ƒ resonant dc link and forced commutated converters
The single-phase load-resonant converter, which is extensively used in induction heating applications, is
presented and analysed in this chapter. Such resonant load converters use an L-C load which
oscillates, thereby providing load zero current or voltage intervals at which the converter switches can
be commutated with minimal electrical stress. Resonant switch dc-to-dc converters are presented in
chapter 15.9.
ξ is the damping factor. The capacitor voltage is important because it specifies the energy retained in the
L-C-R circuit at the end of each half cycle.
ω
i
vc (ωt ) = Vs − (Vs − vo ) o e −αt cos (ωt − φ ) + o e −α t sin ωt
(14.76)
ω
ωC
461
Two basic resonant-load single-phase inverters are used, depending on the L-C load arrangement:
ƒ current source inverter with a parallel L-C resonant (tank) load circuit:
switch turn-off at zero load voltage instants and turn-on with zero voltage
switch overlap is essential (a continuous source current path is required)
ƒ voltage source inverter with a series connected L-C resonant load:
switch turn-off at zero load current instants and turn-on with zero current
switch under lap is essential (to avoid dc voltage source short circuiting)
Each load circuit type can be fed from a single leg (or arm) circuit or H-bridge circuit depending on the
load Q factor. This classification is divided according to
ƒ symmetrical full bridge for low Q load circuits (class D)
ƒ single bridge leg circuit for a high Q load circuit (class E)
High Q circuits can also use a full bridge inverter configuration, if desired, for higher through-put power.
In induction heating applications, the resistive part of the resonant load, called the work-piece, is the
active load to be heated - melted, where the heating load is usually transformer coupled. Energy
transfer control complication is usually associated with the fact that the resistance of the load work-piece
changes as it heats up and melts, since resistivity is temperature dependant. However, control is
essentially independent of the voltage and current levels and is related to the resonant frequency which
is L and C dependant. Inverter bridge operation is near the load resonant frequency so that the output
waveform is essentially sinusoidal. By ensuring operation is below the resonant frequency, such that
the load is capacitive, the resultant leading current can be used to self commutate thyristor converters
which may be used in high power series resonant circuits. This same capacitive load commutation effect
is obtained for parallel resonant circuits with thyristor current source inverters operating just above
resonance. The output power is controlled by controlling the converter output frequency.
At the series circuit resonance frequency ωo, the lowest possible circuit impedance results, Z = R, hence
it can be termed, low-impedance resonance. The series circuit quality factor or figure of merit, Qs, is
defined by
reactive power 2π × maximum stored energy
=
Qs =
average power
energy dissipated per cycle
(14.77)
Z
2π ½ Li 2 ωo L 1
=
=
=
= o
2
½ Ri / f o
2ξ
R
R
Where the characteristic impedance is
L
Zo =
(Ω)
C
−j
ωC
jωL
i
Vs
Is
high
Q
high
Q
low
Q
low
Q
Is
vcapacitor
iseries
iinductor
vparallel
ωt
ideal commutation
instants
∞
|Z(ω)|
R
|Z(ω)|
R
Qs
decreasing
→
BWs
√2
1
∞
+90°
0
Z
ωo
ωu
1
Qp
1
√2
+90°
decreasing
→
BWp
0
Z
inductive
ωℓ
capacitive
ωt
ideal commutation
instants
θZ(ω)
The series L-C-R circuit current for a step input voltage Vs, with initial capacitor voltage vo and series
inductor current io is given by
V −v
ω
i (ωt ) = s o × e −α t × sin ωt + io × e −α t × o × cos (ωt + φ )
(14.75)
ω
ωL
where
1
R
1
R
tan φ = α
ω 2 = ωo2 (1 − ξ 2 ) = ωo2 − α 2
ωo =
α=
=ξ =
and
ω
2L
2Qs
2ωo L
LC
v
R
−j
ωC
Vs
14.3.1i - Series resonant L-C-R circuit
jωL
Is
R
14.3.1 L-C resonant circuits
L-C-R resonant circuits, whether parallel or series connected are characterised by the load impedance
being capacitive at low frequency and inductive at high frequency for the series circuit, and visa versa
for the parallel case. The transition frequency between being capacitive and inductive is the resonant
frequency, ωo, at which frequency the L-C-R load circuit appears purely resistive and maximum power is
transferred to the load, R. L-C-R circuits are classified according to circuit quality factor Q, resonant
frequency, ωo, and bandwidth, BW, for both parallel and series circuits. The characteristics for the
parallel and series resonant circuits are related since every practical series L-C-R circuit has a parallel
equivalent, and vice versa. The parallel circuit can be series R-L in parallel with the capacitor C.
As shown in figure 14.30 each resonant half cycle is characterised by
ƒ
the series resonant circuit current is zero at maximum capacitor stored energy
ƒ
the parallel resonant circuit voltage is zero at maximum inductor stored energy
The capacitor in a series resonant circuit must have an external path through which to release its stored
energy. The parallel resonant circuit can release its stored inductive energy within its parallel circuit,
without an external circuit. The stored energy can internally resonate, transferring energy back and forth
between the L and C, gradually dissipating in the circuit R, as heat.
462
θZ(ω)
ω=2πf
0
Z
inductive
ωℓ
ωu
ωo
ω=2πf
Z
capacitive
-90°
-90°
(a)
(b)
Figure 14.30. Resonant circuits, step response, and frequency characteristics:
(a) series L-C-R circuit and (b) parallel L-C-R circuit.
Power Electronics
463
Power Inverters
The series circuit half-power bandwidth BWs is given by
ω 2π f o
BWs = o =
Qs
Qs
and upper and lower half-power frequencies are related by ω = ωA ωu .
ωAu = ωo ± α
(14.78)
(14.79)
R
4π L
Figure 14.30a shows the time-domain step-response of the series L-C-R circuit for a high Q load and a
low Q case. In the low Q case, to maintain and transfer sufficient energy to the load R, the circuit
requires re-enforcement every half sine cycle, while with a high circuit Q, re-enforcement is only
necessary once per sinusoidal cycle. Thus for a high circuit Q, full bridge excitation is not necessary,
yielding a simpler power circuit as shown in figure 14.31a and b.
The energy transferred to the load resistance R, per half cycle 1/2fr, is
f Au = f o ±
W½ =
π
∫ i (ω t ) R d ω t
2
(14.80)
0
The active power transferred to the load depends on the repetition rate of the excitation, fr.
P = W½ × f r
(W)
(14.81)
characteristic
series
s
Resonant angular frequency
rad/s
Damping factor
pu
Damping constant
/s
Characteristic impedance
ξs = ½
ω = ωo 1 − ξ = ωo − α
Quality factor
Bandwidth
2
Qs =
1
Qp
2
R
= ½ ωo C R
ωo L
αs =
π
=
pu
=
ωo CR
=
L
ωL
C = o
R
R
2π (½LI p2 )
(½RI ) τ
ω
BW s = o
Qs
2
p
1
T3 D3
T1 D1
Vs
2CR
T1 D1
C
R
1
R
=
=
= ωo CR
L
2ξ p Z o
2π (½CV p2 )
R
=
ωo L
 V p2 
 ½
 τ
 R 
ω
BW p = o
Qp
C R
R
VSI
T2 D2
(b)
CSI
I constant
I constant
L large
L large
C
Vs
L
T4D4
(a)
C
=
L
T4 D4
ω = ωo 1 − ξ p
Qp =
(14.87)
ωo L
1
=½
R
ωo C R
2
Z
1
= o =
2ξs
R
1
1
L
1
= ωo L =
C
ωo C
ω = ωo 1 − ξs
Qs =
(14.86)
LC
ξp = ½
2
rad/s
2
The active power to the load depends on the repetition rate of the excitation, fr.
P = W½ × f r
(W)
αp =
Zo =
The inductor current is important since it specifies the tank circuit stored energy at the end of each half
cycle.
ω
v
(14.83)
iL (ωt ) = I s − ( I s − io ) × o × e −αt × cos (ωt − φ ) + o × e −α t × sin ωt
ω
ωL
where
1
α=
2CR
The parallel circuit Q for a parallel resonant circuit is
R
R
1
=
=
(14.84)
Qp = ωo RC =
ωo L Z o Qs
where Zo and ωo are defined as in equations (14.75) and (14.77), except L, C, and R refer to the parallel
circuit values.
The half-power bandwidth BWp is given by
ω
2π f o
BWp = o =
(14.85)
Qp
Qp
0
R
2L
Ω
rad/s
1
τ
(14.82)
W½ = ∫ v (ω t ) / R d ω t
τ = LC
Damped resonant angular frequency
2
parallel
ωo = 2π f o =
I s − io −α t
ω
× e × sin ωt + vco × e −αt × ωo × cos (ωt + φ )
ωC
and upper and lower half power frequencies are related by ω = ωAωu .
At the parallel circuit resonance frequency ωo, the highest possible circuit impedance results, Z = R,
hence it can be termed, high-impedance resonance.
The energy transferred to the load resistance R, per half cycle 1/2fr, is
Table 14.4 Characteristics and parameters of parallel and series resonant circuits
Resonant period/time constant
v (ωt ) = vc (ωt ) =
464
L
R
T1 D1
C
Vs
T3 D3
L
14.3.1ii - Parallel resonant L-C-R circuit
The load for the parallel case is a parallel L-C circuit, where the active load is represented by series
resistance in the inductive path. For analysis, the series L-R circuit is converted into its parallel R-L
equivalent circuit, thus forming the equivalent parallel L-C-R circuit shown in figure 14.30b. A parallel
resonant circuit is used in conjunction with a current source inverter, thus the parallel circuit is excited
with a step input current. The voltage across a parallel L-C-R circuit for a step input current Is, with initial
capacitor voltage vo and initial inductor current io is given by
T1 D1
T3 D3
(c)
T4 D4
R
T2 D2
(d)
Figure 14.31. Resonant converter circuits: (a) series L-C-R with a high Q; (b) low Q series L-C-R;
(c) parallel L-C-R and high Q; and (d) low Q parallel L-C-R circuit.
Power Electronics
465
Power Inverters
14.3.2 Series-resonant voltage-source inverters
Series resonant circuits use a voltage source inverter (class D series) as considered in 14.1.1 and
shown in figure 14.31a and b. If the load Q is high, then the resonance of energy from the energy
source, Vs, need only be re-enforced every second half-cycle, thereby simplifying converter and control
requirements. A high Q circuit is characterised by successive half-cycle capacitor voltage peak
magnitudes being of similar magnitude, that is the decay rate is
π
vc
= e 2 Q ≈ 1 for Q 1
(14.88)
vc
n
n +1
Thus there is sufficient energy stored in C to be transferred to the load R, without need to involve the
supply Vs. The circuit in figure 14.31a is simpler and control is easier.
Also, for any Q, each converter can be used with or without the shown freewheel diodes. Without
freewheel diodes, the switches have to block high reverse voltages due to the energy stored by the
capacitor. MOSFET and IGBTs require series diodes to achieve the reverse voltage blocking
requirements. In high power resonant applications, the reverse blocking abilities of the GTO and GCT
make them ideal converter switches. Better load resonant control is obtained if freewheel diodes are not
used.
D4
T4
D1
T1
D4
symmetrical H-bridge conducting devices
T1 T2
D3 D4
T3 T4
D1 D2
T1 T2
D3 D4
φ
lagging
IT1
H-bridge output
voltage
IT1
t
0
IT4
Zero for half
bridge
switch T1/T2
hard turn-off
IT1
0
Vref
Vref
IT4
Operation and switch timing are as follows:
Diode D4 is conducting when switch T1 is turned on, which provides a step input voltage Vs to the
series L-C-R load circuit, and the current continues to oscillate. The capacitor charges to a maximum
voltage and the current reverses through D1, feeding energy back into the supply. T1 is then turned off
with zero current.
The switch T4 is turned on, commutating D1, and the current oscillates through the zero volt loop
created through T4 and the load. The oscillation current reverses through diode D4, when T4 is
turned off with zero current.
T1 is turned on and the process continues.
Analysis – single inverter leg
For a square wave input voltage, 0 to Vs, of frequency ω ≈ ωo , the input voltage fundament of magnitude
2 Vs / π produces the dominant load current component, since higher frequency components are
attenuated by second order L-C filtering action. That is, the resonant circuit excitation voltage is
V i = 2Vs π .
t
Vref
Operation and switch timing are as follows:
Switch T1 is turned on while its anti-parallel diode is conducting and the current in the diode reaches
zero and the current transfers to, and begins to oscillate through the switch T1. The capacitor charges
to a maximum voltage and before the current reverses, the switch T1 is hard turned off. The current is
diverted through diode D4. T4 is turned on which allows the oscillation to reverse. Before the current in
T4 reaches zero, it is turned off and current is diverted to diode D1, which returns energy to the
supply. The resonant cycle is repeated when T1 is turned on before the current in diode D1 reaches
zero and the process continues.
Without the freewheel diodes the half oscillation cycles are controlled completely by the switches. On
the other hand, with freewheel diodes, the timing of switch turn-on and turn-off is determined by the load
current zeros, if maximum energy transfer to the load is to be gained.
φ
lagging
IT1
1 - Lagging operation (advancing the switch turn-off angle, f > fo)
If the converter is operated at a frequency above resonance (effected by commutating the switches
before the end of an oscillation cycle), the inductor reactance dominates and the load appears inductive.
The load current lags the voltage as shown in figure 14.32. This figure shows the conducting devices
and that a switch is turned on when its parallel connected diode is conducting. Turn-on therefore occurs
at a low voltage (hence low switch turn-on loss and no need for fast recovery diodes), while turn-off is as
with a hard switched inductive load (associated with switch high turn-off loss and turn-off Miller
capacitance effects).
2 - Leading operation (delaying the switch turn-on angle, f < fo)
By operating the converter at a frequency below resonance (effectively by delaying switch turn-on until
after the end of an oscillation cycle), the capacitor reactance dominates and the load appears capacitive.
The load current leads the voltage as shown in figure 14.33. This figure shows the conducting devices
and that a switch is turned off when its parallel diode is conducting. Turn-off therefore occurs at a low
current, while turn-on is as with a hard switched inductive load. Fast recovery diodes are therefore
essential. Switch output capacitance charging and discharge (½CV2) and the Miller effect at turn-on
(requiring increased gate power) are factors to be accounted for.
asymmetrical bridge conducting devices
T1
466
switch T4/T3
hard turn-off
t
0
Figure 14.32. Series L-C-R high Q resonance using the converter circuit in figure 14.31a and b,
with a lagging power factor φ.
14.3.2i – Series-resonant voltage-source inverter – single inverter leg
Operation of the series load single leg circuit in figure 14.31a depends on the timing of the switches.
The series circuit steady-state current at resonance for the single-leg half-bridge can be approximated
by assuming ωo≈ω, such that in equation (14.75) io = 0:
V
1
× s × e −αt × sin ωt
(14.89)
0 ≤ ωt ≤ π
i (ωt ) =
−απ
ωL
ω
1− e
which is valid for the + Vs loop (through T1) and zero voltage loop (through T4) modes of cycle operation
at resonance, provided the time reference is moved to the beginning of each half-cycle.
In steady-state the successive capacitor voltage absolute maxima are
∧
∨
1
e −απ / ω
Vc = Vs
and Vc = − Vs
1 − e −απ / ω
1 − e −απ / ω
The peak-to-peak capacitor voltage is therefore
1 + e −απ / ω
2ω
× Vs = Vs × coth (απ / 2ω ) ≈
× Vs
Vc =
απ
1 − e −απ / ω
p− p
(14.90)
(14.91)
Power Electronics
467
Power Inverters
The magnitude of the resistor voltage is therefore
R
1
= Vi
vR (ω ) = Vi
2
2
1 
ω
L


1 
1+ 
−
R2 +  ω L −


ωC 
 R ω RC 

1
= Vi
2
 ω ωo 
− 
1 + Q2 
 ωo ω 
asymmetrical bridge conducting devices
T1
D1
T4
D4
T1
D1
T1 T2
D1 D2
symmetrical H-bridge conducting devices
T1 T2
D1 D2
T3 T4
D3 D4
φ
leading
IT1
IT1
H-bridge output
voltage
t
0
Zero for half
bridge
IT4
φ
leading
IT1
switch T1/T2
hard turn-on
IT1
t
0
Vref
Vref
Vref
IT4
switch T4/T3
hard turn-on
468
t
0
Figure 14.33. Series L-C-R high Q resonance using the converter circuit in figure 14.31a and b,
with a leading power factor φ.
(14.95)
14.3.2ii – Series-resonant voltage-source inverter – H-bridge voltage-source inverter
When the load Q is not high, the capacitor voltage between successive absolute peaks decays
significantly, leaving insufficient energy to maintain high efficiency energy transfer to the load R. In such
cases the resonant circuit is re-enforced with energy from the dc source Vs every half-resonant cycle, by
using a full H-bridge as shown in figure 14.31b.
Operation is characterised by turning on switches T1 and T2 to provide energy from the source during
one half of the cycle, then having turned T1 and T2 off, T3 and T4 are turned on for the second resonant
half cycle. Energy is again drawn from the supply Vs, and when the current reaches zero, T3 and T4 are
turned off.
Without bridge freewheel diodes, the switches support high reverse bias voltages, but the switches
control the start of each oscillation half cycle. With freewheel diodes the oscillations can continue
independent of the switch states. The diodes return energy to the supply, hence reducing the energy
transferred to the load. Correct timing of the switches minimises currents in the freewheel diodes, hence
minimises the energy needlessly being returned to the supply. Energy to the load is maximised. As with
the single-leg half-bridge, the switches can be used to control the effective load power factor. By
advancing turn-off to before the switch current reaches zero, the load can be made to appear inductive,
while delaying switch turn-on produces a capacitive load effect. The timing sequencing of the
conducting devices, for load power factor control, are shown in figures 14.32 and 14.33.
The series circuit steady-state current at resonance for the symmetrical H-bridge can be approximated
by assuming ωo ≈ ω, such that in equation (14.75) io = 0:
V
2
× s × e −αt × sin ωt
(14.96)
0 ≤ ωt ≤ π
i (ωt ) =
−απ
ωL
1− e ω
which is valid for the ± Vs voltage loops of cycle operation at resonance, provided the time reference is
moved to the beginning of each half-cycle.
In steady-state the capacitor voltage absolute maxima are
∧
∨
1 + e −απ / ω
(14.97)
Vc = Vs
= Vs × coth (απ / 2ω ) = − Vc
1 − e −απ / ω
The peak-to-peak capacitor voltage is therefore
1 + e −απ / ω
4ω
(14.98)
Vc = 2 ×
Vs = 2Vs coth (απ / 2ω ) ≈
× Vs
απ
1 − e −απ / ω
The energy transferred to the load R, per half sine cycle (per current pulse) is
p− p
The energy transferred to the load R, per half sine cycle (per current pulse) is
2
2
W=
∫
π /ω
0
i 2 Rdt =
∫
π /ω
0
(
= ½CVs2 coth απ
 1

V

× s × e −αt × sin ωt  R dt
−απ


ωL
ω
 1− e

2ω
W =∫
(14.92)
)
The input impedance of the series circuit is

 ω ωo  
1 

= R  1 + jQ s 
−
Z s = Ze j ϕ = R + j  ωL −


ωC 
ω  

 ωo

(14.93)
  ω ωo  
−
where ϕ = tan−1 Q s 

ω  
  ωo
The frequency ratio terms in the equation for the input phase angle φ show that the resonant circuit is
inductive (φ > 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω<ωo.
From the series ac circuit, the voltage across the resistor, vR, at a given frequency, ω, is given by
R
(14.94)
vR (ω ) = Vi
1 

R + j ωL −

ωC 

π /ω
0
i 2 R dt = ∫
(
= 2CVs2 coth απ
π /ω
0
 2

V

× s × e−α t × sin ωt  R dt
−απ


ωL
ω
 1− e

)
(14.99)
2ω
Notice the voltage swing is twice that with the single-leg half-bridge, hence importantly, the power
delivered to the load is increased by a factor of four.
From the series ac circuit, the voltage across the resistor, vR, at a given frequency, ω, is given by
R
(14.100)
vR (ω ) = Vi
1 

R + j ωL −

ωC 

The magnitude of the resistor voltage is therefore
Power Electronics
469
R
vR (ω ) = Vi

1 
R2 +  ω L −

ωC 

1
= Vi
2
= Vi
Power Inverters
14.3.3i – Parallel-resonant current-source inverter – single inverter leg
1
 ωL
1 
−
1+ 

 R ω RC 
2
(14.101)
2
 ω ωo 
1 + Q2 
− 
 ωo ω 
The frequency ratio terms in the equation for the input phase angle φ show that the resonant circuit is
inductive (φ > 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω<ωo.
These resonant circuit resistor expressions are the same as for the half bridge case except the input
voltage Vi for the full bridge is twice that of the half bridge case, for the same supply voltage Vs.
If the input voltage Vi is expressed as a Fourier series then the resistor current can be derived in terms
of the summation of all the harmonic component according to
∑
∞
470
i ( nω ) = ∑ n=1 vR ( nω ) / R
∞
(14.102)
n=1 R
For a square wave input voltage, ±Vs, of frequency ω ≈ ωo , the input voltage fundament of magnitude
4Vs / π produces the dominant load current component, since higher frequency components are
attenuated by second order L-C filtering action. That is, V i = 4Vs π .
Figure 14.31c shows a single-leg half-bridge converter for high Q parallel load circuits. Energy is
provided from the constant current source every second half cycle by turning on switch T1. When T1 is
turned on (and T3 is then turned off) the voltage across the L-C-R circuit resonates from zero to a
maximum and back to zero volts. The energy in the inductor reaches a maximum at each zero voltage
instant. T3 is turned on (at zero volts) to divert current from T1, which is then turned off with zero
terminal voltage. The energy in the load inductor resonates within the load circuit, with the load in an
open circuit state, since T1 is off. The sequence continues when the load voltage resonates back to
zero as shown in figure 14.30b.
The parallel circuit steady-state voltage at resonance for the single-leg half-bridge can be approximated
by assuming ωo ≈ ω, such that in equation (14.82) vo = 0:
I
1
0 ≤ ωt ≤ π
× s × e −α t × sin ωt
(14.103)
v (ω t ) =
−απ
ωC
1− e ω
which is valid for both the +Is loop and open circuit load modes of cycle operation, provided the time
reference is moved to the beginning of each half-cycle.
In steady-state the successive inductor current absolute maxima are
∧
∨
1
−e −απ / ω
I L = Is
and I L = I s
(14.104)
1 − e −απ / ω
1 − e −απ / ω
The energy transferred to the load R, per half sine cycle (per voltage pulse) is
2
½C
T1
D1
L
R
½C
Vs
C
D4
T4
L
(b)
R
Cs
C
L
R
(a)
(c)
Figure 14.34. Different resonant load arrangements: (a) switch turn-off snubber capacitor Cs;
(b) split capacitor; and (c) series coupled circuit for induction heating.
14.3.2iii - Circuit variations
Figure 14.34a shows an single-leg half-bridge with a turn-off snubber Cs, where Cs << C, hence
resonant circuit properties are not affected. The capacitive turn-off snubber is only effective if switch
turn-off is advanced such that switch hard turn-off would normally result, that is, the resonant circuit
appears capacitive. The snubber acts on both switches since small signal wise (short dc sources),
switches T1 and T4 are in parallel.
Figure 14.34b shows a series resonant load used with split resonant capacitance. Resonance reenforcement occurs every half cycle as with the full H-bridge topology, but only two switches are used.
Figure 14.35c shows a transformer-coupled series circuit which equally could be a parallel circuit with C
in parallel with the coupled circuit, as shown. Under light loads, the transformer magnetising current
influences operation.
14.3.3 Parallel-resonant current-source inverters
Parallel resonant circuits use a current source inverter (class D, parallel) as considered in 14.2.1 and
shown in figure 14.31 parts c and d. If the load Q is high, then resonance need only be re-enforced
every second half-cycle, thereby simplifying converter and control requirements. A common feature of
parallel resonant circuits fed from a current source, is that commutation of the switches involves overlap
where the output of the current source can be briefly shorted.
W =∫
π /ω
0
v2
dt = ∫
R
π /ω
0
 1

I

× s × e −α t × sin ωt 
dt
−απ

 /R
ωC
ω
 1− e

(14.105)
 απ 
= ½ LI s2 coth 

 2ω 
To drive a parallel circuit from a voltage source inverter leg the resonant circuit inductance is series
connected to the parallel R-C circuit. The input impedance of the series plus parallel circuit is
2

ω 
1 ω 
1 −   + j

Q
ω

p ωo 
 o
Z p = Ze j ϕ = R 

ω


1 + jQ p
(14.106)
ωo




2


ω  ω 
1
   − 2 − 1 
where ϕ = tan−1 Q p


 ωo  ωo  Q p



For a voltage source inverter leg, from the series plus parallel ac circuit, the voltage across the resistor,
vR, at a given frequency, ω, is given by
R
jωC
1
R+
1
jωC
(14.107)
= Vi
vR (ω ) = Ve jϕ = Vi
2
R
ω 
1 ω
−
+
1
j


jωC
Qp ωo
jω L +
 ωo 
1
R+
jωC
The magnitude of the resistor voltage is therefore
1
vR (ω ) = Vi
2
2
  ω 2 
1 ω 
1 −    + 2  
  ωo   Qp  ωo 
(14.108)
1 ω
where ϕ = − tan −1
Q p ωo
2
ω 
1−  
 ωo 
The maximum resistor voltage is Q p / 1 − 1 / 4Q p2 at f = f o 1 − 1 / 2Q 2 . The effective input voltage Vi is
2Vs /π.
Power Electronics
471
Power Inverters
14.3.3ii – Parallel-resonant current-source inverter – H-bridge current-source inverter
Solution
If the load Q is low, or maximum energy transfer to the load is required, the full bridge converter shown
in figure 14.30d is used.
Operation involves T1 and T2 directing the constant source current to the load and when the load
voltage falls to zero, T3 and T4 are turned on (and T1 and T2 then turned off). Overlapping the
switching sequence ensures a path always exists for the source current. At the next half sinusoidal cycle
voltage zero, T1 and T2 are turned on and then T3 and T4 are turned off.
The parallel circuit steady-state voltage for the symmetrical H-bridge can be approximated by assuming
ωo ≈ ω, such that in equation (14.82) vo = 0:
I
2
v (ω t ) =
0 ≤ ωt ≤ π
× s × e −α t × sin ωt
(14.109)
−απ
ωC
ω
1− e
which is valid for both the + Is loops of cycle operation, provided the time reference is moved to the
beginning of each half-cycle.
In steady-state the successive inductor current absolute maxima are
∧
∨
1 + e −απ / ω
= I s × coth (απ / 2ω ) = − I L
I L = Is
(14.110)
1 − e −απ / ω
The energy transferred to the load R, per half sine cycle (per voltage pulse) is
i.
2
W =∫
π /ω
0
v2
R
dt = ∫
π /ω
0
 2

I

× s × e −αt × sin ωt  / R dt
−απ


ω
C
 1− e ω

From ωo = 2π f o = 1/ LC the necessary capacitance for resonance at 10kHz with 100µH is
1
C=
= 2.5µF
2
( 2 × π × 10kHz ) ×100µH
The circuit quality factor Q is given by
Z
L
100µH
Q= o =
/R=
/1Ω = 6.3
R
C
2.5µF
Therefore
α = 5×103 Ω/H
ω = 62.6 krad/s (9.968 kHz)
ξ = 0.079
BWs = 9.97 krad/s (1.587kHz)
ii.
472
Zo = 6.3 Ω
The steady-state current is given by equation (14.89)
V
1
i (ωt ) =
× s × e −αt × sin ωt
−απ
ωL
ω
1− e
= 245.5 × e −5000 t × sin ( 2π 10kHz × t )
Since the Q is high (6.3), a reasonably accurate estimate of the∧ peak current results if the current
expression is evaluated at sin(½π), that is t =25µs, which yields i = 216.7A. The rms load current is
216.7A/√2 = 153.2A rms.
 απ 
= 2 LI s2 coth 

 2ω 
As with a series resonant circuit, the full bridge delivers four times more power to the load than the
single-leg half-bridge circuit. Similarly, the load power and power factor can be controlled by operating
above or below the resonant frequency, by delaying or advancing the appropriate switching instances.
In the case of a voltage source, the expressions for the voltage across the load resistor are the same as
equations (14.106) to (14.108), except the input voltage Vi is doubled, from 2Vs /π to 4Vs /π.
From equation (14.90) the maximum capacitor voltage extremes are
∧
∨
1
−e −απ / ω
Vc = Vs
and Vc = Vs
1 − e −απ / ω
1 − e−απ / ω
340V
340Ve −0.25
=
=−
−0.25
1− e
1 − e −0.25
= 1537V
= −1197V
Example 14.5: Single-leg half-bridge with a series L-C-R load
iii.
The bridge output voltage is a square wave of magnitude 340V and 0V, with a 50% duty cycle.
The rms output voltage is therefore 340/√2=240.4V.
Since the load is at resonance, the current is in phase with the fundamental of the bridge output voltage.
An single-leg half-bridge inverter as shown in the figure 14.31a, with the dc rail L-C decoupling shown in
figure 14.36, supplies a 1 ohm resistance load with series inductance 100 µH from a 340 V dc source. If
the bridge is to operating at 10kHz, determine:
i.
the necessary series C for resonance at 10kHz and the resultant Q
ii.
the peak load current, its steady-state time domain solution, and peak capacitor voltages
iii.
the bridge rms voltage and fundamental voltage across the series L-C-R load
iv.
the power delivered to the load and the frequency when half power is delivered to the load.
What is the switching advance/delay time?
v.
the peak blocking voltage of each semiconductor type (and for the case when the freewheel
diodes are not employed)
vi.
the average, rms, and peak current in the switches and diodes
vii. the resonant capacitor specification
viii. the dc supply current and the dc link capacitor rms current
ix.
summarise conditions if the load is supplied from an H-bridge and also calculate the load
power supplied at the third harmonic frequency, 3ω.
Ldc
Idc
iC
Cdc
T1
D1
Vs
340V
D4
C
100µH
1Ω
T4
Figure 14.36.
Single-leg half-bridge series-resonance circuit.
The fundament voltage magnitude is given by
2V
1 π
b1 = ∫ Vs sin1ωt = π s = 216.5V peak
π
0
2V
≡ π s = 153V rms
The rms load current results because of the fundamental voltage, that is, the peak sine current is
216.5V/1Ω = 216.5A peak or 153V/1Ω = 153A rms. This agrees with the current values calculated in
part b.
iv.
The power delivered to the load is given by
2
P = irms
R = ib21 R
= 153A 2 × 1Ω = 23.41kW
Substitution into equation (14.92) gives 23.15kW at a pulse rate of 2×10kHz. Alternately
P = Vs × I = Vs ×0.45 × I rms
= 340V×0.45 × 153A=23.42kW
The half-power frequencies are when the reactive voltage magnitude equals the resistive voltage
magnitude.
R
f Au = f o ±
4π L
= 10kHz ± 796Hz
Thus at 9204 Hz and 10796 Hz the voltage across the resistive part of the load is reduced to 1/√2 of the
inverter output voltage, since the voltage vectors are perpendicular. The power (proportional to voltage
squared) is therefore halved (11.71kW) at the half-power frequencies.
Operating above resonance, f > fo produces an inductive load and this is achieved by turning T1 and T4
off prematurely. Zero current turn-on occurs, but hard switching results at turn-off. To operate at the
Power Electronics
Power Inverters
10796Hz (92.6µs) upper half-power frequency the period has to be reduced from 100µs (10kHz) to
92.6µs. The period of each half cycle has to be reduced by ½×(100µs - 92.6µs) = 3.7µs
∨
1 + e −απ / ω
= − Vc
1 − e −απ / ω
1 + e −0.25
= 340V
= 2734V
1 − e −0.25
The power delivered to the load is four times the single-leg half-bridge case and is
2
P = irms
R = 306.4A 2 × 1Ω = 93.88kW
The average switch current is 194.8A, but the average supply current is four times the single-leg halfbridge case and is 275.5.6A.
473
Operating below resonance, f < fo produces a capacitive load and this is achieved by turning T1 and T4
on late. Zero current turn-off occurs, but hard switching results at turn-on. By delaying turn-on of each
switch by ½×(109µs - 100µs), 4.5µs, the effective oscillation frequency will be decreased to the lower
half-power frequency, 9204Hz.
v.
The bridge diodes, which do not conduct at resonance, clamp switch and diode maximum
supporting voltages to the rail voltage, 340V dc.
Note that if clamping diodes were not employed the device maximum off-state voltages would occur
during switch change over, when one switch has just been turned off, and just before the on-going
switch is turned on. The load current is zero, so the load terminal voltage is the capacitor voltage.
Switch T1 would need to support
∨
∧
a forward voltage of Vs - v = 340V + 1197V =1537V = v and
∧
∨
a reverse voltage of v - Vs = 1537V - 340V = 1197V = - v , while
Switch T4 supports
∧
a forward voltage of v = 1537V and
∨
a reverse voltage of - v = 1197V.
Thyristor family devices must be used, or devices with a series connected diode, which will increase the
converter on-state losses.
vi.
At resonance the two freewheel diodes do not conduct.
The rms load current is 153.2 A at 10 kHz, where switch T1 conducts half the cycle and T4 conducts the
other half which is the opposite polarity of the cycle. Each switch therefore has an rms current rating of
153.2/√2 = 108.3A rms.
Since both switches conduct the same current shape, each has an average current rating of a half-wave
rectified sine of magnitude 216.5A, that is
1 π
1
I T1 =
216.5sinωt dt = × 216.5A
2π ∫ 0
π
= 0.45 × 216.5 / 2 = 68.9A
By Kirchhoff’s current law, this current value for T1 is also equal to the average dc input current from the
supply Vs.
vii.
The 2.5µF capacitor has a bipolar voltage and current requirement of ±1537V and ±216.7 A.
The rms ratings are therefore ≈1087V rms and 153A rms. A metallised polypropylene capacitor capable
of 10kHz ac operation, with a maximum dv/dt rating of approximately ½×(1537+1197)×ω, that is
85.6V/µs, is required.
viii.
The dc supply current is the average value of the half-wave rectified sinusoidal load current,
which is the average current in T1. That is
I dc = 0.45 × 153.1A rms
= 68.9A dc
The rms current in the dc link capacitor Cdc is related to the dc input current and switch T1 rms current
(as found in part vi.), by
2
− I dc2
I c = I rms
= 108.32 − 68.92 = 83.6A rms
ix.
The load dependant parameters C, ωo, ω, α, Q, BW, ξ, and half power points remain
unchanged, being independent of switching frequency.
From equation (14.96) the steady-state current is double that for the asymmetrical bridge,
V
2
i (ωt ) =
× s × e −α t × sin ωt
−απ
ωL
1− e ω
= 491× e −5000 t × sin ( 2π 10kHz × t )
∧
The peak current is i = 433.4A.
The rms load current is 433.4A/√2 = 306.4A rms
From equation (14.97) both the maximum capacitor voltages are
474
∧
Vc = Vs
For a square wave, the third harmonic is a third the magnitude of the fundamental. From equation
(14.101), for operation at the lower half power frequency 9204Hz, (which would result in the largest
harmonic component magnitude after L-C filtering attenuation) f3 = 27.6kHz.
4V
1
vR (ω½− ) = 13 × s ×
2
π
 3ω½− ωo 
2
1+ Q 
− −
 ωo 3ω½ 
4 × 340V
1
1
= 3×
×
2
π
2π 10kHz 
2  3 × 2π 9.204 kHz
1 + 6.3 
−

3 × 2π 9.204kHz 
 2π 10kHz
4 × 340V
1
= 13 ×
×
2
π
10 
 3 × 9.204
1 + 6.32 
−

10
3
9.204
×


= 144.3V × 0.066 = 9.53V
The magnitude of the third harmonic current is therefore 9.5V/1Ω = 9.5A or 6.7A rms. The load power at
this frequency is 6.7V2/1Ω = 45.1W. This is clearly insignificant compared to the fundament power of
93.88kW being delivered to the 1 Ω load.
♣
14.3.4 Single-switch, current source, series resonant inverter
The single switch inverter in figure 14.35 is applicable to high Q load circuits such that the output is
essentially sinusoidal, with zero average current. Based on the operating mechanisms, a sinusoidal
current implies the switch has a 50% duty cycle. The switch turns on and off at zero volts so switch
losses are low, so the operating frequency can be high. The input inductor Llarge in conjunction with the
input voltage source, during steady state operation, act as a current source input, Is, for the resonant
circuit, such that Vs Is is equal to the power delivered to the load R.
When the switch T1 is turned on, with zero terminal voltage, it conducts both the constant current Is and
the current io resonating in the output circuit, as shown in the circuit waveforms in figure 14.35. The
resonating load current builds up. The switch T1, which is in parallel with Cs, is turned off. Current from
the switch is diverted to Cs, which charges from an initial voltage of zero. Cs thus forms a turn-off
snubber in parallel with T1. The charge on Cs eventually resonates back to zero at which instant the
switch is turned on, again, with zero turn-on loss.
The resonant frequency is ωo = 1/ Lo Co and because of the high Q, a small change in the switching
frequency significantly decreases the output current, hence output voltage.
As with any current source inverter, the peak switch voltage is in excess of Vs. Since the current is
sinusoidal, the average load voltage and inductor voltage are zero. Therefore the average voltage
across Co and Cs is the supply voltage Vs. The peak switch voltage can be estimated to be in excess of
Vs /0.45 which is based on a half-wave rectified average sinusoidal voltage.
If the load conditions change and the switch duty cycle is varied from δ = ½, circuit voltages increase
and capacitor Cs voltage discharges before the circuit current reaches zero. The capacitor and switch
are bypassed with current flowing through the diode D1. This diode prevents the switch from
experiencing a negative voltage and the capacitor from charging negatively.
Although such resonant converters offer features such as low switching losses and low radiated EMI,
optimal control and performance are difficult to maintain and extremely high circuit voltages occur at low
duty cycles.
Power Electronics
475
Power Inverters
Llarge
Vs
Vs
Vs
½Vs
iD1
T1 D1
Vs
Vs /N-1
Is
iT
476
iCs
Lo
Co
Rload
Cs
a
a
io
Vs /N-1
a
Vs
Va0
½Vs
Va0
Va0
Vs /N-1
0
0
0
switch conducting
δ=½
io
switch off
1/2fo
+½Vs
switch conducting
1/2fo
+½Vs
Is
+½Vs
+¼Vs
0V
0V
t
t
t
-½Vs
-½Vs
(a)
Is
iT1
(b)
-¼Vs
(c)
-½Vs
IT1 = Is + io
Figure 14.37. One phase leg of a voltage-source bridge inverter with:
(a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and waveform for five levels.
Is
A multilevel inverter allows higher output voltages with low distortion (due to the use of both pulse width
and amplitude modulation) and reduced output dv/dt.
There are three main types of multilevel converters
• Diode clamped
• Flying capacitor, and
• Cascaded H-bridge
iCs = Is + io
iCs
iD1
14.4.1 Diode clamped multilevel inverter
VT1
io
io
↑
Is
IT1
Rload
↑
Is
ICs
Rload
Figure 14.35. Single-switch, current-source series resonant converter circuit and waveforms.
14.4
Multi-level voltage-source inverters
The conventional three-phase, six-switch dc to ac voltage-source inverter is shown in figure 14.7. Each
of the three inverter legs has an output which can provide one of two voltage levels, Vs, when the upper
switch (or diode) is on, and 0 when the lower switch (or diode) conducts. The quality of the output
waveform is determined by the resolution and switching frequency of the pwm technique used.
A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of the leg can be more
than two discrete levels, as shown in figure 14.37 for a diode clamped multilevel inverter model. In this
way, the output quality is improved because both pulse width modulation and amplitude modulation can
be used. The output pole is made from more than two series connected, clamped switches, so the total
dc voltage rail can be the sum of the voltage rating of the individual switches. Very high output voltages
can be achieved, where each device does not experience a voltage in excess of its individual rating.
Figure 14.37 shows the basic principle of the diode clamped (or neutral point clamped, NPC) multilevel
inverter, where only one dc supply, Vs, is used and N is the number levels present in the output voltage
between the leg output and the inverter negative terminal, Va-neg. The capacitors split the dc rail voltage
into a number of lower voltage levels, each of which can be tapped and connected to the leg output
through switches (and diodes). Only one string of series connected capacitors is necessary for any
number of output phase legs.
The number of levels in the line-to-line voltage waveform will be
k = 2N −1
(14.111)
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k − 1
(14.112)
The number of capacitors required, independent of the number of phase, is
(14.113)
N cap = N − 1
while the number of clamping diodes per phase is
Dclamp = 2 ( N − 1)
The number of possible switch states is
nstates = N phases
and the number of switches in each leg is
Sn = 2 ( N − 1)
(14.114)
(14.115)
(14.116)
The basic three-level inverter (±½Vs, 0) is shown in figure 14.38, along with the basic three-level voltage
from the leg output to centre tap of the capacitor string, R (neutral point). When switch T1 is on, its
complement T1′ is off, and visa versa. Similarly for the pair of switches T2 and T2′. Specifically T1 and T2
on give the output +½Vs, T1′ and T2′ on give the output -½Vs, and T2 and T1′ on give the output 0.
Essential to attaining these output levels, are the clamping diodes Du and Dℓ. These two diodes clamp
the outer switches to the capacitor string mid-point, which is half the dc rail voltage. In this way, no
switch experiences a voltage in excess of half the dc rail voltage. Inner switches must be turned on (or
off) before outer switches are turned on (or off).
Power Electronics
477
Power Inverters
The five-level inverter uses four capacitors, and eight switches in each inverter leg. A set of clamping
diodes (three in total for each leg) clamp the complementary switches in each leg. The output is
characterised by having five levels, ±½Vs, ±¼ Vs, and zero. Some of the clamping diodes experience
voltages in excess of that experienced by the main switches. Series connection of some of the clamping
diodes avoids this limitation, but at the expense of increasing the number of clamping diodes from 2×
(N-1) to (N-1)×(N-2) per phase. Thus, depending on the diode position in the structure, two diodes have
blocking requirements of
N −1− k
VRB =
Vs
(14.117)
N −1
where 1 ≤ k ≤ N-2. These diodes require series connection of diodes, if all devices in the structure are to
support Vs /(N-1). For N > 2, capacitor imbalance occurs.
The general output voltage, to the centre of the capacitor string is given by
V
Van = s (T1 + T2 + .. .. + TN −1 − ½ ( N − 1))
(14.118)
N −1
+½Vs
D1
T2
D2
0
T1
′
D1
′
D2
T2
-½Vs
iL > 0
Cu
½Vs
T1
D1
T2
D2
+½Vs
′
T1
′
vo
iL > 0
′
vo = ½Vs
T2
D2
T1
′
D1
′
D2
iL > 0
′
vo
iL > 0
′
D1
T2
D2
T1
′
D1
′
D2
T2
-½Vs
vo = 0
vo
i >0
iL > 0
′ L
′
vo = -½Vs
(c)
+½Vs
′
′
T1
0
(b)
+½Vs
Vs
D1
T2
-½Vs
+½Vs
′
T1
0
(a)
Dcu
478
+½Vs
′
′
T1
D1
T1
D1
T1
D1
T2
D2
T2
D2
T2
D2
T1
′
D1
T1
′
D1
T1
′
D1
′
D2
′
D2
′
D2
R
C
Cℓ?
T1’
½Vs
Dcℓ
D
c?
T2’
D1’
0
vo
iL < 0
0
′
vo
iL < 0
0
′
vo
iL < 0
D2’
neg
T2
-½Vs
ia
VaR
′
ib
ic
b
iL < 0
′
vo = ½Vs
(d)
+½Vs
t
o
Vba
0
-½Vs
c
T2
-½Vs
iL < 0
vo = 0
(e)
′
T2
-½Vs
iL < 0
′
vo = -½Vs
(f)
Figure 14.39. The six output voltage and current combinations for the NPC bridge inverter:
(a), (b), (c) output current iL > 0; and (d), (e), (f) output current iL < 0.
Vao
a
14.4.2 Flying capacitor multilevel inverter
Figure 14.38. Three-phase, voltage-source, three-level, diode-clamped (NPC) bridge inverter.
Table 14.5. Conduction paths in the diode clamped three-level inverter
Vout
On
switches
Output current and path
I
- iL
+ iL
Active clamping
diodes
½ Vs
T1 T2
T1 T2
Fig 14.39a
D1 D2
Fig 14.39d
none
0
T1 ′ T2
Dcu T2
Fig 14.39b
T1′ Dcℓ
Fig 14.39e
Dcu Dcℓ
-½ Vs
T1 ′ T2 ′
D1′ D2′
Fig 14.39c
T 1 ′ T2 ′
Fig 14.39f
none
Table 14.5 in combination with the six parts of figure 14.39, show the conducting devices for the six
different output voltage and current combinations of the NPC inverter leg.
One leg of a fly-capacitor clamped five-level voltage source inverter is shown in figure 14.40b, where
capacitors are used to clamp the switch voltages to ¼Vs. The available output voltages are ±½Vs, ±¼Vs,
and 0, where the output is connected to the dc link (Vs and 0) indirectly via capacitors. Figure 14.40
shows that in general, switches Tn and Tn+1 connect to capacitor Cn. The configuration offers more
usable switch states than the clamped diode inverter, and this redundancy allows better, flexible control
of capacitor voltages. For example, Table 14.5 shows that there are six states for obtaining 0V output,
and four states for each of ±¼Vs. The output states ±½Vs do not involve the capacitors, hence they offer
no redundant states. The basic switch restriction is that only one complementary switch (for example, T4
or T4′ ) is on at any time, so as to prevent shorting of a flying capacitor (e.g., T4 and T4′ would short C3).
The number of levels in the line-to-line voltage waveform will be
k = 2N −1
(14.119)
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k − 1
(14.120)
The number of capacitors required, which is dependent of the number of phase, is for each phase
N cap = ½ ( N − 1)( N − 2 )
(14.121)
Power Electronics
479
Power Inverters
Table 14.6. Five-level flying-capacitor inverter output states (phase A to R)
The number of possible switch states is
nstates = N phases
and the number of switches in each leg is
Sn = 2 ( N − 1)
(14.122)
(14.123)
The current output paths in Table 14.6 are made up by the series (and parallel) connection of the flying
capacitors through the turn-on of the appropriate switches. Capacitors shown as negative are
discharging in the formed path, while those shown as positive are charging. Use of the shown
redundant states allows control to maintain the necessary voltage level on all the flying capacitors, while
providing the desired output voltages.
A feature of the flying capacitor multilevel inverter is its ride through capability due to the large
capacitance used. On the other hand, the capacitors have a high voltage rating and suffer from high
current ripple, since they conduct the full load current when connected into an active output voltage
state. Capacitor initial charging is also problematic, especially given the capacitors for each leg, and
between the different legs, are independent.
VC1
T1 D1
Vs
VC1
VCu
T2 D2
R
Cℓ
C
?
Cu
T1?D1?
VCℓ
V
C?
C3
T4 D4
R
¾Vs
C
Cℓ?
½Vs
¼Vs
phase
a
¼Vs
N-1
states
3
0
2
N -4N+1
states
-¼Vs
phase
a
5
-½Vs
capacitors
C2
C3
paths
1
1
1
1
=
=
=
½Vs
1
1
1
0
=
=
+
½Vs
-VC3
1
1
0
1
=
+
-
½Vs
-VC2+VC3
1
0
1
1
+
-
=
½Vs-VC1+VC2
0
1
1
1
-
=
=
-½Vs+VC1
1
1
0
0
=
+
=
½Vs
1
0
1
0
+
-
+
½Vs-VC1+VC2 -VC3
0
1
1
0
-
=
+
-½Vs+VC1-VC3
1
0
0
1
+
=
-
½Vs-VC1+-VC3
0
1
0
1
-
+
-
-½Vs+VC1-VC2+VC3
-VC2
0
0
1
1
=
-
=
-½Vs
1
0
0
0
+
=
=
½Vs-VC1
0
1
0
0
-
+
=
-½Vs+VC1-VC2
0
0
1
0
=
-
+
-½Vs
-VC2 -VC3
0
0
0
1
=
=
-
-½Vs
+VC3
0
0
0
0
=
=
=
-½Vs
+VC2
(a)
(b)
The number of levels in the line-to-line voltage waveform will be
k = 2N −1
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k − 1
The number of capacitors or isolated supplies required per phase is
N cap = ½ ( N − 1)
′ D′4?
T4?
′ D′3?
T3?
′ D′2?
T2?
2
C1
The N-level cascaded H-bridge, multilevel inverter comprises ½(N-1) series connected single-phase Hbridges per phase, for which each H-bridge has its own isolated dc voltage source. For each bridge, as
shown in table 14.7, three output voltages are possible, ±Vs, and zero, giving a total number of states of
3½( N −1) , where N is odd. Figure 14.41 shows one phase of a seven-level cascaded H-bridge inverter.
The cascaded H-bridge multilevel inverter is based on multiple two level inverter outputs (each Hbridge), with the output of each phase shifted. Despite four diodes and switches, it achieves the
greatest number of output voltage levels for the fewest switches.
Its main limitation lies in the need for isolated power sources for each H-bridge and for each phase,
although for VA compensation, capacitors replace the dc voltage supplies, and the necessary capacitor
energy is only to replace losses due to inverter losses. Its modular structure of identical H-bridges is a
positive design feature.
T3 D3
Vs
C2
½Vs
switching states
T2
T3
T4
14.4.3 Cascaded H-bridge multilevel inverter
VC?
C1
1
T1
T2?D2?
VCℓ
VC3
VAR
N-1
states
C1
T2 D2
mode
4
T1 D1
Cu
VCu
VC2
480
′ D′1?
T1?
Figure 14.40. One leg of a voltage-source:
(a) three-level and (b) five-level, flying capacitor clamped bridge inverter.
The number of possible switch states is
nstates = N phases
and the number of switches in each leg is
S n = 2 ( N − 1)
Vs
On
switches
T2 T3
(14.125)
(14.126)
(14.127)
(14.128)
Table 14.7. Three output states of H-bridges and their current paths.
Vℓ
(14.124)
Bidirectional current paths
+ iL
- iL
T2 T3
D2 D3
0
none
D4 D1
D2 D3
-Vs
T1 T4
T1 T4
D2 D3
Power Electronics
481
Power Inverters
482
½Vs
0
¼Vs
Vs
D2 T2
T1 D1
0
0
π
-¼Vs
V1
π
D4 T4
T3 D3
-½Vs
1
½
0
Vs
D2 T2
T1 D1
V1
-½
D4 T4
T3 D3
-1
0
0
0
Vs
D2 T2
T1 D1
0
V1
Figure 14.42. Multi-carrier based pwm generation for 1 phase of a voltage-source, 5-level, inverter.
D4 T4
T3 D3
14.4.4i - Multiple offset triangular carriers
Figure 14.41. One leg of a voltage-source, seven-level, cascaded H-bridge inverter.
A comparison between the three basic multilevel inverters is possible from the numerical summary of
component numbers for each inverter, as in Table 14.8.
The diode clamped inverter requires many clamping diodes; the flying capacitor inverter requires many
independent capacitors; while the cascaded inverter requires many isolated dc voltage power supplies.
Table 14.8. Multilevel inverter component count, per phase.
Inverter type
VA-0V
levels
VA-B
VA-N
switches
& // diodes
diodes
clamping
flying
capacitors
Level
capacitors
Isolated
supplies
diode clamped
N
2N-1
4N-3
2(N-1)
(N-1)(N-2)
0
(N-1)
0
fly capacitor
N
2N-1
4N-3
2(N-1)
0
½(N-1)(N-2)
(N-1)
0
cascade
N
2N-1
4N-3
2(N-1)
0
0
½ (N-1)*
½(N-1)*
* either /or
14.4.4 PWM for multilevel inverters
Two basic approaches can be used to generate the necessary pwm signals for multilevel inverters.
Each approach is based on the extension of a two level equivalent.
• Modulating waveform comparison with offset triangular carriers
• Space vector modulation based on a rotating vector in multilevel space
Various sinusoidal pwm techniques were considered in sections 14.1.3v and 14.1.3vi of this chapter.
Figure 14.42 shows how a triangular carrier is associate with each complementary switch pair, four
carriers (N-1) for the five-level inverter as illustrated. The parts of figure 14.42 show how the four
individual carriers can be displaced with respect to one another. The figure also shows how triplen
injection is incorporated. The appropriate five-level switch states, as in tables 14.4 to 14.6, can be used
to decode the necessary switching sequences. To minimise losses, switching only occurs between
adjacent levels.
14.4.4ii - Multilevel rotating voltage space vector
Space vector modulation for the two-level inverter was considered in section 14.1.3vi of this chapter.
The basic hexagon shape for two levels is extended to higher levels as shown in figure 14.43, for three
levels. The number of triangles, vectors, and states increases rapidly as the level number increases.
Table 14.9. Properties of N-level vector spaces
levels
states
N
N
3
triangles
6(N-1)
2
vectors
3N(N-1)+1
vectors
in each hexagon
2
8
6
7
(1+6)
3
27
24
19
(1+6)+12
5
125
96
61
(1+6)+12+18+24
Power Electronics
483
Power Inverters
484
From table 14.9, the states for the two and three level inverters can be specified as follows.
α1
The 2-level inverter
The zero state matrix is
[000 111]
The first and only hexagon is shown in figure 14.22a.
[100 110 010 011 001 101]
L
α2
The three level inverter
The zero state matrix is
[000 111 222]
The first hexagon matrix is
100 110 010 011 001 101 
 211 221 121 122 112 212 


The second hexagon matrix is
[ 200 210 220 120 020 021 022 012 002 102 202 201]
P
(a )
N
d c lin k
α1
L
α2
These pole states are shown figure 14.43.
(b )
120
020
010
121
021
110
221
000
111
222
011
122
022
001
112
012
002
220
100
211
200
α2
201
202
(c )
Figure 14.43. Rotating voltage space vector approached applied to three phases of a voltage-source
three-level, inverter.
A 0  represents the minimum voltage obtainable from the multilevel converter and N-1 represents the
maximum value. For example, in a two-level converter, 0  is equivalent to 0V and 1  is equivalent to Vs,
where Vs is the converter DC link voltage. In a three-level converter 0  is equivalent to -½Vs, 1  is
equivalent to 0 V, and ‘2’ is equivalent to ½Vs where Vs is the dc link voltage of the multilevel converter.
When the rotating vector is drawn in the vector space, it is decomposed into vectors bordering the
triangle it lies in. When operating in the outer hexagon, the vectors states used in the inner most
hexagon mean that that level of the converter is operating with a six-step quasi-square output voltage
waveform, to which is added a modulated square waveform for the next higher level.
14.5
N
α1
101
212
102
P
210
P
(d )
The dual or double converter circuit in figure 14.44a and b will accommodate four-quadrant dc machine
operation, where the circuit performs as two fully controlled converters in anti-parallel. Each converter is
able to rectify and invert, but because of their inverse parallel connection, one converter (the positive
converter P) operates in quadrants QI and QIV, while the other (the negative converter N) operates in
quadrants QII and QIII, as shown in figure 14.45.
The two converters can be operated synchronously, called simultaneous control or independently where
one is always blocking, called independent control.
d c lin k
in p u t L -C
filte r
o u tp u t
filte r
re ctifier/
co n ve rter
3Φ
in p u t
Reversible dc link converters
Power inversion by phase angle control is attained with a fully controlled single-phase converter as
discussed in section 11.3.3. Power regeneration is also possible with the fully controlled three-phase
converter shown in figure 11.17. If a fully controlled converter supplies a dc machine, two-quadrant
control is possible (QI and QIV), motoring in one direction of rotation and generating in the other
direction. Power regeneration into the supply is achieved by reversing the dc output voltage by
controlling the converter phase delay angle. The converter current is uni-directional, that is, the
converter output current can not reverse.
N
in verte r
3Φ
o u tp u t
½L
Figure 14.44. Reversible converter allowing four-quadrant control of: (a) a dc machine with
independent converters; (b) a dc machine with simultaneously controlled converters; and (c)
voltage and (d) current fed induction machine.
14.5.1 Independent control
Simultaneous converter control can be used if continuous load current can be guaranteed. Otherwise
only one converter, depending on the quadrant, need operate at anyone time (the other is in a blocking
state), as shown in figure 14.44a. No circulating currents arise due to possible mismatched N and P
converter output voltages. The continuous current condition may be difficult to ensure at light load levels.
Additional series armature inductance, L in figure 14.44a and b, helps with current smoothing and
ensuring continuous machine current.
Power Electronics
Power Inverters
A machine rotational direction change is affected by the following converter operating procedure.
• Initially the motor is operating in quadrant I, with 0° ≤ α1 ≤ 90° for the positive converter P. The
negative converter, N, is in the fully blocking state, with all thyristors turned off.
• The positive converter is put into the inverting mode with 90° ≤ α1 ≤ 180°, changing the average
output voltage from positive to negative. The machine current rapidly falls to zero. The machine
rotational speed slows, the rate depending on the load inertia.
• After a dead time, the positive converter blocks and the negative converter N starts in a motor
braking mode in quadrant II. The motor speed falls rapidly to zero.
• The second converter operates in quadrant III and rapidly accelerates the motor in the opposite
direction, with 0° ≤ α2 ≤ 90°.
The dead time before turning on the negative converter N is to ensure the positive converter P is fully
off, otherwise the three-phase input voltage lines may short through the two converters. Such a current
condition cannot be controlled with line-commutated thyristors. Operation is characterised by transitions
from QI to QII to QIII for reversal, and transitions from QIII to QIV to QI for returning to the original
direction of rotation.
A machine rotational direction change is affected by the following converter operating procedure.
• Initially the motor is operating in quadrant I for the rectifying, positive converter, with 0° ≤ α1 ≤
90°. The other converter is operating in the inverting mode with 90° ≤ α2 ≤ 180°, such that α1 + α2
= 180°. The output voltage for both converters is the same, and the negative converter N carries
only the circulating current.
• For rotational direction reversal, α1 ≥ 90° and α2 ≤ 90°, such that α1 + α2 = 180°. The armature
back emf voltage now exceeds the converter output voltages, and current diverts to the negative
converter N and the machine regeneratively brakes, operating in quadrant II. The current rapidly
falls to zero and the positive converter P carries only the ac circulating current.
• The speed rapidly falls to zero, with α1 = α2 = 90° giving zero output voltage, so as to control the
armature current since the back emf is zero. Then with α2 < 90° the machine rapidly accelerates
in quadrant III, in the reverse direction to the original rotation.
485
sp eed
vo
Ia
Ia
+
N
P
E
α1
E
vo
α2
rege nera tive brak in g
/in vers io n
II
m o to r/rectification
N
III
Ia
m o to r/rectification
to rq u e
IV
rege nera tive brak in g
/in versio n
Ia
P
E
α2
I
+
vo
Ia
α1
E
For reversing the direction of rotation from Q III the operation sequence is QIII to QIV to QI. Since no
converter dead time is introduced, a fast dynamic response can be attained. A small dc circulating
current is deliberately maintained, that is greater in magnitude than the peak of the ac ripple current. The
ac current can then flow continuously in both converters, both of which can operate in the continuous
conduction mode without the need for continuous converter current reversal operation.
14.5.3 Inverter regeneration
+
vo
486
vo
+
Figure 14.45. Four quadrants of reversible converter operation.
14.5.2 Simultaneous control
Simultaneous converter control, also called circulating current control, functions with both converters
always in operation which gives a faster dynamic response than when the converters are used mutually
exclusively. To avoid supply short circuits requires that the output voltage of both converters (rectifier Vr
and inverter Vi) be the same in order to minimise circulating currents.
Vr + Vi = 0
V cos α1 + V cos α 2 = 0
(14.129)
cos α1 + cos α 2 = 0
that is α1 + α 2 = 180°
Equation (14.129) implies that both converters operate with firing angles that sum to 180°. Each
converter produces the opposite polarity output voltage, which is cancelled by reversing the relative
output connections. Under such conditions the load current can be maintained continuous. To minimize
any circulating current due to ripple voltage produced by instantaneous voltage differences between the
two converters, inductance is usually inserted between each converter and the dc machine load, as
shown in figure 14.44b. Adversely the cost and weight are increased, and the supply power factor and
drive efficiency are decreased, compared to that obtained with independently controlled converters.
The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link voltage from
reversing. The dual or double converter circuit in figure 14.44c will allow inversion with a three-phase
voltage source inverter. One converter rectifies, the other converter inverts, functioning as a selfcommutated inverter, transferring power from the dc link to the ac supply. Complete four-quadrant
control of the three-phase ac machine on the inverter is achieved in conjunction with control of the dc to
ac inverter. That is, motor reversal is achieved by effectively interchanging the pwm control signals
associated with two phases. The real power flow back into the ac supply is controlled by the converter
phase delay angle, while the reactive power flow is controlled by the voltage magnitude. The angle and
voltage are not independent. In the case of a pwm controlled inverter fed ac machine, the ac to dc
converter can be uncontrolled, using all diodes, since dc output voltage reversal is not utilised.
Figure 14.44d shows a fully reversible current controlled converter/inverter configuration, using selfcommutating devices. The use of self-commutated switches (rather than mains commutated converter
thyristors) offers the possibility to minimise the input current distortion and to reduce the inductor size
hence improve the dynamic current response. The switch series diodes are essential since the shown
IGBTs have no useable reverse blocking capability. The use of reverse blocking GCTs avoids the need
for the series blocking diodes, which reduces the on-state voltage losses but increases gate drive
complexity and power rating. Series connection of devices is necessary above a few kV, and above 1
MVA the GCT dominates.
14.6
Standby inverters and uninterruptible power supplies
Standby inverters and uninterruptible power supplies (ups’s) provide a 50/60 Hz supply in the event of
an ac mains failure. An ups must provide ac output such that mains failure is undetected by the load. To
achieve this, an ups continually feeds the load from an inverter. A load that can tolerate a short
interruption of the ac supply is fed from a standby inverter which becomes operational within 1-5 ms
after the ac supply failure. In communications, computing, and automated production lines, ups’s are
essential for even brownouts (V and f outwith bounds for reliable equipment operation), while in lighting
and heating applications, standby inverters are used since a few missing ac cycles (due to a blackout –
total interruption of the mains power) may be tolerated. In each power supply case, the alternative
energy source is a standby dc battery. The ups keeps the battery charged when the ac input is
supplying the output power.
14.6.1 Single-phase UPS
A basic single-phase UPS is shown in figure 14.46. A key safety objective is to retain the supply neutral
at both the supply input and the ac output, without resorting to any from of isolating transformer.
Consequently, the input ac mains is half-wave rectified by diodes DR+ and DR− . Boost converters on the
positive and negative groups ensure supply sinusoidal input current and unity power factor. The output
H-bridge (T1-T4) uses pwm and feedback control to produce a fixed frequency and magnitude output
Power Electronics
487
Power Inverters
(and ac mains phase synchronisation if required), which is filtered by an L-C filter. In the event of a loss
of the ac supply, the backup batteries, V+ and V -, provide energy to the boost converters, hence to the
output inverter. The battery backup voltage magnitude is much less than the ac supply magnitude and
diodes, DB+ and DB− , isolate the batteries from the rectified ac supply voltage. The shown ups has two
basic limitations that manufactures strive to overt.
• If the battery is to be connected to neutral, then two batteries are necessary. Proprietary
attempts using only one battery involve circuit complications and limitations. At best, with one
battery, it is one forward biased diode voltage drop from neutral.
• Because the batteries supplies are not isolated during normal operation, during part of the
mains cycle near zero voltage, the batteries alternately provide energy. This decreases their
lifetime and necessitates more complicated trickle charge circuits. The input current is also
distorted at the 0V crossover. Replacement of the blocking diodes DB by switches involves
complexity and battery backup operation requires detection and is not fail safe.
½ wave rectifier
+
DR
ac
+
boost converter
+
L
H-bridge inverter
+
D
V
+
+
C
+
-
T1
D1
D3
Lo
N
N
-
T
-
C
+
-
T4
D4
D2
-
DB
DR
Power filters
+
T
Co
V
Figure 14.47 shows a basic three-phase ups, used up to a few tens of kilowatts. The ac supply is
rectified and filtered. A forward converter controls the dc link voltage to just above the battery voltage
level. This dc voltage is boosted to a dc level such that after inversion it provides the required output
voltage magnitude. If the input ac fails or droops, the dc link power is provided by the battery via diode
DB. The output inverter is usually operational in a pwm mode, which allows precise frequency control,
voltage control, ac mains phase synchronisation, and minimisation of low frequency output harmonics.
With pwm control minimal filtering is required, which minimises the filter weight, cost, size, and losses. A
three-phase ups can utilise third harmonic injection (14.1.4(iv)).
A three-phase boost input converter can be used to maintain sinusoidal ac supply input currents at unity
power factor.
Power L-C filters are used to reduce harmonics or ripple from
• the rectifier output (dc filter)
• the inverter output (ac filter).
T3
DB
14.6.2 Three-phase UPS
14.7
L-C filter
488
L
D
-
T2
o/p
L-C low-pass, second-order filters are shown in figures 14.44, 14.46, and 14.47. In figure 14.47, the L-C
smoothing filter at the rectifier output, filters the ac mains frequency components leaving dc. The same
type of filter is used in the inverter output to filter pwm harmonics, leaving the relative low frequency
modulation frequency.
The L-C filter fundamental cut-off frequency is dependent on L, C, and the load impedance ZL
vo
1
1
=
=
(14.130)
vi 1 + jω L ( Z1L + jωC ) 1 − ω 2 LC + j ωZ LL
The simplest design approach is to assume a non-load condition, ZL → ∞, whence the filter cut-off
frequency is f o = 1/ 2π LC .
Frequency components below fo, including dc, are passed. Those components above fo are attenuated
by a second order fall-off in gain. Any frequency components inadvertently around the resonant
frequency, fo, will be amplified. For this reason, the filter may be damped with parallel connected R-C
snubbers.
(
)
Figure 14.46. Single-phase uninterruptible power supply.
Reading list
See chapter 11 reading list.
DB
Hart, D.W., Introduction to Power Electronics,
Prentice-Hall, Inc, 1994.
Mohan, N., Power Electronics, 3rd Edition,
Wiley International, 2003.
Figure 14.47. Three-phase uninterruptible power supply.
Power Electronics
489
Problems
14.1.
The inverter in figure 14.7 is supplied from a 340 V dc source. The load has a resistance of 10
ohms and an inductance of 10 mH. The basic operating frequency is 50 Hz, with three notches
per half cycle giving half the maximum output, similar to that shown in figure 14.13.
Determine the load current waveform over the first two cycles and determine the power
delivered to the load based on the current waveform of the final half cycle.
14.2.
The inverter and load in problem 14.1 are controlled so as to eliminate the third and fifth
harmonics in the output voltage.
Determine the load current waveform over the first two cycles and the power delivered to the
load based on the current waveform of the last half cycle.
14.3.
Output voltage harmonic reduction can be achieved by employing multiphase, selected notching
modulation control on a three-phase bridge as discussed in 14.1.4. An output as in figure 14.14b
with α1 = 16.3° and β1 = 22.1° eliminates the 5th and 7th harmonics.
Determine the fundamental voltage output component and compare it with that of a square
wave. Determine the output rms voltage.
14.4.
With the aid of figure 14.11 determine the line-to-neutral and line-to-line output voltage of a dc to
three-phase inverter employing 120° device conduction.
Calculate the interphase:
i.
mean half-cycle voltage
ii.
rms voltage
iii.
rms voltage of the fundamental.
14.5.
The three-phase inverter bridge in figure 14.4 has a 600 V dc rail and a 10 Ω per phase load.
For 180° and 120° conduction calculate:
i.
the rms phase current
ii.
the power delivered to the load
iii.
the switch rms current.
[24.5 A, 18 kW, 17.3 A; 28.3 A, 24 kW, 14.15 A]
14.6
A single-phase square-wave inverter is supplied from a 340V dc source and the load is a 17 Ω
resistor. Determine switch average and rms current ratings. What power is delivered to the
load?
14.7
A single-phase square-wave inverter is supplied from a 340V dc source and the series R-L load
is a 20 Ω resistor and L=20mH. Determine:
i.
an expression for the load current, hence the maximum switch current
ii.
rms load current
iii.
average and rms switch current
iv.
maximum switch voltage
v.
average source current, hence power delivered to the load
vi.
load current total harmonic distortion.
Power Inverters
Blank
490
Gerd Terorde, Electrical Drives and Control Techniques, 2004.
1. Voltage-Source PWM Inverter
1.1 Introduction
In contrast to grid connected ac motor drives, hardly variable in speed, power
electronic devices (e.g. inverter), providing voltage supply variable in both
frequency and magnitude, are used to operate ac motors at frequencies other than the
supply frequency. Developments in this direction have taken place long ago, but a
techno-economical solution could not be found until the late 1980s because of
stringent space requirements, non-availability of high power devices and prohibitive
cost of electronic devices and components.
Rapid developments in the field of power electronics (inverter grade thyristor, GTO
thyristor, IGBT etc.) and miniaturization/mass production of control electronics
(development of VLSI technology and microprocessor based digital control
systems) have reached such a stage that variable ac inverter drives are becoming
increasingly popular in today’s motor drives. Presently, inverter drives meet not
only weight and space constraints, but also are economically viable.
In general, two basic types of inverters exist: Voltage-source inverter (VSI),
employing a dc link capacitor and providing a switched voltage waveform, and
current-source inverter (CSI), employing a dc link inductance and providing a
switched current waveform at the motor terminals. CS-inverters are robust in
operation and reliable due to the insensitivity to short circuits and noisy
environment. VS-inverters are more common compared to CS-inverter since the use
of Pulse Width Modulation (PWM) allows efficient and smooth operation, free from
torque pulsations and cogging [Bose 97]. Furthermore, the frequency range of VSI is
higher and they are usually more inexpensive when compared to CSI drives of the
same rating [Dub 89].
In this chapter, only voltage-source inverters are considered. Although the power
flow through the device is reversible, it is called an inverter because the predominant
power flow is from the dc bus to the three-phase ac motor load. Bi-directional power
flow is an important feature for motor drives as it allows regenerative breaking, i.e.
the kinetic energy of the motor and its load is recovered and returned to the grid
when the motor slows down. In electric vehicle application, the dc bus energy is
supplied directly from primary energy sources, e.g. batteries.
2
Chapter 1
In ac grid connected motor drives, a rectifier, usually a common diode bridge
providing a pulsed dc voltage from the mains, is required. Alternatively, a second
ac-to-dc converter, acting as a rectifier during the motoring mode and an inverter
during the breaking mode, is used between drive and utility grid. An additional
benefit of the active front end is enabling unity power factor, (sinusoidal) current
flows to or from the grid.
Although the basic circuit for an inverter may seem simple, accurately switching
these devices provides a number of challenges for the power electronic engineer.
The most common switching technique is called Pulse Width Modulation (PWM).
PWM is a powerful technique for controlling analog circuits with a processor’s
digital outputs. PWM is employed in a wide variety of applications, ranging from
measurement and communications to power control and conversion. In ac motor
drives, PWM inverters make it possible to control both frequency and magnitude of
the voltage and current applied to a motor. As a result, PWM inverter-powered
motor drives are more variable and offer in a wide range better efficiency and higher
performance when compared to fixed frequency motor drives. The energy, which is
delivered by the PWM inverter to the ac motor, is controlled by PWM signals
applied to the gates of the power switches at different times for varying durations to
produce the desired output waveform.
There are several PWM modulation techniques. It is beyond the scope of this book
to describe them all in detail. The following illustration describes the basic threephase inverter topology and typical pulse width modulation methods. Furthermore,
issues of phase voltage distortion/identification due to the inverter non-linearity are
discussed in detail.
1.2 Voltage-Source PWM Inverter
A typical voltage-source PWM converter performs the ac to ac conversion in two
stages: ac to dc and dc to variable frequency ac. The basic converter design is shown
in figure 1.1. The grid voltage is rectified by the line rectifier usually consisting of a
diode bridge. Presently, attention paid to power quality and improved power factor
has shifted the interest to more supply friendly ac-to-dc converters, e.g. PWM
rectifier. This allows simultaneously active filtering of the line current as well as
regenerative motor braking schemes transferring power back to the mains.
The dc voltage is filtered and smoothed by the capacitor C in the dc bus (figure 1.1).
The capacitor is of appreciable size (2-20 mF) and therefore a major cost item
[Bose 97]. Alternatively, the inverter can be supplied from a fixed dc voltage. The
filtered dc voltage is usually measured for control purpose. Because of the nearly
constant dc bus voltage, a number of PWM inverters with their associated motor
drives can be supplied from one common diode bridge. The inductive reactance L
between rectifier and ac supply is used to reduce commutation dips produced by the
rectifier, to limit fault current and to soften voltages spikes of the mains.
Voltage-Source PWM Inverter
3
Rectifier
DC bus
Inverter
T1
T3
L
D1
C
power
supply
T5
D3
D5
AC
motor
Udc
T4
T6
T2
D4
D6
D2
Switching logic
Figure 1.1: Basic three-phase voltage-source converter circuit.
Neglecting the voltage drop of the inductances (current depending) and diodes
(Ud ≈ 1V if i > 0), the positive potential of the dc bus voltage equals the highest
potential of the three phases and the negative potential equals the lowest potential of
the three phases. Since each phase owns one negative and one positive maximum
potential during one period of the net frequency, the rectifier input voltage equals
the maximum of the positive and negative line voltages, respectively. Thus, the
rectifier input voltage traces six pulses as shown in figure 1.2 by the thick line.
500
400
uab -uca
0
5
ubc
-uab uca
10
t [ms]
15
-ubc
0
5
1
10
t [ms]
uab -uca
0
5
0
5
0
5
40
0.5
0
Udc
500
400
20
iB6 [A]
1
iB6 [A]
600
Udc
U dc [V]
U dc [V]
600
15
-ubc
-uab
uca
10
15
20
10
15
20
10
15
20
t [ms]
20
0
20
ubc
40
t [ms]
ia [A]
ia [A]
20
0
-1
0
5
10
t [ms]
15
20
0
-20
-40
t [ms]
Figure 1.2: Line voltages (uab, ubc, uca), dc bus voltage Udc, line current
of the first phase ia and output current iB6 of a B6-diode bridge.
Left: No inverter output power (inverter losses ≈ 10 W).
Right: Inverter output power Pout ≈ 5,5 kW.
Figure 1.2 presents typical voltage and current waveforms of a B6-diode bridge
supplied by a stiff grid. As indicated by the dashed lines, the rectifier current iB6
increases, if the absolute value of a line voltage is higher than the dc voltage.
Consequently, the dc voltage increases slightly. A dc voltage higher than the current
voltage supply causes a reduction of the rectifier input current until the current
4
Chapter 1
equals zero and the diode bridge blocks the supply voltage. The rectifier current iB6
is identically reflected by the line currents. The sign of each line current depends on
the two non-blocking diodes each conducting the positive and negative rectifier
current, respectively.
During the conducting period, the difference of line and dc voltage is active as
voltage drop over the line inductances and resistances. The higher the line
inductances, the smaller the line current peaks. However, the value of the line
inductances is limited due to economic and efficiency reasons. Furthermore, the
average dc voltage depends on the line inductances and the inverter output power.
The maximum dc voltage (no load) is equal to the maximum amplitude of the line
voltages. Due to voltage drops of line inductances, resistances and rectifier diodes,
the dc voltage slightly decreases with increasing load. For more details concerning
the rectifier, see [Bose 97], [Dub 89] et al.
According to figure 1.1, the dc voltage is switched in a three-phase PWM inverter
by six semiconductor switches in order to obtain pulses, forming three-phase ac
voltage with the required frequency and amplitude for motor supply. The switching
devices must be capable of being turned “on” as well as turned “off”. During the last
years, major progress has been made in the development of new power
semiconductor devices. The simpler requirement driving the power switches and the
higher maximum switching-frequency, enabling higher operating frequencies
(higher motor speed), provide continually rising output power. The new generation
of switching devices is capable of conducting more current and blocking higher
voltages. The alternatives at present are gate turn-off thyristor (GTO), MOS
controlled thyristor (MCT), bipolar junction transistor (BJT), MOS field effect
transistor (MOSFET) and insulated gate bipolar transistor (IGBT).
The IGBT is a combination of power MOSFET and bipolar transistor technology
and combines the advantages of both. In the same way as a MOSFET, the gate of the
IGBT is isolated and its driving power is very low. However, the conducting voltage
is similar to that of a bipolar transistor. Presently, IGBTs dominate the mediumpower range of variable speed drives. Since the maximal current rating of IGBT
modules is around 1 kA and the voltage rating is approximately 3 kV, they will
gradually replace GTOs at higher power levels [Vas 99].
Parallel to the power switches, reverse recovery diodes are placed conducting the
current depending on the switching states and current sign. These diodes are
required, since switching off an inductive load current generates high voltage peaks
probably destroying the power switch. Exemplary for one inverter leg, figure 1.3
presents the basic configuration and the inverter output voltage depending on the
switching state and current sign. The basic configuration of one inverter output
phase consists of upper and lower power devices T1 and T4, and reverse recovery
diodes D1 and D4.
When transistor T1 is on, a voltage ½ Udc is applied to the load. Considering an
inductive load, the current increases subsequently. If the load draws positive current,
Voltage-Source PWM Inverter
5
it will flow through T1 and supply energy to the load. To the contrary, if the load
current ia is negative, the current flows back through D1 and returns energy to the dc
source.
T1 on
½ Udc
C/2
T1
D1
ia > 0
½ Udc
½ Udc
C/2
C/2
ωt
T1
D4
T1 off
ua0
T4 off
½ Udc
ua0
T4
D1
drop
T1
drop
ua0
D1
ia < 0
½ Udc
0
ua0
T4
C/2
ia
0
T1 on
T4 on
ωt
τdead
-½ Udc
D4
D4
drop
T4
drop
T4 on
Figure 1.3: Basic configuration of a half-bridge inverter and center-tapped inverter output voltage.
Left: Switching states and current direction. Right: Output voltage and line current.
Similarly if T4 is on, which is equal to T1 off, a voltage -½ Udc is applied to the load
and the current decreases. If ia is positive, the current flows through D4 returning
energy to the dc source. A negative current yields T4 conducting and supplying
energy to the load.
According to figure 1.3, with T1 on and drawing positive load current ia, the output
voltage ua0 will be less than ½ Udc by the on-state voltage drop of T1. When the load
current reverses, the output voltage will be higher than ½ Udc by the voltage drop
across D1. Similarly, the output voltage is slightly changed by the voltage drop of
the lower devices T4 and D4.
Normally, the on-state voltage and diode drops (≈1 V) are ignored and the centertapped inverter is represented as generating the voltage ½ Udc and -½ Udc,
respectively. Neglecting additionally the dead-time interval τdead, the behavior of the
power devices together with the reverse recovery diode is equally described by ideal
two-position switches.
6
Chapter 1
1.3 Pulse Width Modulation
Usually, the on- and off-states of the power switches in one inverter leg are always
opposite. Therefore, the inverter circuit can be simplified into three 2-position
switches. Either the positive or the negative dc bus voltage is applied to one of the
motor phases for a short time. Pulse width modulation (PWM) is a method whereby
the switched voltage pulses are produced for different output frequencies and
voltages. A typical modulator produces an average voltage value, equal to the
reference voltage within each PWM period. Considering a very short PWM period,
the reference voltage is reflected by the fundamental of the switched pulse pattern.
Apart from the fundamental wave, the voltage spectrum at the motor terminals
consists of many higher harmonics. The interaction between the fundamental motor
flux wave and the 5th and 7th harmonic currents produces a pulsating torque at six
times of the fundamental supply frequency. Similarly, 11th and 13th harmonics
produce a pulsating torque at twelve times the fundamental supply frequency
[Dub 89]. Furthermore, harmonic currents and skin effect increase copper losses
leading to motor derating. However, the motor reactance acts as a low-pass filter and
substantially reduces high-frequency current harmonics. Therefore, the motor flux
(IM & PMSM) is in good approximation sinusoidal and the contribution of
harmonics to the developed torque is negligible. To minimize the effect of
harmonics on the motor performance, the PWM frequency should be as high as
possible. However, the PWM frequency is restricted by the control unit (resolution)
and the switching device capabilities, e.g. due to switching losses and dead time
distorting the output voltage.
There are various PWM schemes. Well-known among these are sinusoidal PWM,
hysteresis PWM, space vector modulation (SVM) and “optimal” PWM techniques
based on the optimization of certain performance criteria, e.g. selective harmonic
elimination, increasing efficiency, and minimization of torque pulsation [Jen 95].
While the sinusoidal pulse-width modulation and the hysteresis PWM can be
implemented using analog techniques, the remaining PWM techniques require the
use of a microprocessor.
A modulation scheme especially developed for drives is the direct flux and torque
control (DTC). A two-level hysteresis controller is used to define the error of the
stator flux. The torque is compared to its reference value and is fed into a three-level
hysteresis comparator. The phase angle of the instantaneous stator flux linkage space
phasor together with the torque and flux error state is used in a switching table for
the selection of an appropriate voltage state applied to the motor [Dam 97],
[Vas 97]. Usually, there is no fixed pattern modulation in process or fixed voltage to
frequency relation in the DTC. The DTC approach is similar to the FOC with
hysteresis PWM. However, it takes the interaction between the three phases into
account. In the following subsections, hysteresis PWM, sinusoidal PWM and SVM
are discussed in more detail.
Voltage-Source PWM Inverter
1.3.1
7
Hysteresis PWM Current Control
Hysteresis current control is a PWM technique, very simple to implement and taking
care directly for the current control. The switching logic is realized by three
hysteresis controllers, one for each phase (figure 1.4). The hysteresis PWM current
control, also known as bang-bang control, is done in the three phases separately.
Each controller determines the switching-state of one inverter half-bridge in such a
way that the corresponding current is maintained within a hysteresis band ∆i.
Switching
logic
Hysteresis band ∆i
ia
Current reference
Real current
ia*
ia
∆i
ib
∆i
0
ib*
ua0
1/2 Udc
ic*
ic
∆i
Output
voltage
0
ωt
ωt
-1/2 Udc
Figure 1.4: Hysteresis PWM, current control and switching logic.
To increase a phase current, the affiliated phase to neutral voltage is equal to the half
dc bus voltage until the upper band-range is reached. Then, the negative dc bus
voltage -½ Udc applied as long as the lower limit is reached &c. More complicated
hysteresis PWM current control techniques also exist in practice, e.g. adaptive
hysteresis current vector control is based on controlling the current phasor in a α/βreference frame. These modified techniques take care especially for the interaction
of the three phases [Jen 95].
Obviously, the dynamic performance of such an approach is excellent since the
maximum voltage is applied until the current error is within predetermined
boundaries (bang-bang control). Due to the elimination of an additional current
controller, the motor parameter dependence is vastly reduced. However, there are
some inherent drawbacks [Brod 85]:
•
•
•
•
•
No fixed PWM frequency: The hysteresis controller generates involuntary
lower subharmonics.
The current error is not strictly limited. The signal may leave the hysteresis
band caused by the voltage of the other two phases.
Usually, there is no interaction between the three phases: No strategy to
generate zero-voltage phasors.
Increased switching frequency (losses) especially at lower modulation or
motor speed.
Phase lag of the fundamental current (increasing with the frequency).
8
Chapter 1
Hysteresis current control is used for operation at higher switching frequency, as this
compensates for their inferior quality of modulation. The switching losses restrict its
application to lower power levels. Due to the independence of motor parameters,
hysteresis current control is often preferred for stepper motors and other variablereluctance motors.
A carrier-based modulation technique, as described in the next subsection,
eliminates the basic shortcomings of the hysteresis PWM controller [Bose 97].
However, when being compared to the hysteresis PWM, an additional current
control loop, calculating the reference voltages, is required when subsequent
modulation schemes are applied to high-performance motion control systems.
1.3.2
Sinusoidal Pulse Width Modulation
Three-phase reference voltages of variable amplitude and frequency are compared in
three separate comparators with a common triangular carrier wave of fixed
amplitude and frequency (figure 1.5-1.6). Each comparator output forms the
switching-state of the corresponding inverter leg [Dub 89], [Leo 85]. In torque
controlled ac motor drives using sinusoidal PWM, the reference voltages (u*a, u*b, u*c)
are usually calculated by an additional current control loop (FOC).
d,q
ud*
id*
id
comparator
ub*
Current
controller
uq*
iq*
iq
Current
controller
Switching
logic
ua*
comparator
uc*
a,b,c
comparator
Carrier wave
Figure 1.5: Sinusoidal PWM, current control and switching logic.
As shown in figure 1.6, a saw-tooth- or triangular-shaped carrier wave, determining
the fixed PWM frequency, is simultaneously used for all three phases. This
modulation technique, also known as PWM with natural sampling, is called
sinusoidal PWM because the pulse width is a sinusoidal function of the angular
position in the reference signal.
Voltage-Source PWM Inverter
Phase a
9
Phase b
Phase c
Carrier wave
Uref
ωt
ua0
Upper switch “on”
Udc/2
ωt
-Udc/2
Lower switch “on”
ub0
ωt
uc0
ωt
uab
ωt
Figure 1.6: Principle of sinusoidal PWM generation.
Since the PWM frequency, equal to the frequency of the carrier wave, is usually
much higher than the frequency of the reference voltage, the reference voltage is
nearly constant during one PWM period TPWM. This approximation is especially true
considering the sampled data structure within a digital control system. Depending on
the switching states, the positive or negative half dc bus voltage is applied to each
phase. At the modulation stage, the reference voltage is multiplied by the inverse
half dc bus voltage compensating the final inverter amplification of the switching
logic into real power supply.
According to figure 1.7, the mean value of the output voltage, resulting from a
reference voltage being constant within one PWM-period, depends on the on- and
off-states of the affiliated switch:
u ao =
1
TPWM
1
u a 0 dt =
(∆t1 − ∆t 2 ) U dc
∫
2
T
PWM
T
PWM
(1.1)
10
Chapter 1
u a* 0
U dc 2
1
0
0
t
Saw-tooth
carrier wave
-1
∆t1
∆t2
u a*0
U dc 2
1
t
-1
∆t1/2
ua0
∆t2 ∆t1/2
Triangular
carrier wave
ua0
ua0
Udc /2
ua0
Udc /2
u a 0 = u a*0
u a 0 = u a* 0
t
t
-Udc /2
-Udc /2
TPWM
TPWM
Figure 1.7: Sinusoidal modulation at constant or sampled reference voltage for one phase.
Left: Saw-tooth shaped carrier wave. Right: Triangular-shaped carrier wave.
The switch on- and off-times (∆t1 and ∆t2) are calculated according to figure 1.7 by
setting the carrier wave equal to the reference voltage related to the dc bus voltage:
−1+
2
!
TPWM
⇒ ∆t1 =
∆t1 =
TPWM
2
u a* 0
U dc 2
(1.2)

u* 
1 + a 0 
 U 2
dc


∆t 2 = TPWM − ∆t1 =
TPWM
2
(1.3)

u* 
1 − a 0 
 U 2
dc


(1.4)
Applying (1.3)-(1.4) on (1.1) shows the mean value of the output voltage ua0 being
equal to the reference voltage u*a0:
u ao =
1
TPWM
⇒ u ao = u a*0
U dc
2
 TPWM

 2


u*  T
1 + a 0  − PWM
 U 2
2
dc



u* 
1 − a 0  
 U 2 
dc


(1.5)
(1.6)
Apart over-modulation, this modulation technique produces an average voltage
value, equal to the reference voltage within each PWM period. Therefore, the
Voltage-Source PWM Inverter
11
fundamental of the switched pulse pattern equals the corresponding reference
voltage.
The modulation technique using a saw-tooth shaped carrier wave always sets the
output to a high level at the beginning of each PWM period, resulting in
asymmetrical PWM pulses. The pulses of an asymmetric edge-aligned PWM signal
always have the same side aligned with one end of each PWM period. On the
contrary, the pulses of a symmetrical PWM signal, e.g. obtained by using a
triangular-shaped carrier wave, are always symmetric with respect to the center of
each PWM period. The symmetrical PWM is often preferred, since it generates less
current and voltage harmonics [Bose 97], [Dub 89].
The sinusoidal PWM is easy to realize in hardware by using analog integrators and
comparators for the generation of the carrier and switching states [Ter 96]. However,
due to the variation of the reference values during a PWM period, the relation
between reference and carrier wave is not fixed. This introduces subharmonics of the
reference voltage causing undesired low-frequency torque and speed pulsations. In
contrary, software implementation provides sampled data during a PWM period
(uniform/ regular sampling) and hence, the pulse widths are proportional to the
reference at uniformly spaced sampling times. Compared to the analog
implementation, the modulation with uniform sampling has lower low-frequency
harmonics. Since the phase relation between reference and carrier wave is fixed,
even for the asynchronous mode, the subharmonics and the associated frequency
beats are not present [Dub 89].
The ratio of the reference magnitude to that of the carrier wave is called modulation
index m. Considering the mean output voltage equal to the reference phase voltage
(1.6) in the linear range (m ≤ 1), the fundamental component of the line voltage is:
U line
=
U dc
3
3 Uˆ phase
m,
=
2 2
2 U dc
m≤1
(1.7)
The boundary of the sinusoidal modulation is reached at the modulation index m = 1
(figure 1.8). For m > 1, the number of pulses becomes less and the modulation
ceases to be sinusoidal PWM. The modulation is still working, but the output
voltages are no longer sinusoidal: they correspond to the reference values with
limitation to the half dc bus voltage. The fundamental component of the line voltage
then is [Jen 95]:
U line
3 
 1
1
=
m ⋅ arcsin  + 1 −  2
U dc
π 2 
m
m

 ,
 
m>1
(1.8)
12
Chapter 1
0.8
6
π
0.7
[]
0.6
3
/U
dc
0.5
2 2
U
line
0.4
0.3
0.2
0.1
0
0
1
2
3
4
m[]
Figure 1.8: Line voltage (rms) in function of the modulation index.
When m is made sufficiently large, the phase voltage becomes a square wave and the
line voltage becomes a 6-step waveform.
ub*0
U dc 2
*
u
1
-1
u a* 0
U dc 2
ωt
carrier wave
ua0
4 U dc
π 2
−
ua0
fundamental
ωt
U dc
2
u
uab
U dc
U dc
2
U dc
2
−U dc
−
ub0
ωt
Figure 1.9: Strong overmodulation and square-wave shaped output voltage with affiliated fundamental.
Top: Reference voltages (u*a0, u*b0) and carrier wave. Middle: Phase-to-neutral output voltage ua0 and
affiliated fundamental. Bottom: Phase-to-neutral output voltage ub0 and line voltage uab.
The square wave of the phase voltage expressed in Fourier-coefficients is:
ua0 =
4 U dc
π 2
∞
1
∑n 2n − 1 sin[(2n − 1) ωt ]
(1.9)
Using sinusoidal PWM generation, the maximum fundamental phase voltage is
limited by the dc bus voltage:
Voltage-Source PWM Inverter
13
2
Uˆ phase,max = U dc
(1.10)
π
However, this maximum voltage should not be exploited since overmodulation
results in a strong increased spectrum of lower voltage and current harmonics
especially for the 5th, 7th and 11th harmonics. In figure 1.10, the current of an
induction motor (scalar control) in the linear range (m = 1) and at overmodulation
(m = 1,33) is presented to illustrate the involuntary current distortion.
4
m=1
ia [A]
2
0
m = 1,33
-2
-4
0
0.01
0.02
t [s]
0.03
0.04
0.05
Figure 1.10: Measured current at different modulation indexes.
(induction motor in open loop: uref = 200 V sin(ωt); Udc = 400 V and Udc = 300 V resp.)
Basic drawbacks of the sinusoidal PWM are the not ideal use of the dc bus voltage
and the non-existent interaction between the three phases resulting in superfluous
changes of switching states, increasing semiconductor losses and introducing a
higher harmonic content at the motor terminals.
1.3.2.1
Injection of a Third Harmonic
According to (1.9), also multiple of third harmonics are present in the voltage
spectrum. However, the third harmonics are eliminated and not existent in the
current spectrum since the sum of the phase current of a three-phase ac machine
equals zero. As shown in figure 1.11, the range of the sinusoidal PWM can be
increased by adding third harmonics to the reference voltages. The same third
harmonic is added to each of the three reference voltages. Adding third harmonics
agrees with a simultaneous variation of the potential in all phases, thus not
recognized at the terminals of an ac motor with isolated neutral point:
!
u ab = u a 0 − ub 0 =(u a 0 + uthird ) − (ub 0 + uthird )
(1.11)
Therefore, the introduction of a third harmonic does not distort the line voltages
since third harmonic components in the phase voltages are cancelled.
14
Chapter 1
A geometrical calculation yields the maximum possible increase of the linear area
with the harmonic amplitude being 1/6 of the reference voltage amplitude. Such an
injection of a third harmonic results in a 15,5% higher maximum output voltage
without overmodulation. According to [Jen 95], the harmonic content of the
resulting current spectrum of ac motor drives is minimal at injection of a third
harmonic with the amplitude being 1/4 of the reference voltage amplitude, still
increasing the maximum output voltage without overmodulation by 12%.
u*a0
u a*0
U dc 2
reference plus
third harmonic
third harmonic
t
1
t
-1
ua0
carrier wave
U dc
2
−
U dc
2
t
Figure 1.11: Injection of a third harmonic and modulation.
Obviously, also multiple of third harmonics do not disturb the current spectrum and
are suitable injection signals. As can be shown [Jen 95], the subsequently described
space vector modulation is equal to the sinusoidal PWM with injection of a suitable
triangular-shaped signal containing all existing multiple of third harmonics.
1.3.3
Space Vector Modulation (SVM)
Space-vector pulse width modulation has become a popular PWM technique for
three-phase voltage-source inverters in applications such as control of induction and
permanent magnet synchronous motors. The mentioned drawbacks of the sinusoidal
PWM are vastly reduced by this technique. Instead of using a separate modulator for
each of the three phases, the complex reference voltage phasor is processed as a
whole. Therefore, the interaction between the three motor phases is exploited. It has
been shown, that SVM generates less harmonic distortion in both output voltage and
current applied to the phases of an ac motor and provides a more efficient use of the
supply voltage in comparison with direct sinusoidal modulation techniques [Jen 95].
Voltage-Source PWM Inverter
15
As shown in table 1.1, there are eight possible combinations of on and off patterns
for the three upper electronic switches feeding the three-phase power inverter
(figure 1.1). Notice that the on and off states of the lower power switches are
opposite to the upper ones and so completely determined once the states of the upper
power electronic switches are known. The phase voltages corresponding to the eight
combinations of switching patterns can be mapped into the α/β frame through α/βtransformations [Hen 92]. This transformation results in six non-zero voltage vectors
and two zero vectors. The non-zero vectors form the axes of a hexagonal containing
six sectors (S1 − S6) as shown in figure 1.12. The angle between any adjacent two
non-zero vectors is 60 electrical degrees. The zero vectors are at the origin and apply
a zero voltage vector to the motor. The derived α/β voltages in terms of the dc bus
voltage Udc are summarized in table 1.1.
Table 1.1: Switching table and α/β transformation of affiliated state voltage vectors.
α/β-transformation of the states
Switch no.
State
S1
S3
S5
Ux,α
Ux,β
|Ux|
000
OFF
OFF
OFF
0
0
0
100
ON
OFF
OFF
2 U dc 3
0
2 U dc 3
U dc
3
2 U dc 3
U dc
3
2 U dc 3
110
ON
ON
OFF
U dc 3
010
OFF
ON
OFF
− U dc 3
011
OFF
ON
ON
−2 U dc 3
001
OFF
OFF
ON
− U dc 3
− U dc
3
2 U dc 3
101
ON
OFF
ON
U dc 3
− U dc
3
2 U dc 3
111
ON
ON
ON
0
2 U dc 3
0
0
0
Uβ
010
110
S2
S3
S1
Uα
000
111
011
S4
001
S5
S6
100
101
Figure 1.12: Hexagon, formed by the basic space vectors and sector definition (S1 − S6).
Using the transformation of the three phase voltages to the α/β reference frame, the
voltage phasor Uref represents the spatial phasor sum of the three phase voltages.
When the desired output voltages are three-phase sinusoidal voltages with 120°
16
Chapter 1
phase shift, Uref becomes a revolving phasor with the same frequency and a
magnitude equal to the corresponding line-to-line rms voltage.
The objective of the space vector PWM technique is to approximate the reference
voltage phasor Uref by a combination of the eight switching patterns. Practically,
only the two adjacent states (Ux and Ux+60) of the reference voltage phasor and the
zero states should be used [Jen 95] as demonstrated by the example in figure 1.13.
The reference voltage Uref can be approximated by having the inverter in switching
states Ux and Ux+60 for t1 and t2 duration of time respectively.
U ref =
1
TPWM
(t1 U x + t 2 U x+60 )
(1.12)
Of course, the affiliated sector must be known first. The sector identification and the
calculation of t1 and t2 are presented in the next subsection. Since the sum of t1 and t2
should be less than or equal to TPWM, the inverter has to stay in zero state for the rest
of the period. The remaining time t0 is assigned to one or both zero-voltage phasors.
t 0 = TPWM − t1 − t 2
(1.13)
Applying only one of the two zero-voltage states during a PWM period, results in an
asymmetric edge-aligned PWM signal. This is often undesired (higher harmonics)
but reduces the required switching number by 33% since one inverter leg does not
switch during that particular PWM period. Here, the remaining time t0 is equally
assigned to both states. As illustrated in figure 1.13, all state changes are obtained in
each case by switching only one inverter leg.
000
111
000
100 110
110 100
40% ‘100’
ua0
5% ‘000’
50% ‘110’
Uref = U ejωt
ub0
5% ‘111’
uc0
TPWM
Figure 1.13: Example of duty-cycle generation.
As mentioned above, the reference voltage is actually equal to the desired threephase output voltages mapped to the α/β frame. The envelope of the hexagonal
formed by the basic space vectors, as shown in figure 1.12, is the locus of the
maximum output voltage. In order to avoid overmodulation, the magnitude of Uref
must be limited to the shortest radius of this envelope. This gives a maximum rms
value of the line-to-line and phase output voltages of
Voltage-Source PWM Inverter
U line , max =
3
2
17
U
Uˆ phase , max = dc
2
(1.14)
being approximately 15% higher when compared to the original sinusoidal PWM.
1.3.3.1
Real-Time Implementation of the SVM
Presently in industry, the SVM is often applied as inverter control strategy because
of its advantages when compared to other PWM techniques: SVM provides efficient
use of the supply voltage and low harmonic distortion in both output voltage and
current. Furthermore, it can easily be implemented with modern DSP-based control
systems. Even recent developments of the DTC-algorithm are modified in regard to
exploit the advantages of the SVM.
As shown in table 1.1, the reference voltage Uref, usually represented by its α/β
components Uα* and Uβ*, can be approximated easily by a linear combination of the
two adjacent states and the zero states, i.e. no trigonometric functions are required to
calculate the duty cycles. First, the sector must be identified to determine the
appropriate states. This is performed, as illustrated in figure 1.14, by a comparison
of the α/β components specifying the position in the α/β-plane. For instance, if the
reference voltage Uβ* is positive, the sector of the reference voltage is in the upper
half of figure 1.12 (sector S1, S2 or S3). Otherwise, the sector is in the lower half.
Further sector splitting/identification is done by comparison (geometrical
calculation) of the α- and β-components. The applied normalization at the beginning
eliminates the dc bus voltage dependence of the output voltages. The resulting duty
ratios (a*, b* and c*), as required for PWM generation using e.g. TI’s TMSM320P14
DSP, are calculated according to following flowchart. A duty ratio a* = 1 indicates a
continuously closed upper switch of the first inverter leg. At a duty ratio a* = 0, the
turn-on time during each PWM period is equally distributed to the lower and upper
switch and the resulting mean value of the phase voltage ua0 is zero. At a duty ratio
a* = -1, the lower switch is continuously closed, etc.
The relation between the duty cycles of the three phases in percent (relation of the
switch-on to the switch-off times of the three inverter legs within one PWM period)
and the given duty ratios a*, b* and c* is:
 a* + 1
;
duty cycles a ; b; c = 
 2
b* + 1
;
2
c* + 1 
 100 %
2 
(1.15)
Usually, the presented algorithm is easily incorporated into the initialization part of
the real-time program, e.g. by including handwritten C-code. Then, the duty ratios
are directly mapped by a DSP into signals driving the inverter switching logic. As
illustrated in figure 1.14, a final data processing and transmission is required, when
18
Chapter 1
additionally a slave DSP generating the PWM pulses, e.g. TI’s TMSM320P14, is
used. To avoid overflow of the fixed-point slave DSP, all duty ratios must be limited
to ± 1. Since the P14 DSP uses 16-bit compare registers for the PWM generation,
the calculated values are adjusted by the given multiplication before they are finally
transmitted to the slave DSP generating the PWM signals. As illustrated in a
subsequent chapter (e.g. figure 3.2), each two PWM channels are employed to
generate the correct pulses for the inverter.
Voltage
reference
Uα*, Uβ *
3 1
2 U dc
normalization
uβ ≥ 0
*
No
Yes
uα* ≥
1
3
No
u *β
uα* ≥
Sector 1
No
−1
3
Sector 2
Sector 1 & 4:
1 *
a * = uα* +
uβ
3
b * = −uα* +
3
3
u *β
No
No
Sector 3
Sector 4
uα* ≥
1
3
Sector 5
Sector 2 & 5:
c * = −a *
b* =
2
3
u *β
u *β
u *β
Sector 6
c * = −uα* −
15
2 -1
|u| ≤ 1
Overflow
protection
3
b * = −a *
c * = −b*
duty ratios:
(a*; b*; c*)
−1
Sector 3 & 6:
1 *
a * = uα* −
uβ
3
a * = 2 uα*
u *β
uα ≥
P14
DSP
3
3
u *β
PWM 1−6
16 bit
compare
register
Figure 1.14: Flowchart of SVM and data transmission to a TMSM320P14 DSP.
The turn-on times t0, t1 and t2 of the applied switching states during each PWM
period, as introduced in (1.12)-(1.13) for illustration purpose, are not required for
implementation of the SVM. However, they are easily calculated by the duty cycles
of the three phases. For instance, the zero states ‘000’ and ‘111’ are each equal to
the minimum of the duty cycles given in (1.15) multiplied by the PWM period TPWM.
Voltage-Source PWM Inverter
19
1.4 Dead-Time Effect & Voltage Distortion
For voltage-source PWM inverters, a dead-time interval is required to prevent the
“shoot-through” effect of a half-bridge during a change of the switching states. All
semiconductor-switching devices react delayed to the turn-off signals owing to the
storage time. During this storage time, depending on the operating point, the switch
is not able to block the dc link voltage. Therefore, to avoid a short circuit of the halfbridge, a dead-time interval must be introduced between the turn-off signal of a
switch and the turn-on signal controlling the opposite switch. The dead time τdead is
usually constant and determined as the maximum value of storage time τst plus an
additional safety margin. The dead times of common IGBT-inverters used in
industry vary between τdead ≈ 1-5 µs.
Although the dead time is short, it causes deviations from the desired fundamental
inverter output voltage. The effects of the dead time on the output voltage will be
described from one half-bridge of the PWM inverter according to figure 1.15. The
basic configuration consists of upper and lower power devices T1 and T4, and
reverse recovery diodes D1 and D4.
T4 off
T1 on
½ Udc
T1
C/2
D1
½ Udc
T1
C/2
D1
ia < 0
ia > 0
½ Udc
ua0
C/2
T4
½ Udc
D4
ua0
C/2
T4
D4
T4 on
T1 off
Ideal gating
pulse pattern
T1
T4
pulse pattern
with dead time
T1
T4
T1
T4
pulse pattern
with dead time
T1
T4
UT1
τdead
τdead fPWM Udc
½ Udc
UD1
ua0
τdead fPWM Udc
ua0
½ Udc
τdead
Ideal gating
pulse pattern
-½ Udc
-½ Udc
UD4
UT4
Figure 1.15: Error voltage due to the dead-time effect.
Left: Positive load current. Right: Negative load current.
Considering the no-load case, the storage time of the semiconductors is very small
when compared to the dead time: Switching off a power device, the current
20
Chapter 1
commutates directly to the diodes. This condition results in the desired voltage,
which is applied to the motor terminals. In contrast to this, switching on a power
device is delayed by the dead time. During the dead-time interval, the diode
continues conducting until the dead time elapses and the opposite power device is
switched on. This condition results in a loss of voltage at the motor terminals
indicated by the gray marked area in figure 1.15. With a positive current, the duty
cycles are shorter and with negative currents longer than required. Hence, the actual
duty cycle of a bridge is always different from the one of the reference voltage. It is
either increased or decreased, depending on the load current polarity. Furthermore,
the voltage drops of the power switches UT, respectively the voltage drop of the
reverse recovery diode UD, are considered. Summarizing, the voltage distortion can
be described by an error voltage ∆U
∆U ≈
UT + U D
+ τ dead ⋅ f PWM ⋅ U dc
2
(1.16)
depending on the dead time τdead, the dc bus voltage Udc, the PWM frequency fPWM
and the voltage drops UD and UT of IGBT and diode [Bose 97]. This error voltage
and the resistances RT and RD of the switch changes the inverter output voltage ua0
from its intended value uref to:
u a 0 ≈ u ref − i ⋅
RT + RD
− ∆U ⋅ sign(i ) ,
2
(1.17)
The dead time reduces the effective turn-on time and produces the undesired fifthand seventh-order harmonics in the inverter output voltage [Dod 90]. Furthermore, it
generates sub-harmonics, resulting in torque pulsation and possible instability at
low-speed and light-load operation [Leg 97], [Mur 92]. The resulting speed
oscillation and the voltage distortion are illustrated in figure 1.16 showing the deadtime effect on a 1,5 kW induction motor drive in open loop (scalar) control at low
speed and light-load operation. Considering the given drive setup (τdead = 2,5 µs;
fPWM = 10 kHz) and according to (1.16), the error voltage amounts to ∆U = 12,5 V
(equal to 15,3 V in the alpha/beta reference frame). A reduction of the average
voltages occurs according to (1.17) when one of the phase currents changes its sign.
The motor currents have the tendency to maintain their values after a zero crossing.
In generator mode, the behavior of the motor current is contrary resulting in a
steeper rise of the current after zero crossing. In any case, the motor torque is
influenced as it can be observed by speed oscillations at six times of the fundamental
frequency.
The dead-time problem is more serious in high-power gate-turn-off thyristor (GTO)
inverter systems than in the case of IGBT or MOSFET inverters, since the GTO
requires a longer dead time. However, the use of fast switching devices using high
carrier frequencies (5-20 kHz) with lower dead-time values (1-5 µs), will not free
the system of the described distortion. Higher PWM frequencies improve the
Voltage-Source PWM Inverter
21
waveform quality by raising the order of theoretical harmonics, but low frequency
sub-harmonics persist due to the dead time. Furthermore, to avoid unnecessary
switching losses and short-term overheating of a switching device, minimum time
duration in the switching states must be forced. If the commanded voltage value is
less than the required minimum, the affiliated switching state must be either
extended in time or skipped. This causes additional distortion of the inverter output
voltages. Therefore, a compromise must be made by choosing a suitable PWM
frequency: a high PWM frequency improves the theoretical quality of the waveform,
but may increase simultaneously the voltage distortion due to the dead-time effect.
4
60
55
n [rpm]
0
α
I [A]
2
-2
-4
50
45
40
0
0.25
0.5
0.75
35
1
0
0.25
0.5
0.75
1
t [s]
40
20
20
U [V]
40
uref
uβ (uα)
0
β
0
α
U [V]
t [s]
uα
-20
-40
-20
uref
0
0.25
0.5
0.75
1
t [s]
-40
-40
-20
0
20
40
U [V]
α
Figure 1.16: Open-loop control of an induction motor & dead-time effect (Udc =500 V, no load).
Left: Measured current Iα, measured voltage Uα and reference voltage Uref.
Right: Measured/reference speed and voltage trajectories.
1.4.1
Dead-Time Compensation
Remarkable efforts have been made to compensate the voltage distortion due to the
dead-time effect [Choi 96], [Leg 97], [Sep 94]. Most dead-time compensation
methods are based on an average value theory: the lost voltage is averaged over an
operating cycle and added vectorially to the command voltage [Mur 87], [Jeo 91].
Dead-time compensation can be implemented in hardware or software.
The hardware compensator operates by closed loop control [Mur 87]. Previous
commutation times are measured and used to control the next duty cycles. However,
a potential-free measurement of the inverter output voltages is required. Software
compensators are mostly designed in feed-forward mode. Depending on the sign of
the respective phase current, a fixed time delay is either added to or subtracted from
the command voltage.
22
Chapter 1
However, a complete compensation of the dead-time effect may not be achieved
since the actual storage delay is not exactly known. Furthermore, the PWM
generation is a part of a superimposed high-bandwidth current control loop
compensating the involuntary torque/speed distortions to a certain extent. This may
eliminate the need for a separate dead-time compensator. Figure 1.17 illustrates the
dead-time effect on an induction motor drive in field-oriented speed control mode at
low speed and light-load operation. Except the control mode, the conditions are the
same as in figure 1.16.
4
60
55
n [rpm]
0
α
I [A]
2
-2
-4
50
45
40
0
0.25
0.5
0.75
35
1
0
0.25
20
20
U [V ]
40
0
0.75
1
uref
uβ (uα)
0
β
uα
-20
-40
0.5
t [s]
40
α
U [V ]
t [s]
-20
uref
0
0.25
0.5
t [s]
0.75
1
-40
-40
-20
0
20
40
U [V ]
α
Figure 1.17: Field-oriented control of an induction motor & dead-time effect (Udc =500 V, no load).
Left: Measured current Iα, measured voltage Uα and reference voltage Uref.
Right: Measured/reference speed and voltage trajectories.
The influence of the dead time on the current/torque is vastly reduced by the speed
and current control loop. Of course, the falsification of the motor terminal voltages
is the same, but the harmonic distortion of the fundamental voltage is transmitted to
the reference voltages. Due to the arguable compensation by the current controller,
common industrial drives are not always equipped with an additional dead-time
compensation.
Note, that permanent magnet synchronous motor drives behave more sensitive to the
dead-time effect than induction motor drives: Due to the absence of a magnetizing
component in the stator current and the low main reactance, they tend to operate
partly in discontinuous current mode at light load. These machines require an
advanced compensation scheme when applied to high-performance motion control
systems or, alternatively, an additional d-axis current to bridge the discontinuous
current time intervals [Bose 97].
Voltage-Source PWM Inverter
1.4.2
23
Dead-Time Generation
The switching transitions of real switches, especially the transition from current
conducting to voltage blocking, are not infinitely fast. After conducting, a finite time
is required, mainly to remove the space charge, before a semiconductor switch is
able to block the supply voltage. Switching off a power device, the current
commutates to the opposite recovery diode (constant current direction) and the
power switch starts to block the dc voltage. If a switch of one inverter leg is turned
on before the opposite switch blocks the dc bus voltage, the whole dc bus voltage is
shorten across this leg (figure 1.1) resulting in a very high short-circuit current only
limited by the resistances of the power switches. Obviously, such a high short-circuit
current may destroy the power switches as well as the drive system and the dc link
capacitor.
To avoid such short-circuit conditions, a dead-time interval is added between the
turn-off signal of a switch and the turn-on signal controlling the opposite switch.
Dead time control prevents any cross-conduction or shoot-through current from
flowing through the main power switches during switching transitions by controlling
the turn-on times of the semiconductor drivers. The high-side driver is not allowed
to turn on until the voltage at the junction of the opposite power switch is low and
vice versa. During the dead-time interval, recovery diodes continue conducting until
the dead time elapses and the opposite power device is switched on.
In modern DSP systems, the dead time generation is usually programmable, e.g.
added as extra time in a compare register/timer. Considering analog circuits, the
fixed dead-time generation of one half-bridge is easily generated by a RC-circuit
coupled to two optocouplers, each controlling the opposite switches of one inverter
half-bridge as described in figure 1.18. Additionally, such a hardware realization
takes care for galvanic isolation of the digital control system and the power
electronics. The resistance R is calculated by the resistance voltage drop divided by
the operating current of the optocoupler IP:
R=
Us −Ud
IP
(1.18)
According to figure 1.18, changing the switching signal Us from a positive to a
negative voltage (e.g.: Us = ±12V) results in a discharging of the capacitor
depending on the photodiode operating voltage (Ud ≈ 1V if i > 0). While the
photodiode P1 directly blocks, the dead-time τdead passes before the capacitor
voltage equals the voltage -Ud, equal to the on state of photodiode P2 driving the
opposite switch of the inverter leg:
 −τ dead

!
U c (t = τ dead ) = (U s + U d )  e R C − 1 + U d =− U d




(1.19)
24
Chapter 1
Thus, a minimum capacitor value is required to guarantee the dead-time interval
τdead:
⇒ C≥
τ dead

2 Ud
R ln1 −
 Us + Ud
(1.20)



Switching logic
US
Optocoupler 1
IP1
t
-Us
UC
UC
-Ud
UC
C
PWM logic:
US = ±12V
IP2
Optocoupler 2
R
t
-Ud
IP
IP1
IP2
τdead
IP1
τdead
t
Figure 1.18: Analog dead-time generation. Left: Exemplary hardware circuit for one inverter leg.
Right: Switching logic, voltage and affiliated current of an optocoupler driving the power switch.
1.5 PWM Inverter Drives and Motor Insulation
Variable speed ac drives are used in ever-increasing numbers because of their wellknown benefits for energy efficiency and for flexible control of processes and
machinery using low-cost readily available maintenance-free ac motors. While the
connection of a motor to an inverter supply is straightforward, some basic
considerations are necessary to ensure trouble free long-term operation. Insulation
performance is one of the considerations required in engineering variable speed
drive solutions. Following summary provides basic information to enable the correct
matching of low voltage ac motors and PWM inverters with respect to motor
insulation:
Motor winding insulation experiences higher voltage stresses when used
with an inverter than when connected directly to the ac mains supply.
The higher stresses are dependent on the motor cable length and are caused
by the fast rising voltage pulses of the drive and transmission line effects in
the cable.
For supply voltages less than 500V ac, most standard motors are immune to
these higher stresses.
Voltage-Source PWM Inverter
25
For supply voltages over 500V ac, a motor with an enhanced winding
insulation system is required. Alternatively, additional components can be
added to limit the voltage stresses to acceptable levels.
Where the drive spends a large part of its operating time in braking mode,
the effect is similar to increasing the supply voltage by up to 20%.
For drives with PWM active front ends (regenerative and/or unity power
factor), the effective supply voltage is increased by around 15%.
1.6 Conclusions
Controlled power supply for electric drives is obtained usually by converting the
mains ac supply. A typical converter consists of power electronic circuits,
employing switching devices such as thyristors, transistors, GTOs, MOSFETSs,
IGBTs and diodes as well as a host of associated control and interfacing circuits.
The conversion process allows fast control of voltage, current or power to the motor
via the gate circuits of the converter switches. In this way, the required dynamic
response requirements of high-performance ac motor drives can be met.
This chapter provides a detailed survey of voltage-source PWM inverter drives with
emphasis on the modulators and control methods. The most common three-phase
inverter topology is that of a switch mode voltage source inverter. VS-inverters
consist of two main sections, a controller to set the operating frequency and a threephase inverter to generate the required sinusoidal three-phase voltage from a dc bus
voltage.
The basic concepts of pulse width modulation are illustrated. PWM is the process of
modifying the width of the pulses in a pulse train in direct proportion to a small
control signal. The greater the control voltage, the wider the resulting pulses
become. By using a sinusoid of the desired frequency as control voltage for a PWM
circuit, it is possible to produce a high-power waveform whose average voltage
varies sinusoidally in a manner suitable for driving ac motors. Due to the significant
flexibility in controlling the inverter switches, a large number of switching
algorithms were introduced and some of these have gained wide acceptance and are
fully developed.
Usually, the behavior of the power devices together with the reverse recovery diode
is described by ideal two-position switches. In practice, a dead-time interval is
required to prevent the “shoot-through” effect of a half-bridge during a change of the
switching states. Although the dead time is short, it causes deviations from the
desired fundamental inverter output voltage. Issues of the resulting phase voltage
distortion due to the inverter non-linearity as well as compensation methods are
discussed in detail.
台灣新竹交通大學前瞻電力電子中心808實驗室 (Power Electronics Systems and Chips Design Lab)
電力電子系統與晶片、開關電源、綠色能源、數位電源、馬達驅動、伺服控制
[References] Space Vector PWM and Carrier-Based PWM
Slides
[1]
[2]
Chapter 8 Switch-Mode DC-AC Inverters: DC  Sinusoidal AC, Power Electronics:
Converters, Applications and Design, N. Mohan, T. M. Undeland, and W. P. Robbins,
John Wiley & Sons, 3rd Ed., 2002.
Power Electronics Chapter 6 PWM Techniques, Course Note.
Introduction
[3]
Chapter 14 Power Inverters of Power Electronics: Devices, Drivers, Applications,
and Passive Components, by B. W. Williams, Mcgraw-Hill; 2 Sub Ed., September
1992.
[4] Gerd Terorde, Chapter 1: Voltage Source PWM Inverter, Electric Drives and Control
Techniques, 2004.
[5] Chapter 5 Inverters of The Power Electronics Handbook, by Timothy L. Skvarenina,
CRC Press, 1 Ed., November 20, 2001.
[6] Chapter 2 Pulse-Width Modulation (Jian Sun) of Dynamics and Control of Switched
Electronic Systems - Advanced Perspectives for Modeling, Simulation and
Control of Power Converters, Vasca, Francesco; Iannelli, Luigi (Eds.), Springer,
2012.
[7] “Chapter 2 Inverter control with space vector modulation” of Vector Control of ThreePhase AC Machines - System Development in the Practice, N. P. Quang and J.-A.
Dittrich, Springer, 2008.
[8] Chapter 4: PWM Techniques for Three-Phase Voltage Source Converters of Control in
Power Electronics: Selected Problems, Marian P. Kazmierkowski, Ramu Krishnan,
Frede Blaabjerg – 2002.
[9] Dorin O. Neacsu, "Space Vector Modulation – An Introduction," IEEE IECON Tutorial,
2001.
[10] J. Holtz, "Pulsewidth modulation for electronic power conversion," Proc. of IEEE, vol.
82, no. 8, pp. 1194-1214, Aug. 1994.