2⊕
國立中山大學電機工程學系研究所
碩士論文
Department of Electrical Engineering
National Sun Yat-Sen University
Master Thesis
自動增益控制器、高壓積體電路、底板收發器之研製
Study and Implementation of Automatic Gain Control, High
Voltage Integrated Circuits, and Backplane Transceiver
研究生︰楊上賢
Shang-Hsien Yang
指導教授︰王朝欽 博士
Dr. Chua-Chin Wang
中華民國 100 年 6 月
June 2011
To my parents.
Acknowledgement
I knew that life would be different ever since the first day I entered this university.
Little did I know, however, how much help and assistance I would receive. Thus,
through this acknowledgement, I wish to express my gratitude toward the people and
organizations that helped me through these years.
First of all, I would like to express my special thanks and appreciations to my
advisor, Prof. Chua-Chin Wang (王朝欽). In the past three years, he has shown me
everything from aligning figures to arranging international conferences. Under his
guidance, I was given the opportunity and latitude to conduct my research on numerous
challenging and exciting topics, and I am also heavily in debt to him of the time he
spent refining my manuscripts. Furthermore, much more appreciation and respect goes
to him for what he has done for the department of electrical engineering as the
Head-of-Department. Thanks to his endless efforts, both our laboratory and the
department of electrical engineering are running in pristine order.
I must acknowledge the members of the oral defense committee, Prof. M.-D. Ker
(柯明道), Prof. C.-L. Wei (魏嘉玲), and Prof. K.-C. Kuo (郭可驥) for the advices they
offered to my work.
I would also like to pay my deepest gratitude to Prof. C.-T. Kuo (郭啟東), the
Head-of-Department of the department of physics. Without his considerate and timely
help, my academic journey would have terminated prematurely and mentioning
anything else would have been meaningless. An equal amount of appreciation goes to
Dr. J. Liu (劉傑), from whom I learned fundamental skills of analyzing and designing
analog circuits. The knowledge of everything I wrote in this thesis all began in the small
classroom where he taught tirelessly with chalk and his old microphones.
i
In addition, I must as well thank Prof. J.-C. Chiu (邱日清), Prof. S.-R Kuang (鄺獻
榮), Prof. C.-H. Tsai (蔡建泓), Prof. C.-L. Wei (魏嘉玲), Prof. R. Rieger, Prof. C.-N.
Lu (盧展南), Prof. S.-H. Yu (余祥華) and Prof. C.-I. Lee (李杰穎) for the efforts they
put into the courses they offered to me. The knowledge and insights I obtained through
these courses have been marvelous, and I believe that they will be invaluable to me in
the future. It is also an honor to receive timely advices from Prof. K. S.-M. Li (李淑敏),
Prof. K.-C. Kuo (郭可驥), Prof. X.-X. Moo (莫清賢), and Prof. P. T.-J. Liang (梁從主).
Furthermore, I also have to mention the help I receive from the members of the
VLSI laboratory, including Prof. T.-J. Lee (李宗哲), Dr. (to be) C.-H. Hsu (許家豪),
C.-L. Chen (陳致霖), R.-C. Kuo (郭容齊), D. S.-B. Tseng (曾紹賓), Y.-R. Lin (林晏如),
H.-H. Hou (侯筱涵), H. D.-H Yeh (葉岱灝), Y.-D. Tsai(蔡岳達), W. Luo(羅時偉),
W.-C. Hsiao (蕭瑋志), Y.-C. Chen (陳韻琦), W. Yuan (曾信遠), S.-Z. Lin (林聖智),
Mevis Hsieh(謝依潔), J.-J. Li (李傑俊), Y.-H. Wu (吳益宏), D.-S. Wang (王登賢), Y.
Hu (胡毅), F.-J. Schao (趙芳頡), C. Chuang (莊凱涵), S.-F. Huang (黃淑芬), S. Shen
(沈子敬), and other past members including but not limited to J.-W. Liu (劉人瑋), J.-Y.
Ruan (阮俊穎), J. Chen (陳柏誠), C.-L. Wang (王清霖), and S.-F. Yen (顏韶甫).
Without their guidance and assistance, the research I conducted through the past few
years would have been so much harder.
The Chip Implementation Center (CIC) has allowed me to research on integrated
circuit design. I have to thank them and several remarkable individuals, namely, H.-H.
Tsai, Y.-D. Hsieh, and C.-L. Fang for their support. Last but not least, the past
contributors to the conferences, journals, and transactions of IEEE have laid the
foundations of my research. I thank them all.
Shang-Hsien Yang
ii
摘要
托 CMOS 積體電路技術進步之福，許多傳統上由 BJT 類比製程的電路，逐漸
的被整合到 CMOS 電路製程裡。截至目前為止，將數位、類比、甚至高壓元件通
通整合至一單晶片(System-on-a-Chip，SoC)之技術已逐漸成熟。為了迎接新技術所
帶來的新挑戰，本論文將專注在三個重要的議題上加以討論、設計、與實作，並
希望提供能夠重複使用之設計方法。
本論文第一個主題探討自動增益控制器之理論與實作。在電路實現的部分，
包含了一分貝線性可變增益放大器、高輸入輸出擺幅之可變增益放大器、雙偵測
單儲存峰值偵測器、前授輸出擺幅自動增益控制器、與可程式化增益放大器。
第二個主題探討高壓製程電路的研製。本主題涵蓋了將低電壓類比訊號轉成
高電壓高擺幅訊號之運算放大器與一串聯式電池充電電路。另外，關於高壓製程
之相關特性，在本論文裡一併加以討論。
最後一個主題專注於底板收發器之設計，包含了一預加重發送器與判斷回授
平等化接受器之電路實作。發送器電路之傳送速度可高達每秒 500 Mbps，接收器
之接收速度則約 125 Mbps。
關鍵詞︰自動增益控制器、可變增益法大器、高壓製程、充電電路、運算轉導放
大器、底板收發器
iii
Abstract
Thanks to the advance in CMOS technology, an extensive category of applications
has been migrated from traditional BJT-based processes. System-on-a-Chip (SoC)
realization of digital, analog, and even high voltage devices is now a reality. To address
the challenge imposed by integrating analog and high voltage devices in standard
CMOS processes, this thesis aims at the design of three specific topics in particular.
With regard to the contents of the thesis, first of all, the theory of linear-in-dB
automatic gain control (AGC) is discussed. In succession, a linear-in-dB variable gain
amplifier (VGA) is mentioned. The implementation of a Feed-forward Output Swing
Prediction AGC featuring a Prediction Parallel-Detect Single-Store Peak Detector
(PDSSPD) and a High Input/Output Swing VGA is also described. Furthermore, a
digitally programmable gain amplifier for a ZigBee wireless receiver is also mentioned.
In response to the advent of CMOS-compatible high voltage tolerant
Bipolar-CMOS-DMOS (BCD) process, an operational amplifier for level converting
operation is disclosed. A 60-V Li-ion battery charger has also been proposed, along with
a novel battery charge mode, namely, the incremental charge (IC) mode. Practical issues
regarding the high voltage tolerant BCD process is also briefly discussed.
Finally, a backplane transmitter featuring pre-emphasis and a receiver utilizing
decisive feedback equalization (DFE) designed for CIC MorPack technology are
presented. When packaged in a Leadless Ceramic Carrier (LCC) package, the
transmitter can transmit up to 500 Mbps and the receiver can receive up to 125 Mbps,
both through DuPont connectors without impedance matching.
Keywords: AGC, VGA, PDSSPD, Charger, BCD, OTA, DFE, pre-emphasis
iv
Contents
Acknowledgement ........................................................................................ i
摘要 (Mandarin Abstract) ........................................................................ iii
Abstract ..................................................................................................... iv
Contents ...................................................................................................... v
List of Figures ............................................................................................. ix
List of Tables............................................................................................. xiv
Chapter 1: INTRODUCTION ................................................................... 1
1.1 Motivation ............................................................................................................. 1
1.2 Overview ............................................................................................................... 3
1.2.1
Automatic gain control circuits ............................................................................... 3
1.2.2
High voltage integrated circuits............................................................................... 4
1.2.3
Backplane transceivers ............................................................................................ 5
1.3 Prior Arts ............................................................................................................... 6
1.3.1
AGC, VGA, and PGA ............................................................................................. 6
1.3.2
High voltage designs using LDMOS ....................................................................... 8
1.3.3
Charger operation .................................................................................................. 10
1.3.4
Transceiver systems ............................................................................................... 15
v
1.4 Overview of the Thesis ....................................................................................... 18
Chapter 2: AGC ....................................................................................................... 21
2.1 Constant Settling Time AGC ............................................................................... 21
2.2 A Linear-in-dB VGA ........................................................................................... 24
2.2.1
Approximation of exponential gain characteristics ............................................... 24
2.2.2
VGA circuit with exponential gain characteristics ................................................ 28
2.2.3
Measurement results of the VGA .......................................................................... 33
2.3 An AGC with FROST and PDSSPD ................................................................... 39
2.3.1
Low power implementation of an AGC ................................................................ 39
2.3.2
Feed-forward output swing prediction (FROST) .................................................. 40
2.2.3
Parallel-detect single-store peak detector (PDSSPD) ............................................ 41
2.3.4
Proposed VGA....................................................................................................... 46
2.3.3
Implementation Results ......................................................................................... 47
2.4 1-dB Gain Step PGA ........................................................................................... 53
2.4.1
Implementation of a ZigBee receiver .................................................................... 53
2.4.2
Operational amplifier............................................................................................. 54
2.4.3
Multiple feedback filter ......................................................................................... 55
2.3.4
Design of a programmable gain amplifier ............................................................. 57
2.5 Summary ............................................................................................................. 63
vi
Chapter 3: HV IC DESIGN ..................................................................... 65
3.1 High Voltage IC Design Overview ..................................................................... 65
3.3.1
0.25 μm BCD 60 V process overview ................................................................... 65
3.3.2
Voltage signal conversion ..................................................................................... 67
3.2 DIFC Amplifier ................................................................................................... 69
3.2.1
Small-signal design ............................................................................................... 69
3.2.2
Circuit level design ................................................................................................ 73
3.2.3
Simulation of a DIFC amplifier ............................................................................. 76
3.3 60 V Charger Design ........................................................................................... 79
3.3.1
Charger architecture .............................................................................................. 79
3.3.2
Embodiment of the proposed charging solution .................................................... 80
3.3.3
IC, CC, and CV charge modes .............................................................................. 81
3.3.4
CV loop and diode-based CC clamp ..................................................................... 83
3.3.5
CV loop and diode-connected load as CC clamp .................................................. 80
3.3.6
Incremental current loop........................................................................................ 88
3.3.7
Over-temperature protection ................................................................................. 92
3.3.8
Antenna effect protection PAD ............................................................................. 94
3.3.9
Implementation ...................................................................................................... 96
3.4 Summary ........................................................................................................... 101
vii
Chapter 4: MORPACK TRANSCEIVERS .......................................... 102
4.1 Fundamentals of Backplane transceivers .......................................................... 102
4.1.1
Uni-polar/differential signaling at high frequency .............................................. 102
4.1.2
Skin effect............................................................................................................ 106
4.1.3
Eye diagram and inter-symbol interferences ....................................................... 108
4.2 CIC MorPack Transmitter Design .................................................................... 110
4.2.1
Pre-emphasis ....................................................................................................... 110
4.2.2
A transmitter with pre-emphasis.......................................................................... 111
4.2.3
Simulation of the transmitter with pre-emphasis ................................................. 115
4.2.4
Measurement of the transmitter with pre-emphasis ............................................ 116
4.3 CIC MorPack Receiver Design ......................................................................... 118
4.3.1
Decision feedback equalizer ................................................................................ 118
4.2.2
A DFE receiver .................................................................................................... 120
4.2.3
Simulation of the DFE receiver ........................................................................... 123
4.2.4
Measurement of the DFE receiver ....................................................................... 123
4.4 Summary ........................................................................................................... 119
Chapter 5: CONCLUSION AND FUTURE WORKS ........................ 126
References ................................................................................................ 129
viii
List of Figures
Fig. 1.1.100 A SoC example. ........................................................................................ 1
Fig. 1.2.100 An AGC model. ........................................................................................ 3
Fig. 1.3.100 A variable tranconductor and a variable load. .......................................... 7
Fig. 1.3.200 A tranconductor and a switchable load .................................................... 7
Fig. 1.3.300 An OPA with switchable feedback........................................................... 7
Fig. 1.3.400 A BSBR DC/DC converter ....................................................................... 9
Fig. 1.3.500 A PWM controller using FRT ................................................................ 10
Fig. 1.3.700 Charging with fixed and variable voltage supply ................................... 13
Fig. 1.3.800 Charging with fixed and variable voltage supply ................................... 14
Fig. 1.3.900 A pre-emphasis transmitter..................................................................... 15
Fig. 1.3.10 0A pre-emphasis transmitter..................................................................... 16
Fig. 1.3.11 0Decision feedback equalization .............................................................. 17
Fig. 1.3.12 0A 1st order DFE ...................................................................................... 18
Fig. 1.3.13 0DFE loop unrolling ................................................................................. 18
Fig. 1.4.100 Thesis structure ....................................................................................... 19
Fig. 2.1.100 Model of the generalized AGC circuit. .................................................. 21
Fig. 2.2.100 Approximation of the exponential function ........................................... 25
ix
Fig. 2.2.200 The block diagram of the proposed VGA .............................................. 29
Fig. 2.2.300 IC 1 and IC 2 current generator ............................................................ 29
Fig. 2.2.400 The half circuit ....................................................................................... 30
Fig. 2.2.500 The main VGA ....................................................................................... 31
Fig. 2.2.600 The measurement setup for the proposed VGA ..................................... 33
Fig. 2.2.700 The measured Bode plot ......................................................................... 34
Fig. 2.2.800 The simulated Bode plot ......................................................................... 34
Fig. 2.2.900 Measured gain with respect to Vcontrol ..................................................... 37
Fig. 2.2.10 0Simulated gain, gm, and ro with respect to Vcontrol ................................... 38
Fig. 2.3.100 The proposed AGC ................................................................................. 40
Fig. 2.3.200 A conventional peak detector ................................................................. 42
Fig. 2.3.300 The proposed PDSSPD........................................................................... 42
Fig. 2.3.400 Response of PD1, PD2, and the PDSSPD .............................................. 44
Fig. 2.3.500 Response of PD1, PD2, and the PDSSPD .............................................. 45
Fig. 2.3.600 The proposed VGA................................................................................. 46
Fig. 2.3.700 Input voltage vs. variation of voltage across sources of M1 and M2 ...... 47
Fig. 2.3.800 The input signal vs. the output signal of the AGC. ................................ 48
Fig. 2.3.900 Gain control voltage vs. gain (in dB) ..................................................... 49
Fig. 2.3.100 Bode plot ................................................................................................ 49
x
Fig. 2.3.11 0The DFT of VGA output at gains of 0 dB, 12 dB, and 20 dB ................ 50
Fig. 2.3.12 0Noise performance of the VGA working at 0 dB, 12 dB, and 26 dB ..... 51
Fig. 2.4.100 A ZigBee receiver................................................................................... 53
Fig. 2.4.200 A rail-to-tail operational amplifier ......................................................... 54
Fig. 2.4.300 An active multiple feedback filter .......................................................... 55
Fig. 2.4.400 A programmable gain differential to single amplifier ............................ 57
Fig. 2.4.500 A non-inverting programmable gain amplifier....................................... 58
Fig. 2.4.600 Output buffer. ......................................................................................... 59
Fig. 2.4.700 The simulated Bode plot. ........................................................................ 59
Fig. 2.4.800 The simulated differential output of a mixer. ......................................... 60
Fig. 2.4.900 The simulated signal after filtering and amplification............................ 60
Fig. 3.1.100 The maximum voltages of N-type and P-type LDMOS allowed ........... 65
Fig. 3.1.200 A layout floor plan for devices with different voltage tolerant abilities 65
Fig. 3.1.300 A SoC with 2.5 V, 5 V circuits, and high voltage devices ..................... 67
Fig. 3.2.100 The proposed DIFC topology ................................................................. 69
Fig. 3.2.200 Schematic of the DIFC amplifier ........................................................... 73
Fig. 3.2.300 The slew rate with and without feed-forward stage ............................... 76
Fig. 3.2.400 The Bode plot of proposed operational amplifier................................... 77
Fig. 3.2.500 DFT of a 10 mHz sine wave output with a 50 V voltage swing............. 78
xi
Fig. 3.3.100 Bulk charger, small chargers, and combination of both ......................... 79
Fig. 3.3.200 Architecture of the battery charger ......................................................... 80
Fig. 3.3.300 Regulation of the difference between VDD-var and Vbat ........................... 81
Fig. 3.3.400 Current vs. voltage for chargers with TC and IC mode.......................... 82
Fig. 3.3.500 The aftermath of inductive kickback ...................................................... 83
Fig. 3.3.600 Relationship between Ihvcs and Rcvs. ........................................................ 86
Fig. 3.3.700 Relationship between Ihvcs and temperature ............................................ 87
Fig. 3.3.800 IC controller augmented to CC/CV loops .............................................. 89
Fig. 3.3.900 V-to-I converter ...................................................................................... 90
Fig. 3.3.100 BGR with over-temperature protection .................................................. 93
Fig. 3.3.110 Hysteresis comparator ............................................................................ 93
Fig. 3.3.120 Antenna effect protection PAD .............................................................. 95
Fig. 3.3.13 0Measured and simulated charging current .............................................. 99
Fig. 3.3.14 0Measured and simulated charging efficiency ....................................... 100
Fig. 4.1.100 Electromagnetic behavior of wire channels.......................................... 103
Fig. 4.1.200 Uni-polar and differential signaling wire channels .............................. 103
Fig. 4.1.300 NEXT and FEXT interactions of TX and RX ...................................... 105
Fig. 4.1.400 Transient characteristics ....................................................................... 105
Fig. 4.1.500 Definitions of the eye diagram ............................................................. 109
xii
Fig. 4.1.600 Inter-symbol interferences .................................................................... 109
Fig. 4.2.100 Comparisons of waveforms with and without pre-emphasis ............... 111
Fig. 4.2.200 A transmitter with pre-emphasis .......................................................... 112
Fig. 4.2.300 A 4 × 8 latch array ................................................................................ 113
Fig. 4.2.400 A true single phase clock latch ............................................................. 113
Fig. 4.2.500 A true single phase clock D flip-flop ................................................... 114
Fig. 4.2.600 Unit delays and gate drivers ................................................................. 114
Fig. 4.2.700 Simulation of the received waveforms ................................................. 115
Fig. 4.2.800 Measurement environment for the transceiver ..................................... 116
Fig. 4.2.900 Measurement of the transmitter, at a data rate of 500 MB/s ................ 117
Fig. 4.2.100 Measurement of the transmitter, at a data rate of 1 GB/s ..................... 117
Fig. 4.3.100 Structure of a DFE receiver .................................................................. 118
Fig. 4.3.200 A DFE receiver ..................................................................................... 120
Fig. 4.3.300 CSN A/CSN B ...................................................................................... 120
Fig. 4.3.400 A signal slicer ....................................................................................... 121
Fig. 4.3.500 A hysteresis comparator ....................................................................... 121
Fig. 4.3.600 An ISI-deteriorated difference signal and the recovered output........... 123
Fig. 4.3.700 Measurement of the DFE receiver ........................................................ 124
xiii
List of Tables
Table 2.2.100 Comparison with Prior Works ............................................................. 37
Table 2.3.100 Comparison with Prior Works ............................................................. 52
Table 2.4.100 Comparison with Prior Works ............................................................. 61
Table 2.4.200 Overall Performance ............................................................................ 62
Table 3.2.100 System Parameters ............................................................................... 72
Table 3.2.200 Device Parameters ............................................................................... 75
Table 3.2.300 System Specification ........................................................................... 78
Table 3.3.100 Chargers Comparison .......................................................................... 98
xiv
CHAPTER 1: INTRODUCTION
1.1
Motivation
Fig. 1.1.1 A SoC example†.
Ever since the advent of integrated circuit technology since the early 1970s, the
number of transistors that can be placed inexpensively on an integrated circuit doubles
approximately every two years, as predicted by the Moore’s Law [1]. As more discrete
signal processing algorithms and digital control methodology have been made feasible
with Very-Large Scale Integration (VLSI), many experts in the 1980s predicted the
demise of analog integrated circuits [2]. Nevertheless, this prediction is only verified to
be partially true nowadays. Although the semiconductor industry is now generally
driven by the digital process dedicated to the utilization of standard CMOS process cell
libraries, the interfacing with analog signals is an still an indispensable part for most
circuits and systems. Hence, the roles of analog circuits remain irreplaceable in a
mixed-signal System-on-Chip (SoC) system such as an example shown in Fig.1.1.1.
†
Courtesy Shao-Bin Tseng et. al. [3]
1
Since analog circuits fabricated using bipolar processes often provide better
performance than their CMOS counterparts, analog circuits designed before the 1980s
were seldom realized using CMOS technologies [4]. However, since analog circuits are
now required to be implemented on the same chip as a part of a larger digital circuit, it
is now very clear that standard digital CMOS process should become the technological
choice for the design of high quality analog circuits in a mixed-signal environment [5].
These analog circuits are operating with much lower supply voltage that are equivalent
to digital circuits, which propel designers to develop novel circuit design techniques to
amend for the low voltage swings and low voltage head rooms [6].
While most high-voltage, high power circuits and systems still make use of
discrete power elements such as IGBT as switches, SoC compatible power transistors
supporting from 16 V to 800 V have also been available with recent advance of
semiconductor technology [3]. These SoCs are fabricated using novel semiconductor
technologies with both high voltage power devices and standard digital CMOS
transistors. Thus, fast prototyping of digital controllers using cell-based standard digital
libraries and full-custom high voltage circuits can add new avenues to design
methodology and significantly shortens time-to-market of new products.
Finally, despite the continuous trend of device scaling, the parasitic associated with
packaging and printed circuit boards (PCB) do not decrease accordingly [7], and
traditional single-ended inverter buffer is no longer adequate. On the other hand, data
rate has been elevated to a very high range, which makes lumped circuit approximations
of PCB boards no longer adequate. Instead, transmission line models should be used.
RLC model extraction of PCB is necessary so that appropriate impedance matching can
be achieved [8]. To accommodate for these design challenges outside the chip, it
2
becomes evident that both the packaging technology of integrated circuit and PCB
technology have become self-prominent issues in circuit design.
To allow the readers to quickly grasp all of the topics mentioned in this thesis, a
synopsis of these topics is described in the following section. Furthermore, a literature
review is provided to address the problems to be resolved. Finally, this chapter
concludes with the structure and outline of this thesis.
1.2
Overview
1.2.1
Automatic gain control circuits
Vin
Vout
VGA
G(Vc)
Vc
Loop
Filter
Σ
-Vp
Peak Detector
+
Vref
Fig. 1.2.1 An AGC model [10].
Automatic Gain Control (AGC) plays an essential role in modern wireless
transceivers which are designed for analog/digital radio systems, GPS, WLAN,
Bluetooth, ZigBee, and many other applications [9]. As shown in Fig. 1.2.1, they are in
charge of adjusting the gain, G(VC ) , of the associated Variable Gain Amplifiers (VGA)
so that constant amplitude of the demodulated signal amplitude is provided to
3
downstream circuits of a direct conversion receiver given a variable input amplitude, Ain.
A Peak Detector (PD) in AGC is responsible for detecting the amplitude of the output
signal, Vout . The acquired amplitude is compared with a reference voltage Vref , which
produce an error signal. A loop filter is used to shape the frequency response of the
AGC to generate Vc , the gain control voltage of the VGA.
Notably, data recovery from the input signal can proceed only after the AGC circuit
has been adjusted to provide an appropriate gain. Such an amplitude adjustment must be
faster than the preamble of the transmitted data. For the efficiency of channel bandwidth
utilization, the adjustment time should be as short as possible [10].
1.2.2
High voltage integrated circuits
Circuits fabricated using standard CMOS processes offer broad possibilities of
applications. However, due to the thin thickness of transistor gate oxide in these
processes, integrated power management solutions are limited to mobile and consumer
applications such as smart phones, tablet PCs, and digital cameras.
To remove this limitation, certain high voltage processes that feature Vertical
Double-Diffused MOS (VDMOS) devices have been developed to meet the demand of
high voltage (HV) applications [11]. However, the channel length of these HV
transistors does not depend on the resolution of the photolithography. Instead, they are
controlled by the lateral spreads of phosphorus and boron diffusions. The non-planar
characteristics make integration of these devices into standard digital CMOS processes
relatively difficult [12]. An alternative approach around this problem is to use Lateral
Double-Diffused MOS (LDMOS) transistors. These devices have lateral drift extension,
4
which are similar to standard digital CMOS process. The integration of such devices
and the standard digital CMOS process has been reported in [13]. However, it is almost
a decade of advancement in semiconductor technologies before this process is made
mature enough for mass production. Now, a broad portfolio of commercially available
high voltage processes that feature both LDMOS and standard CMOS devices are
released [14]. Among these processes, the TSMC 0.25 μm Bipolar-CMOS-DMOS
(BCD) process that covers voltage up to 60 V has been made available to the academic
users in Taiwan [15], [16].
1.2.3
Backplane transceivers
Gb/s transmission within an integrated chip is made a reality thanks to the
advancement in modern VLSI systems and semiconductor process. However, the device
scaling of transistors merely increases their cut-off frequency. It does not benefit the
performance of external communications with another integrated circuit, since the
fundamental limit of such data transmission is dictated by wire channels comprising
components such as printed circuit board traces and bond-wires. In these traces and
bond-wires, the parasitic capacitance and inductance limit the bandwidth, which
imposes a maximum data rate. Furthermore, electromagnetic interferences, crosstalk,
ground bouncing, skin effect, intersymbol interferences and many other issues all sum
up to the challenge in designing a transmitter suitable for Gb/s transmission. Hence, an
effective Gb/s transmitter and receiver data for external wire channels has been
recognized as a task to beat.
5
1.3
Prior Arts
1.3.1
AGC, VGA, and PGA
Typical realization of VGA can be sorted into three categories, as shown in Fig.
1.3.1, 1.3.2, and 1.3.3. Referring to Fig. 1.3.1, the design of a VGA is carried out using a
variable transconductor, Gmtune, and a variable load, Rotune, to adjust the gain [17] - [22].
Such a VGA can provide the highest gain tuning range and bandwidth when compared
to VGAs using other topologies, given the same power consumption. However, the
input range of the transconductors is limited [23]. Large input signals will also affect the
transconductance of the transconductors, which is not acceptable for direct conversion
(Zero-IF) receivers that highly rely on the matching of VGA gain for both I and Q
channels [24]. Furthermore, the inconsistent performance of these VGA in different
process, voltage, temperature (PVT) corners greatly hinders overall system performance.
Therefore, they appear more often on academic research papers than on actual
commercial products. Nevertheless, pseudo-exponential gain control, which will be
mentioned in the next section, can only be realized using this class of VGA, at the
expense of degraded performance.
A VGA consisting of a fixed transconductor, Gmfix, and switchable loads, Roswitch, is
shown in Fig. 1.3.2. Since the input transconductor is no longer made variable, higher
input signal is allowed. Although they also exhibit different characteristics in different
PVT corners, the minimum system requirements of a receiver can still be met as long as
enough dynamic range (DR) margins are provided. Such a VGA provides similar
performance when compared to VGA with a variable transconductor and a variable load
6
Rotune
Gmtune
Fig. 1.3.1 A variable tranconductor and a variable load.
Gmfix
Roswitch
Fig. 1.3.2 A tranconductor and a switchable load.
Rfswitch
Fig. 1.3.3 An OPA with switchable feedback.
[25] - [36]. However, they are limited by the resolution of their gain steps (GS). Fine GS
increases system complexity and lowers system bandwidth, while coarse GS degrades
the performance of data recovery from the input signal. Since their gain is digitally
programmable, they are more often regarded as Programmable Gain Amplifiers (PGA)
[25] - [35], or digital VGAs [36]. It is worth pointing out that the term “digital VGA” is
generally referred to as a digital multiplier [10]. To avoid ambiguity, such a usage
7
should be avoided.
Finally, operational amplifiers with a negative feedback can be used as PGAs [37],
as shown if Fig. 1.3.3. It is achieved by changing the feedback resistors, Rfswitch, to
constitute various inverting configurations. This class of VGA (or PGA) has inherited
most advantages and disadvantages of a closed-loop feedback system. For example,
since its gain is determined by the feedback factor rather than the transconductance or
output resistance of MOS transistors, they possess consistent performance regardless of
PVT corners. Although the intrinsic bandwidth of the PGA would become a function of
gain, its effects are irrelevant as long as the minimum bandwidth is larger than that of
the cascaded low pass filters. Furthermore, the use of rail-to-rail operational amplifiers
would enable full swing operation, creating negligible distortion on the output signal.
All of these advantages can be attained with a hefty price of approximately 100 times
larger area on silicon and 10 times power consumption when compared to the VGA with
a variable transconductor and a variable load for the same performance. However, if
robustness is the only concern, they are the PGA of choice.
1.3.2
High voltage designs using LDMOS
In the past, LDMOS transistors are generally limited to applications such as RF
power amplifiers [13]. Hence, unlike conventional VDMOS-based high voltage tolerant
integrated circuit designs, very few power management designs carried out using
LDMOS were reported in literatures [32], [33].
In Fig. 1.3.4 [32], a “buck store boost restore” (BSBR) DC/DC boost converter
responsible of converting a supply voltage to another voltage was proposed. This boost
8
Boost Converter
12.4 V
9.3 V
Augmented DC/DC Converter
Buck Store
Boost Store
Digital
Circuit
PWM Generator
Control Signals
BSBR Controller
Fig. 1.3.4 A BSBR DC/DC converter [32].
converter has been designed to provide power to LED drivers. Since the turn on voltage
of red, green, and blue LEDs are different, the output voltage of the boost converter
switches between 9.3 V (for red LED) and 12.4 V (for green and blue LED).
However, when the boost converter attempts to switch from 12.4 V to 9.3 V, the
output capacitor of the boost converter has to be uncharged, wasting the charges stored
in the capacitor. To resolve this problem, an additional DC/DC converter is augmented
to the system to extract the charges from the output capacitor of the boost capacitor and
transfer them to another capacitor (buck store). The augmented DC/DC converter
restores the charges back when the boost converter attempts to switch from 9.3 V to
12.4 V (boost restore). Furthermore, the charges extracted from the output capacitor can
also be used to provide power to digital circuits that tolerates voltage supplies with
voltage ripples.
The boost converter in [33] offers similar (albeit slightly different) charge
recycling mechanism when compared to [32]. However, an additional fast reference
tracking (FRT) technique for PWM control was also proposed in [33]. As depicted in
Fig. 1.3.5. A PWM controller using FRT technique includes a current sensor which
senses input voltage information and deducts this current Ifeed with the output current, Ic,
9
Ifeed
+
Ifeed
Ia
Ic
Vfb
Vref
Saw-tooth
Generator
Fig. 1.3.5 A PWM controller using FRT [33].
of an error amplifier. Ic is dependent of the reference voltage, Vref, and the output
feedback voltage, Vfb. The difference of the aforementioned current is compared with
saw-tooth current, Ia, using a current comparator. It has been claimed by the authors in
[33] that the transient response can be improved, and the duty cycle can rapidly be
determined by the difference of the saw-tooth signal with a switching voltage reference.
Both designs, [32] and [33], used external diodes instead of the integrated diodes
offered by the TSMC 0.25 μm BCD 40 V process. Although no explicit evidence has
been made through experiments, well-informed designers were warned against the use
of these diodes by individuals who prefer not to address this issue in public.
1.3.3
Charger operation
A conventional battery charger starts the charging sequence by sourcing a regulated
current to the battery when the voltage of the battery is low. This mechanism is well
known as the constant current (CC) mode. When the battery voltage rises, its internal
ESR also increases. The battery charger is then switched into the constant voltage (CV)
mode as soon as the battery voltage reaches a predefined level, where the charging
voltage of the battery is regulated. When the battery voltage reaches the designated
10
Charging
Current
Battery
Voltage
Predefined
Voltage
CC Mode
(a)
Charging
Current
Predefined
Voltage
Charging
Current
Predefined
Voltage
Time
CV Mode
CC Mode
Charge Mode
Battery
Voltage
Battery
Voltage
(b)
Time
CV Mode
Charge Mode
Charging
Current
Predefined
Voltage
Battery
Voltage
Time
Time
CC Mode
CV Mode
CC Mode
CV Mode
Hysteresis Charge Mode
Hysteresis Charge Mode
(c)
(d)
Fig.1.3.6 Charging current vs. battery voltage.
voltage level, the charging sequence is terminated. This charging strategy depicted in
Fig. 1.3.6(a) is popularly regarded as the constant-current/constant-voltage (CC/CV)
technique, which has been widely used in prior literatures [34] - [38]. However,
straight-forward implementation of the CC/CV technique using independent error
amplifiers for both CC mode and CV mode and a voltage comparator can result in a
potential stability problem during charge mode transition. As conceptually shown in Fig.
1.3.6(b), the charger switches from CC mode to CV mode when the feedback voltage
from the battery becomes larger than the predefined reference voltage. An abrupt
change of the charging current on the parasitic resistance causes a sudden voltage drop
on the charging path from the charger to the battery, which in turn causes the sensed
feedback voltage to drop. Consequently, the predefined reference voltage has a larger
11
voltage value in comparison, and the charger is switched back to CC mode [34]. Such
back-and-forth transitions can occur for an indefinite number of times after the battery
voltage approaches the predefined value.
An apparent solution is to add hysteresis to the comparator to squelch the unstable
rapid transitions between CC and CV modes, as demonstrated in Fig. 1.3.6(c) and (d).
However, it is not easy to define an appropriate range of hysteresis. Assume that the
feedback voltage is connected to the positive node of the comparator and the predefined
voltage is coupled to the negative input of the comparator. Potential overheating of the
battery may occur if the positive hysteresis range is made too large, delaying the
entrance to CV mode. [32]. By contrast, if negative hysteresis is used and the range is
made too large, it will cause the battery charger to enter CV mode prematurely. Finally,
if the hysteresis range is made too small, the rapid oscillation may still occur [34].
To resolve this problem, [34] proposed a highly complicated digitally-controlled
built-in resistance compensator (BRC) to estimate the parasitic resistance of the
charging path and extend the range of CC mode operation. On the other hand, a dual
loop topology was proposed [36]. As shown in Fig. 1.3.7, its implementation of the
CC/CV technique is accomplished using an independent error amplifier, EAcc, for CC
mode and an operational amplifier, OPcv, for CV mode. Interestingly, instead of using a
voltage comparator to determine CC/CV mode, a diode is used to separate the outputs
of the error amplifier, Vcco and the operational amplifier, Vcvo. When the battery voltage
is low, the DC level of Vcco is substantially higher than Vcvo such that diode is cut-off.
Hence, the operation of OPcv cannot interfere with the charging operation. As the
battery voltage increases, Vcvo, becomes higher than Vcco such that the diode starts
conducting. The equivalent resistance seen by the output of EAcc at the Vcco node, Rdio
12
Current
Reference
Current
Feedback
Rout
EAcc
Rdio
Vcco
Vcvo
OPcv
Voltage
Reference
Voltage
Feedback
Supply
Voltage
Battery
Fig. 1.3.7 Charging with fixed and variable voltage supply [36].
drops significantly, killing the gain of EAcc. Thus, the operation of EAcc cannot interfere
with the charging operation.
There is another serious issue worth mentioning. Referring to Fig. 1.3.8(a), the
charger consisting of a Power MOS MP-fix and a CC/CV regulator starts its charging
sequence in CC mode. Since the battery is uncharged, the voltage node at Vbat is at a
low voltage and the drop-out voltage VDS across the transistor MP-fix is as high as the
voltage difference between VDD-fix and Vbat. VDS will become gradually smaller as the
battery is charged and Vbat increases. However, since the charger charges the battery by
regulating a high current to the battery in CC mode, the charging current will also flow
directly through MP-fix to cause a significant power loss on MP-fix. Thus, such chargers
are only capable of providing an inherently low charging efficiency. Heat dissipation
can be another side effect as well. The charger has different cooling requirement
throughout the charging sequence, which must be accounted for the worst case when
most power are dissipated across the transistor MP-fix. Therefore, economic packaging,
e.g., Side-Brazed Dual In-Line Packages, cannot meet the cooling constraint imposed
by such chargers. By contrast, the charger shown in Fig. 1.3.8(b) is supplied by a
13
VDD-fix
VDD-var
Charger MP-fix
CC/CV
Regulator
Charger MP-var
CC/CV
Regulator
Vbat
(a)
Vbat
(b)
V
V
VDD-var
VDD-fix
Vbat
Vbat
VDS of MP-fix
VDS of MP-var
Time
Time
(c)
(d)
Fig. 1.3.8 Charging with fixed and variable voltage supply.
variable supply voltage, VDD-var. This supply voltage is intended to track and provide a
voltage slightly higher than Vbat. Hence, the drop-out voltage VDS across the transistor
MP-fix is maintained at a predefined value such that the charging efficiency is
significantly improved in the CC mode. The cooling requirement of such chargers in CC
mode is also made less stringent as well. This mechanism was implemented in [35] and
[36]. In [35], a complete AC/DC converter is used. The integrated charger circuit
provides an adaptive reference voltage to control the AC/DC regulator chip, which in
turn regulates its power stage to provide a variable supply voltage for the charger. On
the other hand, a boost converter was proposed used in [36] to provide the similar
function.
14
1.3.4
Transceiver systems
vout
common
resistors
transconductor
Dz-3
Dz-2
Dz-1
D
c3 c
2c
1c
0
Dz-1
z-1
D
Dz-2
z-1
z-1
Dz-3
Fig. 1.3.9 A pre-emphasis transmitter.
High speed data transmission through band-limited lossy channels on fire-retardant
glass laminate substrate material (FR-4) requires equalization to remove intersymbol
interferences (ISI) and other issues [39]. Notably, though a complete coverage on the
design challenges circulating transceiver designs is given in to the first section of
Chapter 4, a survey of existing architectures is provided in this section.
Generally, an equalizer attempts to de-emphasize the low frequency components of
a signal and boost the high frequency components during transitions between different
binary signals. Equalization can be done at either the transmitter end [40] - [43] or at the
receiver end [40], [43] - [46].
Referring to Fig. 1.3.9, a generic pre-emphasis transmitter is shown. Unit delay
blocks are implemented using D flip-flops to provide symbols delayed by a predefined
15
vbiasp
vout
vbiasp
vin
vin
vr
vr
CS
transconductance
stage
transimpedance
stage
Fig. 1.3.10 A pre-emphasis transmitter.
number (e.g., 3 in this figure) of unit intervals, Dz-1, Dz-2, and Dz-3. These symbols are
connected to a congregation of 4 transconductors, which sink currents from two
common resistors. The current values are determined by their respective current sources,
which in turn are controlled by coefficients, c0 to c4. Such transmitters have been widely
used, [40] - [42], because of their ability to de-emphasize low frequency components.
Therefore, the pre-emphasis transmitters are sometimes referred to as de-emphasis
transmitters.
Equalization can be achieved at the receiver end either by analog or digital means.
In Fig. 1.3.10, an analog equalizer composed of a transconductance stage and a
transimpedance stage provides two zeros [44]. The locations of the zeros are controlled
by the voltage, vr, which governs the equivalent resistance of the MOS transistors acting
as resistors. At the boundary channel bandwidth frequency, these zeros can boost the
gain such that low frequency components and high frequency components are
equalized.
16
y[n]
+
x[n]
-
w2
y[n-3]
- -
w1
y[n-2]
z-1
w0
y[n-1]
z-1
z-1
Fig. 1.3.11 Decision feedback equalization.
If digital equalization is preferred, a mechanism known as decision feedback
equalization (DFE) can be used [43], [45]. As shown in Fig. 1.3.11, the decision of the
3rd order DFE example is made by deducting the incoming signal, x[n], with the
product of y[n] delayed by unit intervals and coefficients w0, w1, and w2. Since the
feedback components are binary digital signals, these signals are less prone to noise.
Furthermore, as long as the decision of y[n] is correct, only the high frequency
component of x[n] is emphasized, while the associated analog noise is not.
However, if the DFE circuit is operating at very high frequencies, the loop delay
for the signal to propagate around the loop may become too long to meet the system
requirement. To overcome this design challenge, loop unrolling can be used to ease the
timing constraint. Consider a first order DFE circuit in Fig. 1.3.12. The decision of y[n]
can only be made after the previous y[n], y[n-1], is known, and arrives at the negative
port of the subtractor. However, if loop unrolling is applied, both outcomes are assumed
in Fig. 1.3.13. The final decision is made at the multiplexor stage where y[n-2] is used
to determine for y[n-1]. This structure and its variant [46] are commonly used in
receivers using digital equalization.
17
x[n]
y[n]
+
w0
y[n-1]
z-1
Fig. 1.3.12 A first order DFE.
1
w0
x[n]
x[n]
-
y[n]1
+
z-1
1
y[n-1]
y[n]0
+
-
z-1
z-1
y[n-2]
0
w0
0
Fig. 1.3.13 DFE loop unrolling [46].
1.4
Overview of the Thesis
The chapters encompassed in this thesis deal with 3 topics:
1.
Theory, comparison, and circuit realization of AGCs in low voltage integrated
circuit technology.
18
Chapter 1
Introduction
Chapter 5
Chapter 2
Conclusions
Automatic Gain
Control: Theory and
Implementations
Backplane
Transceivers
High Voltage IC
Designs: OTA and
Chargers
Chapter 4
Chapter 3
Fig. 1.4.1 Thesis structure.
2.
Overview of CMOS compatible high voltage process, along with design
examples.
3.
Implementation
of
backplane
transceivers
with
for
board-to-board
communications.
A brief description of the chapters in this thesis is described as follows:
Chapter 2 focuses on automatic gain control of modern wireless receivers. The
derivations on constant gain settling time [10] of AGCs are provided. A low power
pseudo-exponential VGA is presented in Section 2.2. In Section 2.3, an AGC circuit
with Feed-foRward Output Swing predicTion (FROST) and Parallel-Detect SingleStore Peak Detector (PDSSPD) is described. Furthermore, a 47 dB DR Programmable
Gain Amplifier (PGA) suitable for digital AGCs is presented in Section 2.4.
19
Chapter 3 begins with an overview of CMOS compatible high voltage process,
namely, the TSMC 0.25 μm 1-poly 3-metal Bipolar-CMOS-DMOS (BCD) 60 V process.
Section 3.2 presents a Domestic Indirect Feedback Compensation (DIFC) operational
amplifier for systems with both low voltage and high voltage domains. Meanwhile, a
novel 60-V battery charger is presented in Section 3.3 along with a comparison with
prior works.
In Chapter 4, a briefing on the challenges of backplane transceiver is provided. The
design of a transmitter with pre-emphasis and a receiver with DFE carried out using
TSMC 0.35 μm CMOS process are described in Section 4.2 and 4.3, respectively.
Finally, conclusions of this thesis are made in Chapter 5.
20
CHAPTER 2: AGC
2.1
Ain
Constant Settling Time AGC
ln(Ain/kv1)
x(t)
+
y(t)
Σ
Aout
kv1ey
+
ln(G(Vc))
Vc
Gm
C
Σ
-
kv2ln(Aout/kv1)
+
kv1ez
ln(Vref/kv1)
Vref
Fig. 2.1.1 Model of the generalized AGC circuit [10].
In an AGC loop model shown in Fig. 2.1.1, the feedback loop will only responds to
the peak amplitude of the output voltage, Vout . The amplitude of Vout is:
Aout
G(VC )
21
Ain
(2.1.1)
According to Fig. 2.1.1, Eqn. (2.1.1) can be expanded as:
Aout
kv1
G(Vc ) Ain
kv1
kv1 exp[ln G(Vc )
ln(
Ain
)]
kv1
(2.1.2)
where kv1 is a constant in the unit of volts. Under the assumptions that peak detectors
are assumed to be much faster than the operation of the loop. They are removed from
the model of Fig. 2.1.1. Furthermore, the loop filter is expressed as an ideal integrator
Gm / sC [10]. Hence, the output of the loop filter
with a transfer function of H (s )
can be expressed as:
Vc (t )
tG
m
0 C
kv1e z
k e y[ ]
kv 2[ln( v1
)] d
kv1
(2.1.3)
y(t )
x(t )
ln G(Vc )
(2.1.4)
and
By taking the derivative of y(t ) with respect to time, we obtain:
dy(t )
dt
dx (t )
dt
dx(t )
dt
d ln[G(Vc )]
dt
1 dG(Vc ) Gm 2
[k e z - kv 2y( )]
G(Vc ) dVc C v1
dx (t )
dt
kxkv1e z - kxkv 2y( )
dx (t )
dt
kxVref - kxkv 2y( )
22
(2.1.5)
and
1
kxkv 2
1
1 dG(Vc ) Gm
k
G(Vc ) dVc C v 2
constant
(2.2.6)
which also implies:
1 dG(Vc )
G(Vc ) dVc
kG 1
constant
(2.2.7)
1 dG(Vc )
kG 1 dVc
kG 1ekG 1Vc
(2.2.8)
Finally, G(Vc ) can be expressed as:
G(Vc )
Evidently, we reach a conclusion that the realization of a constant settling time
AGC circuits which is independent of the amplitude of the incoming waveforms would
require a VGA with characteristics of Eqn. (2.2.8). Such a VGA can amplify the
incoming waveforms must be able to adjust its gain linearly in decibels with respect to
the gain controlling voltage [10].
Unfortunately, with the absence of devices providing an exponential characteristic
in standard CMOS process, it is difficult to design such a VGA. To overcome this
problem, pseudo-exponential functions that attempt to approximate the real exponential
function have been reported [10], [17] - [21], and circuits with a pseudo-exponential
function behavior have also been proposed [17] - [21].
23
2.2
A Linear-in-dB VGA
2.2.1
Approximation of exponential gain characteristics
By using Taylor series expansion, the exponential function can be expanded as:
eax
1
a2 2
x
2!
a
x
1!
...
an n
x
n!
(2.2.1)
The terms in Eqn. (2.2.1) with n > 3 has negligible influence to the function. Thus the
function can be approximated by [17]:
eax
1
a
x
1!
a2 2
x
2!
1
2
[1
(1
ax )2 ]
(2.2.2)
under the restriction that a <<1 to work well. Fortunately, the decibel linear range can
be improved by changing the constant 1 into a decimal number 0.12 and using the
relation, e 2ax
eax / e -ax , which results in the following equations [18]:
eax
e 2ax
0.12
eax
e -ax
(1
0.12
0.12
ax )2
(1
(2.2.3)
ax )2
(1-ax )2
(2.2.4)
Nevertheless, the constant 0.12 cannot be easily implemented accurately with analog
circuits. By contrast, the decimal 0.125 can be realized by using a current mirror with a
ratio of 1:8.
24
2.5
2
1.5
f(x) (dB)
1
0.5
0
-0.5
-1
Exponential Function
Constant = 0.125
Constant = 0.12
-1.5
-2
-2.5
-1.5
-1
-0.5
0
0.5
x
1
1.5
Fig. 2.2.1 Approximation of the exponential function.
It can be shown in Fig. 2.2.1 that the approximation using a constant of 0.125 is as
good as using 0.12. Hence, the constant 0.125 is adopted in Eqn. (2.2.5) of this design
instead of 0.12.
eax
e 2ax
e -ax
0.125
0.125
(1
ax )2
(1-ax )2
(2.2.5)
Now, the current paths used to realize Eqn. (2.2.5) can be expressed with as follows.
I D,M
I D,M
I D,M
I D,M
P2
N1
P1
1
8
N2
1
8
(VDD -Vthn )2
(2.2.7)
(VDD - | Vthp |)2
(2.2.8)
(Vcontrol -Vthn )2
(VDD -Vcontrol - | Vthp |)2
25
(2.2.9)
(2.2.10)
where β is selected such that knCox(W/L)N1 = kpCox(W/L)P1. This relationship also
dictates the aspect ratio of transistors MN1, MN2, MP1, and MP2. From KCL, IC 1 and
IC 2 are the sum of drain currents from MP1, MP2 and MN1, MN2, respectively. With
some algebraic manipulation, we obtain:
IC 1
[
1
8
(VDD -Vcontrol - | Vthp |)2
1
8
2
(VDD -Vcontrol - | Vthp |)
(VDD -Vcontrol - | Vthp |)
AI 1
2
VDD - | Vthp |
AI 1
VDD -Vcontrol - | Vthp |
2
Vcontrol
1VDD -Vcontrol - | Vthp |
1
8
2
(VDD - | Vthp |)2 ]
AI 1 (2.2.11)
and
IC 2
[
1
8
(Vcontrol -Vthn )2
(VDD -Vthn )2 ]
(Vcontrol -Vthn )2
1
8
VDD -Vthn
Vcontrol -Vthn
(Vcontrol -Vthn )2
1
8
1-
AI 2
2
Vcontrol -VDD
Vcontrol -Vthn
AI 2
2
AI 2
(2.2.12)
where AI 1 and AI 2 are the current gains of the respective current mirrors. Now, by
selecting an appropriate Vcontrol such that:
VDD -Vcontrol - | Vthp |
(2.2.13)
2 Vcontrol -Vthn + | Vthp |
(2.2.14)
Vcontrol -Vthn
VDD
26
and the assumption that:
VDD
(2.2.15)
Vthn - | Vthp |
the following equation is attained by dividing IC 2 with IC 1 :
IC 2
IC 1
(Vcontrol -Vthn )2
AI 2
(VDD -Vcontrol - | Vthp |)2
1
8
AI 2
AI 1
AI 2
AI 1
1-
AI 1
1
8
Vcontrol -2 Vcontrol -Vthn + | Vthp |
2
2
VDD -Vcontrol - | Vthp |
Vcontrol
1VDD -Vcontrol - | Vthp |
1
8
-Vcontrol
1VDD -Vcontrol - | Vthp |
1
8
Vcontrol
1VDD -Vcontrol - | Vthp |
0.125
2
Vcontrol
1VDD -Vcontrol - | Vthp |
1
8
0.125
AI 2
AI 1
V
-V
1- control DD
Vcontrol -Vthn
1
8
Vcontrol
1+
VDD -Vcontrol - | Vthp |
1-
Vcontrol
VDD -Vcontrol - | Vthp |
2
2
2
2
2
(2.2.16)
If the factor of the variation in the control voltage, x, then
Vcontrol -Vthn
VDD -Vcontrol - | Vthp | >> | xVcontrol -Vcontrol |
27
(2.2.17)
Eq. (2.2.16) can be simplified into as follows.
IC 2
IC 1
AI 2
AI 1
[
0.125
0.125
(1
ax )2
2
(1-ax )
]
AI 2
AI 1
eax
(2.2.18)
where
a
Vcontrol
Vcontrol -Vthn
Vcontrol
VDD -Vcontrol - | Vthp |
(2.2.19)
Apparently, if the gain of an amplifier is a linear function of Eqn. (2.2.16), the
particular amplifier will provide pseudo-exponential gain characteristics, and
linear-in-dB characteristics is achieved as long as Eqn. (2.2.17) is valid.
2.2.2
VGA circuit with exponential gain characteristics
To realize an amplifier with the required pseudo-exponential gain characteristics, a
system topology shown in Fig. 2.2.2 is used. A current generator is used as a V-to-I
circuit, which converts the control voltage Vcontrol into IC 1 and IC 2 , as shown in Fig.
2.2.3. The current IC 1 and IC 2 will be mirrored to both main VGA and half circuit.
The half circuit is in charge of generating additional bias voltages, V1, V2, and V3,
which are supplied to main VGA as functions of IC 1 and IC 2 . With the appropriate
bias currents and bias voltages from the current generator and the half circuit, the main
VGA amplifies the incoming voltage, Vin, by an amplitude according to the control
voltage Vcontrol. Notably, Vin and Vout are fully differential in physical implementation.
28
IC2
Vcontrol
IC1
V1V2V3
eax Current
Generator
Vin
Half
Circuit
Vout
Main VGA
Fig. 2.2.2 The block diagram of the proposed VGA.
MP2
(
ΔVcontrol
Vcontrol
(
MP1
W
W
) : ( ) = 1: 8
L P 2 L P1
W
W
) : ( ) = 1: 8
L N 2 L N1
MN2
Vc1
Ic1
Vc2
Ic2
MN1
Fig. 2.2.3 IC 1 and IC 2 current generator.
As shown in Fig. 2.2.4, IC 2 is mirrored to MR1 through VC1, which flows through
R1 to generate a voltage IC 2
R1 . Recall that the transconductance of a MOS transistor
operating in triode region is expressed as follows.
gm
ID
Vgs
W
1
) (Vgs -Vth )Vds - Vds 2
L
2
Vgs
pCox (
29
W
)V (2.2.20)
L ds
pCox (
V3
Mp-out
Vc1
Vbias
MT1
EA1
VS,common
VD,common
R1
IC2
Mcommon
Vin-common
IC1
V2
MB
EA2
Mn-out1
Vc2
MR1
Mn-out2 EA3
V1
Vout-common
Fig. 2.2.4 The half circuit.
If we bias Mcommon in triode region and ensure that the voltage across the transistor
is equivalent to the voltage across R1, the transconductance of Mcommon becomes:
gm
W
)I R
L C2 1
pCox (
(2.2.21)
To ensure that the drain node of MT1 remains constant regardless of IC 2 , an error
amplifier EA1 is used to regulate the drain of MT1 to Vbias by adjusting the gate of MT1
withV3 . EA2 senses the drain node of MR1 and regulate the drain of Mcommon to be
consistent by adjusting the gate of MB with V2 . In this way, both the source and drain
nodes of transistor Mcommon is well-defined:
VS ,common = Vbias
VD,common = Vbias
30
IC 2R1
(2.2.22)
(2.2.23)
Mp-out+
V3
Vin+
IC1
Mp-out-
MT2
Min1
Min2
Vin-
R2
MB1
Vout
+
Mn-out1+
Vc1
2·IC2
MB2
Vout
V2
Mn-out2+
V1
MR2
IC1
-
Mn-out1-
Vc2
Mn-out2V1
Fig.2.2.5 The main VGA.
Both V2 and V3 are used to bias the main VGA, forcing both the input
transistors Min1 and Min2 into triode region and their transconductances will be governed
by Eqn. (2.2.21).
The output resistance of an amplifier is determined by:
ro
1
ID
( pI D,M
p -out
n I D,Mn -out 1
-1
n I D,Mn -out 2 )
(2.2.24)
which is the shunted output resistance of Mp-out, Mn-out1 and Mn-out2. Since I D,M
I D,M
n -out 1
I D,M
n -out 2
and let I D,M
ro
IC 1 , we have:
p -out
1
p IC 1
p -out
1
n IC 1
(
p
n )IC 1
(2.2.25)
By multiplying Eqn. (2.2.21) with Eqn. (2.2.25), we attain an expression of the
overall gain:
31
AvVGA
W
AI 3 pCox ( )2R2
L
( p
n)
W
AI 3 pCox ( )IC 2 2R2
L
( p
n )IC 1
AI 2
AI 1
[
0.125
(1
0.125
ax )2
2
(1-ax )
]
B
eax
(2.2.26)
By Eqn. (2.2.26), we obtain a VGA circuit shown in Fig. 2.2.5 that provides a gain
linearly in decibels with respect to gain controlling voltage, which is realized using
transconductors given the MOS operating in triode region and output resistance given
the MOS operating in saturation region.
Current balancing is achieved using EA3, Mn-out1+, Mn-out2-, and Mn-out2. EA3 can be
interpreted as a linear regulator, which attempts to regulate the drain nodes of Mp-out,
Mn-out1 and Mn-out2 to a predefined voltage, Vout ,common . As EA3 controls the gate
voltage of Mn-out2, Mn-out1+ and Mn-out2- are simultaneously controlled as well. Hence, the
DC level of the output nodes of both main VGA and half circuit will be kept at
Vout ,common regardless of the the gain control voltage, Vcontrol. In this design,
Vout ,common is chosen to be
1
2
VDD . This is important because we need to ensure Mp-out,
Mn-out1, Mn-out2, Mp-out+, Mn-out1+, Mn-out2+, Mp-out-, Mn-out1-, and Mn-out2-, all working in
saturation so that the VGA operates in a manner dictated by Eqn. (2.2.26). Furthermore,
it is important for the outputs of the VGA to
1
2
VDD to attain the maximum voltage
swing. However, if the input stage of the cascaded circuit requires a DC bias other than
1
2
VDD , Vout ,common can be adjusted to a corresponding value.
32
2.2.3
Measurement results of the VGA
eax Current
Generator and
Half Circuit
Vcontrol
ABM
PRT3230
Power
Supply
Bias Voltages
Bias Currents
and Voltages
Vout+
AC Ground
VGA
Proposed
VGA
Vin
Vout-
Audio
Precision
Sys-2712
Personal
Computer
Fig. 2.2.6 The measurement setup for the proposed VGA.
This design has been implemented using TSMC 0.18 μm standard CMOS process.
Simulation results show that the VGA has a minimum bandwidth of 3 MHz with no RC
load, and 5 kHz with 50 pF loading on both outputs. The measurement was conducted
with personal computer-controlled Audio Precision Sys-2712, which has approximately
50 pF capacitive load on both probes. ABM PRT3230 was used to supply power,
provide bias voltages, and generate gain control voltage. The measurement setup is
shown in Fig. 2.2.6, and the measured and simulated Bode plots are given in Fig. 2.2.7
and Fig. 2.2.8, respectively.
Measurement results plotted in Fig. 2.2.9 also show that current IC 1 and IC 2
are capable of adjusting forward gain from -3 dB to 45 dB, which is 12 dB narrower
than the simulated result of -18 dB to 42 dB shown in Fig. 2.2.10. Nevertheless, the gain
tuning range of two such cascaded VGAs is still more than enough for most wireless
receivers [24].
33
Gain (dB)
Frequency (Hz)
Fig. 2.2.7 The measured Bode plot.
50
40
Gain (dB)
30
Simulated
iii
Frequency
iii iii
Response
of the
VGA without
RC load.
Simulated Frequency
Response of the VGA
with RC load.
20
10
0
-10
-20 00
10
10
01
10
02
10
03
10
04
10
05
10
06
Frequency (Hz)
Fig. 2.2.8 The simulated Bode plot.
34
10
07
10
08
10
09
To address the nonlinearity characteristic exhibited in the measurement and
simulation results, we have to separate the transconductance, gm , and output resistance,
ro , and plot their values against the gain control voltage, Vcontrol . Apparently, ro
closely follows Eqn. (2.2.21), and the gain linearly in decibels with the gain controlling
voltage is achieved. However, the tunable range of ro should not be large to prevent an
excessive difference in the bandwidth of VGA with a different gain. On the other hand,
gm has a large tuning range, yet showing nonlinear characteristics against Vcontrol ,
which deviates from Eqn. (2.2.17). The major reason of this problem lies in the usage of
square-law modeling of MOS transistors. Since Eqn. (2.2.17) is attained by
differentiating the square-law drain current equation of a MOS transistor working in
triode region, linearity is limited to very small range where the square-law model is
accurate. The same phenomenon also applies to MOS transistors working in saturation,
which has been reported in prior works [17], [21]. VGAs demonstrated in these
literatures use MOS transistors working in saturation as the input transconductor and
diode-connected loads as active loads such that their gain can be described as follows,
AvVGA
gm,transconductor
gm,diode -load
∝
I transconductor
Idiode -load
(2.2.24)
where gm,transconductor and gm,diode -load represents the input transconductor and the
diode-connected load, I transconductor and Idiode -load represents their bias currents,
respectively. Apparently, the gain of such VGAs exhibits a square-root relationship with
their gain control current, I transconductor and Idiode -load , whereas the VGA described in
this work is directly proportional to its gain control current, IC 1 and IC 2 . In other
words, the difference in bias current flowing through the proposed VGA can be made
half for the same gain tuning range in comparison with the prior works. Hence, the
35
variation in the bandwidth of the VGA is also reduced. By contrast, the tunable gain
range is doubled for the same change in gain control current. If gain linearity is stringent,
certain circuits can be added to the current mirror shown in Fig. 2.2.2 to prevent the
system from adjusting the VGA into regions where Eqn. (2.2.17) is no longer valid, and
still retain an acceptable gain tuning range. Comparing Fig. 2.2.9 with Fig. 10, it is
apparent that the gain tuning range measured is greatly deviated from the simulation.
When Vcontrol is lower than 0.9 V, the currents flowing through Mp-out, Mp-out+, and
Mp-out- become larger than what is anticipated by simulations. The widths of Mn-out2,
Mp-out-, and Mp-out2- are not sufficiently large to handle such a current. Hence, EA3 can
no longer regulate the DC level of the VGA output to Vout
common
such that the VGA
functions properly.
The proposed VGAs have a simulated power consumption ranging from 433 μW to
549 μW depending on its gain. Limited by the current resolution given by ABM
PRT3230, we can only verify that the current of this VGA is less than 1 mA, which
implies the overall power consumption is less than 1.8 mW. The micrograph of this
VGA is shown in Fig. 2.2.11, and a tabulated comparison of this VGA along with other
prior works is shown in Table 2.2.1.
36
Table 2.2.1 Comparison with Prior Works
Proposed
[17]
[20]
[21]
Gain (dB)
-3 to 45
0 to 95
-10 to 17
-5 to 10
Stages
1
3†
2
1
Bandwidth
3 MHz Min.
32 MHz
1.25 GHz
150 MHz
Core Area
0.0045 mm2
0.4 mm2
0.0887 mm2
0.15 mm2
Supply Voltage
1.8 V
1.8 V
1.8 V
3.3 V
Power (mW)
0.433-0.549
6.48
43.2
2.5
Process (μm)
0.18
0.18
0.18
0.5
Year
2010
2006
2008
1998
Variable Gain Stage + 1 Constant Gain Stage
45
40
35
Voltage Gain (dB)
†
30
25
20
15
10
5
0
-5
0.9
1
1.1
1.2
1.3
1.4
1.5
Control Voltage (V)
Fig. 2.2.9 Measured gain with respect to Vcontrol.
37
1.6
50
Voltage Gain (dB)
40
30
20
10
0
-10
-20
0.6
0.7
0.8
0.9
1
1.1
1.2
1
1.1
1.2
1
1.1
1.2
Control Voltage (V)
(a)
-95
-100
-105
gm (dB)
-110
-115
-120
-125
-130
-135
-140
0.6
0.7
0.8
0.9
Control Voltage (V)
(b)
140
138
136
ro( dB)
134
132
130
128
126
124
122
120
0.6
0.7
0.8
0.9
Control Voltage (V)
(c)
Fig. 2.2.10 Simulated (a) gain, (b) gm, (c) ro with respect to Vcontrol.
38
2.3
An AGC with FROST and PDSSPD
2.3.1
Low power implementation of an AGC
Traditionally, constant settling gain adjustment time VGAs with exponential gain
characteristics are implemented using BJTs or emulated with CMOS circuits. However,
when the output of the VGA has already saturated, which is usually the case for low
power receivers, the actual AGC characteristics deviate from the small signal model that
leads to the desired constant settling time adjustment. In other words, there would be no
constant settling time adjustment even if the VGA has exponential gain characteristics
under such circumstances. Furthermore, the emulation of the exponential gain
characteristics in a standard CMOS process usually comes with a high overhead in
hardware and degraded performance in bandwidth and power compared with VGAs that
are not intentionally designed to attain exponential gain characteristics.
To overcome the aforementioned issues, a 100 MHz AGC operating at 1 V supply
voltage is presented. The Feed-foRward Output Swing predicTion (FROST) technique
which can quickly adjust the gain of the VGA to the desired value according to the
envelope of the input signal provided by the Parallel-Detect Single-Store Peak Detector
(PDSSPD). The characteristics and analysis of the proposed PDSSPD which can
quickly track the decrease of the input signal envelope is presented. A VGA based on
rail-to-rail electronic Zener diode structure capable of high swing input and output stage
is also mentioned. The simulation results with gain, bandwidth, response time, and
harmonics are also included.
39
2.3.2
Feed-forward output swing prediction (FROST)
Auxiliary
VGA
PDSSPD
Vpredict
Vpeak
Vin
Subtract
Difference Vref
Gain
Controller
Vgainctrl (Adjust Gain)
Main VGA
Vout
Fig. 2.3.1 The proposed AGC.
Unlike traditional AGC loops, a PDSSPD is used to detect the peak of the
incoming signal instead of using a traditional peak detector to detect the output of the
VGA. As shown in Fig. 2.3.1, the DC value, Vpeak , generated by the PDSSPD is fed to
the auxiliary VGA which in turn generates Vpredict , a predicted envelope of the actual
amplified signal at Vout . Gain Controller, which is essentially an error amplifier,
attempts to adjust Vpredict to a pre-defined value Vref by tuning the gain control
signal Vgainctrl of the auxiliary VGA. Since the gain of the main VGA is also
controlled by Vgainctrl , the gain tuning of the auxiliary VGA and that of the main VGA
will be carried out simultaneously. Hence, the gain of the main VGA can be adjusted to
the appropriate value as long as the incoming signal is within the dynamic gain range of
the VGAs. The assumption of such a design is that the amplifier has equal gain for sine
40
signals and pulse train. One of the key advantages over traditional AGCs lies in the
prevention of saturating the output of main VGA. As soon as an rising Vpredict is
generated, the gain controller immediately begins to adjust the gain of the VGA to make
Vpredict = Vref , while a traditional AGC needs to wait for the output of the VGA to be
saturated before gain adjustment begins. On the other hand, the traditional AGC will
have no idea how ''saturated'' the VGA is, and it has to keep adjusting gradually until the
VGA returns to the linear operating condition. Furthermore, the main AGC in this
proposed design does not drive a peak detector, thus reducing the capacitive load. The
improvement in bandwidth can be substantial when the VGA is operating with the
maximum gain, since its output resistance would also be adjusted to the maximum value
to provide the largest possible RC time constant.
The gain controller is compensated with a Miller Capacitor to ensure stability
throughout the entire input range of operation. The size of the Miller Capacitor will
determine the response time of the gain controller. The optimum size of the Miller
capacitance is that results in a damping factor of 0.707 to yield the shortest response
time for amplitude adjustment.
2.3.3
Parallel-detect single-store peak detector (PDSSPD)
Traditional peak detectors typically consist of an error amplifier, a MOS diode, and
a capacitor. The error amplifier serves as a voltage follower charging the capacitor
corresponding to the input signal. The MOS diode prevents the capacitor from being
discharged. This type of peak detector is often modified by replacing the MOS diode
with a current mirror [47], as shown in Fig. 2.3.3. Theoretically, the peak voltage is
41
PDout1 or
PDout2
Vin
rst1
or
rst2
Vbpd
Fig. 2.3.2 A conventional peak detector.
Vin
PD1
PDout1
Vpeak
rst1
PD2
PDout2
rst2
Q
D
DFF1
En
Reset
Fig. 2.3.3 The proposed PDSSPD.
stored in the capacitor and the envelope of the signal is known. However, when the
amplitude of the input signal has dropped drastically, the voltage at the output terminal
of the capacitor does not discharge spontaneously. Thus, the peak detector will create an
invalid voltage for the AGC loop, and the gain of the VGA will not be raised to an
appropriate value corresponding to the decrease in input amplitude.
In this PDSSPD, as shown in Fig. 2.3.3, two parallel traditional peak detectors are
used to acquire the amplitude of the incoming signal. The peak values, PDout1 and
42
PDout2, stored in the peak detectors will be compared by a comparator. The result of
the peak detector with a lower voltage value is stored in DFF1. When a reset pulse
appears at Reset, the input nodes of the NAND gates, the output of DFF1, Q, masks the
reset pulse for one of the two reset signals, rst1 or rst2. The capacitor of the peak
detector with the higher voltage is discharged while the voltage value of the other peak
detector remains in its own capacitor. The comparator also controls the analog MUX
consisting of two transmission gates so that the appropriate voltage value is passed
down to Vpredict . Consequently, when the amplitude of the input signal becomes
smaller, PDSSPD can refresh their stored voltage immediately when Reset is triggered.
However, when the amplitude of the input signal remains constant or becomes larger,
the input amplitude acquired by both PD1 and PD2 remains constant or becomes larger
simultaneously. Hence, triggering Reset will not affect Vpeak . This idea is further
illustrated in Fig. 2.3.4. The voltage value of the input envelope appearing at Vpeak
(Fig. 2.3.4(c)) will not be discharged completely by the reset pulse as PD1 (Fig. 2.3.4(a))
and PD2 (Fig. 2.3.4(b)). Instead, it is switched between PD1 and PD2 with the correct
voltage value (white region). The output of PD1 and PD2 are masked in the shaded
region. In this design, the Reset signal pulse is selected to be 9 MHz to reduce
unnecessary power consumption. When the input signal amplitude is dropped
significantly (shown in Fig. 2.3.5(a)), a spurious increase of the peak detector voltage
could occur as a result of unwanted charge-injection. As depicted in Fig. 2.3.5, To avoid
misjudgment of gain tuning, the comparator of the PDSSPD automatically switches
back to the other peak detector (shown in Fig. 2.3.5(b)) to squelch the problem. The
spurious voltage is removed after 1.24 μs, as shown in Fig. 2.3.5(c).
43
V
PD1
1
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
μs
(a)
V
PD2
1
Interval between
Reset pulses
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
μs
(b)
V
Vpeak
1
Interval between
Reset pulses
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
(c)
Fig. 2.3.4 Response of (a) PD1, (b) PD2, and (c) the PDSSPD.
44
1.4
μs
V
PD1
1
0.8
Charge-Injection
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
(a)
V
1
1
1.2
1.4
Interval between
Reset pulses
μs
PD2
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
(b)
V
1
1
1.2
1.4
Interval between
Reset pulses
μs
Vpeak
Spurious
Voltage
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
(c)
Fig. 2.3.5 (a) PD1 with unwanted charge-injection. (b) PD2.
(c) PDSSPD with spurious voltage correction.
45
1.4
μs
μs
2.3.4
Proposed VGA
Vbvga2
M1
Vbvga2
M3
M5
Vin
M2
M9
M7
M6
Current
Summing
M4
Electronic Zener Diode
M8
Vbvga3
Vout
Vbvga3
Load
Variation
M10
Vbvga4
Fig. 2.3.6 The proposed VGA.
To allow a wide input swing, both PMOS (M1) and NMOS (M2) transistors are
used, as shown in Fig. 2.3.6. To avoid the dependence of the input stage
transconductance to the input voltage, an electronic Zener diode consisting of transistors
M3 to M6 is used to regulate the total transconductance. According to [48], the total
transconductance can be made constant by regulating the voltage across source
terminals of M1 and M2. Simulation result shown in Fig. 2.3.7 suggests that this voltage
varies around 10 mV when a rail-to-rail input voltage is applied. However, the
assumption of constant transconductance is made with square-law devices. In physical
implementation, the total transconductance is deviated from hand calculations.
Furthermore, without the presence of feedback from Vout , considerable harmonics will
be generated at the output even with the slightest inconsistency in transconductance.
The currents are summed at M7 and M8, and the gain is adjusted by increasing or
decreasing the current of M9 and M10. An extra bias circuit not shown in Fig. 2.3.6 is
46
V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
0
2
4
6
8
10
12
14
16
18
20 ns
0
2
4
6
8
10
12
14
16
18
20 ns
0.914
0.912
0.91
0.908
0.906
0.904
0.902
Fig. 2.3.7 Input voltage (a) vs. (b) variation of voltage across sources of PMOS
M1 and NMOS M2.
used to balance the current of M7 and M8 to ensure that the DC value of Vout is half of
the supply voltage to allow the maximum possible output swing.
2.3.5
Implementation results
This design has been implemented using TSMC 0.18 μm standard CMOS process.
The AGC with a minimum bandwidth of 100 MHz is capable of detecting input signal
amplitude and adjusting the desired corresponding gain to provide constant signal
amplitude to downstream circuits, as depicted in Fig. 2.3.8.
47
V
1
Start-up Gain Controller
Time Adjustment Time
Interval between
Reset pulses
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
μs
Fig. 2.3.8 The input signal (black) vs. the output signal of the AGC (gray).
Fig. 2.3.9 shows that the gain tuning range is from 0 dB to 26.4 dB. Notably, the
relationship between the gain and the gain control voltage begins to saturate at 0.6 V,
where the gain is 25 dB. However, the time for the gain controller to rise from 0.6 V to
1 V is in the order of several nanoseconds, which is insignificant compared with the
time for the PDSSPD to drop its output signal, which may last as long as 240 ns.
The proposed main and auxiliary VGAs consume a total of 77 μW when the entire
AGC works at a gain of 26.4 dB and a bandwidth of 100 MHz. When the VGAs drops
to a gain of 0 dB (bandwidth = 400 MHz), the power consumption soars up to 400 μW.
The Bode plot of the VGA at 0 dB, 12 dB, 26.4 dB is shown in Fig. 2.3.10.
In Section 2.3.4, harmonics involving the VGA has been mentioned. The
corresponding simulation results with inputs of 90 mV (20 dB gain), 225 mV (12 dB
gain) and 900 mV (0 dB gain) with input voltage swings of 900 mV, 225 mV, and 90
mV, respectively, are depicted in Fig. 2.3.11, from top to bottom. 1024 samples were
taken in each DFT from the transient simulation of 1 μs. DC component is omitted.
Noise performance is shown in Fig. 2.3.12. It is apparent that the VGA is less noisy
when consuming more current.
48
30
25
dB
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Gain Control Voltage (V)
Fig. 2.3.9 Gain control voltage vs. Gain (in dB).
30
20
10
26 dB / 100 MHz
13 dB / 250 MHz
0
0 dB / 400 MHz
dB
-10
-20
-30
-40
-50
-60 00
10
01
10
02
10
03
10
04
10
05
10
06
10
Frequency
Fig. 2.3.10 Bode plot
49
07
10
08
10
09
10
10
10
11
10
Component Ratio
0.6
0 dB
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
Frequency (MHz)
(a)
Component Ratio
0.6
12 dB
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
Frequency (MHz)
(b)
Component Ratio
20 dB
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
Frequency (MHz)
(c)
Fig. 2.3.11 The DFT of VGA output at gains of (a) 0 dB, (b) 12 dB, and (c) 20 dB.
50
7
0 dB
Vn2
-08
4.50x10
-08
3.00x10
-08
1.50x10
00
0.00x10
00
10
01
10
02
10
03
10
04
10
05
10
06
10
07
10
08
10
09
10
10
10
11
10
Frequency (Hz)
(a)
Vn
12 dB
2
-07
2.00x10
-07
1.00x10
00
0.00x10
00
10
01
10
02
10
03
10
04
10
05
10
06
10
07
10
08
10
09
10
10
10
11
10
Frequency (Hz)
(b)
Vn
26 dB
2
-06
2.00x10
-06
1.00x10
00
0.00x10
00
10
01
10
02
10
03
10
04
10
05
10
06
10
07
10
08
10
09
10
10
10
11
10
Frequency (Hz)
(c)
Fig. 2.3.12 The noise performance of the VGA working at (a) 0 dB, (b) 12 dB, and (c)
26 dB, respectively.
51
A tabulated comparison of this AGC along with other prior works is shown in
Table 2.3.1. This table suggests that the proposed AGC has the lowest power
consumption, and lowest supply voltage. Our design also has the largest output swing,
largest gain per stage, large input swing, fast response time, and wide bandwidth. The
response time of 250 ns can be made even shorter by increasing the frequency of the
Reset signal shown in Fig. 2.3.3 at the expense of extra power consumption. On the
other hand, if the input signal amplitude does not vary in a fast function, the Reset
signal can be made slower, or be event-driven by downstream digital circuits to
conserve power dissipation.
Table 2.3.1 Comparison with Prior Works
Proposed
[17]
[19]
[21]
[22]
[25]
[28]
Gain (dB)
0 to 26
dB
0 to 95
-10 to 17
-17 to 16
-8 to 32
-10 to 50
2 to 24
Stages
1
2+1
CGA†
2
5
2
Bandwidth
100 MHz
Min.
32 MHz
1.25
GHz
470 MHz
Min.
18 MHz
200 ns
N/A
1.6 μs
N/A
5.6 μs
20μs
~1 Vp-p
N/A
N/A
N/A
1.8 V
1 Vp-p
N/A
N/A
500 mV
Vp-p
0.75 V
0.0024
0.4
0.0887
0.3182
0.563
0.45
0.3844
1V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Response
Time
Input
Swing
Output
Swing
Core Area
(mm2)
Supply
Voltage
550 mV
Vp-p
160 mV
Vp-p
2+1
CGA†
18 MHz
Min.
3
4 GHz
200 ns
60 mV
Vp-p
400 mV
Vp-p
Power
400 μW
6.48 mW 43.2 mW
22 mW
11.6 mW
2.178
mW
84 mW
Process
0.18 μm
0.18 μm
0.18 μm
0.18 μm
0.18 μm
0.18 μm
0.18 μm
Year
2010
2006
2008
2007
2008
2010
2009
†CGA =
Constant Gain Stage
52
2.4
1-dB Gain Step PGA
2.4.1
Implementation of a ZigBee receiver
Differential
to Single
LNA
PGA
PGA
ADC
0°
Baseband
90°
Differential
to Single
PGA
0, 1, 2, 3 dB
0, 4, 8, 12 dB
PGA
ADC
0, 16, 32 dB
The Implemented ZigBee Receiver
Fig. 2.4.1 A ZigBee receiver
ZigBee is a wireless networking protocol mainly developed by the ZigBee Alliance.
It provides a low speed, low power, low cost solution supporting a large number of
network nodes and multiple network topologies. Because of this nature, Direct
Conversion (Zero-IF) architectures are used whereas superheterodyne architectures are
adopted in other 2.4 GHz solutions, i.e., Bluetooth.
While a few ZigBee receiver circuits have been reported in literature [49] - [51], no
such receivers have never been designed and implemented by any academic institute in
Taiwan. To investigate the possibility of implementing ZigBee receivers with a
domestic team, PGAs and active filters are fabricated along with other components of a
ZigBee receiver, targeting to provide a complete ZigBee solution in the future. However,
only the PGAs and the Multiple Feedback (MFB) active low pass filters (LPF) are
discussed in this thesis. The local oscillator, LNA, and Mixers contributed by other
individuals are left as open questions.
53
2.4.2
vb2
Operational amplifier
vb1
Floating
Current
Source
P-type
Input
Stage
v-
vb3
vb1
v
vb2
+
N-type
Input
Stage
Floating
Current
Source
vb1
vb2 Push-Pull
Stage
vb3
vout
vb2
Gain
Stage
Fig. 2.4.2 A rail-to-tail operational amplifier.
The operational amplifier serves as a key building block to carry out the design of
PGAs and MFB LFPs. The operational amplifier used in this section incorporates both
an N-type and a P-type input stage. The currents produced by the N-type and P-type
input stages are summed at the cascoded current mirror of the gain stage. To make the
bias current less dependent on the supply voltage, a floating current source was
proposed [52] to bias the gain stage. In this work, the N-type and P-type input stages are
also biased this way to reduce the sensitivity of transconductance against the supply
voltage. The gain stage is cascaded by the push-pull stage, which also provides
frequency compensation to the operational amplifier. Since the maximum closed-loop
gain used in this section is 32 dB, which is well below the DC gain of 110 dB of this
amplifier operating using only the N-type or P-type input stage, constant
transconductance regulation is not included to save area and reduce power consumption.
Bias voltages vb1, vb2, and vb3 are provided off-chip. Notably, they can be generated by a
bandgap reference generator as well.
54
2.4.3
Multiple feedback filter
RII
RI
CI
RIII
Vo,LPF
OPLPF
CII
Vin,LPF
Fig. 2.4.3 An active Multiple Feedback Filter [53].
A MFB topology is useful for realizing filters with high quality factors, Q, for
bandpass filters [53]. As can be seen from Fig. 2.4.3, RII provides a positive feedback
path that can be modified to control Q. However, it is useful for realizing LPFs as well.
st
RI and C II forms a 1 order RC passive LPF, while RIII C I , and OPLPF forms a
1st order integrator, which can also be interpreted as an active LPF.
The transfer function [54] of a MFB can be described as:
K
T (s )
s
0
2
0
Q
2
s
(2.4.1)
0
2
where
RII
RI
K
1
0
RII RIIIC IC II
55
(2.4.2)
(2.4.3)
C II
CI
Q
1
RII RIII
RI
RIII
RII
(2.4.4)
RII
RIII
From Eqn. (2.4.2) to (2.4.4), we can attain the following equation if we normalize
C I and C II as 1 F:
RII
K
RI
2
RII
1
(2.4.5)
K
(2.4.6)
2
0
0
Q
Q
4C I
1
0RII
RIII
0
2
1
K
(2.4.6)
For LPFs, Q is not a concern, and RI , RII can be easily obtained using Eqn.
(2.4.2) and (2.4.5), and RIII with Eqn. (2.4.6). RI , RII , and RIII can later be
de-normalized corresponding to C I and C II . In this implementation, 2 stages of
cascaded MFB LPF are used, which provide an overall 80 dB/decade after the cut-off
frequency.
56
2.4.3
Design of a programmable gain amplifier
Difference
Amplifier
Vinpos
OPpos
OPneg
Vdtos
Vinneg
resistor array
Fig. 2.4.4 A programmable gain differential to single amplifier.
As shown in Fig. 2.4.1, the ZigBee receiver includes two differential-to-single
amplifiers in charge of converting the differential output signals of the mixers into
single-ended signals. By converting differential signals to single-ended signals, the
layout area of LPFs can be conserved considerably, since the required number of
passive devices is halved. The differential-to-single amplifier in Fig. 2.4.4 consists of
two non-inverting amplifiers formed by OPpos and OPneg , which provides infinite
input resistance for signal source Vinpos and Vinneg . The gain of these non-inverting
amplifiers is determined by the resistor array, which can be 0 dB, 1 dB, 2 dB, and 3 dB.
Gain range is made low so that the high frequency components will not saturate the
channel. The cascaded unity-gain difference amplifier substracts the voltage output of
57
Vo,PGA
Vin,PGA
resistor array
Fig. 2.4.5 A non-inverting programmable gain amplifier.
OPpos with the voltage output of OPneg , and produce Vdtos , which will be amplified
in cascaded stages. Due to its Instrument Amplifier (IA)-like structure, CMRR is
inherently high. High CMRR can suppress DC offset of the mixers, preventing the
unwanted DC component from being amplified in the cascaded stages. As illustrated in
Fig. 2.4.1, the differential-to-single amplifier is succeeded by MFB LPF shown in Fig.
2.4.3, which in turn is cascaded by a PGA shown in Fig. 2.4.5. It provides 0 dB, 4 dB, 8
dB, and 16 dB of programmable gain, depending on the resistor array configuration.
Followed by the PGA are a MFB LPF which further attenuates out-of-band components,
and another PGA which provide 0 dB, 16 dB, 32 dB of gain. This makes the overall
gain tuning range to be 47 dB, with 1 dB gain step (GS). Recall that from Fig. 2.4.1, this
work is intended to drive the capacitive load of an analog-to-digital converter (ADC).
Hence, an analog unity-gain buffer stage is used to drive the 8 pF input capacitance of
an ADC through a 3 mm bonding-wire with parasitic inductance of 1 to 3 nH. The
transient response from an input Fig. 2.4.8 is shown in 2.4.9. A performance comparison
is shown in Table 2.4.1, while the overall performance of the ZigBee receiver is
tabulated in Table 2.4.2.
58
1 to 3 nH
Vo,buf
Vin,buf
8 pF
Fig. 2.4.6 Output buffer.
40
20
Gain (dB)
0
-20
-40
-60
-80 00
10
10
01
10
02
10
03
10
04
10
Frequency (Hz)
Fig. 2.4.7 The simulated Bode plot.
59
05
10
06
10
07
1.8
1.6
(V)
1.4
1.2
1
0.8
0.6
0.4
0
0.5
1
1.5
2
2.5
μs
3
3.5
4
4.5
5
4.5
5
Fig. 2.4.8 The simulated differential output of a mixer.
1.8
1.6
1.4
(V)
1.2
1
0.8
0.6
0.4
0.2
0
0.5
1
1.5
2
2.5
μs
3
3.5
4
Fig. 2.4.9 The simulated signal after filtering and amplification.
60
Table 2.4.1 Comparison with Prior Works
Proposed
[27]
[30]
[31]
0 to 47 dB
-15 to 60
-30 to 40
-22 to 30
1 dB
2 dB
2 dB
1 dB
Stages
5
3
3
3
Bandwidth
3-MHz
140 MHz
95MHz
17 MHz
Input Swing
1.8 Vp-p
N/A
N/A
N/A
1.8 Vp-p
N/A
N/A
N/A
0.567†
0.06
0.286
0.72
1.8 V
1.8 V
3.3 V
1V
Power
9 mW†
11.85 mW
32.7 mW
2.178 mW
Process
0.18 μm
0.18 μm
0.35 μm
0.35 μm
Year
2010
2007
2005
2008
Gain (dB)
Gain Step
(dB)
Output
Swing
Core Area
(mm2)
Supply
Voltage
†
Including filters and output buffers for both I/Q channels.
61
Table 2.4.2 ZigBee Overall Performance
LNA S11 @ 2.45 GHz
-43.688 dB
LNA S22 @ 2.45 GHz
-11.967 dB
LNA Gain @ 2.45 GHz
17.376 dB
Noise Figure
LNA:
2.712 dB
Mixer:
5.074 dB
Mixer Gain:
Out-of-channel IIP3
7.876 dB
-7.234 dBm
PLL Phase Noise
1 MHz:
-127 dBc/Hz
3 MHz:
-137.7 dBc/Hz
10 MHz:
-148.2 dBc/Hz
PLL Lock Time @ 2.45 GHz
<20 μs
VCO Gain
130 MHz/V
PLL Bandwidth
200 kHz
Max. VGA Gain
47 dB
Min. VGA Gain
0 dB
Filtered VGA Bandwidth
2 MHz
2
Active Core Area
3.5 mm
88 mW
Total Power:
LNA:
53 mW
Mixer:
5 mW
PLL:
21 mW
VGA, Filter, Buffer:
9 mW
62
2.5
Summary
In this chapter, the derivation on constant gain settling time of AGCs has been
discussed. A low power Variable Gain Amplifier (VGA) circuit with an approximation
to exponential gain characteristic has been presented in Section 2.2. It has been
achieved using current mirrors to generate appropriate current signals to bias the input
stage of the VGA circuit working in triode region, and the output stage working in
saturation region, respectively. The presented VGA circuit comes with a 549 μW
maximum power consumption given a 1.8 V supply. It has a linear-in-dB 48-dB
dynamic gain range (DR) per stage, which is suitable for direct-conversion (Zero-IF)
architectures. The effect of the input trasconductance and the output resistance on the
linearity of gain control has also been discussed. It was fabricated using a 0.18 μm
standard CMOS process with a core area of 0.0045 mm2. In Section 2.3, an AGC circuit
operating at 1 V supply with 200 to 530μW average power consumption has been
described. The included AGC comes with 0.9 V input and output stages and has a
minimum bandwidth of 100 MHz. Feed-forward Output Swing Prediction (FROST) is
used to adjust the gain of the VGA corresponding to the signal envelope detected by a
Parallel-Detect Single-Store Peak Detector (PDSSPD). With an appropriate refresh rate
control, the AGC is capable of adjusting the gain of the VGA within less than 250 ns
when the input signal envelope is reduced by 20 dB, and 100 ns when raised by 20 dB.
The circuit design has been carried out using the TSMC 0.18 μm standard CMOS
process with a core area of 0.0024 mm2. Finally, a 47 dB DR Programmable Gain
Amplifier (PGA) for digital AGCs has been presented in Section 2.4. It is cascaded with
Multiple Feedback Low Pass Filters (MFB LPF) and shows a -3 dB bandwidth of 3
63
MHz. These circuits provide a gain roll-off of 80 dB/decade after the cut-off frequency.
After acquiring the receiver signal strength indicator (RSSI), a digital baseband circuit
can adjust the gain of the PGA with resolution of 1 dB/step. The circuit design is carried
out using the TSMC 0.18 μm standard CMOS process with a core area of 0.567 mm2.
64
Chapter 3: HV IC DESIGN
3.1
High Voltage IC Design Overview
3.1.1
0.25 μm BCD 60 V process overview
60 V
5V
60 V
5V
60 V
60 V
(b)
(a)
Fig. 3.1.1 The maximum voltages of (a) N-type, and (b) P-type LDMOS allowed.
5 V Circuits
N-type
LDMOS
P-type
LDMOS
Depleted
NMOS
2.5 V Circuits
Diodes
Resistors
Capacitors
Fig. 3.1.2 A layout floor plan for devices with different voltage tolerant abilities.
The TSMC 0.25 μm BCD 60 V process offers a variety of devices that can meet
the requirement of various applications. Low voltage analog circuit designs as well as
cell-based standard digital library designs can be carried out using 0.25 μm standard
65
CMOS. 0.5 μm standard CMOS can be used to realize high quality analog circuits
operating at a power supply of 5 V. LDMOS transistors can support up to 60 V, making
them useful for high voltage applications. Diodes are available for both high voltage
domain and low voltage domain. High resistivity resistors with 1 kΩ/□ are available,
making it feasible to realize resistors with large resistance using small silicon area [15],
[16]. It is important to point out that N-type and P-type LDMOS transistors are
asymmetrical devices. Hence, the maximum sustainable voltages between the three
terminals are not equivalent. As depicted in Fig. 3.1.1, the gate-drain and drain-source
voltages can endure up to 60 V, but the maximum voltage between gate and source is
strictly limited to 5 V.
Since the voltage different devices can sustain are different, it is important to
isolate them in their respective wells. Isolation is achieved by connecting the guard
rings to the system voltage supplies and ground. As shown in Fig. 3.1.2, 2.5 V circuits,
5 V circuits, and LDMOS transistors are separated in their respective wells. Each
LDMOS transistors generally must have their own individual wells, unless for specific
applications where two LDMOS transistors are cascoded. Well-sharing of low voltage
diodes as well as other low voltage circuits is acceptable, while high voltage diodes
must also have their own individual wells. Resistors can reside in the same well with
other low voltage circuits. However, keeping resistors in their independent wells can
help shielding them from unwanted interferences. Capacitors, on the other hand, can be
placed both inside and outside of any wells. As with the resistors, by placing the
capacitors in independent wells also help shielding against unwanted interferences.
66
3.1.2
Voltage signal conversion
Fig. 3.1.3 A SoC with 2.5 V, 5 V circuits, and high voltage devices.
With the help of the TSMC 0.25 μm BCD 60 V process, integration among
different devices, namely, 0.25 μm, 0.5 μm, and high voltage transistors allows a
multiple voltage system to be implemented on a single chip, as shown in Fig. 3.1.3.
Converting an analog voltage signal from the 2.5 V circuit domain and amplifying it
into the 5 V circuit domain can be achieved with operational amplifiers designed using
0.5 μm transistors without too much difficulty. However, problems arise when
attempting to convert an analog voltage signal from the circuits in the 5 V domain and
amplify it into a signal of large voltage swing in the high voltage domain, i.e., 60 V. A
major contribution to the difficulty lies in the design of these operational amplifiers.
First of all, the high voltage transistors offered in this process are bilateral devices. The
gate to source voltage is limited to a low voltage of 5 V even when their drain to source
voltage can sustain up to 60 V. Thus, it would be meaningless to design the input stage
of an operational amplifier with high voltage transistors. Also recall that each high
voltage transistor requires an independent isolation ring, which can make the actual
67
layout area several times larger than the intended dimensions of high voltage transistors.
By contrast, all the 5 V transistors can all be fitted into a single isolation ring.
Apparently, we can achieve smaller layout area using 5 V transistors. That is, we can
avoid using an excessive number of high voltage transistors, especially if their
functionalities can be achieved using 5 V transistors. Thus, the stages of an operational
amplifier should be divided into a 5 V voltage domain and a high voltage domain.
Furthermore, the Metal-Insulator-Metal (MIM) capacitors offered in this process are not
meant to sustain high voltage. This fact prevents the use of Miller capacitors which
connect one of its nodes to the output of the operational amplifier working in the high
voltage domain, while the other is connected to the node in the 5 V voltage domain.
To resolve this problem, the feed-forward compensation schemes that do not
require any Miller capacitor proposed in [55] may seem promising at first.
Unfortunately, such frequency compensation schemes would require additional high
voltage transistors. Furthermore, according to many prior empirical experiments, the
measurement results of these high voltage transistors often deviate from the
characteristic obtained through simulations. It will cause a problem to carry out
pole-zero cancelation, which is the main idea of feed-forward compensation. The
doublets caused by pole-zero mismatches further worsen the settling time of the
operational amplifier. For the sake of robustness, such a compensation scheme should
be avoided. In comparison with high voltage transistors, the characteristics of 0.5 μm
transistors are found to be more consistent. Hence, reliability of the frequency
compensation can be ensured if the compensation is merely carried out in the 5 V
voltage domain.
68
3.2
DIFC Amplifier
3.2.1
Small-signal design
gmcb
Cm
Rcb
+
Vin
-
gmout
Vout
gm1
Rout1
Cpar1
gm2
Rout2
Cpar2
gmff
Rout
CL
offering
voltage
Fig. 3.2.1 The proposed DIFC topology.
To
design
an
operational
transconductance
amplifier
level-converting in a Multiple-Voltage SoC, a novel frequency compensation scheme is
proposed. This scheme solely performs compensation in 5 V voltage domain. The Miller
capacitor, C m , is entirely positioned in the 5 V voltage domain. Additional discussions
on applying feed-forward compensation to the proposed Domestic Indirect Feedback
Compensation (DIFC) amplifier are also taken into account. Simulation results of gain,
frequency response, distortion and slew rate are reported to demonstrate the
performance of this operational amplifier. Device dimensions of both 0.5 μm transistors
and high voltage transistors are provided for reference.
The small signal model of the proposed DIFC amplifier without the grey
feed-forward amplifier is shown in Fig. 3.2.1, and the transfer function can be obtained
using KCL.
69
ADC
Av (s )
s2
s
(1
(1
3
s
s
s2
1
3
2
4
4
s
5
)
s5
6
(3.2.1)
)
7
The symbols shown in Eqn. (3.2.1) are defined by Eqn. (3.2.2) - (3.2.9), and some
of the expressions are approximated by truncating terms that are relatively much smaller
than the others.
ADC
gm1gm 2gmout Rout 1Rout 1Rout
1
1
C mRout 2
(3.2.3)
RcbC m
1
2
3
2C mRout 2
(3.2.4)
RcbC m2 Rout 2
C LRout
1
C mgm 2gmcbRout 1Rout 2Rcb
1
4
gm 2gmcbRout 1Rout 2RcbC m (C LRout
2
C mRout
2)
1
5≈
2
C LC m2 gm 2gmcbRout 1Rout
2Rout Rcb
1
6≈
C LC m2 Rout 2RcbRout (C par 2Rout 2
2C par 1Rout 1 )
1
7
2
C par 1C par 2C LC m2 Rout1Rout
2RcbRout
70
(3.2.2)
(3.2.5)
(3.2.6)
(3.2.7)
(3.2.8)
(3.2.9)
The dominant pole can be approximated to:
1
| p-3dB | ≈
C mgm 2gmcbRout 1Rout 2Rcb
(3.2.10)
Hence, the gain-bandwidth product can be approximated by:
ADC | p-dB | ≈
2 GBW
t
gm1gmout Rout
C mgmcbRcb
(3.2.11)
If the grey feed-forward amplifier is taken into account, (3.2.1) becomes:
ADC
s2
s
(1
1
Av (s )
f1
2
s
(1
3
s2
s
s2
s3
4
5
)
f2
4
s
6
AFF (1
s5
s
f3
)
(3.2.12)
)
7
and
AFF
gm1gmff Rout1Rout
1
f 1≈
C mRout 2
f 2≈
f 3≈
RcbC m
1
RcbC m2 Rout 2
1
C m (Rout 2
Rcb )
(3.2.13)
(3.2.14)
(3.2.15)
(3.2.16)
The denominators of Eqn. (3.2.1) and (3.312) are the same, except the fact that
C par 1 will be slightly increased. The added terms of the numerator in Eqn. (3.2.12) is
composed of the additional DC gain contributed by Eqn. (3.2.13) and the zeros
71
contributed by Eqn. (3.2.14), (3.2.15), and (3.2.16). As will be revealed later, the
addition of the feed-forward stage does not affect Rout . The gain-bandwidth product
can be doubled, while still maintaining the same phase margin of 85 degrees. However,
the addition of the gmff is not always beneficial. This will be addressed later. A
complete list of system parameters are tabulated below.
Table 3.2.1 System Parameters
gm1
2.15μ
gm2
19.03μ
gmout
457.7μ
gmcb
2.56μ
gmff
501μ
Rout1
565 MΩ
Rout2
2.25 MΩ
Rout
240 kΩ
Rcb
1.09 MΩ
Cm
577 fF
72
3.2.2
Circuit level design
VDD,5V
Vb1
MLP0
MLP3
MLP4
gmcb
Vb2
MLP1
gm1
Cm
MLP5
MLP2
MLP11 g
m2
Rcb
Mcb
Vo1
Rout1
Vb3
MLN7
Rout2
MLN8
Vb4
MLN9
MLN10
Vb5
MLN12
VDD,HV
MHP15
MHP13
Vout
Rout
RFA
gmout
MHN16
gmff
Vb6
or Vo1
MHN14
RS
Vfb
CL
RFB
Fig. 3.2.2 Schematic of the DIFC amplifier.
As shown in Fig. 3.2.2, the proposed DIFC amplifier consists of two 5 V stages
and a high voltage stage. The first stage, gm1 , is realized using a classical folded
cascode differential amplifier consisting of 0.5 μm transistors MLP1 to MLN10. The output
73
resistance, Rout 1 is made large to produce a high RC time constant. 0.5 μm transistors
MLP11 and MLN12 constitute gm 2 , i.e., a common source amplifier used to provide large
DC gain and multiply the Miller capacitor, C m . The two terminals of this capacitor are
coupled to the output of the common source amplifier and the source of Mcb to avoid
creating the RHP zero, which would appear if the terminal is coupled to the output of
the classical folded cascode differential amplifier. This forms the domestic indirect
feedback path. Mcb serves as a current buffer with a transconductance of gmcb , which
also prevents the high frequency shorting effect of the output terminals of the folded
cascode differential amplifier and the common source amplifier.
The high voltage part of this operational amplifier has 2 high voltage N-type
transistors, MLP14, MLP16 (NLD60G5 1 μm transistor in 0.25 μm BCD process), and 2
P-type transistors, MLP13, MLP15 (PA60G5 0.8 μm transistor in TSMC 0.25 μm BCD
process). Depending on configuration, the gate of MLP14 is either connected to the output
terminal of the folded cascode differential amplifier, Vo1 , or to a bias voltage Vb 6 . If it
is connected to Vb 6 , it will provide a DC bias current to MLP13, and mirrored to MLP15.
MLP16 serves as gmout , which is the third stage of the operational amplifier using MLP15
as an active load. The output resistance of the third common source stage is kept small
to prevent loading effect of the operational amplifier when driving resistors.
Furthermore, an external source degeneration is added to MLP16 to adjust gmout
corresponding to any possible process variation. Feedback resistors, RFA and RFB
with values of 220.1 kΩ and 19.9 kΩ, respectively, are selected to reduce the quiescent
current consumption caused by the DC path these resistors introduced. The output
resistance of the DIFC operational amplifier, Rout is the shunt resistance of RFA +
RFB with roHN 16 and roHN 15 . By coupling the gate of MLP14 to Vo1 , the
74
feed-forward stage, gmff , is realized. Since its transconductance is mirrored to the
output through current mirror formed by MLP13 and MLP15, Rout will not be affected.
However, due to the uncertainty in transconductance of high voltage transistors,
implementing the feed-forward stage might result in undesired pole-zero doublets,
prolonging settling time of the operational amplifier. It is clearly evident by inspecting
Eqn. (3.2.12), (3.2.13), and (3.2.16) that if the zero dominated by gmff is shifted to
high frequency, the stability of the operational amplifier may possibly be jeopardized.
Similarly to other multi-stage operational amplifiers [56], [57], the slew rate of this
amplifier is constrained by the slowest stage. Generally, the slew rate can be estimated
with:
SR
I
I
min( D1 , Dout )
Cm C L
(3.2.17)
where I D1 and I Dout represent the currents of the folded cascode differential
amplifier and the output stage, respectively. Apparently, Eqn. (3.2.17) is dependent of
the capacitive load driven by the operational amplifier.
The device parameters used in this operational amplifier are shown in Table II.
Table 3.2.2 Device Parameters (dimensions are in μm)
MLP0
0.7
1
MLP1
1
1
MLP2
1
1
MLP3
0.6
2.4
MLP4
0.6
2.4
MLP5
8
0.5
Mcb
8
0.5
MLN7
0.6
1.5
MLN11
1.65
0.5
MLN12
0.6
1.5
MLN13
70
0.8
MLN14
8
3
MLN15
70
0.8
MLN16
4.4
1
Cm
Rs
RFA
RFB
CL
577 f
900
220.1k
19.9 k
10 p
75
MLN8
0.6
1.5
MLN9
0.73
1.5
MLN10
0.73
1.5
3.2.3
Simulation of the DIFC amplifier
60
Output Voltage (V)
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Time (ms)
Fig. 3.2.3 The slew rate with (gray) and without (black) feed-forward stage.
This design is carried out using TSMC 0.25 μm 1-poly-3-metal BCD process. It
consumes 15 μW from the 5 V supply and 127.7 mW from the 60 V supply. As shown
in Fig. 3.2.3, the slew rate is 3.6 V/μs. However, it will require an additional delay of 48
μs for the output stage to charge the capacitive load. The simulation result in Fig. 3.2.4
suggests that the gain-bandwidth of this operational amplifier is 2.6 MHz and 1.3 MHz
with or without the feed-forward stage, respectively. Both configurations have a phase
margin of 85 degrees. DC gains are 133 dB with the feed-forward stage and 128 dB
without the feed-forward stage, respectively. The feed-forward stage has minor
significance discharging the capacitive load. By performing discrete Fourier transform
(DFT) on the output waveform of the operational amplifier, we can assume that the
distortion caused by this operational amplifier is negligible by inspecting Fig. 3.2.5.
Overall system specifications are tabulated in Table 3.2.3.
76
150
Gain (dB)
100
50
0
-50
-100
-150 -06 -05 -04 -03 -02 -01 00 01 02 03 04 05 06 07 08 09 10 11
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz)
0
-50
Phase (degree)
-100
-150
-200
-250
-300
-350
-400
-450 -06 -05 -04 -03 -02 -01 00 01 02 03 04 05 06 07 08 09 10 11
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz)
Fig. 3.2.4 The Bode plot of proposed operational amplifier
with feed-forward stage (gray) and without (black).
77
25
Magnitude
20
15
10
5
0
0
10000
20000
30000
40000
50000
60000
Frequency (Hz)
Fig. 3.2.5 DFT of a 10 mHz sine wave output with a 50 V voltage swing.
Table 3.2.3 System Specification
GBW
2.6 / 1.3 MHz
Power
15 μW + 127.7 mW
VDD
5 V, 60 V
CL
10 pF
ADC
133 / 128 dB
PM
85°
GM
24 dB
SR
3.6 V/μs
78
3.3
60 V Charger Design
3.3.1
Charger architecture
Bulk Charger
(a)
Bulk Charger
Small
Charger
Small
Charger
Small
Charger
Small
Charger
Small
Charger
Small
Charger
(b)
(c)
Fig. 3.3.1 (a) Bulk charger, (b) small chargers, and (c) combination of both.
Traditionally, battery chargers dedicated to charge series connected lithium-ion
batteries are implemented using inductors, capacitors, transformers, power transistors,
analog or digital controllers, and many other discrete devices. Basically, battery charger
topologies used to charge series connected batteries can be sorted into three categories.
These topologies include a bulk charger that charge all the batteries, a series of small
chargers that independently charge their respective batteries, or a combination of both,
as illustrated in Fig. 3.3.1 [59]. To take full advantage of the HV tolerance offered by
this process, the bulk charger topology is selected for exemplification. Although
balanced charging by the bulk charger is not inherently achieved without a series of
small chargers, it can be easily enhanced with the inclusion of a battery management
79
Charger
(This Work)
DC/DC
Converter
AC/DC
Converters
DC/DC
Converters
BMS
Fig. 3.3.2 Architecture of the battery charger.
system (BMS) chip or system which actively balance and redistribute energy among the
batteries. A complete embodiment of the system shown in Fig. 3.3.2 would also require
AC/DC and DC/DC converters to provide a voltage dedicated for the charger so that
high charging efficiency can be achieved throughout the charging sequence [35].
3.3.2
Embodiment of the proposed charging solution
As depicted in Fig. 3.3.2, a complete battery charging system should at least
include a BMS, AC/DC Converters, DC/DC Converters, and a bulk charger [59]. The
BMS is in charge of balancing the serially connected Li-ion batteries. The AC/DC
Converter and DC/DC Converters are used to provide power for both the charger and
80
DC/DC Vref,DC/DC
Converter
Charger
MP-var
VDD-var
_
EAref
+
1.2 V
Fig. 3.3.3 Regulation of the difference between VDD-var and Vbat.
the BMS. Since the DC/DC converter in Fig. 3.3.3 should provide a variable voltage for
the charger, its reference voltage, Vref,DC/DC, is made variable as well. This is achieved
by connecting the negative node of an error amplifier, EAref, to VDD-var - Vbat. The
difference between VDD-var and Vbat can be regulated at 1.2 V by adjusting the duty cycle
of the associated DC/DC converter. Hence, an appropriate VDD-var is supplied to the
proposed charger.
3.3.3
IC, CC, and CV charge modes
During the initial charging sequence, it may be inappropriate to charge deeply
uncharged batteries with a high current. The trickle current (TC) mode [35] can resolve
this problem by sourcing a smaller current to the battery. Then, the entire system is
switched to CC mode when the battery voltage reaches a predefined value, as shown in
Fig. 3.3.4 (a). In practical scenarios, the charger circuit fabricated on a chip must be
packaged, thereby introducing parasitic inductance on the bond-wires with a value
81
Charging
Current
Trickle
Current
Mode
Constant
Current
Mode
Constant
Voltage
Mode
Charging
Process
Terminated
Constant
Voltage
Mode
Charging
Process
Terminated
Battery
Voltage
(a)
Charging
Current
Incremental
Current
Mode
Constant
Current
Mode
Battery
Voltage
(b)
Fig. 3.3.4 Current vs. voltage for chargers with (a) TC and (b) IC mode.
ranging from 1 nH to 3 nH on the charging path. The parasitic inductance depends on
the length of the bond-wires, which cannot be easily estimated before the chip is
packaged. If both the parasitic inductance and the charge current are large enough, a
sudden switch from the TC mode to the CC mode will result in an inductive kickback,
melting both the bond-wires and the connected pads, as shown in Fig. 3.3.5. To prevent
such catastrophes, the TC mode is modified into the incremental current (IC) mode, as
shown in Fig. 3.3.4 (b). The charging current becomes a function of the battery voltage.
82
Melted bond-wires
and bond pads
Fig. 3.3.5 The aftermath of inductive kickback.
More specifically, the charging current increases gradually as the battery voltage
increases. However, this charging current does not increase unlimitedly. It is clamped at
a predefined value, which the charger enters the CC mode without a discontinuous
transition with respect to the charging current.
3.3.4
CV loop and diode-based CC clamp
As depicted earlier in Fig. 1.3.6, the sudden switching from CC and CV mode is a
hazardous problem. Apparently, smooth charge mode transition between CC to CV
modes is essential to the stability of a charger. To elegantly resolve this problem, the CV
regulating loop should be able to clamp the maximum output charging current. In other
words, the CC and CV feedback loops are combined into one, which has been reported
in [38]. As shown in Fig. 3.3.6(a), this scheme consists of a linear dropout regulator
83
VDDHV
VDDHV
To
Battery
Packs
D1
Constant Current Clamp
Vcvref
Vcv
Vcvfb
EAcvfb
Ihvcs
DN
MPower
Constant Current Clamp
ICharge
Vcvref
Mhvcs
Vcv
Vcvfb
Rcvs
To
Battery
Packs
Mccc
Ricfb
EAcvfb
Ihvcs
Iccc
MPower
ICharge
Mhvcs
Rcvs
Rcvfb
Ricfb
Rcvfb
Constant Voltage Controller
Constant Voltage Controller
Fig. 3.3.5 (a) CV loop and diode as CC clamp [38],
and (b) CV loop and diode-connected load as CC clamp.
(LDO)-like Constant Voltage Controller and a series of diodes D1 to DN, where N is the
number of diodes. In CV mode, the charger behaves analogously to a typical LDO. An
error amplifier, EAcvfb, is used to generate an error voltage, Vcv, based on the difference
of the shunt-feedback battery voltage Vcvfb and the reference voltage Vcvref. Vcvref is
responsible of driving the cascaded level shifter which in turn biases the Power MOS,
MPower, so that an appropriate amount of current is regulated into the battery.
When Vcvfb is far lower than the predefined Vcvref,, Vcv is pulled up near the supply
voltage of EAcvfb, and Mhvcs will attempt to pull the gate of MPower all the way to ground.
However, since Mhvcs is designed with the minimum width and long length in dimension,
and it is also source-degenerated with Rcvs, its current sinking ability is limited. Hence,
the diodes D1 to DN will clamp the gate of MPower at a value of VClamp lower than VDDHV.
This can ensure that the maximum value of ICharge is limited to a finite value governed
by:
84
1 'W
K
V
2 p L Clamp
ICharge
1 'W
K
N
2 p L
2
Vthp
VDon
Vthp
2
(3.3.1)
As revealed in Eqn. (3.3.1), the absolute resistance value of Rcvs does not affect the
charging current, as long as the diodes can be turned on. The sensitivity of the charging
current with respect to the voltage variation over the diode string is given as follows.
ICharge / ICharge
I
SNCharge
V
Don
Vthp
(N
VDon
Vthp ) / (N
ICharge
(N
VDon
K p'
N
Vthp )
W
N
L
VDon
ICharge
VDon
VDon
Vthp )
Vthp
ICharge
Vthp
2
2
(3.3.2)
This indicates that the charging current ICharge is sensitive to both VClamp and Vthp by
a factor of 2. For example, if VClamp - Vthp is only 80 % of the desired value (20 %
variation), ICharge becomes 64 % of the anticipated maximum charging current (36 %
variation). Hence, the actual charging current will deviate greatly from simulation
results. This also explains the low charging current and, consequently, the low
efficiency of the charger proposed in [38].
85
3.3.5
CV loop and diode-connected load as CC clamp
9
8
7
Ihvcs (μA)
6
5
4
3
2
1
0
10
20
30
40
50
Rcvs (Ω)
60
70
80
90
100
Fig. 3.3.6 Relationship between Ihvcs and Rcvs.
To avoid such an undesired deviation, the voltage clamp should be made adjustable
after the charger has been fabricated on silicon to account for process variation. Instead
of placing serially connected diodes to clamp the voltage, a diode-connected power
PMOS Mccc is used, as shown in Fig. 3.3.5(b). According to the following equations,
Vcv
Iccc
Vgs,hvcs
I hvcs
I hvcs
Rcvs
1 ' W
K ( )(Vgs,hvcs
2 n L
5
(3.3.3)
Vthn )2
(3.3.4)
we attain
VClamp
2Vgs,hvcs
10
Rcvs
86
K p'
Vthp
(3.3.5)
6.2
6
Ihvcs (μA)
5.8
5.6
5.4
5.2
5
0
10
20
30
40
50
60
70
Temperature (°C)
80
90
100
Fig. 3.3.7 Relationship between Ihvcs and temperature.
where Vgs,hvcs is the gate-source voltage of Mhvcs, Vcv is the gate voltage of Mhvcs pulled
up to the supply voltage value of 5 V, and 10 is two times of the 5 V supply voltage.
Evidently, the maximum gate-source voltage VClamp of Mccc and MPower is no longer a
fixed value, but an adjustable voltage determined by the resistance value of Rcvs. The
nonlinear relationship between Ihvcs and Rcvs is plotted in Fig. 3.3.6.
This implementation can also be interpreted as a current mirror copying the current
that flows through Rcvs, multiplying the current by the aspect ratio of MPower vs. Mccc,
and generating ICharge to charge the battery.
If an npn transistor is used in the place of Mhvcs, this equation becomes:
VClamp
10
2Vgs,hvcs
Rcvs
Vthp
K p'
87
8.6
Rcvs
K p'
Vthp
(3.3.6)
Since MPower also shares the same Vthp and K p' with Mccc, ICharge becomes a clearly
defined value with respect to Rcvs. Unfortunately, with the absence of an npn transistor
with high β value in this process, this solution is currently unavailable.
Note that the resistance of Rcvs is also a function of temperature, making ICharge
temperature-dependent. The resistor value can be generally approximated by [60]:
R(T )
R0
1
TC 1
T
TC 2
T2
(3.3.7)
where TC1 and TC2 are temperature coefficients, R0 is the resistance measured at room
temperature, and ΔT is the difference between the temperature with the room
temperature 25° C. The nonlinear relationship between of ICharge and temperature is
plotted in Fig. 11(b) using a resistor of 10 kΩ with coefficients TC 1
TC 2
3.3.6
10
4
10
2
and
as Rcvs.
Incremental current loop
Fig. 3.3.8 shows the schematic of the Incremental Current Controller augmented to
the original CV controller. The V-to-I converter is responsible of generating a reference
current, Ivtoi, corresponding to the contemporaneous battery voltage. As depicted in Fig.
3.3.9, the virtual-short characteristic of the error amplifier EAvtoi causes the feedback
voltage Vicfb to be copied to Vicfb'. This in turn generates a current signal Iicfb' that flows
through both Mvtoi1 and Mvtoi2. Mvtoi3 copies Iicfb' and generates Ivtoi [61], which flows
through Micfb1 to create a voltage signal at the negative node of the error amplifier
EAicfb.
88
Constant Current Clamp
VDDHV
V-to-I
Converter
Mvcs,rep
Vicadj
Micls2
Mccc,rep
Ivcs,rep
Vicfb
Ivtoi
Micfb1
Vic
EAicfb
Iccc,rep
5V
Micls1
Vicadj
MPower,rep
Ivcs
Vcvref
Mhvcs,rep
Ihvcs,rep
Vcv
Vcvfb
Rics2
Rics1
Mvcs
EAcvfb
Ihvcs
ICharge,rep
To
Battery
Packs
Mccc
Iccc
MPower
Mhvcs
Rcvs
Ricfb2
Micfb2
Incremental Current Controller
Rcvfb
Constant Voltage Controller
Fig. 3.3.8 IC controller augmented to CC/CV loops.
By making Mvtoi1 wide enough, we can obtain the transition voltage, Vtr, from IC
mode to CC mode using the following relationships:
Vtr
Rvoti
I icfb(max )
5
Vvtoi 2
Vvtoi1
(3.3.8)
where 5 is the voltage supply, Vvtoi1 is the overdrive voltage of Mvtoi1, and Vvtoi2 is the
gate-source voltage of Mvtoi2.
Vvtoi1 and Vvtoi2 can be expressed as:
2I icfb(max )
Vvtoi 1
W
Kn' ( )vtoi 1
(3.3.9)
L
Vvtoi1
2I icfb(max )
Vthp
W
K p' ( )vtoi 2
(3.3.10)
L
W
W
where ( )vtoi1 and ( )vtoi 2 are the aspect ratios of Mvtoi1 and Mvtoi2, respectively.
L
L
89
ICharge
Ricfb1
To
Battery
Packs
MPower
Vicfb
5V
ICharge
Mvtoi3
Mvtoi2
Ricfb1
Ivtoi
Mvtoi1
Ricfb2
EAvtoi
Rcvfb
Iicfb
Vicfb'
Rvtoi
Fig. 3.3.9 V-to-I converter.
Hence,
Vtr
5
Vthp
2I icfb(max )
2I icfb(max )
W
Kn' ( )vtoi1
W
K p' ( )vtoi 2
L
(3.3.11)
L
By using some algebraic manipulation, we obtain
Vtr
1
2
5
Vthp
1
(3.3.12)
where
Rvtoi
2 2
W
Kn' ( )vtoi1
L
90
W
K p' ( )vtoi 2
L
(3.3.13)
If Mvtoi1 is narrow, Vtransit(max) will be limited by 5 - Vthnʹ. Notably, due to body
effect, Vthnʹ will be significantly larger than Vthn. The overall Vtransit(max) can be defined
as:
Vtr
min 5
Vthn ,
1
2
5
Vthp
1
(3.3.14)
Direct sensing of ICharge to attain a precise current signal is difficult. Instead, a
replica circuit consisting of Mhvcs,rep, Mccc,rep, MPower,rep, and Rics2 is used to generate
ICharge,rep, which is a fractionized ICharge. The gate of Mhvcs,rep is connected to the voltage
supply, mimicking Vcv which is also pulled to the voltage supply by EAcvfb before the
charger enters CV mode. It is worth noting that the gate of Mhvcs,rep must be connected
to the supply voltage internally, since N-type LDMOS transistors are susceptible to ESD
[62]. The value of Rics2 should be made close to Rcvs. However, the direct matching
between the two is unnecessary. The mismatch between the two resistance will only
cause negligible effect on ICharge,rep during IC mode.
EAicfb indirectly drives Mvcs,rep through Micls1 and Micls2 to steal current Ivcs,rep from
Iccc,rep, which is the drain current of Mccc,rep. Consequently, ICharge,rep flowing through
MPower,rep and Micfb2 is scaled proportionally to Iccc,rep. EAicfb regulates the voltage
generated by ICharge,rep to the voltage generated by Ivtoi, which simultaneously regulates
the current ICharge,rep itself to Ivtoi. Since the gate of Mvcs and Mvcs,rep are driven by the
same voltage, Vicadj, the amount of current Ivcs stolen from Iccc will be proportional to the
amount Ivcs,rep stolen from Iccc,rep. Hence, ICharge will be proportional to ICharge,rep, which
in turn is proportional to the feedback voltage, Vicfb.
91
Throughout the charging sequences, the IC loop and the CV loop do not interact
with each other. Whenever a loop is controlling the behavior of the charger, the other
loop is saturated such that it cannot affect the operation of the charger. Hence, stability
issues are dramatically simplified and smooth transition between charge modes is
ensured regardless of what mode the charger is.
3.3.7
Over-temperature protection
Under the circumstances that the charger circuit is experiencing excessive
temperature, certain mechanisms are required to prevent the charger from continuing the
charging sequence. Although a vast number of thermal sensors have been reported to
extract a precise temperature [63] - [65], they are generally complex circuits with layout
area too large for a charger circuit to accommodate on silicon. Instead of using
temperature sensors, two additional DC paths are augmented to the bandgap voltage
reference generator (BGR), as shown in Fig. 3.3.10. One path provides a proportional to
absolute temperature (PTAT) voltage, VPTAT, and the other generates a complementary to
absolute temperature (CTAT) voltage, VCTAT. These two voltages are compared with a
hysteresis comparator [66] shown in Fig. 3.3.11. To prevent the charger from turning on
and off rapidly, a hysteresis of 20°C is added in our design. According to the
simulations, the charger turns off at approximately 110°C and turns back on when the
temperature drops below 88°C. The bandgap reference voltage, Vcvref, is served as the
voltage reference for the charger in CV mode as well.
92
Vcvref
VPTAT
VCTAT
D3,k
VCMP
Icvref
D1,1
D2,k
Fig. 3.3.10 BGR with over-temperature protection.
VCMP
VCTAT
VPTAT
VBCMP
Fig. 3.3.11 Hysteresis comparator.
93
3.3.8
Antenna effect protection PAD
The antenna effect, more formally known as the plasma induced gate oxide
damage, can potentially damage integrated circuits during the manufacture process [67]
- [72]. Such an effect occurs when the metal coupled to the gate of a MOS transistor
somehow acquires a voltage higher than the maximum sustainable voltage of that
transistor during fabrication. Since the gate dielectric is only a few molecules thin,
breakdown may occur [71]. Furthermore, if an input transistor of a differential pair is
subject to the plasma induced gate oxide damage, an offset voltage is induced [72] and
the overall system closed-loop accuracy is degraded. To prevent plasma induced gate
oxide damage, foundries often provide antenna rules based on antenna ratio, AR, which
is the allowable ratio of metal area to gate area. The definition of AR can be found in
[73], [74]. However, since the ultra-thick top metal (UTM) thickness of this process is
30 kÅ (3 μm) [16], the height of both the metal and the polysilicon should be taken into
account:
AR
WM
LM
WP
LP
HM
HP
(3.3.15)
where WM, LM, and HM are the width, length, and height of the metal, respectively. WP,
LP, and HP are the width, length, and height of the polysilicon of the MOS transistor
connected to the metal. κ is a coefficient.
A bonding PAD typically consumes an area of 70 μm × 80 μm on all three metal
layers. Hence, transistors with their gate node connected to bonding pads must be large
94
Fig. 3.3.12 Antenna effect protection PAD.
enough to meet the minimum AR requirements. Unfortunately, such requirements
restrict the user from connecting an external node to small transistors such that
unnecessary dilemmas regarding the selection of transistor aspect ratios may appear. To
resolve this issue, the proposed antenna effect protection pads can be deployed instead
of standard pads. The antenna effect protection PAD is obtained by adding a dummy 0.5
μm PMOS transistor beneath the standard PAD, as shown in Fig. 3.3.12. Notably, both
drain and source of the PMOS transistors are coupled to Metal 1 (M1) using contacts.
The drain and source node can provide forward diode connection when a voltage is
higher than 5 V appears on any metal layers so that the gate oxide of the connected
95
small transistors is protected. The isolation rings are connected to ground and the 5 V
supply voltage, respectively. Since the N-well is also connected to the 5 V supply
voltage and drain/source are shorted together, high DC impedance is achieved. Parasitic
capacitance existing between bulk and the other three shorted terminals is at its
minimum value, since the PMOS is in cut-off region. Hence, antenna effect protection
pads have negligible impact on circuit behavior while providing adequate protection to
meet the AR requirements set by foundries. The parasitic capacitance can be estimated
as follows [75]:
C pad
ox
1.15
Apad
1.4
h
ppad
t
h
0.222
(3.3.16)
where Apad, ppad and t are the area, periphery, and thickness of the antenna effect
protection pad, respectively. h is the distance of the bottom metal plate to the substrate,
and εox is the dielectric constant of SiO2. Since the M1 layer is removed, h is increased
and the total parasitic capacitance is reduced. Finally, since antenna effect protection
pads do not require additional silicon area, they can be placed under top metal layers
without enlarging the total layout of the chip.
3.3.9
Implementation
To evaluate the charging current with respect to the battery voltage, the targeted
battery load of 14 × 4.2 V Li-ion batteries are emulated with Prodigi 3311D
Programmable DC Electronic Load, and the variable voltage is supplied by a Chroma
62012p-600-8 Programmable Power Supply.
96
As shown in Fig. 3.3.13, the charger begins with a charging current of 36 mA,
which slowly rises to 136 mA. To improve efficiency, resistor Rcvs is increased to 20 kΩ
instead of the value 14.5 kΩ used in simulation. It has caused an impact on the
characteristics of the charger in IC mode, but it is possible to remove the deviation if
Rics2 is also connected externally and made equal to Rcvs. These results are tolerable,
since they only interfere with the initial charging sequence of the batteries. IC mode
neither determines when the battery transits from CC mode to CV mode nor decides
when the charging sequence ends. Charging efficiency with respect to the battery
voltage is plotted in Fig. 3.3.13. This charger has a peak efficiency up to 92 % during
the charging sequence. Notably, even a most deeply uncharged 4.2 V battery may still
have more than 2 V such that a series of 14 batteries should at least have a voltage of 28
V. Therefore, the simulated low efficiency below 26 V shown in Fig. 3.3.14 would never
occur in practical scenario.
The proposed chargers have been fabricated using TSMC 0.25 μm BCD 60 V
technology. The first chip [38] featured diode-based constant Current Clamp, bandgap
reference with the augmented CTAT and PTAT voltage generators. It also features an
unusable trickle current mode, which results in an inductive kickback that permanently
damages the charger when triggered. It occupies a total silicon area of 586 × 879 μm2
(with pads).
The TC mode has been replaced with IC mode in our second chip. Unlike the first
chip which used low voltage transistors with long lengths, feature-sized transistors were
used instead in this new design. This greatly reduces silicon area occupied by low
voltage (LV) circuits. Since this charger is intended to be integrated into a complete
BMS solution in the future, Vcvref is made to be adjustable such that bypassing batteries
97
in the charging path is allowed. Hence, the bandgap reference is removed so that Vcvref
can be adjusted directly using a digital-to-analog converter (DAC). This charger
occupies a total silicon area of 414 × 900 μm2 (with pads). Finally, a comparison of
these two chargers is tabulated in Table 3.3.1. Since TC mode is not functional, it is
denoted with a “×” symbol.
Table 3.3.1 Chargers Comparison
Charger [38]
Charger (with TC mode)
Supply Voltage
60 V
60 V
Maximum Charge Current
52 mA
136 mA
Peak Efficiency
80 %
92 %
Supported Charge Modes
CC/CV/TC(×) Modes
CC/CV/IC Modes
Over Temperature
Protection
Yes
No
Antenna Effect Protection
No
Yes
Silicon Area
586 × 879 μm2
414 × 900 μm2
98
140
Measured
Charging Current (mA)
120
100
80
60
40
20
0
0
10
20
30
40
50
60
Battery Voltage (V)
140
Simulated
Charging Current (mA)
120
100
80
60
40
20
0
20
25
30
35
40
45
50
Battery Voltage (V)
Fig. 3.3.13 Measured and simulated charging current.
99
55
60
100
Measured
Battery Efficiency (%)
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Battery Voltage (V)
100
Simulated
Battery Efficiency (%)
90
80
70
60
50
40
30
20
10
0
20
25
30
35
40
45
50
Battery Voltage (V)
Fig. 3.3.14 Measured and simulated charging efficiency.
100
55
60
3.4
Summary
This chapter provides an overview of CMOS compatible high voltage process,
namely, the TSMC 0.25 μm 1-poly 3-metal Bipolar-CMOS-DMOS (BCD) 60 V process.
Section 3.1 describes the devices offered by this process. Section 3.2 presents a
Domestic Indirect Feedback Compensation (DIFC) operational amplifier for systems
with both low voltage and high voltage circuits. The DIFC operational amplifier is
capable of converting a voltage signal and amplifying it into a large voltage signal to
drive high voltage load. Since the Metal-Insulator-Metal (MIM) capacitors are not
designed for high voltage applications and the feed-forward compensation causes
pole-zero doublet as a result from the deviation of high voltage transistor characteristics
from shuttle to shuttle, the DIFC is performed only using low voltage circuits. In other
words, the feedback by connecting the output node of the operational amplifier is
avoided.
A novel 60-V battery charger is presented in Section 3.3. The newly proposed
smooth charge mode transition can ensure smooth transitions between incremental
current (IC), constant current (CC), and constant voltage (CV) modes. The charger
sources a current of 136 mA in CC mode and has efficiency up to 92 % during the
charging sequence. Intentional saturation of both the IC and CV regulation loops ensure
the stability of the charger throughout the charging sequence. Bonding PAD designed to
remove the restrain on the aspect ratio of input transistors as a prevention of antenna
effect is also disclosed.
101
Chapter 4: MORPACK
TRANSCEIVERS
4.1
Fundamentals of Backplane Transceivers
A MorPack system is a set of stacked PCB boards with integrated circuits on
each board. The aim of MorPack is to split a microprocessor-based system into
several chips so that academic designers can focus on a specific part of the system and
reuse the other parts without redesigning the entire system from scratch.
The performance of such a system is dominated by the bandwidth of the channel
that connects different chips and different PCB boards. However, since digital signals
must travel though a significant distance from the transmitter to the receiver,
designing a high bandwidth transceiver becomes very challenging due to many
negative effects. These effects include electromagnetic interferences, crosstalk,
ground bouncing, skin effect, intersymbol interferences and many other problems can
make the design of a high bandwidth transmitter challenging. Thus, a Gb/s transmitter
dedicated to transmit and receive data through external wire channels requires
sophisticated circuit design methodologies to meet the physical demand.
4.1.1
Uni-polar/differential signaling at high frequency
In the low frequency analysis, a lumped circuit approximation can accurately
predict the waveforms of signals traveling through separate nodes. However, at high
frequencies, electromagnetic interferences (EMI) and crosstalk (XT) noise effects
102
I1
I1
H1
H1
I2
(a)
H2
(b)
Fig. 4.1.1 Electromagnetic behavior of (a) uni-polar
and (b) differential signaling wire channels [39].
Aggressor
Victim
(a)
Aggressor 1
Victim
Aggressor 2
(b)
Fig. 4.1.2 (a) Uni-polar and (b) differential signaling wire channels [2].
come into play. EMI are often generated by the magnetic flux of the inductance on the
wire channels [76], as shown in Fig. 4.1.1 (a). This phenomenon which interferes with
adjacent victim channels may degrade the bit error rate (BER) performance thereof. If
differential signaling is used instead of uni-polar signaling, the adjacent currents I1
103
and I2 flowing toward opposite directions will cancel the electromagnetic emissions
H1 and H2 from the two different channels, as shown in Fig. 4.1.1 (b) [39]. However,
it is apparent that the wire channels of these two differential signals must be spatially
adjacent to each other such that EMI can be reduced. It is also worth noting that a
greater cancellation can be achieved if the wire channels are twisted with each other
[76]. The parasitic capacitance between adjacent channels is also another cause of
crosstalk. Unwanted high frequency signals will be coupled from one wire channel
(the aggressor) to the other (the victim), and DC bias voltages might be corrupted as
shown in Fig. 4.1.2 (a). If differential signaling as shown in Fig. 4.1.2 (b) is used
instead, the differential high frequency signals from two different aggressors
contribute the opposite amount of interferences their victim, where these signals are
expected to cancel out each other [2].
Before moving any further, it may be worthwhile to discuss the definition of
crosstalk given different conditions. In the receiver/transmitter topology shown in Fig.
4.1.3, receiver 2 (RX2) is made to receive signal from transmitter 5 (TX5). However,
signal transmitted by transmitters TX1 and TX3 on the same end with RX2 are also
coupled to RX2, where the amounts of coupled signal components are denoted as
NEXT21 and NEXT23. Notably, NEXT stands for near-end crosstalk. On the other
hand, interferences generated by transmitters 4 and 6 on the other end, probably on a
remote chip, are denoted as FEXT24 and FEXT26, where FEXT stands for far-end
crosstalk [77]. In short, NEXT and FEXT are defined as the interferences from
individual wire channels. If the interferences are from a different group or bundle of
remote wire channels, they are defined as Alien crosstalk, or AXT. Differential
signaling is good for cancelling out FEXT and AXT, since both the received positive
104
TX1
BUS
NEXT21
RX4
FEXT24
RX1
AXT
TX4
TX2
RX5
Desired Signal
RX2
TX5
RX3
BUS
TX3
RX6
NEXT23
FEXT26
TX6
Fig. 4.1.3 NEXT and FEXT interactions of TX and RX [77].
ΔI2
ΔV2
ΔV=0
Idrive-ΔI1+ΔI2
ΔI1=ΔI
2
ΔV1
ΔI1
(a)
ΔV=0
(b)
Idrive-ΔI1+ΔI2
(c)
Fig. 4.1.4 (a) Ground jumping, (b) transient supply voltage drop, and (c)
differential driver does not suffer from such problems.
and negative signals are affected by the interferences with approximately the same
amount. As for interferences from NEXT, the adjacent transmitters may have different
coupling coefficient to the positive and negative signaling paths. Hence, the
improvement of performance using of differential signaling scheme over uni-polar
105
signaling may not be as high in NEXT as compared to AXT and FEXT.
Meanwhile, it is also important to address the difference of how differential
signaling and uni-polar signaling transmitters affect their respective supply voltage
sources and ground connections. As depicted in Fig. 4.1.4 (a), the transmitter when
pulling down the output node results in an abrupt dynamic current and short-circuit
current (denoting the sum as ΔI1) that flows through the transmitter. ΔI1 in turn causes
a voltage spike on the inductor connected to the ground node by ΔV1. This
phenomenon is well known as ground bouncing. Similar effect appears when the
transmitter tries to pull up the output node to VDD in Fig. 4.1.4 (b). An abrupt dynamic
current and short-circuit current (denoting the sum as ΔI2) that flows through the
transmitter causes a voltage spike on the inductor connected to the supply voltage
node by ΔV2. Ground bouncing and transient voltage droop will result in spurious
signals in the receiver end to degrade BER performance.
Although differential signaling requires double the hardware, they provide far
superior performance over conventional uni-polar signaling schemes. In the design of
high speed data transmitters, differential signaling schemes are often the only choice
left.
4.1.2
Skin effect
To investigate how skin effect throws an impact on the performance of
transmitters operating at high frequency, the analysis can start from the definition of
resistance.
Generally, the resistance given a conductor can be expressed with:
106
l
A
R
where l ,
(4.1.1)
, and A are the length, conductivity, and the cross section area of the
respective resistance. Apparently, a wire with larger A can reduce its overall
resistance, resulting in a smaller RC time constant, if the wire channel is terminated
with a capacitive load, which is usually the parasitic input capacitance of MOS
transistors in the input stage. However, Eqn. (4.1.1) only gives a valid definition for
resistors operating at DC or low frequency. Unlike DC or low frequency signals, high
frequency signals result in a magnetic field such that electrons flowing through the
conductor are forced to shift to the area near the surface. Hence, the actual available
cross section area of the conductor is reduced, and the expression in Eqn. (4.1.1) can
be modified into:
l
Aeff
R
(4.1.2)
and
Aeff
where
r2
(4.1.3)
2
s)
(r
r 2 is the cross section area A at DC or low frequency, and
(r
)2 is
the area influenced by the magnetic field not available for flowing electrons. The
effective skin depth,
s,
is a function of conductivity,
, permittivity,
0,
and most
important of all, the frequency, f .
2
1
s
0
0
f
(4.1.4)
A list of conductivity can be found in [8]. Several materials are quoted here as a
reference for readers.
107
Table 4.1.1 Conductivity of materials at 20°C
Aluminum
3.816 × 107 S/m
Bronze
1 × 107 S/m
Copper
5.813 × 107 S/m
Gold
4.098 × 107 S/m
Iron
1.03 × 107 S/m
Silicon
4.4 × 104 S/m
Solder
7 × 106 S/m
Among the list above, the conductivity of copper, aluminum, and gold are of
special interest, since they are the materials used to make printed circuit board traces
and bond-wires.
4.1.3
Eye diagram and inter-symbol interferences
Due to the impedance associated with a typical lossy wire channel, they can be
modeled as a low pass filter with a frequency response of Hc ( f ) , and a transient
response of hc (t ) . The received signal r (t ) of a transmitted signal m(t ) through
such a wire channel can be expressed as:
r(t )
m(t ) hc (t )
(4.1.5)
The low pass characteristics of hc (t ) filters out the high frequency components
108
Sampling and
Decision Time
Zero
Crossing
Jitter
Noise
Margin
Amplitude Distortion
Fig. 4.1.5 Definitions of the eye diagram [78].
Transmitted Signal
Received Signal
time
0
1 UI
2 UI
3 UI
4 UI
Fig. 4.1.6 Inter-symbol interferences [78].
of m(t ) , degrading the quality of the waveform received. The quality of the received
signal can be evaluated using the eye diagram [78], as shown in Fig. 4.1.5.
The performance of BER is determined by how wide the eye is “opened”, which
in turn is determined by the amount of zero crossing jitter, amplitude distortion, noise
109
margin, and the precise timing of sampling and decision. To ease the restraint of
timing precision and improve BER, inter-symbol interferences (ISI) has to be
minimized. Referring to Fig. 4.1.6, a rectangular pulse transmitted through a
band-limited low pass wire channel hc (t ) is distorted and spread a certain number of
unit intervals. This phenomenon results in deterministic jitters, which interfere with
subsequent symbols to cause difficulty in the decision threshold of the received bit
sequence.
4.2
CIC MorPack Transmitter Design
4.2.1
Pre-emphasis
The pre-emphasis [78] technique is an effective strategy to remove distortion
caused by preceding signal pulses and reduce ISI. To elucidate this idea, consider Fig.
4.2.1. A non-return to zero (NRZ) data sequence of 0110010001111000 is transmitted
through the channel in Fig 4.2.1(a). In Fig 4.2.1(b), the pre-emphasis transmitter
emphasizes every bit transition, both from 0→1 and 1→0. Hence, the high frequency
components are emphasized while the DC components are de-emphasized. These two
signals are transmitted through the same low pass channel, and the received
waveforms are shown in Fig 4.2.1(c) and (d). Apparently, potential decision errors
may appear at the receiver during transitions if the signal waveform has not reached
the decision threshold before the sampling and decision time. By contrast, the
difficulty associated with determining a received pre-emphasized signal given the
same transmission bit rate is significantly reduced.
110
(c)
(d)
Original Data
Data with
Pre-emphasis
Received Signal
without Pre-emphasis
(b)
Received Signal
with Pre-emphasis
(a)
Fig. 4.2.1 Comparisons of waveforms with and without pre-emphasis.
4.2.2
A transmitter with pre-emphasis
According to Fig. 4.2.1 (b), it is apparent that the current output voltage is
emphasized at transitions, making them a function of the previously transmitted bit
sequence. The relation can be expressed as follows.
vout[z ]
a0 SignalA[z ]+a1 SignalA[z
1]
...
aN SignalA[z
N]
N
0
an SignalA[z
111
n]
(4.2.1)
Signal A Signal Az-1
R
Signal Az-N TX1
Vref1
Veye1 V
ref2
Veye2
RTX2
Vout,diff
Transconductor N
VrefN
VeyeN
Current
Switch 1N
...
Current
Switch MN
Current
Switch 2N
Signal Az-1...
Signal A
z-1
z-1
z-1
... z-1
Signal Az-N
Fig. 4.2.2 A transmitter with pre-emphasis.
where a 0 to aN are the weighed weighted coefficients and SignalA[z
N ] is the
input signal at the instant N.
A physical realization of Eqn. (4.2.1) consists of N sets of transconductors with
coefficients a 0 to aN ,as shown in Fig. 4.2.2. The current that biases each
transconductor are controlled by current switch 1n to Mn (n ranges from 0 to N),
which determines the weighted coefficient associated with the respective
transconductor. The adjusted transconductors will sink appropriate amount of current
through resistors RTX1 and RTX2 according to coefficients a 0 to aN , such that the
differential output voltage Vout,diff behave in accordance to Eqn. (4.2.1).
To ensure that the output voltage swing of each transconductor is carefully
controlled, a replica circuit is used to generate Veyen, (n ranges from 0 to N), which
calibrates the voltage swing of each transconductor according to Vrefn, (n ranges from
0 to N). In this thesis, the number of transconductors is 4 (making N = 4), and each
has 8 current switches (M = 8).
To store the controlling bit values of 1n to Mn, a 4 × 8 array of latches is
112
EN0
EN1
EN2
EN3
I0
D
Q
EN
A0
D
Q
EN
B0
D
Q
EN
C0
D
Q
EN
D0
I1
D
Q
EN
A1
D
Q
EN
B1
D
Q
EN
C1
D
Q
EN
D1
I6
D
Q
EN
A6
D
Q
EN
B6
D
Q
EN
C6
D
Q
EN
D6
I7
D
EN
Q
A7
D
EN
Q
B7
D
Q
EN
C7
D
Q
EN
D7
Fig. 4.2.3 A 4 × 8 latch array.
D
EN
Q
Fig. 4.2.4 A true single phase clock latch.
used. As depicted in Fig. 4.2.3, 4 independent columns of latches are controlled by 4
enable signals, EN0 to EN3, where t will determine the columns of latches that should
store the input I0 to I7 as the controlling bits. The latches are realized using true single
phase clock (TSPC) structure [79], as depicted in Fig. 4.2.4. The implementation of
the latch array can reduce the amount of I/O ports required to configure the
transmitter (the receiver in this work as well) during measurement. The values can be
easily written into the chip using a pattern generator.
113
CLK
D
CLK
Q
CLK
Q
CLK
Fig. 4.2.5 A true single phase clock D flip-flop.
z-1
z-0
D
D
Q
D
Q
z-2
D
Q
z-3
D
Q
CLK
Fig. 4.2.6 Unit delays and gate drivers.
Unit delays (z-1) are implemented using TSPC D Flip Flops shown in Fig. 4.2.5,
and the overall sub-circuit is shown in Fig. 4.2.6, where the inverter chains are the
gate drives of the transconductors shown in Fig. 4.2.2. The width of each inverter is
made 3 times wider than the preceding stages to maximize current driving capability
and minimizes delay. The lengths of these transistors are minimized to reduce
parasitic capacitance. Note that an actual implementation of Fig. 4.2.6 is made
differential, and all PVT corner simulations must be performed to ensure the delay of
both positive and negative signal arrive at the transconductor.
114
Received Difference Signal (V)
4.2.3
Simulation of the transmitter with pre-emphasis
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0
5
10
15
20
25
30
35
40
25
30
35
40
Received Difference Signal (V)
Time (ns)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
5
10
15
20
Time (ns)
Fig. 4.2.7 Simulation of the received waveforms.
To evaluate the performance of the transmitter, a simulation is performed through
a channel with a parasitic inductance of 20 nH, a parasitic capacitance of 40 pF, and a
parasitic resistance of 10 Ω. These values have been extracted from a manufacturer’s
data sheet describing the parameters of PCB boards with regard to the length of the
channel.
Apparently, the received difference signal waveforms from a transmitter through
the channel in Fig. 4.2.7 suffers less to ISI with pre-emphasis (bottom) than without
(top).
115
4.2.4
Measurement of the transmitter with pre-emphasis
Fig. 4.2.8 Measurement environment for the transceiver.
The measurements were conducted in the Analog Measurement Laboratory of
Chip Implementation Center (CIC). Due to the missing components such as a phase
locked loop (PLL) and a pseudo-random bit sequence (PRBS) generator on chip, the
extraction of system parameters such as BER cannot be obtained accurately. Since the
clock signal and the data waveforms are provided externally, a significant amount of
jitter and noise are coupled on these signals before they enter the chip.
For the reasons stated above, only the transient waveforms are measured. When
the transmitter operates at 500 MB/s non-return to zero (NRZ) mode, it has
approximately a cycle-to-cycle jitter of 288.37 ps while consuming 40 mW. On the
other hand, the cycle-to-cycle jitter becomes 222.91 ps at 1 GB/s NRZ with power
consumption below 45 mW. A portion of jitter are contributed by interferences
injected in the clock and data signals.
116
Fig. 4.2.9 Measurement of the transmitter at a data rate of 500 MB/s, NRZ.
Fig. 4.2.10 Measurement of the transmitter at a data rate of 1 GB/s, NRZ.
117
4.3
CIC MorPack Receiver Design
4.3.1
Decision feedback equalizer
y[n]
+
x[n]
-
w2
y[n-3]
- -
w1
y[n-2]
z-1
w0
y[n-1]
z-1
z-1
Fig. 4.3.1 Structure of a DFE receiver.
As depicted in Fig. 4.3.1, a Decision Feedback Equalizer (DFE) is a nonlinear
equalizer [78] consisting of a symbol detector (a signal slicer) and a set of feedback
paths. The decision of the received bit x[n] is made by the symbol detector to generate
y[n]. y[n-1], y[n-2], and y[n-3] are generated using unit delays and multiplied by
coefficients w0, w1, and w2, respectively. Recall that ISI are basically the interference
caused by pre-cursors to the current symbol. Hence, with an appropriate selection of
w0, w1, and w2 of the feedback paths, it is possible to reduce the low frequency
components of x[n] such that the ISI is reduced and the BER of y[n] is also decreased.
y[n ]
x[n ]
w0y[n
1]
118
w1y[n
2]
w2y[n
3]
(4.3.1)
Furthermore, since y[n-1], y[n-2], and y[n-3] are digital signals, the immunity of
the feedback path against noise is good. However, the risk of using a DFE receiver is
because the decision made by the symbol detector is highly dependent on y[n-1],
y[n-2], and y[n-3], any error in the previous decision will result in error in the
subsequent bits, causing error to appear in bursts [80]. Such characteristics prevent the
use of general error correction codes to recover the incorrect bits.
4.3.2
A DFE receiver
The structure of the DFE receiver is shown in Fig. 4.3.2. The transconductors are
driven by the input signal, x[n], and the feedback signal, y[n-1], y[n-2], and y[n-3],
respectively. Additional analog equalization is applied to the transconductor, Gmx, with
x[n] as an input by using the Cherry-Hooper [81] topology. The overall transfer
function of Gmx can be expressed in terms of the input transistor’s transconductance
gmxin, RCH, and CCH as follows.
Gmx
1
gmxin
0.5RCH
gmxin (
1
(4.3.2)
sCCH RCH
)
The frequency response of such a transfer function exhibits a peaking near the -3
dB point, which can partially compensate for signal loss caused by the channel.
The values of coefficients w0, w1, and w2 are controlled by current switching
networks CSN A and CSN B shown in Fig. 4.3.3. These switches determines the
multiplier of the current references, IbCSNA and IbCSNB, to bias the transconductor.
Unlike the current switches of the transmitter, the exact transconductor voltage swing
119
Slicer
icsp
Gmx
x[n]
RCH
CCH
y[n-1]
CSN A CSN A
y[n-2]
CSN B
CSN B
icsn
y[n-3]
CSN B
Fig. 4.3.2 A DFE receiver.
IbCSNA/
IbCSNB
Current
Switch 1n
Current
Switch 2n
...
Current
Switch Mn
Fig. 4.3.3 CSN A/CSN B.
is not important. Therefore, no additional error amplifiers are used to calibrate the
bias voltages of these switches.
Basically, CSN A is a CSN B with all its transistor widths halved to provide bias
currents independently for the two transistors of Gmx such that RCH, and CCH can be
placed to achieve analog equalization.
A symbol detector is realized using a signal slicer circuit shown in Fig. 4.3.4. It
is responsible of comparing current icsn and icsp generated by the transconductors and
make binary decision of the value of y[n]. When the clock signal clk is low, icsn and icsp
flows through resistors Rsli+ and Rsli-, respectively, causing a voltage drop difference
120
Rsli+
icsn
icsp Rsliclk
clk
From
transconductors
clk
clk
y[n]
xn
xp
z-1
y[n-1]
z-1
z-1
y[n-2]
Fig. 4.3.4 A signal slicer.
y[n]p
y[n]n
xp
xn
vbias
Fig. 4.3.5 A hysteresis comparator.
between nodes xn and xp. This voltage difference is further magnified by a
back-to-back connected inverter pair, which normally results in either xn or xp to be
pulled to the power rails. When the clock signal clk is high, xn and xp are shorted
together. The DC levels of these nodes are determined by the resistance values of Rsli+
and Rsli-, and the equivalent on resistance of the inverters. In this design, they are
made approximately half of the supply voltage to minimize the time required for the
121
back-to-back connected inverter pair to be pull xn and xp to the supply rails when clk
is low.
Since the values of xn and xp reset half of the supply voltage when the clock
signal clk is high, these nodes cannot be connected to the unit delay circuits directly.
Hence, it is required to cascade another comparator stage shown in Fig. 4.3.5, which
has internal hysteresis. By adding this stage, y[n]p and y[n]n only change their values
when clock signal, clk, is low.
The unit delay circuits, like their counterparts in the transmitter, are implemented
using D flip-flops. Similarly, controlling bit values of 1n to Mn are stored in a 4 × 8
array of latches.
4.3.3
Simulation of the DFE receiver
The simulation is carried out by emulating an ISI-deteriorated NRZ signal shown
in Fig. 4.3.6 (top). The DFE can recover signal up to 1 GB/s NRZ with a first order
RC time constant of 500 ps, as shown in Fig. 4.3.6 (bottom). No additional load has
been placed for the waveform shown in Fig. 4.3.6. Additional inverters can be
cascaded to drive a capacitive load.
4.3.4
Measurement of the DFE receiver
The transmitter and the receiver are not measured together due to the limited
amount of hardware available. Instead, a 3.3 V rectangular pulse is applied to the
input of the receiver. Due to the loss and low pass characteristic of the channel, the
received waveform is similar to an ISI deteriorated waveform used in the simulation.
122
3.5
Received Signal (V)
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
15
20
Time (ns)
3.5
Comparator Output (V)
3
2.5
2
1.5
1
0.5
0
0
5
10
Time (ns)
Fig. 4.3.6 An ISI-deteriorated difference signal and the recovered output.
The output buffer of this receiver was implemented using inverters, which has
been proven inappropriate through measurement. The limited driving capability of the
inverters causes the measurement of the DFE receiver to be restrained at
approximately 125 MB/s NRZ, as shown in Fig. 4.3.7. The power consumption is
approximately 30 mW at this data rate.
123
Fig. 4.3.7 Measurement of the DFE receiver.
4.4
Summary
In this work, a transmitter with pre-emphasis and a receiver facilitating DFE are
presented. The transmitter is capable of operating at a 500 MB/s data rate (NRZ), with
an approximately a cycle-to-cycle jitter of 288.37 ps while consuming 40 mW. 1 GB/s
NRZ operation requires power consumption below 45 mW, with a cycle-to-cycle jitter
becomes 222.91 ps. Due to the limited driving current of the inverters, the DFE
receiver can perform at only 125 MB/s NRZ with a power consumption of 30 mW.
124
Chapter 5: CONCLUSION AND
FUTURE WORKS
In this thesis, three categories of circuits, namely, automatic gain control circuits,
CMOS compatible high voltage integrated circuits, and backplane transceivers are
exemplified in detail.
In the implementation of analog AGCs and VGAs, the overall system
performance is greatly influenced by process corners and temperature. Furthermore,
although a significant performance improvement can be attained using feature-sized
transistors, the measured system characteristics often greatly deviate from simulation
results. These phenomena will manifest themselves more in the future with the trend
of device shrinking.
By contrast, digitally controlled AGCs not discussed thoroughly in this thesis are
more robust against the influence of PVT corners. The performance of such AGCs is
much more predictable through simulations, but they possess a considerably slower
loop response compared with an analog AGC loop. The delay that slows down loop
response are mainly contributed by the long latency of a SAR ADC or pipeline ADC,
and the received signal strength indicator (RSSI). In addition, to prevent limit cycle
oscillation (LCO), the gain step of a PGA used in the digital AGC loop has to be made
smaller than the resolution of the ADC. If a high resolution ADC is used, the number
of switches required by the PGA will become impractical, not to mention that each
additional switch would contribute additional parasitic capacitance.
Possible future works may be focused on the design of nonlinear gain controllers
consisting of hard-wired look-up tables (LUTs), which can be made to have a faster
126
loop response to their linear counterparts. On the other hand, a possible hybrid
analog/digital AGC can be constructed with a low dynamic range (DR) analog AGC
and a low gain step resolution digital AGC. Since the gain adjustment range of the
analog VGA can be greatly reduced, the amount of current variation within the VGA
is made significantly smaller, which results in a higher bandwidth. The gain step
resolution of the digital AGC can be made almost as low as the entire DR of the
analog AGC. A low gain step resolution can greatly reduce layout area and reduce
parasitic capacitance.
As for the 60 V charger, large scale integration can be realized with the release of
the 0.25 μm low voltage standard cell library. A complete battery management system
(BMS) can be made on a single chip, along with charge balancing circuits required
when charging serially connected batteries. The voltage reference of the constant
voltage loop can be replaced with a digital-to-analog converter (DAC) to provide an
appropriate voltage output for various charging conditions. Fast reference tracking
systems can be realized by changing the topology of regulator configuration and the
inclusion of push-pull drivers for the power PMOS used to charge the batteries.
Moreover, application specific ICs (ASICs) used to control the charger can be
fabricated on the same chip with the charger itself to reduce manufacturing cost and
eliminate the need of an extra DSP or μC. The space and area consumed by such a
system can be made smaller than conventional chargers with a bulk of discrete
components.
Finally, the backplane transceivers reported in this thesis still has a large room
for significant improvements. On-chip pseudo random bit sequence (PRBS)
generators should be provided for transmitters, while serial in parallel out (SIPO)
127
circuits should be provided for the receiver. On-chip clock generation with frequency
synthesizers and PLLs are also crucial to the measurement of such transceivers. The
reported transceiver were implemented using the 0.35 μm process, which was used to
fabricate Pentium Pro chips operating at 166 MHz back in the year 1995. On the other
hand, most literatures on backplane transceivers were published in the past decade
using more advanced technology. This makes the comparison of the reported
transceiver with prior works somewhat unreasonable. Future implementation of
backplane transceivers should be fabricated using the 40 nm or more advanced
technology to be competitive.
128
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