RD53
RD-53 Progress on High Rate
Pixel Readout chip
M. Garcia-Sciveres
Lawrence Berkeley National Lab
Pixel 2014, Niagara Falls,
Sept. 3, 2014
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RD53
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Contents
Introduction to RD53
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Overview of working groups
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Development timeline
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The high rate challenge
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Information flow within the chip
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Data compression (*)
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Conclusion
(*) Ref: M.G-S and Xinkang Wang, not part of RD53.
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RD53
RD-53
www.cern.ch/RD53
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RD53
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19 Institutes so far (2 new institutes joining)
Bari, Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, LPNHE
Paris, Milano, NIKHEF, New Mexico, Padova, Perugia, Pisa, Prague
IP/FNSPE-CTU, PSI, RAL, Torino, UC Santa Cruz.
~100 collaborators
Spokespersons:
Maurice Garcia-Sciveres, LBNL (ATLAS), Jorgen Christiansen, CERN
(CMS)
Institute Board
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About RD53
IB chair: Lino Demaria, Torino
Regular IB meetings
MOU finalized and ready to be signed
Collaboration meetings
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Spring 2014: April 10 & 11 at CERN
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Fall 2014: October 16 & 17 at RAL
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RD53
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Establish guidelines for radiation hardness of CERN
frame contract foundry to 1 Grad
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Or decide the process cannot be used to this level
Develop tools and methodology adequate for 5x108
transistor mixed signal chip in this technology
Define pixel size and and low threshold operation
strategy:
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RD53 Critical Issues
50um x 50um chip pixels (sensor aspect ratio can vary)
Develop high bandwidth readout (2-4 Gbps / chip)
including cable transmission models
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RD53 Working Groups
Radiation hardness: will be covered in separate talk
Simulation test bench:
Verification framework customized for complex pixel chips based on
system Verilog and UVM
(industry standard for ASIC
design and verification)
High abstraction level down to
detailed gate/transistor level
Benchmarked using FEI4 design
Internal generation of appropriate
hit patterns
Integration with ROOT to import
hits from detector simulations and
for analyzing results.
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RD53
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RD53 Working Groups (cont.)
Analog design:
Evaluation, design and test of appropriate low power analog pixel
Front-Ends
Develop analog front-end specifications
Planar, 3D sensors, capacitance, threshold, charge resolution, noise,
deadtime,...
Alternative architectures –implementations to be compared, designed
and tested by different groups
TOT, ADC, Synchronous, Asynchronous, Threshold adjust, Auto
zeroing, etc.
Design / prototyping of FE's ongoing
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RD53
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RD53 Working Groups (cont.)
“IP” blocks:
Make IP blocks required to build pixel chips
About 30 IP's defined and assigned to groups
Review of IP specs June 2014
Defining how to make IPs ready
for integration into design flow
IP expert panel
Common IP/design repository
Prototyping/test of IP blocks
2014/2015
IP blocks ready 2015/2016
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RD53
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RD53 Working Groups (cont.)
Top Level:
Global architecture and floorplanning
Metal stack; power and bias distribution
and shielding; integration of matrix
and IP blocks.
Front ends and bumps for 4 pixels
Synthesized digital “sea”
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I/O:
Command input and data output protocols.
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Single serial input encoding clock and command
High speed drivers. Simulation of performance with
candidate low mass cable designs (interaction with experiments on
cable R&D).
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RD53
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RD53 Timeline
Radiation hardness conclusions – early 2015
Analog, I/O and IP prototype tests chips – now to end of 2015
(multiple submissions)
Full or half-size prototype(s) – 2016 (wafer run order)
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In CERN frame contract process
Test, design iteration and refinements – 2017
Hand over to ATLAS and CMS for final chip designs – 2018
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RD53
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The high rate challenge
imaging analogy
Normal intensity image (present LHC rate and present detectors)
To see finer details (precision Higgs physics, etc.),
turn up the intensity (future high luminosity LHC)
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RD53
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The high rate challenge
Turn up the intensity--> need a faster camera
As the rate goes, so goes the radiation dose (same source for both)
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Single Pixel Details
today
future
Pixel output
voltage
Pixel size
threshold
time
~50 kHz for ATLAS / CMS
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For 50um x 50um (“future”) pixels, this is 2Ghz / sq. cm.
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Digital perspective
voltage
RD53
threshold
0000
0001
0000
0000
0111
0010
0000
0000
0000
0000
0100
0010
0000
0000
0000
0000
0000
1100
1001
0011
0000
0000
time
Contentaddressable
memory
readout
What is this data rate per chip?
Triggers (selected slice times)
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Data rate (simple analysis)
If the total number of possible hit patterns in a chip is known:
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tion
a
m
r
o
Inf
and they are all equally likely, the information entropy is just the
number of bits needed to count up to this number
Can estimate the number of possible hit patterns by assuming
all the hits are random (clusters change the answer, see later)
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For example, take N=40k pixels per chip
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50kHz / pixel gives 50 hits every 25ns
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Information entropy for picking 50 out of 40K is 550 bits
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This gives 22Gb/s for the big green arrow.
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For 50um x 50um pixels that's per cm 2
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ions)
t
a
n
i
b
om
Log 2(c
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Interesting comparison
Are high rate pixel detectors memory chips?
This is for a
memory module
containing 8
silicon chips, so
GB/module =
Gb/chip
(and this is not rad hard)
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Implications for experiments
ATLAS / CMS have 220Tb/s per m2 of detector
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Triggerless would need 500 data links with 400Gb/s each.
While 400Gb/s is the next generation commercial standard, those
will not be rad hard, and need significant space.
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=> triggerless unlikely. Keep external trigger architecture
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In RD53 we are assuming 2MHz trigger rate
(experiments currently asking for 1MHz)
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(LHCb has 10x lower data rate (lower luminosity)
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Only 50 400Gb/s links (or 500 40Gb/s)
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Plenty of space to put them due to fixed target geometry
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Lower radiation.)
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RD53 Classic Pixel Readout Chip Layout
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Array is primarily an
analog circuit
Try to keep clocks and
digital activity out of array
Limited intelligence in
bottom of chip- mainly
buffering and serialization
Current generation already
has gone beyond this
classic picture
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Present generation readout chip
Logic and buffering
moved into array
Bottom of chip blocks
shrank.
Added system
functions to bottom
of chip
...
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RD53
A look inside FE-I4
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Column composed
of identical 4-pixel
regions
Each region logic is
one synthesized
block (10K gates)
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digital
memory &
control
analog
digital
analog
digital
analog
analog
digital
Trend is Clear
digital
digital
control
(looks like commercial chip)
10 yrs ago
<1Gb/s /cm2
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today
RD-53
5Gb/s /cm2
RD53 High Rate Redout Chip – M. Garcia-Sciveres
25Gb/s /cm2
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RD53 Work in Progress Demonstrator Layout
Bump pads on
50um x 50um grid
Each of these
front-end blocks
produces 200kHz
of hits
Synthesized logic
few 1000 gates
per pixel
1FE-I4 pixel
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22Gb/s data “input” to this memory is highly distributed, unlike
computer memory chip with 16 input pins
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2 MHz Triggered readout – back
of the envelope
IBL readout of 160Mb/s/chip will handle 2x1034 luminosity at
13TeV, with 100KHz trigger rate.
Multiply by 2.5 to get to 5x1034
Multiply by 20 to get to 2MHz
Result: 8 Gbps / chip.
That's too high. Need to find a factor of >2
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Phase 2 inner layer is a bit further out than IBL
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Better data compression- being studied (see later)
Reduced information?- being studied. Could go binary for
innermost layer (this would be a knob one can turn)
On-chip clustering and data reduction- proposed, just
conceptual for now
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RD53 BW affects internal architecture as well
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Hits form any part of the chip must make it to the periphery fast
enough to join the high speed readout for the event they belong to.
=> Matrix to periphery latency must be smaller than chip output.
Low latency drives BW up.
Data transmission within the chip is being studied in RD53.
Want low power, but also constant power consumption to minimize
parasitic effects on threshold
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RD53 chip in-time threshold target is <1000e.
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This is needed due to small pixels and thin sensors
Its a challenge
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Data compression efficiency is
clearly of interest
Lossless Compression
10010111001001010000111010011000101011
Compressed data
Can recover
hit pattern
Hit pattern
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What is the actual amount of information?
This lets us calculate an efficiency:
Efficiency =
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information entropy (in bits)
number of bits in compressed data
Can we calculate the information content in a general way?
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Calculating information content
Done first for simplest case of binary strip detectors. See
JINST 9 P04021 (2014) and JINST proceedings of WIT2014
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Work in progress for case of pixel detectors with pulse height ADC
Decompose pattern. Calculate entropy for components. Add them up.
H(Cluster positions): approximately random (can calculate random)
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H(Cluster shapes): many shapes possible but only a few shapes
dominate. Which ones depends on where chip is in detector
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Ensemble of
Hit patterns
H(Cluster total charge): straightforward because we know what
energy deposition looks like. Precision limited by noise.
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H(Fraction of charge in each pixel): less straightforward. Work in
progress- not covered here.
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H(Cluster positions)
If positions are random this is just a combinatorial problem.
H = -log2 (number of possible cluster positions within the chip)
Obviously depends on number of clusters (which is the occupancy)
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So can naturally calculate position entropy vs. occupancy
Chip size (pixels)
Position entropy per cluster (in bits) vs. Occupancy
(note we traditionally use a fixed number of bits per address!)
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Cluster charge useful information
H= -Σ pi log2(pi)
(Measured – true) RMS error (arb. units)
RD53
Entropy, H (bits)
Equal probability bins
200e- noise
Equal size bins
Charge PDF used for above
Sum of 5 Landau's with different means
to cover a range of momenta / incidence angles
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H(Cluster shapes)
Even for small-ish cluster size there are hundreds of possible cluster
shapes (unlike the case for strip detectors where cluster size is the end
of the story)
But, similar situation to cluster charge, where in spite of many ADC
bins, entropy is low because most bins are unlikely.
HOWEVER, which shapes are likely depends on what sensor is
connected to the chip and where it is placed in a detector (barrel,
endcap, B-field, tilt, eta...)
=> To efficiently read out cluster shapes (number of bits close to
entropy), chip will have to learn on-the-job which shapes are likely and
assign short Huffman codes to those
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Chip generates form its own data a Huffman code table for shapes
User decides when to read out that table and tells the chip what table to
use to encode shapes
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RD53
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Conclusion
RD53 collaboration is in place to design next generation readout chips
for ATLAS and CMS.
High hit rate of order 2GHz/cm2 is the leading challenge. This drives
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Readout electronics with high digital logic density, with bandwidths
comparable to high speed computer memory chips
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Extreme radiation tolerance
At one order of magnitude lower hit rate, as for LHCb, triggerless
readout appears feasible.
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But for ATLAS and CMS RD53 is assuming 2 MHz trigger rate.
Data compression plays an important role in enabling high trigger rate
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Analysis of information content (entropy) will allow to optimize data
compression.
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BAC K U P
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Sensor Bump Pattern
Much discussion can be summarized with one question:
Is there any sensor design that prefers one of the two options?
Grid Pattern
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Need sensor metal routing to
reach bumps from rectangular
pixels
Offset Pattern
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Need sensor metal routing to
reach bumps from square pixels
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Yes: One was claimed
3D sensor with 25um x 100um pixels need offset bumps
All other sensor designs work equally well with either one.
NO
YES
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Offset or Grid bump patterns
can actually look very similar
No need for more difficult variant
(no need to stagger every column. Staggering every pair achieves same thing)
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Multicore Concept
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Rad Hard logic lagged Moore's Law
due to ELT, but now caught up
65nm
130nm
0.25um
ELT
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RD53
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FE-I4 Digital Region
Digital block is shared with 4 inputs- each form an identical
analog pixel.
A simple digital processing “core”
100 m
500 m
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