Advance in Electronic and Electric Engineering.
ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 701-710
© Research India Publications
http://www.ripublication.com/aeee.htm
Design of a Low Power XNOR gate Using
MTCMOS Technique
Suman Nehra1 and P. K. Ghosh2
1
Department of Electronics Communication Engineering,
MITS University, Lakshmangarh, Sikar, INDIA
2
Department of Electronics Communication Engineering,
MITS University, Lakshmangarh, Sikar, INDIA.
Abstract
Power consumption plays an important role in any integrated circuit
and is listed as one of the top three challenges in International
technology roadmap for semiconductors. The low-power clubbed with
low-energy has become an important issue in recent trends of VLSI.
This paper presents pre-layout simulations of a 3T XNOR cell at low
voltages. The main objective of design is low power consumption and
full voltage swing which is achieved at low supply voltage. In this
paper, XNOR gates with MTCMOS and without MTCMOS technique
are compared taking power consumption as parameter by varying
voltage, frequency and temperature. The designs are tested in 45nm
technology. The XNOR gate design with MTCMOS technique gives
least power consumption
All the pre-layout simulations have been performed at 45nm
technology on Tanner EDA Tool version 12.6.
Keywords: Component; 3T (3 Transistors), threshold loss.
1. Introduction
Building low-power VLSI system has emerged as significant performance goal
because of the fast technology in mobile communication and computation. The
advances in battery technology are not commensurate with the advances in electronic
devices [1]. So the designers are faced with more constraint; high speed, high
throughput and at the same time, consumption of power as minimal as possible. The
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Suman Nehra & P. K. Ghosh
increasing demand for low-power VLSI circuits can be addressed at different design
levels, such as the architectural, circuit, layout, and the process technology level. At
the circuit design level, the possibility for power savings exists by means of proper
choice of a logic style for implementing combinational circuits [2], [3]. In the absence
of low-power design techniques such applications generally suffer from very short
battery life, while packaging and cooling them would be very difficult and this is
leading to an unavoidable increase in the cost of the product. Historically, VLSI
designers have used speed as the performance metric. High gains, in terms of
performance and silicon area, have been made for Digital circuits. In general, small
area and high performance are two conflicting constraints. The power consumption for
any given function in CMOS circuit must be reduced for either of the two different
reasons: The most important reason is to reduce heat dissipation in order to allow a
large density of functions to be incorporated on an IC chip. Any amount of power
consumption is worthwhile as long as it doesn’t degrade overall circuit performance
[4]. The other reason is to save energy in battery operated instruments same as
electronic watches where average power is in microwatts
Power dissipation can be reduced by scaling the supply voltage. The scaling of
supply voltage linearly with feature size was started from half-micron technology. But
the power supply scaling affects the speed of the circuit the need of the time is to put
efforts in designing low-power and high speed circuits. MTCMOS technology has
emerged as a promising alternative to build logic gates operating at a high speed with
relatively small power dissipation as compared to traditional CMOS. MTCMOS is an
effective circuit-level technique that provides a high performance and low-power
design by utilizing both low and high-threshold voltage transistors. This technology is
used for reducing subthreshold currents in standby mode while maintaining circuit
performance.
2. CMOS Technique
During CMOS (complementary metal oxide semiconductor configuration) design, the
circuit topology is complementary push pull it means that both PMOS and NMOS
networks are contributed in the circuit. Consequently both the transistors contribute
equally in the entire circuit operation. To achieve high density, performance, and lower
power consumption, CMOS devices have been continuously scaled for more than last
40 years. Transistor delay times decrease by more than 30% per technology
generation, resulting in doubling of microprocessor performance every two years. The
supply voltage (VDD) has been scaled down in order to keep the power consumption
under control. Hence, the transistor threshold voltage (Vth) has to be commensurately
scaled to maintain a high drive current and achieve Performance improvement.
However, the threshold voltage scaling results in the substantial increase of the sub
threshold leakage current [5-7]
Power consumption of CMOS consists of dynamic and static components.
Dynamic power is consumed when transistors are switching, and static power is
Design of a Low Power XNOR gate Using MTCMOS Technique
703
consumed regardless of transistor switching. Dynamic power consumption was
previously (at 0.18μ technology and above) the single largest concern for low-power
chip designers since dynamic power accounted for 90% or more of the total chip
power. Therefore, many previously proposed techniques, such as voltage and
frequency scaling, focused on dynamic power reduction. However, as the feature size
shrinks, e.g., to 0.09μ and 0.065μ, static power has become a great challenge for
current and future technologies.
Modern digital circuits consist of logic gates implemented in the complementary
metal oxide semiconductor (CMOS) technology. Power consumption has two
components: Dynamic Power and Leakage power [8]. Dynamic and leakage power
both are the main contributors to the total power consumption. Dynamic power
includes both switching power and short circuit power. Spurious transitions (also
called glitches) in combinational CMOS logic are a well-known source of unnecessary
power dissipation. Reducing glitch power is a highly desirable target [9]. The dynamic
power cannot be eliminated completely, because it is caused by the computing activity.
It can, however, be reduced by circuit design techniques.
Static power refers to the power dissipation which results from the current leakage
produced by CMOS transistor parasitic. Traditionally static power has been
overshadowed by dynamic power consumption, but as transistor sizes continue to
shrink, static power may overtake dynamic power consumption To alleviate the rising
significance of static power in digital systems, static power reduction techniques have
been developed like transistor stacking, dual threshold voltage , MTCMOS etc. Some
of these techniques are state saving and some are state destructive techniques. For
example: Sleep transistor is a state destructive technique. Despite the rising
significance of static power in CMOS circuits, the dynamic power is still the major
contributor to power consumption. Dynamic power is mostly consumed by glitches
which are the unwanted transitions and need to be eliminated. Glitch and leakage
power both are the main contributors to the power consumption and needs to be
reduced.
3. MTCMOS Technique
When the physical design of the MTCMOS circuits is done, it is vital to consider the
large current flowing through the current stopping transistors in active mode and the
electro-migration in the wires should be taken into account. The channel width is also
very important due to the large current. There is a trade-off between the local and
global sleep devices. The bottleneck with local sleep devices is that there will be a
large area overhead due to the fact that there will be a lot of extra transistors[10].
The MTCMOS approach is easy on combinatorial circuits, but it can be tricky on
sequential circuits. Should the power supply be turned off, all data stored in the circuit
will be irreversibly lost. This is the main problem with MTCMOS circuits. To deal
with this problem complex timing scheme must be used or extra circuits have to be
added. Because of these added items the performance of the circuit would be degraded.
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Suman Nehra & P. K. Ghosh
This will also require a larger die area and impose higher power losses. MTCMOS
(multithreshold CMOS) reduces leakage current during standby mode and attains high
speed in active mode [11].
Figure 1: Power gating structure.
In this technique high threshold voltage transistor are used to isolate the low
threshold voltage transistor from supply and ground during standby mode. However by
including extra transistor, MTCMOS circuit faces performance penalty compared to
CMOS circuits, if the transistor are not sized properly.
The high threshold voltage transistor are turned off during standby (sleep mode) ,
this result very low sub threshold passes from Vcc to ground.[10]. MTCMOS includes
high Vt transistor to gate power and ground of a low Vt logic blocks as shown in figure
1.when the high Vt transistor are off resulting in a very low sub threshold leakage
current. When the high Vt transistor are turned on, low Vt are connected to virtual
ground and Vdd.
Figure 2: Schematic diagram of existing XNOR gate.
Design of a Low Power XNOR gate Using MTCMOS Technique
705
However there are three drawbacks in MTCMOS sequential circuits that is need to
be eliminated: first is sequential circuit will lose data when sleep transistor are turned
off, second is timing is critical for sleep signal and third is sizing of sleep transistor is
very difficult task.
The existing design of XNOR gate is shown in Fig.2. It consists of 3 transistors as
one pMOS and two nMOS. When ab=00, nMOS (both) are OFF and pMOS is ON due
to high gate voltage than threshold. As pMOS is strong ‘1’ device it will pass complete
logic “high” signal at the output.
When ab=01, one nMOS is OFF and other nMOS is ON. As nMOS is strong ‘0’
device it will pass complete logic “low” signal at the output. When ab =10, nMOS
(second) and pMOS are ON. As mobility of nMOS is nearly three times greater than
pMOS, hence it will drive the output ignoring the effect of ON pMOS transistors
which results into zero output.
When ab=11, both the nMOS transistors are ON and only nMOS will be
responsible for driving the output.
Table 1: Performance Table of XNOR gate.
a
0
0
1
1
b
0
1
0
1
Expected Output
1
0
0
1
Obtained Output
1.0
0.0
0.1
1.0
Table 1 describes the performance of 3T XNOR gate. Fig.3 shows the schematic of
proposed 3T XNOR gate with MTCMOS technique. Fig.4 shows its input-output
waveform.
Figure 3: Schematic diagram of proposed XNOR gate with MTCMOS.
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Suman Nehra & P. K. Ghosh
Figure 4: Input-output waveform of proposed Circuit.
4. Comparison and Result
All schematic simulations have been performed on Tanner EDA tool version 12.6 at
45nm technology with input voltage ranging from 0.4V to 1V in steps of 0.1V. To
establish an impartial testing environment both circuit have been tested on the same
input patterns which covers all combinations of the input stream.
Power Vs Voltage
2.00E‐04
P
o
w
e
r
1.50E‐04
1.00E‐04
Existing Ckt
5.00E‐05
Proposed Ckt
0.00E+00
0.4
0.5
0.6
0.7
0.8
0.9
1
Voltage
Figure 5: Power consumption with varying supply voltage
707
Design of a Low Power XNOR gate Using MTCMOS Technique
In order to prove that proposed design is consuming low power along with better
performance; simulations are carried out for power, power-delay product at varying
supply voltages, temperatures and frequencies.
Power Delay Product Vs Voltage
6E‐12
5E‐12
P
D
P
4E‐12
3E‐12
2E‐12
Existing Ckt
1E‐12
Proposed Ckt
0
0.4
0.5
0.6
0.7
0.8
0.9
1
Voltage
Figure 6: Power Delay Product with varying supply voltage.
Figure 5 and 6 reveal that the proposed ckt proves its superiority in terms of power
consumption, power delay product at various input voltages over the existing circuit.
Power Vs Frequency
3.50E-05
3.00E-05
P
o
w
e
r
2.50E-05
2.00E-05
1.50E-05
Existing Ckt
1.00E-05
Proposed Ckt
5.00E-06
0.00E+00
100
150
200
250
300
350
400
500
Frequency
Figure 7: Power consumption with varying frequency.
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Suman Nehra & P. K. Ghosh
Now the simulations are carried out for power, power-delay product at varying
frequencies from 100 MHz to 500 MHz, figure 7 and 8 shows the result at different
frequency. Proposed circuit shows the least power consumption.
Power Delay Product Vs Frequency
2.5E-13
2E-13
P
D
P
1.5E-13
1E-13
Existing Ckt
5E-14
Proposed Ckt
0
100
150
200
250
300
350
400
500
Frequency
Figure 8: Power Delay Product with varying frequency.
Figures 9 and 10 shows that the proposed circuit proves its superiority in terms of
power consumption, power delay product at various temperature ranging from -40
to120 over the existing circuit.
Power Vs Temperature
P
o
w
e
r
1.40E-04
1.20E-04
1.00E-04
8.00E-05
6.00E-05
4.00E-05
2.00E-05
0.00E+00
Existing Ckt
Proposed Ckt
-40
0
40
60
80
100
120
Temperature
Figure 9: Power consumption with varying temperature.
709
Design of a Low Power XNOR gate Using MTCMOS Technique
Power Delay Product Vs Temperature
4E‐12
P
D
P
3E‐12
2E‐12
Existing Ckt
1E‐12
Proposed Ckt
0
‐40
0
40
60
80
100
120
Temperature
Figure 10: Power Delay Product with varying temperature.
5. Conclusion
The proposed 8T adder has been designed and simulated on Tanner EDA tool version
12.6 at 45nm technology. The proposed XNOR gate with MTCMOS is found to give
better performance than the existing XNOR gate. It has been tested to have better
temperature sustainability and significantly less power and power-delay product at
various input voltages and frequencies. MTCMOS circuit have a marginal increase in
area compared to the CMOS circuit; overall, we achieved the lowest power dissipation
with MTCMOS technique.
6. Acknowledgements
The authors wish to thank the Management, Dean-FET and the Head of Electronics &
Communication Engineering of Mody Institute of Technology & Science (Deemed
University), Laxmangarh (District Sikar), Rajasthan, India for providing all necessary
support to carry out this research work successfully.
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