ARTICLE IN PRESS
Microelectronics Journal ] (]]]]) ]]]– ]]]
Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
A DC offset and CMRR analysis in a CMOS 0.35 mm operational
transconductance amplifier using Pelgrom’s area/accuracy tradeoff
Juan Pablo Martinez Brito , Sergio Bampi
PGMICRO—Graduate Program on Microelectronics, Federal University of Rio Grande do Sul, UFRGS, Postal Code 15064 Porto Alegre, Brazil
a r t i c l e in fo
abstract
Article history:
Received 18 February 2008
Accepted 22 February 2008
Nonideal factors which play a key role in performance and yield in high-precision operational amplifiers
are rigorously investigated. Expressions for the offset voltage (Vos) and the common-mode rejection
ratio (CMRR) are derived and correlated. The mismatch accuracy is analyzed for different transistor
geometries in a CMOS OTA (operational transconductance amplifier) in 0.35 mm technology by using the
Monte Carlo approach.
& 2008 Elsevier Ltd. All rights reserved.
Keywords:
CMOS differential operational amplifier
MOSFET mismatch modeling
Offset
CMRR
Common-mode gain
Differential gain
1. Introduction
Since the beginning of 2007 when INTEL and IBM announced
that the 45 nm CMOS technology node went into production for
major consumer electronics products [1,2], statistical device
variability became a fundamental consideration in the design of
high-performance integrated circuits for deep-submicron CMOS
technologies [3,4]. Sani Nassif, manager of IBM’s Austin Research
Lab, in an EE Times article stated [5]: ‘‘The problem isn’t the amount
of variability. It’s that we tend to turn variability into uncertainty by
not modeling it. That means we end up vastly overguard-banding our
designs’’. Hence, the problem is that for designers, mismatch (i.e.
intra-die component variations) can be usually circumvented just
by using ‘‘dribbling’’ techniques such as common-centroids and
guard-banding layouts. However, potential improvement in
matching devices may be overcome from handling statistical
design aspects as a standardized step in the design flow.
Moreover, without an accurate transistor mismatch model,
substantial margins and risk yield loss are forced to be included
in the final design given to the foundry [6]. In analog integrated
circuits, the designer had to deal with the random variability of
identical devices since it directly affects the performance of the
overall fabricated circuits and systems. Mismatches between
identically designed transistors lead to offsets in circuits such as
Corresponding author. Tel.: +55 51 3308 7749; fax: +55 51 3308 7308.
E-mail addresses: juanbrito@gmail.com, juanpablo_735@yahoo.com.br, juanbrito@ieee.org (J.P. Martinez Brito), bampi@inf.ufrgs.br (S. Bampi).
comparators, operational amplifiers (op amps), current mirrors,
etc., which then limits the available accuracy in functional blocks
such as analog-to-digital or digital-to-analog converters and
especially voltage references [7]. The large-signal (DC) transistor
mismatch model has already been adjusted/improved for the case
of deep-submicron technologies based on DC measurements of
current mismatch between identically designed transistors.
Several authors start from the physical background to calculate
and model the device mismatch dependence [8–11]. Other
authors [12] rely on experimental results to models threshold
voltage (VTH) and current factor (b ¼ COX m W/L) variations as a
function of technology parameters, bias point, device size and
distance between matched devices. This last is the well-known
Pelgrom’s law [12] for local device mismatch. In a different way,
very few studies of the small-signal (AC) transistor model
behavior and AC circuit blocks concerning mismatch have been
reported in the open literature [13–15]. The DC mismatch
characteristics will automatically lead to AC mismatch behavior
of circuit blocks, but an important open question is how smallsignal transistor parameters (i.e. gm, gds, ro, S parameters, etc.)
are affected by statistical device variability. Nevertheless, some
authors in Ref. [16] described that the drain–source transconductance (gds) is not in agreement with the Pelgrom’s proportionality
related to area (W L)1/2, but instead it follows the (W)1/2
proportionality. Hence, high-frequency analog circuits and radio
frequency integrated circuits heavily depend on device matching.
Their performance and accurate prediction depend upon the
understanding of small-signal transistor mismatches [17,18].
Quadrature generators [19], ring oscillators [20], digital-to-phase
0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2008.02.029
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
2
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
converters [21], all digital phase locked loops [22], etc., are some
circuit examples that heavily depend on the matching for their
accurate AC regime operation.
This paper focuses on a rigorous formulation of the relationship between these parameters and the performance of highprecision finite-gain amplifiers. Simple mathematical expressions
of the common-mode rejection ratio (CMRR) and the offset
voltage are developed and related to the overall performance of
high-precision finite-gain amplifiers. In Section 2 the transistor
mismatch parameters are demonstrated. A review of statistical
analysis on operational amplifier is described in Section 3. The
design procedure of the differential amplifier is in Section 4. In
Section 5 the random DC offset is analyzed. The CMRR is analyzed
in Section 6. The relation between the offset voltage and CMRR is
demonstrated in Section 7. And finally in Section 8 the conclusions
are drawn.
Fig. 2. Transistors biased by the same current.
2. Transistor mismatch parameters
Pelgrom’s model [12] considers that the random physical
variables have a normal distribution with zero mean and their
standard deviation depends on device area (W L) and device
physical distance for pairs of matched transistors. Considering
that threshold voltage (DVTH) and current factor (Db) differences
are the dominant sources of mismatch between identical MOS
transistors [23]. The variance of the relative drain–source current
error and the gate–source voltage error can be described by the
following equations [24]:
DIDS
Db
gm 2 2
þ
s2
s ðDV TH Þ
(1)
¼ s2
b
IDS
IDS
s2 ðDV GS Þ ¼ s2
Db
b
IDS
gm
2
þ s2 ðDV TH Þ
(2)
The above equations are valid for all regions of operations and
Eq. (1) is used for equal voltage biased transistors and Eq. (2) for
equal current biased transistors, which are illustrated in Figs. 1
and 2, respectively.
2.1. Voltage biasing
In practice, it is clear that in most circuits, the VTH mismatch is
dominant over the b mismatch [25]. So, Eq. (1) in terms of
standard deviation and for strong inversion can be approximated
by:
DIDS
1
2AV TH
s
(3)
¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IDS
W L V GS V TH
Fig. 3. NMOS relative drain current mismatch vs. (VGS–VTH).
and for weak inversion, it can be simplified to:
DIDS
1
AV TH
s
¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IDS
W L n UT
where AV TH is the threshold process area proportionally dependent
parameter, n is the slope factor and UT is the thermal voltage. For
this technology [26], AV TH ¼ 8:2 mV mm.
2.2. Current biasing
In the same way, by considering the VTH mismatch dominant
over b mismatch [24], Eq. (2) in terms of standard deviation and,
in this case, for all regions of operations, it can be rewritten as:
AV TH
ffi
sðDV GS Þ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi
W L
Fig. 1. Transistors biased by the same voltage.
(4)
(5)
In the case of the AMS 0.35 mm CMOS technology [26], a highly
representative plot of the measured data provided by the
manufacturer of the relative current error depending on the bias
point are depicted in Figs. 3 and 4. It is clear in these figures that
the current accuracy is inversely proportional to the square root of
the device area and the bias point. We may see that Eq. (3)
precisely predicts the values in Figs. 3 and 4 from moderate to
strong inversion. By taking Eq. (4) as the limiting left corner where
VGS–VTH is near zero. Hence, the larger the device and the higher
the gate–source bias point, the less the relative error causing
mismatch.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
3
Fig. 4. PMOS relative drain current mismatch vs. (VGS–VTH).
During the design of an analog CMOS circuit, the designer has
the freedom to choose the current, width (W) and length (L) of
each transistor. For a given current and bias point (VGS–VTH), only
the aspect ratio (W/L) of the device is fixed, but the width or the
length can still be chosen freely. The use of shorter channel
devices helps to reduce the capacitive load in the circuit. However,
due to device mismatch there is a minimal required device area to
achieve a given DC accuracy. This introduces a constraint in most
analog MOS circuits, especially in operational amplifiers. We will
show that, as a consequence, that the CMRR and the DC offset
voltage cannot be optimized independently of this DC accuracy
requirement.
Fig. 5. CMOS differential operational amplifier.
Table 1
Equations that models the DC behavior
DC characteristic Definition
I5
PDISS
Slew rate (SR)
VCMRmax
VCMRmin
Bias current
Static power consumption
Maximum output voltage rate
Maximum common-mode voltage
Minimum common-mode voltage
Equation
I5
I5(VDDVSS)
I5/CL
(VDDVDS5VSG1)ICMR+
(VSS+VGS3+VSD1VSG1)ICMR
3. Statistical analysis on operational amplifiers
The performance and yield of systems using integrated
operational amplifiers (op amps) are strongly dominated by
random variations on its components. The statistical characteristics of these parameters must be well understood to obtain highprecision performance. The tree major sources of errors in op
amps are: finite gain (Ad), finite CMRR, and nonzero offset voltage
(Vos). Because of the inherent statistical nature of the offset
voltage and CMRR and its nonlinear relationship, the performance
of amplifiers is still not fully formulated [27], causing designers to
still commit bad or nonoptimum designs to the foundry [28].
Several analyses of the random offset [29,30] and the random
CMRR [31,32] in differential amplifiers have been made, but these
analyses do not focus on the mixed effects of these nonidealities
on amplifier performance. The analysis of the random CMRR [33],
made several decades ago, concentrated only on bipolar differential amplifiers. Moreover, they focused on the methods to
increase the CMRR, not on the statistical characteristics of this
parameter which play a key role in the performance of precision
finite-gain amplifiers.
4. CMOS differential operational amplifier
Differential amplifiers are one of the more versatile circuits in
analog IC design. They are also very compatible with most of the
CMOS technologies and serve as the input stage in many Op Amp
topologies. Fig. 5 shows the schematic used in the following
analysis. At the input the NMOS transistors M1/M2 form a
differential pair transforming the differential input voltage in a
differential current. And the current mirror is formed by M3/M4
as an active load which converts the signal current to single ended
output voltage by the output conductance formed by M2 and M4.
It is the perfect combination of a voltage biased block (formed by
the current mirror M3/M4) and a current biased block (formed by
the differential pair M1/M2) as we demonstrated in Section 2. The
DC analyses behavior must be done by assuming that the
differential pair is in saturation region and the currents formed
by the current mirror are identical. In Table 1 we have the
equations that models the circuit in DC regime. The next step is
the AC analysis by its small-signal model. The small-signal model
is depicted in Fig. 6. It is assumed that both sides of the circuit are
matched. Otherwise, the source terminals cannot be connected to
ground. Table 2 shows the AC equations that model the amplifier.
The target specifications are in Table 3. Considering Ref. [34], the
next procedure seeks for the best performance regarding the
above specifications. All the DC and AC characteristics will be
calculated using the equations in Tables 1 and 2. So, the design is
as follows:
By the SR we find out the lower bias current limit which is:
I5 XSR CL ) I5 X50 mA
(6)
By the power specification we find out the upper bias current
limit which is:
I5 ¼
P DISS
) I5 p303 mA
V DD V SS
(7)
By the cutoff frequency we find out the upper limit of the
output resistance:
Rout ¼
1
) Rout p318:31 kO ) I5 X88:7 mA
2pF 3 dB C L
(8)
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
4
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
Fig. 6. Small-signal model for the CMOS differential amplifier.
Table 4
Transistor size for each circuit block
Table 2
Equations that models the AC behavior
Circuit
AC characteristic
Definition
Equation
Ad
Rout
F3 dB
GBW
Differential gain
Output resistance
Cutoff frequency
Gain bandwidth product
gm1 Rout
ro2//ro4 ¼ (2VAn/I5)//(2VAp/I5)
1/(2 p Rout CL)
gm1/2pCL
Table 3
Op Amp specifications
Specifications
Definition
Value
Ad (dB)
F3dB (KHz)
GBW (MHz)
SR (V/ms)
Pdiss (mW)
VCMR max (V)
VCMR min (V)
VDD (V)
VSS (V)
CL (pF)
Differential gain
Cutoff frequency
Gain bandwidth product
Slew rate
Power comsuption
Voltage common mode range max
Voltage common mode range min
Positive power source
Negative power source
Output load
40
X100
15
410
p1
1
0.5
1.65
1.65
5
and M2) will be calculated by the gain specification:
(10)
The size of the PMOS transistors of the current mirror (M3 and
M4) will be calculated by the VCMRmax specification:
W
W
V GS3 ¼ 1:115 V )
¼
L 3
L 4
n ID3
)
25
mo C OX ðV GS3 V TP Þ2
Op Amp05
M1/M2
M3/M4
5
12.5
0.5
0.5
10
25
Op Amp1
M1/M2
M3/M4
10
25
1
1
10
25
Op Amp2
M1/M2
M3/M4
20
50
2
2
10
25
Op Amp3
M1/M2
M3/M4
30
75
3
3
10
25
Op Amp4
M1/M2
M3/M4
40
100
4
4
10
25
Op Amp5
M1/M2
M3/M4
50
125
5
5
10
25
5. Derivation of the random DC offset voltage
The DC offset voltage (Vos) is determined by adding both
contributions in voltage by the two essential blocks: current
mirror (M3/M4) and the differential pair (M1/M2).
For the differential pair (M1/M2), both inputs are connected to
the ground. Since the differential pair is current biased, only a
voltage error will be present, so the contribution of the differential
pair (M1/M2) for the offset voltage is:
V OS12 ¼ sðDV TH Þ12
(11)
Finally, the size of the current source transistor (M5) will be
calculated by the VCMR min specification:
W
2n I5
)
30.
V DS5 ¼ 0:373 V )
L 5
mo C OX ðV DS5 Þ2
Ratio, W/L
(9)
The size of the NMOS transistors of the differential pair (M1
A
Ad ¼ 100 ) gm1 ¼ d ) gm1 ¼ 353:9 mS
ROUT
gm21
W
W
)
¼
¼
10
L 1
L 2 ðmo C OX =nÞID2
Length, L (mm)
Considering these W/L ratios for transistors M1–M5 above,
six circuits had been made for different transistor sizes, while
maintaining the W/L ratio. This can be seen in Table 4.
So the bias current will be:
I5 ¼ 100 mA ) ID1 ¼ ID2 ¼ ID3 ¼ ID4 ¼ 50 mA
Width, W (mm)
(12)
(13)
On the other hand, since the current mirror is voltage biased, the
contribution to the offset voltage will be the current error
multiplied by IDS1/gm1
IDS1
DIDS
V OS34 ¼
s
(14)
gm1
IDS 34
Since in strong inversion gm/ID ¼ 2/(VGS–VTH) and by using Eq. (4)
thus
V OS34 ¼
ðV GS V TH Þ1 2sðDV TH Þ
ðV GS V TH Þ34
2
(15)
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
Using Pelgrom’s definition:
We can rewrite the above equation as
V OS34
ðV GS V TH Þ1
¼
sðDV TH Þ34
ðV GS V TH Þ3
(16)
Therefore, the offset voltage will be the total sum of both
contributions and may be written as:
V OS
ðV GS V TH Þ1
¼ sðDV TH Þ12 þ
sðDV TH Þ34
ðV GS V TH Þ3
5
(17)
V OS ¼
!
AV THNMOS
ðV GS V TH Þ1
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
þ
W L 12 ðV GS V TH Þ3
!
AV THPMOS
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
W L 34
(18)
For a given current, however, the above equation can be
considered only as a function of size and process constants. Thus,
considering the basic SPICE level 1 current model for strong
Fig. 7. Configuration to obtain the input offset voltage.
Fig. 8. Unit-gain transfer curve of the Op Amp.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
6
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
Fig. 9. Offset voltage Monte Carlo histogram.
Table 5
Offset voltages for different transistor sizing
Vos (mV)
Op
Op
Op
Op
Op
Op
Amp05
Amp1
Amp2
Amp3
Amp4
Amp5
Calculated
Monte Carlo
7.558227
3.779113
1.889557
1.259704
0.944778
0.755823
7.74718
3.84391
1.87029
1.28195
1.00129
0.792677
Fig. 11. Configuration to obtain the common-mode gain.
By substitution of Eq. (19) in Eq. (18)
!
AV THNMOS
ffi
V OS ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi
W L 12
!
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ð2IDS =ðmo C OX ÞÞðL=W 1 Þ AV THPMOS
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ð2IDS =ðmo C OX ÞÞðL=W 3 Þ
W L 34
As the current at the branch is the same, we can rewrite the above
equation as
!
AV THNMOS
V OS ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
W L 12
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
s
!
AV THPMOS
1
L
mo C OX W
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
þ
(21)
mo C OX W 1
L 3
1
W L 34
Fig. 10. Half-circuit schematic.
inversion, we can rewrite the overdrive potential as:
V GS V TH
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2IDS
L
¼
mo C OX W
(20)
(19)
This will have the following final format:
!
!
2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
AV THNMOS
AV THPMOS
bP
L
W
ffi
pffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
V OS ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi
þ
W 1 L 3
bN
W L 12
W L 34
(22)
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
By this equation, in accordance with Ref. [35], one design rule
becomes apparent: low offset can be achieve for large values of
the W/L (or small value of L/W) ratio in the transistors of the
differential pair (M1/M2) and, for small values the W/L ratio in the
transistors of the current mirror (M3/M4). It should be pointed
that this formulation for the offset voltage, does not follow the
Pelgrom’s device area proportionality.
5.1. Random offset simulation and statistical analyses
The DC input offset voltage, Vos, can be obtained using the
circuit in Fig. 7 [36]. By simulating the transfer curve (Vout Vin) of
the op amp we may obtain the following curve in Fig. 8. In this
curve the value of the systematic offset voltage will be obtained
by the zero-crossing of the vertical axis (Vout). By taking this point,
and running 1000 runs of Monte Carlo analysis for the six op amps
in Table 4, the following six Gaussian histograms for each circuit
are depicted in Fig. 9. The random offset voltage for each of the six
circuits in Table 4 will be represented the standard deviation of
each Gaussian histogram. These values are compared in Table 5 by
7
taking Eq. (22) and the standard deviation of each histogram in
Fig. 9. Fig. 8 also shows the input common-mode range (ICMR)
pointed out by markers A and B.
6. Derivation of the random CMRR
The CMRR of a differential amplifier measures the tendency of
the device to reject input signals common to both input leads. A
high CMRR is important in applications where the signal of
interest is represented by a small voltage fluctuation superimposed on a (possibly large) voltage offset, or when relevant
information is contained in the voltage difference between two
signals. The CMRR of a differential amplifier determines the
attenuation applied to the offset. The CMRR, in positive decibels, is
defined in terms of the differential gain (AD) and the commonmode gain (AC), as:
CMRR ¼
AD
jAC j
or
CMRR ¼ 20 logðAD Þ 20 logðjAC jÞ
(23)
Fig. 12. Common-mode gain vs. frequency simulation; absolute value.
Fig. 13. Common-mode gain vs. frequency simulation; values in decibels.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
8
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
As shown in Table 2 the differential mode gain AD of the op amp
can be rewritten as:
AD gm1
gm3
(24)
To simplify the common-mode gain calculations we use the
symmetry half-circuit attribute depicted in Fig. 10. As written in
Ref. [37] the common-mode gain can be writing regarding Fig. 10
as:
AD gds5
gm3
gm1 =gm3
¼ gm1 rds5
j gds5 =gm3 j
6.1. Common-mode gain analysis
As defined in Ref. [42] the common-mode gain (AD) can be
defined for transconductance mismatch as:
(25)
AD Thereby, the CMRR will be written as:
CMRR ¼
also affected by random process variations, the common-mode
gain will be the major contribution for a smaller CMRR. The next
section will analyze the common-mode gain under random
process variations using the Monte Carlo approach.
(26)
However, to describe the CMRR as random variations in transistor,
we need to obtain the real behavior under process variations of
the common-mode gain AC. Although the differential gain AD it is
½ðgm1 gm2 Þro3 gm2 =gm3 gds5
1 þ ðgm1 þ gm2 Þ
(27)
Using simulation the common-mode gain may be obtained by
using the circuit topology depicted in Fig. 11. By running 1000 of
statistical analysis using Monte Carlo approach, the commonmode gain vs. frequency is shown in Figs. 12 and 13 for the
absolute and the decibel values, respectively. In each figure, the
arrow shows the first Monte Carlo run, which is the ideal case
Fig. 14. Monte Carlo histogram of common-mode gain; absolute value.
Fig. 15. Monte Carlo histogram of common-mode gain; decibels.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
without transistor mismatches. As shown, the common-mode
gain starts from near zero in Fig. 12 and at approximately 180 dB
in Fig. 13. By taking the DC value of the curve in Fig. 12 the
following histogram in Fig. 14 will be generated by the Monte
Carlo analysis. Regarding Fig. 14 we see that the probability
density function has the form of an exponential distribution. The
exponential distribution occurs naturally when describing the
lengths of the inter-arrival times in a homogeneous Poisson
processes. The exponential distribution may be viewed as a
continuous counterpart of the geometric distribution [39]. Hence,
the common-mode gain does not obey the Pelgrom’s law for
device mismatch. As depicted in Fig. 15 the six histograms are for
the six op amp designed for different transistors sizes in Table 4.
Neither the standard deviation nor the mean of histograms in
Fig. 15 obeys the relation of Pelgrom’s law. That is, compared
with Fig. 9, the values of the standard deviation are decreasing
since the device size is increased. Instead, in Fig. 15 there is not a
9
metric that rules the values arranged in an increased or decreased
order.
6.2. Random CMRR simulation and statistical analyses
Fig. 16 shows the configuration that intuitively extracts the
CMRR directly according to the definition [40]. By dividing the
gain of the right output circuit (differential gain—AD) by the
modulus of the gain on the left output circuit (common-mode
gain—AC) the CMRR can be obtained. The typical CMRR frequency
response without transistors imbalances has the following
response in Fig. 17. Therefore, the CMRR frequency responses
considering the mismatch among transistor are depicted in Figs.
18 and 19 in decibels and in absolute value, respectively. In Fig. 20
the following six histograms for each op amp designed are shown.
Regarding the mean and the standard deviation in Fig. 20, in the
Fig. 16. Configuration to obtain the CMRR.
Fig. 17. Typical CMRR frequency response.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
10
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
Fig. 18. Monte Carlo analyses for CMRR in decibels.
Fig. 19. Monte Carlo analysis for CMRR in absolute value.
Fig. 20. CMRR Monte Carlo histogram in decibel.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
11
same way, the CMRR value does not obey the Pelgrom’s law. This
is because the common-mode gain plays a key role to obtain this
value.
7. Finite CMRR and nonzero DC offset voltage relation
CMRR and offset voltage were related in the 1970s for bipolar
amplifiers [41,42]. The reciprocal CMRR can be thought as the
change in offset voltage (Vos) produced by a unit gain change in
common-mode input voltage (Vcm in). The original equation is
written as:
1
jAC j
qV OS
¼
¼
CMRR
jAD j qV CM
(28)
Indeed defined by Ref. [38], the common-mode gain (AC) can be
interpreted as the change in the output offset voltage (Vos out)
divided by the change in the input common-mode level. So we
write:
AC ¼
DV os out
DV cm in
(29)
As defined in Eq. (23):
CMRR ¼
AD
AD
DV cm in
¼
¼
jAC j DV os out =DV cm in DV os out =AD
(30)
Since DVos out/AD is defined as the input offset voltage (DVos in)
then:
CMRR ¼
DV cm in
DV os in
Fig. 21. Circuit used to obtain the Vos/CMRR relation.
(31)
By combining Eqs. (22) and (27) we may see the relation between
Vos and CMRR [43] as
V os CMRR ¼
V GS1 V TH
ð2gm1 R5 Þ
2
(32)
divided by the differential voltage gain (AD) of the DUT. This
change in vi can be measured at VOUT as approximately 1000 vi.
Thus, the CMRR can be found as
(33)
CMRR ¼
Or, since gm1 ¼ I5/(VGS1 ¼ VTH)
V os CMRR ¼ I5 R5
However, for a single-transistor current source (I5), the output
resistance is simply the early voltage (VA) resistance given by
R5 ¼ VA5 L5/I5. Hence,
V os CMRR ¼ VA5 L5
(34)
Therefore, the offset voltage (Vos) and the CMRR are unambiguously correlated. Hence, techniques that are applied to reduce the
offset voltage will automatically increase the CMRR, and vice
versa.
7.1. Evaluation of CMRR and offset relation
The method to obtain the CMRR Vos relation is given by the
schematic in Fig. 21. The second op amp, which is an ideal op amp,
will not be affected by process variations. Its output is applied to
the op amp under test (DUT) through a 1000:1 V divider, so that
the voltage at the output of the second amplifier is 1000 times the
voltage at the input of the DUT required to produce Va through the
feedback configuration. Since Va in this case is 0 V, the output
voltage VOUT will be just 1000 times of the offset voltage of the
DUT.
From a static viewpoint, to simulate a change in the common
mode input voltage, it is necessary to produce a symmetrical
change in the VSET sources. That is, vary VSET from 1 to +1 V, for
example. This change (DVSET) will cause a variation at the output
and the power supplies to the DUT. As a result of this voltage
variantion, vi will appear at the input of the DUT. In this case, vi
will be equal to the common-mode output voltage (VCM) of 1 V
2000
jDV SET j
(35)
If the VSET sources are replaced by a small-signal voltage called
VICM and since the resulting change in VOUT is just 1000 times the
change in offset voltage (VOS), then it can be shown that the CMRR
can be given as
CMRR ¼ 1000 DV icm
DV os
(36)
Using this approach, one could apply VICM and sweep the
frequency to measure VOS and the CMRR as a function of
frequency.
8. Conclusion
Mathematical relationships between the CMRR and the offset
voltage were developed and correlated to the overall performance
of differential amplifiers. Some inherent parameters in the OTA do
not follow Pelgrom’s law, for example the offset voltage (Vos). In
our case, the common-mode gain (AC) demonstrates that its
probability distribution has the form of an exponential distribution. However, the correlation between the offset voltage and
CMMR is well demonstrated. It seems to be easy to predict
statistical behavior for devices and their interaction with
technology. Nevertheless, the ways to predict these effects by
statistical simulations (Monte Carlo approach) on a system level
are much more complex to accomplish.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029
ARTICLE IN PRESS
12
J.P. Martinez Brito, S. Bampi / Microelectronics Journal ] (]]]]) ]]]–]]]
Acknowledgments
The authors would like to thank the CAPES NSF Brazilian
Agency for the support of the PGMICRO Graduate Program and the
scholarship of CNPq/PNM Program. Thanks also to the anonymous
reviewers for their helpful suggestions.
References
[1] Hafnium-based Intels 45 nm Process Technology, /http://www.intel.com/
technology/45nmS (accessed 17.04.08).
[2] IBM ASIC Solutions Brochure, Publication Number: TGB03004-USEN-00,
Revision date: 4.06.07, /http://www-01.ibm.com/chips/techlib/techlib.nsf/
products/ASIC_Cu-45HPS (accessed 17.04.08).
[3] M.J.M. Pelgrom, SE2 circuit design in the year 2012, in: Solid-State Circuits
Conference 2007, ISSCC 2007, Digest of Technical Papers, IEEE International,
11–15 February 2007, pp. 14–15.
[4] J. Hartmann, Towards a new nanoelectronic cosmology, in: Solid-State
Circuits Conference 2007, ISSCC 2007, Digest of Technical Papers, IEEE
International, 11–15 February 2007, pp. 31–37.
[5] R. Wilson, The dirty little secret: engineers at design forum vexed by rise in
process variations at the die level, EE Times, 25 March 2002, /http://
www.eetimes.com/issue/fp/OEG20020324S0002S, p. 1.
[6] P.G. Drennan, C.C. McAndrew, Understanding MOSFET mismatch for analog
design, IEEE J. Solid-State Circuits 38 (3) (2003) 450–456.
[7] J.P. Martinez Brito, S. Bampi, H. Klimach, A 4-bits trimmed CMOS bandgap
reference with an improved matching modeling design, in: Circuits and
Systems 2007, ISCAS 2007, IEEE International Symposium, 27–30 May 2007,
pp. 1911–1914.
[8] K.R. Lakshmikumar, R.A. Hadaway, M.A. Copeland, Characterisation and
modeling of mismatch in MOS transistors for precision analog design, IEEE
J. Solid-State Circuits 21 (6) (1986) 1057–1066.
[9] J.-B. Shyu, G.C. Temes, F. Krummenacher, Random error effects in matched
MOS capacitors and current sources, IEEE J. Solid-State Circuits 19 (6) (1984)
948–956.
[10] C. Galup-Montoro, M.C. Schneider, H. Klimach, A. Arnaud, A compact model of
MOSFET mismatch for circuit design, IEEE J. Solid-State Circuits 40 (8) (2005)
1649–1657.
[11] T. Mizuno, J. Okamura, A. Toriumi, Experimental study of threshold voltage
fluctuation due to statistical variation of channel dopant number in MOSFETs,
IEEE Trans. Electron Devices 41 (11) (1994) 2216–2221.
[12] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS
transistors, IEEE J. Solid-State Circuits 24 (5) (1989) 1433–1439.
[13] A. Perrotin, D. Gloria, S. Danaie, F. Pourchon, M. Laurens, High frequency
mismatch characterization on 170 GHz HBT NPN bipolar device, in: IEEE
International Conference on Microelectronic Test Structures (ICMTS), March
2006, pp. 163–168.
[14] L.J. Choi, R. Venegas, S. Decoutere, High-frequency measurements of the
mismatch on the Y-parameters of high-speed SiGe:C HBTs, in: IEEE
International Conference on Microelectronic Test Structures (ICMTS), 2006,
pp. 163–168.
[15] K. Waheed, R.B. Staszewski, Digital RF processing techniques for device
mismatch tolerant transmitters in nanometer-scale CMOS, in: Circuits and
Systems 2007, ISCAS 2007, IEEE International Symposium, 27–30 May 2007,
pp. 1253–1256.
[16] R. Thewes, C. Linnenbank, U. Kollmer, S. Burges, U. Schaper, R. Brederlow, W.
Weber, Mismatch of MOSFET small signal parameters under analog operation,
Electron Device Lett. IEEE 21 (12) (2000) 552–553.
[17] B. Razavi, RF Microelectronics, first ed., Prentice-Hall PTR, Upper Saddle River,
NJ, 1998.
[18] T.H. Lee, Design of CMOS Radio-Frequency Integrated Circuits, second ed.,
Cambridge University Press, 1998.
[19] P. Kinget, R. Melville, D. Long, V. Gopinathan, An injection locking scheme for
precision quadrature generation, IEEE J. Solid-State Circuits 37 (7) (2002)
845–851.
[20] A. Balankutty, T.C. Chih, C.Y. Chen, P.R. Kinget, Mismatch characterization of
ring oscillators, in: Custom Integrated Circuits Conference 2007, CICC ’07,
IEEE, 16–19 September 2007, pp. 515–518.
[21] P. Hanumolu, V. Kratyuk, G.-Y. Wei, U.-K. Moon, A sub-picosecond resolution
0.5–1.5 GHz digital-to-phase converter, in: Digest of Technical Papers,
Symposium on VLSI Circuits, June 2006, pp. 75–76.
[22] J.P. Brito, S. Bampi, Design of a digital FM demodulator based on a 2nd order
all-digital phase-locked loop, in: Proceedings of the 20th Annual Conference
on Integrated Circuits and Systems Design, SBCCI ’07, ACM, New York, NY,
2007, pp. 137–141.
[23] P. Kinget, Device mismatch and tradeoffs in the design of analog circuits, IEEE
J. Solid-State Circuits 40 (6) (2005) 1212–1224.
[24] P. Kinget, M. Steyaert, Analog VLSI integration of massive parallel signal
processing systems, Kluwer Academic Publishers, 1997.
[25] P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed–accuracy–power trade-off of analog CMOS circuits, in: Custom Integrated Circuits
Conference 1996, Proceedings of the IEEE 1996, 5–8 May 1996, pp. 333–336.
[26] Austria Mikro System International AG 0.35 mm CMOS C35, Matching
Parameters, Document no. ENG – 228, Rev. 2.0.
[27] C.C. Enz, G.C. Temes, Circuit techniques for reducing the effects of op-amp
imperfections: autozeroing, correlated double sampling, and chopper
stabilization, Proc. IEEE 84 (11) (1996) 1584–1614.
[28] C.G. Kim, R.L. Geiger, Nonideality consideration for high-precision amplifiersanalysis of random common-mode rejection ratio, IEEE Trans. Circuits Syst. I
CAS-40 (1993) 1–12.
[29] P.R. Gray, R.G. Meyer, Analysis and Design of Analog Integrated Circuits,
fourth ed., Wiley, 2001.
[30] R. Gregorian, G.C. Temes, Analog MOS Integrated Circuits For Signal
Processing, first ed., Wiley-Interscience, 1986.
[31] I.J.I. Brown, Differential amplifiers that reject common-mode currents, IEEE J.
Solid-State Circuits SC-6 (1971) 385–391.
[32] P.M. Vanpeterghem, J.F. Duque-Carrillo, A general description of commonmode feedback in fully-differential amplifiers, in: Proceedings of IEEE
International Symposium CAS, McGraw-Hill, New York, 1990, pp. 326–3212.
[33] G. Meyer-Brotz, A. Kley, The common-mode rejection of transistor differential
amplifiers, IEEE Trans. Circuits Theory CT-13 (1966) 171–175.
[34] Current mirror load differential amplifier design procedure, in: P.E. Allen, D.R.
Holberg (Eds.), CMOS Analog Circuit Design, second ed., Oxford University
Press, New York, 2002, p. 197.
[35] Differential stage with active load, in: K. Laker, W. Sansen (Eds.), Design of
Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 540.
[36] Simulation and measurement in Op Amps, in: P.E. Allen, D.R. Holberg (Eds.),
CMOS Analog Circuit Design, second ed., Oxford University Press, New York,
2002, p. 312.
[37] Calculation of the Worst-Case input common-mode range of the N-channel
input, differential amplifier, small signal analysis, in: P.E. Allen, D.R. Holberg
(Eds.), CMOS Analog Circuit Design, second ed., Oxford University Press, New
York, 2002, p. 191.
[38] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[39] L. Devroye, Non-Uniform Random Variate Generation, Springer, New York,
1986.
[40] J. Zhou, J. Liu, On the measurement of common-mode rejection ratio, Circuits
and Systems II: Express Briefs, IEEE Transactions [see also Circuits and
Systems II: Analog and Digital Signal Processing, IEEE Transactions], vol. 52,
no. 1, January 2005, pp. 49–53.
[41] R.C. Jaeger, Unifying the concepts of offset voltage and common-mode
rejection ratio [bipolar differential amplifiers], IEEE J. Solid-State Circuits 11
(4) (1976) 557–561.
[42] P. Gray, R. Meyer, Recent advances in monolithic operational amplifier design,
IEEE Trans. Circuits Syst. 21 (3) (1974) 317–327.
[43] Relation between random Vosr and CMRRr, in: K. Laker, W. Sansen (Eds.),
Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 546.
Please cite this article as: J.P. Martinez Brito, S. Bampi, A DC offset and CMRR analysis in a CMOS 0.35 mm operational transconductance
amplifier using Pelgrom’s area/accuracy tradeoff, Microelectron. J (2008), doi:10.1016/j.mejo.2008.02.029