Thermal Characteristics ___________________________________________________________________________________________________ ZiLOG, Inc. 1H Year 2003 Thermal Characteristics ________________________________________________________________________________________________ DC03-0020 Page 1 of 6 Revision 2 Thermal Characteristics ___________________________________________________________________________________________________ TABLE OF CONTENTS Calculation of Device Junction Temperature............................................................................................3 Device θJA, θJC Table Summary Of Thermal Characteristics For ZiLOG Plastic Packages .................4 Device θJA, θJC Table Summary Of Thermal Resistance For Hermetic Packages ................................6 ________________________________________________________________________________________________ DC03-0020 Page 2 of 6 Revision 2 Thermal Characteristics ___________________________________________________________________________________________________ Thermal Characteristics THERMAL CHARACTERISTICS Calculation of Device Junction Temperature Failure rates and Failures in Time (FITS) obtained from life test data are based on ambient temperatures (TA), and are not corrected to junction temperature (TJ). However, when a significant difference between TA and TJ exists, TJ can be incorporated into the Arrhenius Equation for accelerated failure rates by using the following equations: Junction Temp. (TJ): TJ = (θJA) (PD) + TA where: θJA is the thermal resistance of junction with respect to ambient (C/W). PD is the maximum power dissipation at TA in watts and: TA is the ambient temperature °C. Case Temperature (TC): where: Illustration: TC = TJ – (θJC) (PD) θJC is the thermal resistance of junction with respect to case. In order to calculate junction temperature (TJ) and case temperature (TC) for static airflow for the Z86C04 in an 18L PDIP, we do the following: 1. At 25°C, maximum power dissipation for this device is 0.08 watts. 2. For our example, ambient temperature is denoted by TA and is assumed to be 25°C. For the Z86C04 in plastic (copper); θJA and θJC are 75 and 18°C/watt respectively. Therefore, TJ = 75 x (0.08) + 25 = 31.2°C, and TC = 31.2 – (18 x 0.08) = 29.8°C ________________________________________________________________________________________________ DC03-0020 Page 3 of 6 Revision 2 Thermal Characteristics ___________________________________________________________________________________________________ Table 1-1. Device θJA, θJC Table Summary Of Thermal Characteristics For ZiLOG Plastic Packages Package Type PDIP 18L 20L 28L 40L 42L 48L 52L 64L PLCC 44L 68L 84L QFP 44L 80L 100L VQFP 64L 100L SOIC 8L 18L 20L 28L SSOP 20L 28L 48L EPT SSOP 28 Package Code P θJA θJC Lead Frame 75 75 60 43 42 40 38 42 18 18 12 12 11 8 8 14 Cu Cu Cu Cu Cu Cu Cu Cu 46 43 42 13 14 12 Cu Cu Cu 45 43 38 10 16 17 Cu Cu Cu 70 100 19 25 Cu Cu 110 70 75 60 N/A N/A N/A N/A Cu Cu Cu 75 60 45 18 12 12 Cu Cu Cu 36 10 Cu V F A S HZ HT ________________________________________________________________________________________________ DC03-0020 Page 4 of 6 Revision 2 Thermal Characteristics ___________________________________________________________________________________________________ Table 1-1. Device θJA, θJC Table Summary Of Thermal Characteristics For ZiLOG Plastic Packages Package Type PDIP LCC 44L 52L 68L Package Code P L θJA θJC 53 48 40 7 10 6 Lead Frame ________________________________________________________________________________________________ DC03-0020 Page 5 of 6 Revision 2 Thermal Characteristics ___________________________________________________________________________________________________ Table 1-2. Device θJA, θJC Table Summary Of Thermal Resistance For Hermetic Packages PBGA 256L 256L CERDIP 28 40 48 Ceramic Side Braze 18 28 40 48 Ceramic Window 44L Pin Grid Array 68L Notes: B 25 21 N/A N/A 52 41 32 14 11 5 81 21 49 48 36 11 11 4 32 3 36 6 2 Layer 4 Layer D C K G P=Plastic DIP C=Ceramic DIP D=Cerdip L=LCC-Ceramic Leadless Chip Carrier V=PLCC-Plastic Leaded Chip Carrier F=QFP-Plastic Quad Flat Pack A=VQFP-Very Small Quad Flat Pack G=Ceramic Pin Grid Array S=SOIC-Small Outline Integrated Circuit B=PBGA-Plastic Ball Grid Array HZ=SSOP-Shrink Small Outline Package HT=EPT SSOP-Exposed Pad Thin SSOP ________________________________________________________________________________________________ DC03-0020 Page 6 of 6 Revision 2