Lecture #13
OUTLINE
„ MOSFET ID
vs. VGS characteristic
„ Circuit models for the MOSFET
resistive
switch model
small-signal model
Reading
„
Howe & Sodini: Chapter 8.1, 8.3
„
Hambley: Chapter 12.1-12.5
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
1
Velocity Saturation
At high electric fields, the average velocity of carriers is
NOT proportional to the field; it saturates at ~107 cm/sec
for both electrons and holes:
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
2
1
Current Saturation in Modern MOSFETs
„
In digital ICs, we typically use transistors with the
shortest possible gate-length for high-speed operation.
„
In a very short-channel MOSFET, ID saturates because
the carrier velocity is limited to ~107 cm/sec
v is not proportional to E,
due to velocity saturation
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
3
Consequences of Velocity Saturation
1. ID is lower than that predicted by the mobility model
2. ID increases linearly with VGS − VT rather than
quadratically in the saturation region
V
⎡
⎤
I DSAT = WCox ⎢VGS − VT − DSAT ⎥ vsat
2 ⎦
⎣
L
where VDSAT =
vsat
μn
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
4
2
MOSFET VT Measurement
„
VT can be determined by plotting ID vs. VGS,
using a low value of VDS :
I D = k n′
ID (A)
0
VT
W
L
VDS ⎤
⎡
−
−
V
V
VDS
T
⎢ GS
2 ⎥⎦
⎣
VGS (V)
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
5
Subthreshold Conduction (Leakage Current)
„
The transition from the ON state to the OFF state
is gradual. This can be seen more clearly when
ID is plotted on a logarithmic scale:
„
In the subthreshold
(VGS < VT) region,
VDS > 0
⎛ qV GS ⎞
I D ∝ exp ⎜
⎟
⎝ nkT ⎠
This is essentially the channelsource pn junction current.
(Some electrons diffuse from the
source into the channel, if this
pn junction is forward biased.)
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
6
3
Qualitative Explanation for Subthreshold Leakage
„ The channel Vc (at the Si surface) is capacitively
coupled to the gate voltage VG:
DEVICE
CIRCUIT MODEL
VG
VG
n+ poly-Si
ΔVc =
VD
n+
Cox
n+
Cdep
depletion Wdep
region p-type Si
+
Vc
–
C dep =
Using the capacitive
voltage divider formula:
ε Si
W dep
∝
EE40 Summer 2005: Lecture 13
1
NA
C ox
ΔVG
C ox + C dep
The forward bias on
the channel-source pn
junction increases with
VG scaled by the factor
Cox / (Cox+Cdep)
⇒ n=
Cox + Cdep
Cox
= 1+
Cdep
Cox
Instructor: Octavian Florescu
7
Slope Factor (or Subthreshold Swing) S
„
S is defined to be the inverse slope of the log (ID)
vs. VGS characteristic in the subthreshold region:
VDS > 0
⎛ kT
S ≡ n⎜⎜
⎝ q
⎞
⎟⎟ ln(10)
⎠
Units: Volts per decade
1/S is the slope
Note that S ≥ 60 mV/dec
at room temperature:
⎛ kT ⎞
⎜⎜ ⎟⎟ ln(10) = 60 mV
⎝ q ⎠
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
8
4
VT Design Trade-Off
(Important consideration for digital-circuit applications)
„ Low VT is desirable for high ON current
1<η<2
IDSAT ∝ (VDD - VT)η
where VDD is the power-supply voltage
…but high VT is needed for low OFF current
log IDS Low VT
High VT
IOFF,low VT
IOFF,high VT
VGS
0
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
9
The MOSFET as a Resistive Switch
„
For digital circuit applications, the MOSFET is
either OFF (VGS < VT) or ON (VGS = VDD). Thus,
we only need to consider two ID vs. VDS curves:
the curve for VGS < VT
the curve for VGS = VDD
1.
2.
ID
VGS = VDD (closed switch)
Req
VDS
VGS < VT (open switch)
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
10
5
Equivalent Resistance Req
„
In a digital circuit, an n-channel MOSFET in the
ON state is typically used to discharge a
capacitor connected to its drain terminal:
gate
voltage VG = VDD
source voltage VS = 0 V
drain voltage VD initially at VDD, discharging toward 0 V
Cload
I DSATn =
k n′ W
(VDD − VTn )2
2 L
EE40 Summer 2005: Lecture 13
The value of Req should be
set to the value which gives
the correct propagation
delay (time required for
output to fall to ½VDD):
3 VDD ⎛ 5
⎞
Req ≅
⎜1 − λnVDD ⎟
4 I DSATn ⎝ 6
⎠
Instructor: Octavian Florescu
11
Typical MOSFET Parameter Values
„
For a given MOSFET fabrication process
technology, the following parameters are known:
(~0.5 V)
Cox and k′ (<0.001 A/V2)
VDSAT (≤ 1 V)
λ (≤ 0.1 V-1)
VT
Example Req values for 0.25 μm technology (W = L):
How can Req be decreased?
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
12
6
MOSFET Model for Analog Circuits
„
For analog circuit applications, the MOSFET is
biased in the saturation region, and the circuit is
designed to process incremental signals.
A DC operating point is established by the bias voltages VBIAS
and VDD, such that VDS > VGS – VT
Incremental voltages vs and vds that are much smaller in
magnitude perturb the operating point
The MOSFET small-signal model is a circuit which models the
change in the drain current (id) in response to these
perturbations
vs
ID + id RD
−
+
G
D
+
+ VDD
MOSFET V + v
VBIAS +
DS
ds
–
–
S
EE40 Summer 2005: Lecture 13
S
−
Instructor: Octavian Florescu
13
NMOSFET Small-Signal Model
G
id +
+
gmvgs
vgs
S
ro
−
vds
−
∂i
∂i
id = D v gs + D vds = g m v gs + g o vds
∂vGS
∂vDS
gm ≡
∂iD W
≅ k ′(VGS − VT )
∂vGS
L
go ≡
∂iD
≅ λI D
∂vDS
EE40 Summer 2005: Lecture 13
D
S
transconductance
output conductance
Instructor: Octavian Florescu
14
7
Notation
„
Subscript convention (Lecture 2, Slide 11):
ƒ
„
VDS ≡ VD – VS , VGS ≡ VG – VS , etc.
Double-subscripts denote DC sources (Lecture 23, Slide 7):
ƒ
VDD , VCC , ISS , etc.
To distinguish between DC and AC components of an
electrical quantity, the following convention is used:
•
–
DC quantity: upper-case letter with upper-case subscript
ƒ ID , VDS , etc.
–
AC quantity: lower-case letter with lower-case subscript
ƒ id , vds , etc.
–
Total (DC + AC) quantity:
lower-case letter with upper-case subscript
ƒ iD , vDS , etc.
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
15
P-Channel MOSFET Example
„
In a digital circuit, a p-channel MOSFET in the
ON state is typically used to charge a capacitor
connected to its drain terminal:
gate
voltage VG = 0 V
source voltage VS = VDD (power-supply voltage)
drain voltage VD initially at 0 V, charging toward VDD
VDD
Req ≅
0V
iD
Cload
EE40 Summer 2005: Lecture 13
3 VDD ⎛ 5
⎞
⎜1 − λ pVDD ⎟
4 I DSATp ⎝ 6
⎠
I DSAT = −
k ′p W
V DD − VTp
2 L
Instructor: Octavian Florescu
(
)
2
16
8
Common-Source (CS) Amplifier
„
The input voltage
vs causes vGS to
VDD
vary with time,
which in turn
causes iD to vary. RD
„
iD
−
VBIAS
+
–
vs
The changing voltage
drop across RD causes
an amplified (and
inverted) version of the
input signal to appear
at the drain terminal.
+
+
+
vIN = vGS
EE40 Summer 2005: Lecture 13
−
vOUT = vDS
−
Instructor: Octavian Florescu
17
Load-Line Analysis of CS Amplifier
„
The operating point of the circuit can be determined
by finding the intersection of the appropriate
MOSFET iD vs. vDS characteristic and the load line:
iD (mA)
load-line equation:
VDD = RD iD + vDS
vGS (V)
vDS (V)
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
18
9
Voltage Transfer Function
vOUT
vIN
Goal:
Operate the amplifier
in the high-gain region,
so that small changes
in vIN result in large
changes in vOUT
(1): transistor biased in cutoff region
(2): vIN > VT ; transistor biased in saturation region
(3): transistor biased in saturation region
(4): transistor biased in “resistive” or “triode” region
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
19
Quiescent Operating Point
„
The operating point of the amplifier for zero input
signal (vs = 0) is often referred to as the quiescent
operating point or Q point.
The
Q point should be chosen so that the output voltage
is approximately centered between VDD and 0 V.
vs
varies the input voltage around the Q point.
Note: The relationship between vOUT and vIN is not linear;
this results in a distorted output voltage signal. If the
input signal amplitude is very small, however, we can
have amplification with negligible distortion.
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
20
10
Bias Circuit Example
VDD
RD
R1
R2
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
21
Rules for Small-Signal Analysis
„
A DC supply voltage source acts as a short circuit
Even
if AC current flows through the DC voltage source,
the AC voltage across it is zero.
„
A DC supply current source acts as an open circuit
Even
if AC voltage is applied across the current source,
the AC current through it is zero.
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
22
11
Small-Signal Equivalent Circuit
G
+
vin
D
+
+
R1
gmvgs
R2 vgs
−
ro
RD vout
−
−
S
S
v out = − g m v gs (ro || R D )
voltage gain
Av =
v out
= − g m (ro || R D )
vin
EE40 Summer 2005: Lecture 13
1.
Voltage amplifier
Instructor: Octavian Florescu
Amplifier Types
+
input & output signals are voltages vin
−
2.
23
+
vout
amplifier
−
Current amplifier
input and output signals are currentsiin
iout
amplifier
3.
Transconductance amplifier
input signal is voltage;
output signal is current
+
vin
−
4.
Transresistance amplifier
input signal is current;
output signal is voltage
EE40 Summer 2005: Lecture 13
iout
amplifier
iin
Instructor: Octavian Florescu
+
vout
amplifier
−
24
12
Two-Port Amplifier Model
for a transconductance amplifier
iout
+
vin
Rin
gmvin
Rout
−
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
25
Effect of Source and Load Resistances
Rs
iout
+
vs
+
–
vin
Rin
gmvin
Rout
RL
−
„
Overall transconductance is degraded by the
source resistance Rs and load resistance RL
iout ⎛ Rin ⎞ ⎛ Rout ⎞
⎟
⎟gm ⎜
=⎜
v s ⎜⎝ Rin + R s ⎟⎠ ⎜⎝ R L + Rout ⎟⎠
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
26
13
NMOSFET Summary: Current Flow
NMOSFET Circuit Symbol
NMOSFET Structure
iG
iS
n+ poly-Si
n+
n+
p-type Si
iB
Gate current iG = 0
Body current iB = 0
Æ iS = −iD
EE40 Summer 2005: Lecture 13
iD
vG
+ G
S
−
S
− vDS +
D
If vGS ≤ VT, iD = 0
If vGS > VT, iD > 0
Current is limited by either
• the resistance of the
inversion-charge layer, or
• velocity saturation
Instructor: Octavian Florescu
27
NMOSFET Summary: Modes of Operation
• When vGS ≤ VT, an n-type channel is not formed.
Æ No electrons flow from SOURCE to DRAIN
“CUTOFF mode”
• When vGS > VT, an n-type channel (“inversion” layer of
electrons at the surface of the semiconductor) is formed.
Æ Electrons may flow from SOURCE to DRAIN (iD > 0)
If vDS < vGS–VT, the inversion layer exists across the
entire channel length, and current iD increases with vDS
“LINEAR mode” or “TRIODE mode”
If vDS ≥ vGS–VT, the inversion layer is pinched off at the
drain end, and current iD does not increase with vDS
“SATURATION mode”
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
28
14
NMOSFET Summary: I-V Characteristics
iD
n+
n+
n+
p
“LINEAR”
or
“TRIODE”
n+
p
“SATURATION”
vGS = VG3 > VG2
vDS = vGS–VT ≡ VDSAT
n+
vGS = VG2 > VG1
n+
p
0
“CUTOFF”
( vGS ≤ VT )
EE40 Summer 2005: Lecture 13
vGS = VG1 > VT
vDS
n+
n+
p
Instructor: Octavian Florescu
29
NMOSFET Summary: I-V Equations
“LINEAR” or “TRIODE”
iD = kn′
W
L
“SATURATION”
vDS ⎤
⎡
v
V
vDS
−
−
T
⎢⎣ GS
2 ⎥⎦
iD
iD =
k n′ W
(vGS − VT )2
2 L
vDS = vGS–VT ≡ VDSAT
vGS > VT
vDS
0
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
30
15
PMOSFET I-V Equations
iD
0 v
DS
|vGS| > |VTp|
vDS = vGS–VT ≡ VDSAT
“LINEAR” or “TRIODE”
“SATURATION”
iD = −
k ′p W
(vGS − VTp )2
2 L
EE40 Summer 2005: Lecture 13
iD = −k ′p
W
L
vDS ⎤
⎡
⎢⎣vGS − VTp − 2 ⎥⎦ vDS
Instructor: Octavian Florescu
31
NMOSFET Summary: Non-Ideal Behavior
Channel-length modulation:
„
The length of the pinch-off region, ΔL, increases with
increasing vDS above vGS–VT. It reduces the length of the
inversion layer and hence the resistance of this layer.
cross-sectional
view of channel:
inversion layer
→
iD increases noticeably with vDS, if L is small
λ is the slope
(channel-length
modulation parameter)
iD
0
EE40 Summer 2005: Lecture 13
VDSAT
Instructor: Octavian Florescu
vDS
32
16
(continued)
Velocity Saturation:
„
In a very-short-channel MOSFET, iD saturates because
the carrier velocity is limited to ~107 cm/sec
Æ iD reaches a limit before pinch-off occurs
V
⎡
⎤
iDSAT = WCox ⎢vGS − VT − DSAT ⎥vsat
2 ⎦
⎣
L
where VDSAT =
v
μn sat < vGS–VT
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
33
(continued)
Subthreshold Leakage:
„ For vGS ≤ VT, iD is exponentially dependent on vGS:
log iDS
1/S is the slope
leakage current, IOFF
0
„
VT
vGS
The leakage current specification sets the lower limit for
the threshold voltage VT
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
34
17
NMOSFET Summary: Circuit Models
For analog circuit applications (where we are concerned
only with changes in current and voltage signals, rather
than their total values), the small-signal model is used:
D
G
id
+
„
gmvgs
vgs
1/go
−
S
S
transconductance
output conductance
W
kn′ (VGS − VT )
L
go ≅ λI D where VGS & ID are the
gm ≅
DC bias (Q point) values
EE40 Summer 2005: Lecture 13
Instructor: Octavian Florescu
35
NMOSFET Summary: Circuit Models
„
For digital circuit applications, the MOSFET is modeled
as a resistive switch:
Req
iD
charges,
As the load capacitor dis
V
0
to
ses
VDS decrea
e≅
slop
0
Req ≅
V DD
VDD/2
slope ≅ VDD / 2 IDSAT
EE40 Summer 2005: Lecture 13
/ I DS A T
VDD
3 VDD ⎛ 5
⎞
⎜1 − λnVDD ⎟
4 I DSATn ⎝ 6
⎠
I DSATn =
kn′ W
(VDD − VTn )2
2 L
MOSFET is turned on
(VGS = VDD) when VDS = VDD
vDS
Instructor: Octavian Florescu
36
18