Three-Phase Cascaded Multilevel Inverter Using Power Cells
with Two Inverter Legs in Series
Gierri Waltrich
Ivo Barbi
Student Member, IEEE
Institute of Power Electronics
Federal University of Santa Catarina
P.O.Box 5119 – CEP 88040-970
Florianopolis, Santa Catarina, Brazil
gierri@inep.ufsc.br
Senior Member, IEEE
Institute of Power Electronics
Federal University of Santa Catarina
P.O.Box 5119 – CEP 88040-970
Florianopolis, Santa Catarina, Brazil
ivobarbi@inep.ufsc.br
Abstract - In this paper the study of a modular three-phase
multilevel inverter for application in electrical machines is
proposed. Unlike the Cascaded H-bridge inverter, this topology
uses power cells connected in cascade using two inverter legs in
series. A detailed analysis of the structure and the development
of an equation in the load voltage for n levels is carried out using
PWM phase-shifted multicarrier modulation. The simulations
and experimental results for a 15kW three-phase system, with
nine voltage levels, validate the study presented.
Index Terms - Inverters, cascade systems, multilevel systems,
PWM.
I. NOMENCLATURE
nL
nP
vAB(t)
vAN(t)
Nc
VDC
vn(t)
vn’(t)
vC(t)
d(t)
M
θo
ωo
fo
θc
ωo
fc
mf
vcr
Jn
Ro
Lo
Number of voltage levels from line-to-line output
voltage.
Number of voltage levels from phase-to-neutral
voltage.
Instantaneous line-to-line output voltage.
Instantaneous phase-to-neutral voltage.
Number of power cells per phase.
Isolated dc voltage source.
Instantaneous voltage in the upper switch of the nth
inverter leg, disconsidering the harmonics.
Instantaneous voltage in the lower switch of the nth
inverter leg, disconsidering the harmonics.
Instantaneous voltage in the power cell terminal.
Instantaneous duty cycle.
Index of modulation.
Phase-shifted sinusoidal modulator.
Angular frequency modulator.
Frequency modulator.
Phase-shifted triangular carrier.
Angular frequency triangular carrier.
Frequency triangular carrier.
Frequency modulation index.
Triangular carrier waveform.
Bessel function.
Resistive load.
Inductive load.
978-1-4244-2893-9/09/$25.00 ©2009 IEEE
II. INTRODUCTION
Multilevel inverters [1]-[2], have been attracting wide
industrial interests. It is considered an attractive alternative to
reduce switches stress. The main characteristic of these
converters is that they provide an output waveform with
many voltage levels.
In recent decades, an extensive array of multilevel
structures has appeared [3]-[9], for instance, the Cascaded Hbridge (CHB) [10], Neutral point clamped (NPC) [11] and
Flying capacitor (FC) [12].
Cascaded H-bridge multilevel inverter is a popular
converter topology and has found widespread applications in
industry, for instance, in high-power medium-voltage drives
[13]-[15] and reactive power compensating [16]. It is
composed of multiple units of single-phase H-bridge power
cells, using two inverter legs in parallel powered by isolated
dc supply.
The inverter dc bus voltage is usually fixed, while its ac
output voltage can be adjusted by modulation schemes [10].
The dc supplies are normally obtained by multipulse diode
rectifiers to achieve low line-current harmonic distortion and
high input power factor.
The H-bridge cells are usually connected in cascade on
their ac side to achieve medium-voltage operation and low
harmonic distortion. In practice, the number of power cells in
a CHB inverter is mainly determined by its operating voltage
and manufacturing cost. The use of identical power cells
leads to a modular structure, which is an effective means for
cost reduction.
Cascaded multilevel inverters have been developed to use
unequal dc bus voltages [17] or single dc source [18],
showing the possibility of different alternatives for this
topology.
Thus, a three-phase cascaded multilevel inverter topology
is proposed in this paper. It uses power cells connected in
cascade using two inverter legs in series, instead of two
parallel inverter legs, as used in CHB power cells. An
employed modulation and a load voltage analysis for
forecasting the harmonic spectrum, will also be presented.
Finally, a 15kW prototype with nine voltage levels will be
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implemented to analyze the theoretical studies carried out.
The maximum number of voltage levels of line-to-line
output voltage vAB(t) and phase-to-neutral voltage vAN(t) are
represented, respectively, by (1) and (2)
III. PROPOSED TOPOLOGY
The three-phase multilevel inverter proposed is presented
in Fig. 1. This inverter is composed of (3nL – 3) switches and
a (3nL –3)/2 isolated dc voltage source, where nL is the
number of voltage levels of the line-to-line output voltage.
The load can be connected in delta or wye.
An inverter leg with two switches, working in a
complementary way, is shown in Fig. 2a. Each power cell is
composed of two inverter legs with the connections defined
in Fig. 2b.
Voltage vC(t) in Fig. 2b, is composed by three voltage
levels: VDC, 0 and - VDC. When switches Sn-1 and Sn conduct,
the output voltage in the power cell is vC(t) = VDC. Similarly,
with Sn-1’ and Sn’ switched on, vC(t) = - VDC. To obtain the
level zero, the switches Sn-1 and Sn’ or Sn-1’ and Sn should be
switched on. Thus, connecting power cells in cascade (Fig.
3), with certain phase-shift in the switch command between
two power cells in the same phase, the number of voltage
levels from phase-to-neutral voltage (nP) increases.
nL = 4 N c + 1
nP = 2 N c + 1
(1)
(2)
where Nc is the number of power cells per phase. The number
of voltage levels for this topology is always odd.
Fig. 2.
a) Inverter leg connected to the isolated dc voltage source;
b) power cell using two inverter legs in series.
Fig. 3. Per-phase diagram of power cells in cascade.
To understand how each inverter leg is connected, an
analysis on the output voltage of the inverter leg is necessary.
Based on Fig. 2a the VDC voltage can be defined according to
(3).
VDC = vn (t ) + vn '(t )
Fig. 1. Multilevel inverter proposed.
(3)
The instantaneous voltage vn(t) is obtained by the product
of the duty cycle equation and VDC. For this converter the
duty cycle is variable over time and can be defined by (4).
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d (t ) =
1
(1 + M cos(ωot + θ o ) )
2
(4)
necessary to employ four triangular carriers with phase shifts
of 0, π/2, π and 3π/2.
( k − 1) π
Thus, vn’(t) (Fig. 2a) is defined in (5), disconsidering
harmonics generated by triangular carriers.
vn '(t ) = VDC d (t )
(5)
Substituting (4) into ( 5) is obtained (6).
vn '(t ) =
VDC VDC
+
M cos(ωo t + θ o )
2
2
(6)
2
1.5
VDC VDC
−
M cos(ωot + θ o )
2
2
(7)
The output voltage of each inverter leg can be defined
using (6) and (7). The presence of an average dc voltage
(VDC/2) in these equations is evident. Thus, the phase-toneutral voltage (vAN) in this inverter will also present an
average dc voltage. Although the line-to-line output voltage
does not present this average component, it must be cancelled
to decrease the peak voltage of vAN, to prevent an unbalanced
voltage and consequently a current circulation between the
phases. Therefore, if the inverter legs are connected as
demonstrated in Fig. 2b, the average voltage VDC/2, in the
phase-to-neutral voltage (vAN), is cancelled.
The instantaneous voltage (vC(t)) of the power cell is
defined as:
vC (t ) = vn '(t ) − vn −1 (t )
vC (t ) = VDC M cos(ωo t + θo )
(13)
Only the upper switch-gate signals for one phase are
presented in Fig. 4, because the lower switch-gate signals are
complementary. The other two phases are shifted by ±120o.
From (3) vn(t) is defined on (7).
vn (t ) =
k = 1, 2,..., 2 N c
Nc
v cr1 v cr2 v cr3 v cr4
1
Phase "a" modulator
Carrier from switch Sa1
Carrier from switch Sa2
Carrier from switch Sa3
Carrier from switch Sa4
π /2
|-----------|
0.5
0
0.5
1
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
1
0
Gate signal from switch Sa1
1
0
Gate signal from switch Sa2
(8)
1
(9)
The phase-to-neutral voltage vAN(t) (Fig. 3) with Nc power
cells can be obtained through (10).
0
Nc
Gate signal from switch Sa3
1
vAN (t ) = ∑ vC n (t )
(10)
vAN (t ) = N cVDC M cos(ωo t + θ o )
(11)
0
n =1
Gate signal from switch Sa4
Using phase-to-neutral voltage vAN(t) as reference, through
(11), the line-to-line output voltage for Nc power cells can be
represented by (12).
π
vAB (t ) = N c 3VDC M cos(ωot + )
6
2 V DC
(12)
According to (11) the phase-to-neutral voltage vAN(t) has
null average dc voltage.
Phase voltage
IV. MODULATION STRATEGY
0
In this converter, the PWM phase-shifted multicarrier
modulation technique was used. All the triangular carriers
have the same frequency and the same peak-to-peak
amplitude with a phase shift between any two adjacent carrier
waves, to increase the harmonic cancellations. A phase shift
defined by (13) optimizes the harmonic cancellation
according to [19].
For an inverter with two power cells in cascade, it is
2000
4000
6000
8000
1 .10
4
4
1.2 .10
4
1.4 . 10
4
1.6 . 10
Time ( μ s)
Fig. 4. Simulated waveform of the proposed multilevel inverter (fo = 60Hz,
fc = 180Hz, M = 0.8 and Nc = 2).
To obtain the switch-gate signals a comparison between
the triangular carriers and the modulator is carried out as
indicated in Fig. 4. The resultant signal will be high when the
instantaneous value of the sinusoidal wave exceeds the
triangular carrier, otherwise, it will be null. The duration of
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each pulse width in the output comparator depends therefore
on the time that the sine wave remains above the value of the
triangular wave. These high-frequency pulses are sent to the
switches of the circuit in Fig. 1, with four inverter legs in
cascade.
The carrier waveforms employed in this modulation
technique are usually triangular or sawtooth. In this study the
triangular unipolar format was used, because it reduces the
harmonic content when compared with the sawtooth carrier
[19].
Triangular carriers have, in general, a fixed scale, so the
fundamental magnitude control of the output voltage is
achieved by varying the sinusoidal modulator amplitude. This
alters the pulse widths changing the output voltage amplitude.
In Fig. 5 the modulation schematic for one phase is
presented. All comparators share the same modulator
waveform and each unipolar triangular carrier has a shift
determined by (13).
and the instantaneous line-to-line output voltage vAB(t) for Nc
cells, which includes the harmonics, the method considered in
[21] was used. Voltages vAN(t) and vAB(t) are represented,
respectively, by (15) and (16). By means of those equations,
it is possible to forecast the magnitude of every harmonics
and, thus, the output filter can be easer designed, if it is
necessary.
Equations (15) and (16) are formed, respectively, by (11)
and (12) added to a second term that represents the voltage
harmonics. In both equations it is explicit that the carrier
angular frequency ωc is multiplied by 2Nc. Thus, the voltage
harmonics will also be multiplied by 2Nc. Hence, once the
number of power cells is defined, it is possible to determine
the frequency of undesirable harmonics by analyzing those
equations.
Equations (15) and (16) are represented in a graphical
form in Fig. 6, for an inverter using 2 power cells per phase,
switching frequency of 1260Hz, VDC of 400V, output
frequency of 60Hz and rms fundamental output voltage of
784V, generating a line-to-line output voltage with nine
levels and a phase-to-neutral voltage with five levels. The
maximum line-to-line output voltage and the phase-to-neutral
voltage will be, respectively, 1600V and 800V.
For the same conditions a numeric simulation in PSIM
software is carried out to validate those equations as shown in
Fig. 7.
In Fig. 6 and Fig. 7 the harmonic spectrum of the line-toline output voltage is also presented. It can be observed that
the voltage harmonics are multiplied by 2Nc. The total
harmonic distortion (THD) of the output voltage is
approximately 32%.
Similar results for the harmonic spectrum and THD can be
found in CHB multilevel inverter, using the same modulation
strategy. However, the vAN(t) and vAB(t) voltage equations
derived from CHB inverter will be different [20] when
compared with (15) and (16).
VI. EXPERIMENTATION
Fig. 5. Simplified modulation schematic.
Phase-shift modulation described here, is similar as the
one used in CHB multilevel inverter [19],[20]. A CHB
multilevel inverter with nP voltage levels requires (nP – 1)
triangular carriers. In the phase-shifted multicarrier
modulation, all the triangular carriers have the same
frequency and the same peak-to-peak amplitude, with a phase
shift between any two adjacent carrier waves also defined by
(13), however, the phase-shift between two parallel inverter
legs of each power cell must be 180o.
V. LOAD VOLTAGE ANALYSIS
A 15kW three-phase multilevel inverter was implemented,
using inductive-resistive load (displacement power factor of
0.93), connected in delta, with an index modulation of 0.8
and a carrier wave frequency of 1260Hz. The converter is
supplied by the power grid (220V and 60Hz).
The frequency modulation index is define by
mf =
fc
fo
(14)
where fc and fo are the frequencies of the modulating and
carrier waves, respectively.
To obtain nine levels in the load voltage, it is necessary to
use 2 cells in cascade in each phase, according to (1),
requiring a total of 6 power cells in a three-phase system.
To obtain the instantaneous phase-to-neutral voltage vAN(t)
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v AN (t ) = N c M VDC cos (ω o t + θ o ) +
2VDC
π
∞
∞
∑∑
m =1 n = −∞
1
π⎞
⎛
J ( 2 n −1) (N c mπ M ) sin ⎜ [2 N c m + (2 n − 1)] ⎟ cos ( 2 N c mω c t + (2 n − 1)ω o t )
m
2⎠
⎝
(15)
π⎞
⎛
v AB (t ) = 3 N c M VDC cos ⎜ ωo t + ⎟
6⎠
⎝
∞
∞
4V
1
⎛
π⎞ ⎛
π⎞
π⎞
π⎞ π⎞
⎛
⎛
⎛
+ DC ∑ ∑ J (2 n −1) (N c mπ M ) sin ⎜ [2 N c m + (2n − 1)] ⎟ sin ⎜ [2 N c m + (2n − 1)] ⎟ cos ⎜ 2 N c m ⎜ ωc t − ⎟ + (2n − 1) ⎜ ωo t − ⎟ + ⎟
2⎠ ⎝
3⎠
3⎠
3⎠ 2⎠
π m =1 n =−∞ m
⎝
⎝
⎝
⎝
Voltage VAN (V)
1200
1.20K
1.00K
800
Voltage VAN (V)
(16)
0.80K
0.60K
400
0.40K
0.20K
0
0.0K
-0.20K
400
-0.40K
-0.60K
800
-0.80K
-1.00K
1200
0
0.0019
0.0037
0.0056
0.0074
0.0093
0.0111
0.013
0.0148
-1.20K
0.0167
0.0
4.165
Time (s)
8.33
Time (ms)
12.495
16.66
1.60K
1200
Voltage VAB (V)
16.66
2.00K
1600
1.20K
800
0.80K
400
0.40K
0
0.0K
400
-0.40K
800
-0.80K
1200
-1.20K
1600
-1.60K
0
0.0019
0.0037
0.0056
0.0074
0.0093
0.0111
0.013
0.0148
0.0167
-2.00K
0.0
Time (s)
4.165
Magnitude (V)
1200
1.20K
1.05K
1000
Magnitude (V)
12.495
Voltage VAB (V)
2000
2000
8.33
Time (ms)
0.90K
800
0.75K
600
0.60K
0.45K
400
0.30K
200
0.15K
0
0
5
0.0K
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
0.0
Harmonic order
Fig. 6. Waveforms generated by (15) and (16) and harmonic spectrum of the
0.859
1.717
2.576
3.434
Frequency (KHz)
4.293
5.151
Fig. 7. Numeric simulation waveforms obtained through PSIM software.
output voltage vAB .
The amplitude of each isolated source has the value of
400V and will supply a power of 1.25kW. Consequently,
each voltage step has a value of 400V. As a result, the load
voltage will reach 1600V due to the nine levels imposed. A
12-pulse rectifier was used in each cell to obtain a better
performance. Figure 8 and Fig. 9 show, respectively, a
multilevel inverter schematic and a picture of the complete
circuit implemented.
The line-to-line voltage vAB reached a maximum value of
1600V, being composed of nine levels (Fig. 10). The rms
line-to-line voltage reached a value of approximately 782V
with a rms current of 6.4A. In Fig. 11 the harmonic spectrum
of the line-to-line voltage in the load is presented. This
waveform is similar to those observed in the theoretical
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(Fig. 6) and simulated (Fig. 7) graphs. It can be observed that
the undesirable voltage harmonics were multiplied by 2Nc,
agreeing with (16). The total harmonic distortion of the
output voltage is also approximately 32%. The three-phase
load currents shown in Fig. 12 presents sinusoidal format.
Fig. 9. A 15kW multilevel inverter prototype with nine levels in the output
voltage. This picture shows: the transformers (1), comutation cells and fullbridge rectifier on the heatsink (2), dc-link capacitors (3), IGBT drivers (4),
gate signal circuit (5), auxiliary power supply (6) and circuit protection (7).
220 00 V
220 −1200 V
220 +1200 V
60Hz
Fig. 10. Voltage (vAB) and current (iAB) in the load.
Fig. 8. Three-phase multilevel inverter implemented.
1200
1000
Magnitude (V)
Figure 13 shows the phase-to-neutral voltage with five
levels. Each step has a value of 400V reaching 800V. The
current presents a sinusoidal format, with a peak value of
approximately 10A and frequency of 60Hz. The average dc
voltage in this figure is zero because of the connection done
in Fig. 2b.
In Fig. 14 the switch voltage waveform is presented.
Although output voltage is high, the maximum voltage over
the switches has a value of 400V. The maximum current
value in the switches is approximately 16.4A. The waveforms
for all the inverter switches have the same format, however,
with the phase shift defined by (13).
800
600
400
200
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Harmonic order
Fig. 11. Harmonic spectrum of the line-to-line output voltage vAB.
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Each power cell in the proposed topology employs double
the number of isolated dc voltage sources, with half the
power.
The PWM phase-shifted multicarrier modulation
technique used in the proposed topology is similar as used in
CHB multilevel inverters. However, if instead of this
modulation are employed other techniques, for instance,
PWM level-shifted multicarrier modulation or space vector
modulation, accurate analysis should be done.
Fig. 12. Three-phase load currents.
Fig. 14. Voltage and current in the switches.
Total harmonics distortion in the load current and line-toline output voltage were compared in those two converters
with the same parameters. Similar results are obtained by
using numeric simulations (PSIM software).
Harmonic spectrum for the proposed topology was defined
by (16) and an equivalent illustration for CHB multilevel
inverters, using PWM phase-shifted multicarrier modulation,
can be found in [20] showing the similarity between them.
Fig. 13. Voltage (vAN) and current (iAN) in the phase.
The voltage and current on one of the dc-links are shown
in Fig. 15. The VDC source has a magnitude of 400V with a
small ripple. The inverter is composed of 12 isolated
continuous sources, each one supplying a power of 1.25kW,
totalizing 15kW.
VII. COMPARISON BETWEEN THE PROPOSED
INVERTER AND CHB MULTILEVEL INVERTER
Many characteristics of the proposed topology have been
described in this paper. The main difference between those
two topologies is the form how the inverter legs are
connected.
Those two converters have the same number of switches
on each power cell, thereby, the voltage levels generated in
the terminals of each power cell is the same. Thus, the
number of voltage levels of the phase-to-neutral voltage (vAN)
and line-to-line output voltage (vAB) will also be the same, as
described in Table I.
Fig. 15. Voltage and current in the isolated source VDC.
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[3]
TABLE I
COMPARISON BETWEEN THE PROPOSED INVERTER AND CHB MULTILEVEL
INVERTER
Topology
Proposed
inverter
Cascaded
H-bridge inverter
Phase-to-neutral voltage levels
nP
nP
Line-to-line voltage levels
2nP -1
2nP -1
Number of power cells per phase
(nP - 1)/2
(nP - 1)/2
Number of switches per phase
2 (nP - 1)
2 (nP - 1)
Number of isolated dc voltage
sources per phase
(nP - 1)
(nP - 1)/2
Load voltage THD
Similar
Similar
Modulation strategy
Similar
Similar
Power of each isolated dc
voltage source
Pnominal
3(nP -1)
2Pnominal
3( nP -1)
[4]
[5]
[6]
[7]
[8]
[9]
[10]
VIII. CONCLUSION
[11]
A three-phase multilevel inverter has been proposed. Also,
the principles of operation, simulations and experimental
results have been presented.
The PWM phase-shifted multicarrier modulation
technique presented a satisfactory performance. However, a
study should be conducted with other techniques in order to
find a modulation that reduces the number of switching
commutations and, consequently, reduces the switching
losses and harmonic content.
Equations of the line-to-line output voltage and phase-toneutral voltage were developed. Through those equations it is
possible to define the magnitude of every harmonics and,
once the number of power cells is defined, it is possible to
determine the frequency of undesirable harmonics.
A comparison between the proposed topology and CHB
multilevel inverter was presented, showing similar
characteristics, thus, the topology described in this paper
could be seen as another alternative to be applied in
analogous applications.
Research about characteristics and techniques used in
close-loop control still needs to be done.
ACKNOWLEDGMENT
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
The authors gratefully acknowledge the financial support
provided by CAPES, UFSC and INEP.
[21]
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