Serial Interface
Purpose:
• To show how the serial interface routes data through selected controllers.
Objectives:
• The SIU provides the general “glue logic” for the system providing the bus interface
between the system and CPM, bridging between PPC and local bus, the memory
controller, System configuration and protection, and JTAG, Interrupt control, and Bus
Arbitration. This module will go into depth on how this implementation works.
Contents:
• Functionality of the Core, CPM, and SIU followed by an operating example.
Learning Time:
• There are 18 pages in this module, along with 10 reference slides, which will take
approximately 42 minutes
The purpose of this section is to show how the serial interface routes data through selected
controllers.
The SIU provides the general “glue logic” for the system providing the bus interface between
the system and CPM, bridging between PPC and local bus, the memory controller, System
configuration and protection, and JTAG, Interrupt control, and Bus Arbitration. This module
will go into depth on how this implementation works.
The contents of this module include the functionality of the Core, CPM, and SIU followed by
an operating example.
There are 18 pages in this module, along with 10 reference pages, which will take
approximately
42 minutes
1
Key Features of Serial Interface
• Each TDM can be:
– T1 (USA/Japan) or CEPT (Europe)
– ISDN primary rate, basic rate - IDL & GCI
– E3 or DS3 rate (TDMa only) [45 Mbs stream]
– User defined interface
• Independent, programmable Tx and Rx routing, frame syncs, and clocks
• Selection of rising or falling edge for frame sync and data bits
• Support for one or two clocks per data bit
• Selectable delay between frame sync and frame start ( 0-3 bits)
• Four programmable strobes and four clock (2x) output pins.
• One- or eight- bit resolution in routing, masking and strobe selection
• Supports frames up to 16384 bits long
• Dynamic programming for routing and strobes
• Supports automatic echo and loopback for each TDM
Reference Manual Chapter 14
The key features of the serial interface are as follows:
Each time division multiplexer could control transmission in one of the following formats:
T1 used in the USA and Japan or CEPT used in Europe
ISDN primary rate or basic rate utilizing IDL and GCI.
E3 or DS3 rate using TDMA only at rates up to 45 megabits per second. Or as a user defined interface.
Transmit and receive routing, frame synchronization, and clocks are independently programmable.
Frame sync and data bits can be selected to be handled on rising or falling edges of the clock.
Support for one or two clocks per data bit
Selectable delay between frame sync and frame start of up to three bits.
4 programmable strobes and 4 clock output pins.
1- or 8-bit resolution in routing, masking, and strobe selection
Supports frames up to 16,384 bits long.
Dynamic programming for routing and strobes.
Supports automatic echo and loop-back for each TDM.
2
SI Connections
Enable
MCC1
SI1 RAM
FCC2
FCC3
•
•
•
SCC2
SCC3
SCC4
SMC2
MII1/UTOP8-16/NMSI
•
• •
•
• •
'0'
•
• •
•
• •
•
• •
•
• •
CMXSMR
SMC1
TDM Pins RxD, TxD,
Sync, and Clock
'1'
CMXSCR
SCC1
b
c
d
a
b
c
d
Time Slot
Assignor
Control Logic
SI2
SI2 RAM
RAM
SI1GMR
a
Time Slot
Assignor
Control Logic
CMXFCR
FCC1
Enable
Port Control Logic
MCC1
SI2GMR
MII2/UTOP8/NMSI
MII3/NMSI
NMSI Pins
Rx/Tx
•
• •
•
• •
This is a simplified diagram of how the serial interfaces are connected between the various controllers dealing with the data and the external pins
of the serial interface options. There are two identical serial interfaces indicated here as SI1 and SI2. The serial interface routes data between the
controller, which handles the data, and the time division multiplexer, which transfers the data on the external serial line. It also controls the TDM.
However, to understand the overall process, it is necessary to see the complete picture of how data can be transferred. There are four controllers
that can handle the serial data transfer. The controller, of which there are two, the fast communications controller, of which there are three, the
serial communications controller of which there are four, and the serial management controller, of which there are two.
The controller used depends on the protocol required, and they are all independently selected for connection to the serial interface. The MCC is
handled differently and to understand that you need to study the multi channel controller module. However, you will need to understand the serial
interface for that and so you should study this module first. The routing of data for the FCC‘s, SCC‘s and SMC‘s is handled by three registers,
CMXFCR, CMXSCR and CMXSMR, respectively.
A bit in the register selects whether the data is routed to the serial interface or the NMSI. One very important detail to remember here is that none
of these connections are connected to the outside world after reset of the PowerQUICC II because they are routed via the port control logic to the
parallel ports. Following reset, the ports are all defined as general purpose inputs. It is vital that if any of these functions are to be used, the
parallel ports must be programmed for the pin functionality required for the intended use. Most registers when reset are cleared, and so the default
for these connections is routing via the NMSI.
This connection provides the controller with a completely independent connection. All of the connections indicated here are multiples. For
instance, all the controllers have receive and transmit functionality, and there are control signals associated with them. These connections indicate
the complete group for each controller and interface. Transmit and receive are independently controlled and so they do not both have to be used.
When the routing control registers have the associated bits set, the controller is routed via the serial interface. With this routing the controller data
is multiplexed with other controller data over the external connections.
It is very important to be aware that the serial interface has nothing to do with protocol handling, only control of the TDM‘s and the routing of data
between the TDM and controller. There is no data buffering in the SI and there are no FIFOs. The data is simply transferred via the controller
selected which handles all those details.
Each serial interface has four time division multiplexers (designated A, B, C, D) and each SI has a global mode register, which enables the TDM‘s
independently. When the controllers are connected directly to their own independent interface, they are connected using the required interface for
their protocol. For example, HDLC 10 base T ethernet uses the NMSI, fast ethernet uses the MII, and ATM uses utopia.
3
Time Slot Assignor (TSA)
• TSA routes data between desired pins and channels at the correct times.
• Can be used to independently route transmit and receive data, and can
support four TDM channels
• Can support up to four output signals independently for each time-slot for
user defined purposes
• Defined by SI RAM
The time slot assignor routes data between desired pins and channels at the
correct times.
It can be used to independently route transmit and receive data, and can
support four TDM channels.
It can support up to four output signals independently for each time-slot for
user defined purposes.
It is defined by SI RAM.
4
Theoretical TDM
L1SYNC
Clock
SCCs
SMCs
Matrix
Matrix
FCCs
L1TxD
MCC
SIRAM
ST1
ST2
ST3
ST4
This diagram shows the basic principle of how the time slot assignor works, and can be equated to the early
telephone system uniselectors. The requirement is to connect multiple data streams handled by various controllers to
a single serial data stream with the data from each controller connected to the line for a given period of time.
The controllers are connected into the system via a matrix which enables each controller to be connected to any of
the switch contacts providing complete flexibility of what time in the process any given controller is allotted connection
to the output pin.
The process is started when a signal is received from an input called L1 sync. At that time the output pin is connected
to the first contact, and whatever controller is connected to it will have it’s data transmitted. The rate the data is
transmitted is controlled by the single clock input to the system, and how much data depends on for how many clock
pulses the switch remains at that position. After a given number of clock inputs the switch moves to the next contact,
and whatever controller is connected to that will have it’s data transmitted.
The process continues with the switch moving to the next contact after the allotted number of clock pulses defined for
that position until the switch reaches the last position required by this system. At that time the process stops and waits
for the next sync pulse which will start the process again. The end result is frames of serial data transmitted on the
serial line containing multiple streams of data from several different controllers, all of which could be handling their
own data very differently.
A serial TDM frame will be handling small portions of the controller frames, and it requires many TDM frames to
complete each individual controller frames, all of which could be different. Each time this process repeats the same
frame format is repeated unless the connections within the matrix are modified. There is one additional possibility. It
may be required to have some signals present which are identifiable for each position of the switch.
In this case there are four signals, designated S, T, one through four, known as strobes, which can have a predefined
value for any given position of the switch. There a several reasons this might be necessary. For example how does
the device at the other end of the external connection know when the data is switched from one controller to another.
Presumably it needs to be able to re direct each data stream to its required target. This is the basic principle of the
serial interface. This only explains the transmit process, but the receiver functions in the same way. All of this process
is defined by the SIRAM.
5
TDM -Example
What level would you like to use?
Which edge would you like to use?
L1RSYNCn
L1RCLKn
SCC2
SCC1
FCC2
L1TXDn
Slot 1
Slot 2
L1RXDn
Slot 1
Slot 2
Slot 3
Slot n Slot n+1
SCC4
SCC2
FCC1
SMC2
Slot 3
SMC2
SCC3
Slot 4
Slot n
SCC3
SMC1
Slot n+1 Slot n+2
SCC4
Slot n+2
FCC1
L1ST4
L1ST3
L1ST2
L1ST1
This is an example of how data is controlled by the TDM. The two basic control signals are the sync pulse and clock,
both of which are inputs from the external system. A TDM frame starts with a sync pulse and the user can chose to
start on the leading or trailing edge. All data is transferred using the input clock designated L1R clock for the receiver
and L1T clock for the transmitter.
The user also has the choice of transferring on the rising or falling edge. The controller provides a user defined
number of time slots for the frame, where a time slot is defined as a number of clock pulses. Each slot is independently
controlled. Any of the controllers indicated earlier can be routed in any of the time slots, which enables complete
flexibility for what data is transferred at any given time.
There are four output signals designated L1 strobe 1-4 and any value can be assigned to those signals for each time
slot, providing additional control or status signals for the user. For this example, some random connections have been
chosen simply to show how the controller operates. Two TDM frames are shown, one for transmit and one for receive,
indicating how the data will appear on the pins for L1TXD and L1RXD. The lower case N indicates that this could be
related to any of the TDM‘s.
For the first time slot of the transmitter the data is coming from SCC2 and for the receiver the data is going to SCC4.
The time slot is shown to be three clocks wide. For the second time slot the transmit data is coming from SCC1 and
received data is going to
SCC2 and again the time slot is three clocks wide. The third time slot transmit data is coming from FCC2 and is four
clocks wide, while the receive data is going to FCC1 and is wider than the transmit slot. This shows that the transmit
and receive functions are independent.
Viewing the rest of the example shows this independence for both time slot size and controller connections. In fact
they could both have different clock rates, with separate clock inputs, and so the timing between the two can also be
different. The strobe values are simply random to show how they can be set. The user can use them as needed, and
each strobe can be used as an independent signal or in combination with the others to provide a 4-bit value. This
means that for any time slots a specific signal can be used with it, or using a four in to sixteen out decoder up to
sixteen different codes can be produced.
For example, in this case strobe four could be the control code independently indicating when SCC4 data is on the line
or the value 0001 could be. However, in the case of the strobe signals there are no independent options for both
transmit and receive. There are only the four signals, although the user can chose to use any of them for either
transmit or receive. As you can see, the result is that a data stream can be handled by several different controllers
where any portion of it can be routed to any of those controllers.
6
SIRAM Organization
0
+12000
15
Entry 0
Tx
+121FE
Entry 255
SI1
+12400
Entry 0
Rx
Two serial interfaces control
time division multiplexing.
The TDMs are controlled by
SIRAM, each having 256
16-bit entries for each of
transmit and receive.
+125FE
Entry 255
+12800
Entry 0
Tx
+129FE
Entry 255
SI2
+12C00
Entry 0
Rx
Reference Manual section 14.4
+12DFE
Entry 255
The next question might be how are these TDM’s controlled. Well, time slot
assignment is defined in a table entry in SIRAM. The SIRAM is organized as
two separate blocks one for serial interface one and the other for serial
interface two. SIRAM one is located in dual port ram at offset hex 12000 and
SIRAM two at hex 12800. Each SIRAM block is divided into equal portions
for transmit and receive, with 256 entries for each. Each entry is 16 bits wide
and relates to one time slot. With 256 entries, that means that the maximum
TDM frame size is 256 time slots.
7
SIRAM (Examples)
Start Address
Registers
0
2
SInbMR
0
0
1
SInaMR
4
5
SIndMR
2
X
3
4
Txd
255
0
6
7
255
0
0
1
Rxb
2
X
3
Not allowed
0
1
X
2
3
4
5
5
7
Rxc
Txa
2
Txb
Txc
X
6
255 7
0
Rxa
Rxc
4
0
1
Rxa
2
3
4
4
6
255
0
7
3
5
Rxd
6
255
0
7
Tx
5
Txb
7
2
X
2
4
1
Rxb
1
Txa
3
6
255
0
3
5
Txd
0
0
1
7
4
6
255
Rxa
0
5
6
n = 1 or 2
0
1
Txb
3
SIncMR
64 entry blocks – 32-entry granularity
Rx
5
Rxb
6
255
7
This diagram shows examples of how the SIRAM can be organized and the rules for each example. The diagram
further shows the complete block for one serial interface. Each section shows another alternative organization.
Each SIRAM transmit and receive block is defined as four blocks of 64 entries, but each of those blocks can be
accessed as two halves, which enables the control functions to identify one of eight entries. The top blocks are for
transmit entries and the bottom are for receive. There is no choice of the RAM portion, so there is always 256 entries
for each example.
The different colors indicate the TDM related to that block, and the example shows how the user might chose to define
them. For this explanation, the block on the right is explained first. This is the simplest case where the user only wants
one TDM used for transmit, and one for receive. In that case, all of the top entries relate to the one transmit TDM and
all of the bottom entries relate to the receive TDM. In that case both receive and transmit can use up to 256 time slots
each.
For the second example, the second block in from the right indicates a case where only two TDM‘s are required for
each of receive and transmit. In this example, half of the entries for each receive and transmit are allocated to each
TDM, providing 128 time slots to each. However, this is only one option and the entries could be portioned differently.
In the third example, four TDM‘s are to be used. The available RAM must be shared between all the TDM‘s and how it
is divided depend on how many time slots are required for each TDM. In this case, the example indicates that what the
user would like is 64 time slots for TDMA, 64 time slots for TDMB, 32 for C and 96 time slots for D. However, that is
not the only consideration.
The rules are that not more than one TDM can be associated to one of the 64 entry blocks. So the case for TDMC is
not possible because both C and D are defined in that block. The only possible case for using four TDM‘s is a
maximum of 64 entries per multiplexer. It would be possible to have more entries for a TDM, such as indicated for D, if
only three were used.
The forth example, shown in the block on the left, indicates that only two TDM‘s are required for the transmitter and
three for the receiver. This is possible. Although it might not be the best way to define it, the organization as shown for
the transmitter is itself not a problem. Specifically, the receiver defines TDMA in the second block and the transmitter
defines TDMB in the second block, even though the two entries do not overlap. However, since the rule of sharing
includes both transmit and receive this organization is not allowed.
The fact that three TDM‘s are to be used by the receiver is not a problem and as long as there is no block overlap then
this could easily be done by better organization. There is certainly no reason why the TDM should not start at the first
entry. Each TDM is controlled by a register called the serial interface mode register, shown on the left of the diagram.
The N in the name indicates which serial interface it relates to and the A, B, C and D indicate the TDM. There are a
total of eight of these registers.
8
Dynamic Frame Switching
L1RSYNCn
L1TXDn
SCC3
FCC2
SCM1
SCC3
FCC3
SIRAM 0
SIRAM 0
SIRAM 1
SIRAM 1
SIRAM 2
SIRAM 2
SCM1
Switch
SInRSR
SInCMDR
This diagram shows how the dynamic switch mechanism works. The
proposition is this. What if for a period of time a given frame format is used,
and then, for whatever reason, a different frame format is required? If there
wasn’t a special mechanism for this, then the controller would have to be
disabled, the SIRAM reprogrammed and then the controller enabled again.
All of which would introduce a delay, which might be unacceptable. The
diagram indicates that what is required is a switch to a frame where the main
data stream is transmitted from FCC2 and at a specific time it should change
to the main data coming from FCC3.
For simplicity, only three time slots are shown, as needed, and the three
SIRAM entries to control them. The requirement is that at the end of a frame
the switch should take place and so three new entries are required to handle
the new frame. The switch is performed by setting a bit in a register called the
serial interface command register, shown here as SINCMDR with the alternative
entries specified in advance. At the location defined in the shadow address register,
shown here as SINRSR, the new frame will be transmitted on the next sync pulse.
9
SI RAM Shadow Control (Examples)
0
Registers
0
SInRSE
1
Shadow
Address
2
3
4
SInCMDR
0
Txb
Txa
1
a Shadow
1
Txb
3 b Shadow
2
2
b Shadow
Txc
5 c Shadow
4
6
5
6
6
n = 1 or 2
7
7
0
0
255
Rxb
0
255
0
1
1
2
2
3
3
Rxd
5 d Shadow
4
6
6
4
7
5
Rxc
255
0
3
4
Txd
Shadow
Switch
255
0
0
7
5
Txd
255
0
Rxa
0
Txa
1
2
Txa
Shadow
Txd
Shadow
0
Rxa
4
5
6
255
0
1
2
Rxb
3
Rxc
4
c Shadow
5
255
7
0
2
Rxa
Shadow
Rxa
3
4
Rxd
5
6
Shadow
Txa
Shadow
7
1
6
Rxd
Txa
3
Txd
7
0
255
Rxa
Shadow
7
There is only the SIRAM available that has already been shown. That must
be shared by all TDM’s. If dynamic switching is to take place then the same
SIRAM must be shared for the alternative entries required for the new frame.
This diagram shows some examples of how that is done, and basically
follows the same rules.
Two TDM’s cannot share the same 64 entry block, but the entries for the
new frame for the same TDM can. For example, if 32 time slots or less are
require for a given TDM, then the first half of the block could be used for the
first frame, and the second half for the new frame. The new frame is not
limited to the same number of time slots and can be totally different in makeup. The different blocks show several examples of possible organization, the
arrows indicating how the controller will switch to using a new set of entries
when the switch is made. On the left of the diagram are the registers used
for this.
10
SI General Overview
SI RAM
1 of 2
a
Tx
b
Time Slot
Assignor
Control
Logic
4 Channels of
TDM Pins
c
Rx
d
SInCMDR
Switch Shadow
SInRSR
Shadow Pointers
SInmMR
TDM Pointers
SInGMR
SInSTR
TDM Enable
RAM Status
n = SI number : m = TDM channel
SMCx
SCCx
FCCx
•
•
CMXSMR
CMXSCR
CMXFCR
•
NMSI Pins
•
•
•
MII/UTOPIA/NMSI Pins
This shows one of the Serial interfaces complete with the SIRAM, TDM‘s,
controllers and registers. The only thing left out is the MCC, which is covered
in it’s own module.
11
SI RAM Standard Entries (Standard Use)
0
1
0
SW
TR
2
3
4
5
SSEL1 - SSEL4
Switch Tx/Rx
(Rx RAM only)
MCC
Not MCC use
Strobe Select
Level assigned to each pin, OR'd with
other simultaneous control’s selection
SI RAM
Entry 0
Entry 1
Entry 2
Entry 3
Entry 4
Entry 5
Entry 6
6
0
7
8
9
10
11
13
CNT
CSEL
Channel Select
0000 = Tx tri-state
0001 = SCC1
0010 = SCC2
0011 = SCC3
0100 = SCC4
0101 = SMC1
0110 = SMC2
0111 = D ch grant *
1001 = FCC1
1010 = FCC2
1011 = FCC3
12
14
15
BYT
LST
Count
1 - 8 bits/bytes
Byte Resolution
0 = bit
1 = byte
Last Entry
wait for next sync
(Must be in odd
numbered entry)
“Refer to SCIT Programming”
Reference Manual section 14.4.3
SI RAM Entries standard use
This is an SIRAM entry. It is shown with the format when the MCC is not used with it. When used for MCC data, it takes a
different format.
All of the entries in the SIRAM have this format, each one relating to a time slot on the serial interface. The first entry
indicates the format of the first time slot, and then in consecutive order the format for subsequent time slots. Bit zero
defines if this entry relates to the MCC and that case is shown on the next slide.
One of the first considerations is probably what controller is handling the data for this time slot? That is selected by bits 710, called CSEL. Initializing the values shown will cause the data associated with this slot to be directed via the defined
controller. One definition of interest is the first, tri-state. This means that for this time slot, the external pin is open circuit,
and so some other data could be on the line associated with a totally different controller.
The next consideration is how much data flows during this time slot? First, there are two possible resolutions, bit or byte,
selected by bit 14, and with it goes the count in bits 11 through 13. The count utilizes a fiddle factor where one is added to
whatever is here. Obviously zero is a useless option, so this mechanism offers a better option of from 1 to 8. Thus, the
options range from a minimum of 1 bit to a maximum of 8 bytes.
The controller needs to know when it has reached the end of a TDM frame and that is defined by setting the last bit, bit
15, in the last entry required. When that entry has been dealt with, the controller stops handling data until the next sync
pulse, when it restarts at the first entry, unless a switch has taken place. In that case, it would start at the first entry of the
shadow RAM. As previously mentioned, the user might need a signal present on the strobes for the time slot, so
programming bits 2-5 will result in those bit values appearing on the strobe pins.
Finally, if required, the transmit and receive pin functions can be switched. Sounds like a wonderful idea, if the
connections have been made incorrectly but obviously that’s not what this is for. The possibility could be that at a given
time a single line could be used to receive and then switched to transmit. In that case, changing this bit switches the pin
functionality. This option is only available in the receive RAM entries, the transmit entry for this bit is ignored. It could be
very problematic if this bit worked in both entries and was programmed differently!
One final consideration. The last entry must be programmed to an odd numbered entry. That means that there must
always be an even number of entries in the table. In some cases it may be necessary to define a time slot over two
entries. One further consideration is that if both the MCC and CSEL values are zero, the SI will ignore data for that entry’s
count. This is called a null entry. The receiver will go tri-state and the transmitter goes high.
12
MCC_SI RAM
0
1
2
1
LO
OP
SUP
3
4
Superchannel entry
(all 1 byte entries)
5
6
7
8
MCSEL
MCC Channel Select
Which channel data is
routed to
0-127 for SI1
128-255 for SI2
Loop/Echo
MCC use
Route data via MCC
For MCC operation, see specific MCC section
9
10
11
12
13
CNT
14
15
BYT
LST
Count
If SUP = 0
1 - 8 bits/bytes
If SUP = 1
CNT+BYT =
0001:this is first byte
1110:not first byte
Byte Resolution
0 = bit
1 = byte
Last Entry
wait for next sync
(Must be in odd
numbered entry)
Reference Manual section 14.4.3
When the SIRAM entry is programmed for use with the MCC, defined by bit zero set, the
entry takes a different format as shown here. For MCC use, the MCC channel must be
defined for the entry. So what was a four bit channel select field becomes an eight bit field.
For normal use, the count and resolution select have the same operation, as shown on the
previous page, and the last field also has the same operation. There is a special function for
channel synchronization called super-channel, and if required, bit two must be set. In that
case, the controller must know which time slot contains the first byte of an MCC frame, so
the count and byte fields perform a different function, indicating the first or not the first byte
of a frame. When in super-channel mode, all time slots are one byte wide.
Finally, bit one enables any time slot to loop back internally from the transmitter to the
receiver, and echo the receiver on the transmitter. For further explanation of MCC operation,
study the MCC module.
13
TDM Programming Example
Support a 10-bit IDL bus with B1 channel via SCC2, D channel via SCC1 marked with a
strobe, first 4 bits of B2 via an external device selected by a strobe and last 4-bits via SMC1.
L1CLK
L1SYNC
L1RxD
B1
D1
B2
D2
L1TxD
B1
D1
B2
D2
SCC2
SCC1
STB_D
STB_B2
External Device
SMC1
SCC1
SI_RAM entries (Duplicate for both Tx and Rx )
Entry
0
1
2
3
4
5
MCC
0
0
0
0
0
0
SWTR
SSEL
CSEL
CNT
BYT
LST
0
0
0
0
0
0
0000
0001
0000
0010
0000
0001
0010
0001
0000
0000
0101
0001
000
000
000
011
011
000
1
0
0
0
0
0
0
0
0
0
0
1
Description
8-bits SCC2
1-bit SCC1, Strobe 1
1-bit no support
4-bits Strobe 2
4-bits SMC1
1-bit SCC1, Strobe 1
This is an example of the programming of SIRAM to support a 10-bit IDL bus with B1
channel via SCC2, the D channel via SCC1 and marked with a strobe, the first four bits of
B2 via an external device selected by a strobe, and the last four bits via SMC1. The timing
diagram shows the relationship between the clock, sync pulse, receive and transmit data
lines, and the two strobe lines. Here it can be seen that B, one data is controlled by SCC2,
D1 and D2 by SCC1, half of B2 by an external device, and the other half by SMC1.
Strobes are asserted for D1 and D2, and during the external device activity. Study the table
given and observe the programming. For the example, the MCC and switch transmit and
receive fields can be ignored. Notice for B1 a byte resolution is used, and that the count
specified is always one less than that required because of the built in fiddle factor. The same
programming is required for both transmit and receive in this case.
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Controller Registers
0
31
CMXFCR
SI FCC Routing Register
Selects FCC data routing via the TSA or NMSI, and selects FCC clock in NMSI mode.
0
31
CMXSCR
SI SCC Routing Register
Selects SCC data routing via the TSA or NMSI, and selects SCC clock in NMSI mode.
0
7
CMXSMR
SI SMC Routing Register
Selects SMC data routing via the TSA or NMSI, and selects SMC clock in NMSI mode.
These are the registers required to define the data routing for the FCC’s,
SCC’s and SMC’s, as well as the clock sources for them when not
connected to the serial interface. When they are connected to the serial
interface, they are controlled by the SI clock. To view the registers in more
detai,l click on the one of interest.
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TDM Registers
There is one for each serial interface (n = 1 or 2).
0
7
CMXSInCR
SI Clock source Register – Selects clocks for each receiver and transmiter TDM.
0
7
SInGMR
SI Global Mode Register – Defines the activation state of each TDM.
0
15
SInmMR
SI Mode Register – Defines the operation mode of each TDM.
0
7
There is one for each Serial
Interface (n = 1 or 2) and each
TDM resulting in a total of 8 mode
registers (m = a to d).
SInCMDR
SI Command Register – Initiates switch to shadow RAM for each TDM.
0
15
SInRSR
CMXSMR
SI Shadow address Register – Defines which sub block shadow RAM starts for each TDM.
0
7
SInSTR
SI Status Register – Identifies current-route RAM each TDM.
These are the registers that control the operation of the serial interface. With
the exception of the SI mode register, there is one of these for each serial
interface. The SI mode register relates to the TDM and so there is one for
each TDM for each SI.
The SI clock source register selects clocks for each receiver and transmitter
TDM.
The SI global mode register defines the activation state of each TDM.
The SI mode register defines the operation mode of each TDM.
The SI command register initiates a switch to shadow ram for each TDM.
The SI shadow address register defines which sub-block shadow ram starts
for each TDM.
The SI status register identifies current-route ram for each TDM.
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Completion
• That completes the Serial Interface section.
• It’s important to remember that there are many other considerations
when initializing, such as pin connections and controller functions.
• To test your understanding of this section, complete the exercise
on the next page.
That completes the serial interface section. It’s important to remember that
there are many other considerations when initializing, such as pin
connections and controller functions. To test your understanding of this
section, complete the exercise on the next page.
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Exercise
Define the values required to set up serial interface 1, where:
FCC2, FCC3, SCC2, SCC3, SMC1 and SMC2 are routed to TDMb.
a) First frame consists of FCC2, SCC2, SMC1 and SMC2 as follows:
Transmit 4 bytes from SCC2, followed by 24 bytes from FCC2, 2 bits from
SMC1 with Strobe-1, and 1 bit from SMC2 with Strobe-2, end of frame
b) 1-bit sync delay active on a logic ‘0’ and triggered on a rising edge; all other
controls will be default.
– The first entry in SIRAM will be in the second block.
c) At some time a dynamic switch must be provided to another frame with the
following format:
6 bytes from SCC3 with strobe 3, followed by 16 bytes from FCC3 with
strobe 4, 2-bits from SMC1with strobe-1, and 1 bit from SMC2 with Strobe-2.
– All other controls are the same as those in the previous frame.
– The RAM entries for the new frame must also be in block 2.
d) Indicate how the switch is made.
This exercise will help to check your understanding of how the various
requirements of the serial interface are controlled. The framing requirements
of the controller are defined here. Using these define the values required in
the registers where applicable. Any bits not of interest for this exercise can
be ignored. Define the SIRAM entries necessary to obtain the frame format
indicated. When you are ready, click on the result button to see the correct
result.
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