Horizontal and vertical deflection circuit

TDA8215B
HORIZONTAL AND VERTICAL DEFLECTION CIRCUIT
FEATURES SUMMARY
■ DIRECT LINE DARLINGTON DRIVE
Figure 1. Package
■
DIRECT FRAME-YOKE DRIVE (± 1A)
■
COMPOSITE VIDEO SIGNAL INPUT
CAPABILITY
■
FRAME OUTPUT PROTECTION AGAINST
SHORT CIRCUITS
■
PLL
■
VIDEO IDENTIFICATION CIRCUIT
■
SUPER SANDCASTLE OUTPUT
■
VERY FEW EXTERNAL COMPONENTS
■
VERY LOWCOST POWER PACKAGE
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POWERDIP 16 + 2 + 2
(Plastic Package)
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DESCRIPTION
The TDA8215B is an horizontal and vertical deflection circuit with super sandcastle generator
and video identification output. Used with
TDA8213 (Video & Sound IF system) and
TDA8217 (Pal decoder and video processor), this
IC permits a complete low-cost solution for PAL
applications. The TDA8215B has been specially
designed for direct drive of line DARLINGTON
transistors.
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Figure 2. Pin Connections
r
P
e
VCC1
1
20
VIDEO INPUT
FRAME OSCILLATOR
2
19
SUPER SANDCASTLE OUTPUT
VCC2
3
18
LINE FLYBACK INPUT
FRAME FLYBACK GENERATOR
4
17
LINE OUTPUT
GROUND
5
16
GROUND
GROUND
6
15
GROUND
POWER AMPLIFIER INPUT
7
14
RC NETWORK
VIDEO IDENTIFICATION OUTPUT
8
13
LINE SAWTOOTH INPUT
FRAME POWER SUPPLY
9
12
PHASE DETECTOR
10
11
LINE OSCILLATOR
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FRAME OUTPUT
REV. 2
May 2004
1/15
TDA8215B
Figure 3. Block Diagram
VCC2
VCC1
Video
Identification
1
2
9
8
Frame
blanking
detector
Frame
oscillator
19
Σ
3
4
+
Power
stage
Flyback
generator
-
YOKE
10
2µs
Video
Input
20
7
Frame-Synchro
generator
Line flyback
detector
Output
stage
17
Phase
detector
Input
stage
18
Line
oscillator
Burst gate pulse
generator
2µs
14
13
12
11
Line
Flyback
c
u
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VCC1
VCC1
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Table 1. Absolute Maximum Ratings
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Flyback Generator Supply Voltage
V9
I10NR
Frame Power Supply Voltage
(t s)
Frame Output Current (non repetitive)
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Value
Unit
30
V
35
V
60
V
± 1.5
A
I10
Frame Output Current (continuous)
±1
A
V17
Line Output Voltage (external)
60
V
Ip17
Line Output Peak Current
0.8
A
IC17
Line Output Continuous Current
0.4
A
–40 to 150
°C
Max Operating Junction Temperature
+ 150
°C
Operating Ambient Temperature
0 to 70
°C
Value
Unit
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TSTG
TJ
bs
TAMB
Storage Temperature
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Table 2. Thermal Data
Symbol
Parameter
RTH(j-c)
Max Junction-case Thermal Resistance
10
°C/W
RTH(j-a)
Typical Junction-ambient Thermal Resistance
(Soldered on a 35µm thick 45cm2 PC Board copper area)
40
°C/W
Max Recommended Junction Temperature
120
°C
TJ
2/15
TDA8215B
ELECTRICAL CHARACTERISTICS
VCC1 = 10V, TAMB = 25°C (unless otherwise specified)
Table 3. Supply (Pin 1)
Symbol
Parameter
ICC1
Supply Current
VCC1
Supply Voltage
Min.
Typ.
Max.
15
Unit
mA
9
10
10.5
V
Min.
Typ.
Max.
Unit
Reference Voltage (I20 = -1µA)
1.4
1.75
2
V
Minimum Width of Frame Pulse (When synchronized with TTL signal)
50
Table 4. Video Input (Pin 20)
Symbol
V20
MWF
Parameter
µs
Table 5. Line Oscillator (Pin 11)
Symbol
Parameter
Typ.
Max.
Unit
3.6
V
7.8
V
LT11
Low Threshold Voltage
2.8
3.2
HT11
High Threshold Voltage
5.4
6.6
BI11
Bias Current
DR11
Discharge Impedance
FLP1
Free Running Line Period
(R = 34.9kΩ Tied to VCC1, C = 2.2nF Tied to Ground)
FLP2
Free Running Line Period (R = 13.7KΩ, C = 2.2nF)
OT11
Oscillator Threshold for Line Output Pulse Triggering
∆F
------∆0
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Table 6. Line Output (Pin 17)
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Symbol
1.0
1.4
1.8
kΩ
62
64
66
µs
Pr
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-
Parameter
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LV17
Saturation Voltage (I17 = 800mA during 2µs)
OPW
Output Pulse width (line period = 64µs, negative pulse)
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od
Horizontal Frequency Drift with Temperature (see application)
)
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Min.
Min.
100
nA
27
µs
4.6
V
2
Hz/°C
Typ.
Max.
2.2
Unit
V
19
21
23
µs
Min.
Typ.
Max.
Unit
Bias Voltage
1.8
2.4
3.2
V
Input Impedance
4.5
5.8
8
kΩ
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Table 7. Line Sawtooth Input (Pin 13)
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Symbol
V13
Z13
Parameter
3/15
TDA8215B
Table 8. Phase Detector (Pin 12)
Symbol
Min.
Typ.
Max.
Unit
Output Current During Synchro Pulse
250
350
500
µA
RI12
Current Ratio (positive/negative)
0.95
1
1.05
LI12
Leakage Current
CV12
Control Voltage Range
I12
Parameter
–2
+2
µA
2.60
7.10
V
Table 9. Video Identification (Pin 8)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
6.3
0.9
V
0.6
0.9
V
Min.
Typ.
Max.
Low Level Output when the line synchro tip is centered in the line retrace
VH8
Without Video Signal (I8 = -500µA)
VL8
With Video Signal (I8 = 50µA)
Table 10. Frame Oscillator (Pin 2)
Symbol
Parameter
LT2
Low Threshold Voltage
1.6
2.0
HT2
High Threshold Voltage
2.6
DIF2
LT2 - HT2
Pr
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Unit
2.3
V
od
3.6
V
300
470
700
Ω
20.5
23
25
ms
3.1
1.0
V
30
nA
BI2
Bias Current
DR2
Discharge Impedance
FFP1
Free Running Frame Period
(R = 845kΩ Tied to VCC1, C = 180nF Tied to Ground)
MFP
Minimum Frame Period (I20 = –100µA) with the Same RC
12.8
ms
FFP2
Free Running Frame Period (R = 408kΩ, C = 220nF)
14.3
ms
FPR
Frame Period Ratio = FFP/MFP
(s)
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-
1.7
ct
FG
Frame Saw-tooth Gain Between Pin 1 and non Inverting Input of the
Frame Amplifier
∆F
------∆0
Vertical Frequency Drift with Temperature (see application)
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1.9
–0.4
Hz/°C
4.10–3
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1.8
Table 11. Frame Power Supply (Pin 9)
Symbol
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V9
I9
Parameter
Operating Voltage (with flyback Generator)
Min.
Typ.
Max.
Unit
58
V
11
22
mΑ
Typ.
Max.
Unit
30
V
10
Supply Current (V9 = 30V)
Table 12. Flyback Generator Supply (Pin 3)
Symbol
VCC2
4/15
Parameter
Operating Voltage
Min.
10
TDA8215B
Table 13. Frame Output (Pin 10)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Saturation Voltage to Ground (V9 = 30V)
LV10A
I10 = 0.1A
0.06
0.6
V
LV10B
I10 = 1A
0.37
1
V
Saturation Voltage to V9 (V9 = 30V)
HV10A
I10 = –0.1A
1.3
1.6
V
HV10B
I10 = –1A
1.7
2.4
V
Saturation Voltage to V9 in Flyback Mode (V10 > V9)
FV10A
I10 = 0.1A
1.6
2.1
V
FV10B
I10 = 1A
2.5
4.5
V
Typ.
Max.
Table 14. Flyback Generator (Pin 3 and Pin 4)
Symbol
Parameter
Min.
Flyback Transistor on (output = high state), VCC2 = 30V, V4/3 with
F2DA
I4 →3 = 0.1A
F2DB
I4 →3 = 1A
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Flyback Transistor on (output = high state), VCC2 = 30V, V3/4 with
FSVA
I3 →4 = 0.1A
FSVB
I3 →4 = 1A
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-
Flyback Transistor off (output = V9 - 8V), V9 - VCC2 = 30V
FCI
uc
1.5
Leakage Current Pin 3
Table 15. Super Sandcastle Output (Pin 19)
Symbol
(t s)
Parameter
c
u
d
Output Voltages (R load = 2.2kΩ)
)
s
t(
Unit
2.1
V
4.5
V
0.8
1.1
V
2.2
4.5
V
170
µA
od
3.0
Min.
Typ.
Max.
Unit
2
2.5
3
V
5
V
SANDT2
Frame blanking pulse level
SANDL2
Line blanking pulse level
4
4.5
Burst key pulse level
8
9
Delay between middle of sync pulse and leading edge of burst key
pulse
2.3
2.7
3.1
µs
Duration of burst key pulse
Vertical blanking pulse width
3.7
4
Note 1
5
µs
BG2
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V
Pulses width and timing
SC3
s
b
O
SC2
Note: 1. Width of vertical blanking pulse on SSC output is proportional to the frame flyback time, the switching level is VCC2 -2VBE and the
other input of the comparator is tied to the frame amplifier output. Application circuit uses the frame flyback generator.
5/15
TDA8215B
Table 16. Line Flyback Input (Pin 18)
Symbol
Parameter
Min.
Max.
Unit
Switching level
2
V
Maximum input current at VPEAK = 800V
8
mA
4.3
V
6
µs
Limiting voltage at maximum current
τ
Typ.
RC network time constant (Note 1)
Note: 1. An RC network is connected to this input. Typical value for the resistor is 27kΩ and 220pF for the capacitor. A different time constant
for RC changes the delay between the middle of the line synchro pulse and the leading edge of the burst key pulse but also the
duration of the burst key pulse.
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6/15
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TDA8215B
GENERAL DESCRIPTION
The TDA8215B performs all the video and power
functions required to provide signals for the line
driver and frame yoke.
It contains:
– A synchronization separator
– An integrated frame separator without external
components
– A saw-tooth generator for the frame
– A power amplifier for direct drive of frame yoke
(short circuit protected)
– An open collector output for the line darlington
drive
– A line phase detector and a voltage control
oscillator
– A super sandcastle generator
– Video identification output.
The slice level of sync-separation is fixed by value
of the external resistors R1 and R2. VR is an internally fixed voltage.
The sync-pulse allows the discharge of the capacitor by a 2 x I current. A line sync-pulse is not able
to discharge the capacitor under VZ/2. A frame
sync-pulse permits the complete discharge of the
capacitor, so during the frame sync-pulse Q3 and
Q4 provide current for the other parts of the circuit.
Figure 4. Synchronization Separator Circuit
SL1
SL2
VR
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20
R1
Video
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R2
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Figure 5. Frame Separator
u
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VZ
Q3
Q4
l
ST1
ST2
VZ/2
SL1
3l
7/15
TDA8215B
Figure 6. Line Oscillator
VCC1
R5
11
Phase
comparator
output
R4
c
u
d
The oscillator thresholds are internally fixed by resistors. The discharge of the capacitor depends on
the internal resistor R4. The control voltage is applied on resistor R5. The sync-pulse drives the
current in the comparator. The line flyback integrated by the external net work gives on pin 13 a
saw tooth, the DC offset of this saw tooth is fixed
by VC. The comparator output provides a positive
current for the part of the signal on pin 13 greater
than to VC and a negative current for the other
part.When the line flyback and the video signal are
synchronized, the output of the comparator is an
alternatively negative and positive current. The
frame sync-pulse inhibits the comparator to prevent frequency drift of the line oscillator on the
frame beginning.
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8/15
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Figure 7. Phase Comparator
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Line
Flyback
Integrated
Flyback
Sinc pulse
Output
Current
VC
TDA8215B
Figure 8.
Line output (Pin 17)
It is an open-collector output. The output negative
pulse time is 22µs for a 64µs period.
The oscillator thresholds are internally fixed by resistors. The oscillator is synchronized during the
last half free run period. The input current during
the charge of the capacitor is less than 100nA.
VCC1
12
13
VC
SL2
ST1
Figure 9. Frame Oscillator
c
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VCC1
INPUT CURRENT
COMPENSATION
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)
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Frame
sync pulse
u
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To frame amplifier
Frame output amplifier
This amplifier is able to drive directly the frame
yoke. Its output is short circuit and overload protected; it contains also a thermal protection.
The frame blanking is detected by the frame flyback generator. When the output voltage of the
frame amplifier exceeds VCC2-2VBE, the pulse is
detected. The line flyback detection is provided by
a comparator which compares the input line flyback pulse to an internal reference. The burst gate
pulse position is fixed by the external RC network
s
b
O
(Pin 14). It is referenced to the middle of the line
flyback.
This stage will detect the coincidence between the
line sync pulse (if present) and a 2µs sampling
pulse. This 2µs pulse is positioned at the center of
line sync pulse when the phase loop is locked.
This sampled detection is stored by an external
capacitor Pin 8.
The identification output level is high when video
signal is present.
Important remark: minimum saw-tooth amplitude
on Pin 13 has to be 2VPP (typ.: 2.5VPP).
9/15
TDA8215B
Figure 10. Super Sandcastle Generator
VCC1
Line
Flyback
Input
18
Frame
Output
10
VCC1
Line
Flyback
Detection
Σ
Frame
Blanking
Detection
Burst gate
pulse
generator
RC
400µA
YOKE
RC
Network
14
c
u
d
Figure 11. Video Identification Circuit (Pin 8)
VH
2.75V
13
VR
2.5V
)
s
(
ct
+
-
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d
o
VCC1
o
s
b
O
12µs
5.8Ω
VL
2.25V
e
t
le
Line retrace
+
-
bs
O
10/15
Line
Flyback
1kΩ
+
Line
Sync.
VR1
8
with video
VR1
10µF
VR
VL
Sampling Pulse
1N4148
BC547
VH
VCC1
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Integrated
Flyback
10kΩ
Video
Ident.
Output
SSC
Output
19
l8
Line Sync.
without video
TDA8215B
Figure 12. Typical Application
4.7kΩ
VCC
+24V
VCC1
470µF
100nF
100µF 100nF
VCC1
IN4002
820kΩ
10kΩ
IN4148
27kΩ
Video Identification
BC547
10µF
180nF
220pF
47µF
IN4148
100nF
2.2kΩ
2
1.5kΩ
Video
Input
220nF
1
8
3
9
4
14
10
120pF
560kΩ
20
15kΩ 22nF
Line
Flyback
Frame Yoke
30 mH, 15Ω
lpp = 840mA
TDA 8215B
13
68pF
22nF
7
12
100kΩ
11
5
6
15
16
19
680pF
o
r
P
220pF
22k
2.2nF
12nF
1µF
22kΩ
22kΩ
VCC1
)
s
(
ct
SSC
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t
le
100Ω
Horizontal
Frequency
so
2.2kΩ
b
O
-
220kΩ
17
100kΩ
180pF 4.7k
c
u
d
220kΩ
18
VCC1
10µF
270Ω
100Ω
)
s
t(
1000µF
1Ω
Line Yoke
193mH, 22Ω, ipp = 4A
Line Darlington
SGSD00055
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11/15
TDA8215B
PART NUMBERING
Table 17. Order Codes
Part Number
Package
Temperature Range
TDA8215B
PDIP20
-0 to 70 °C
c
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12/15
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s
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TDA8215B
PACKAGE MECHANICAL
Table 18. PLASTIC POWERDIP Mechanical Data
millimeters
Symbol
Min
a1
0.51
B
0.85
inches
Typ
Max
Min
Typ
1.4
b
0.033
0.055
0.5
b1
0.020
0.38
0.5
D
0.015
0.020
24.8
0.976
E
8.8
0.346
e
2.54
0.100
e3
22.86
0.900
F
7.1
i
5.1
L
0.280
0.130
uc
1.27
0.050
d
o
r
Figure 13. PLASTIC POWERDIP Package Dimensions
N
N
e4
R1
P
e
let
N
K1
I
A
a1
b
B
b1
C
L
R1
e
Z
F
e3
E
Tie Bar Center
D
r
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K
o
s
b
O
-
K2
)
s
(
ct
u
d
o
20
11
1
10
t
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l
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)
s
t(
0.201
3.3
Z
R2
s
b
O
Max
0.020
Note: Drawing is not to scale.
13/15
TDA8215B
REVISION HISTORY
Table 19. Revision History
Date
Revision
Description of Changes
September-1993
1
First Issue
17-May-2004
2
Stylesheet update. No content change.
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14/15
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TDA8215B
c
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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