Technical Seminar H314
Practical Guidelines
for Implementing 5 Gbps
in Copper Today,
and the Roadmap to 10 Gbps
Brent R. Rothermel
David W. Helster
Alex M. Sharf
1
Presentation Overview
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
• Three obstacles to implementing
5 Gbps serial links
– Trace loss
– Connectors
– Board attachment
• Test board results
• The Roadmap to 10 Gbps
10 Gbps
Connector
Board attachment
Trace Loss
2
PWB Materials Review
5 Gbps
tanδ* Relative
@ 1 GHz
Cost**
εr*
ε r*
@ 1 MHz
@ 1 GHz
FR4
4.30
4.05
0.020
1
GETEK
4.15
4.00
0.015
1.1
Results
ROGERS
4350/4320
3.75
3.60
0.009
2.1
10 Gbps
ARLON CLTE
3.15
3.05
0.004
6.8
Trace Loss
Material
Connectors
Board
Attach
Z
* Measured from test data
**Cost factor derived from 10” by 20”, 12-layer backplane
3
5 Gbps Trace Eye Patterns
5 Gbps
FR4
GETEK
FR4
Jitter = 0.043 UI
Opening = 586 mV
Trace Loss
GETEK
Jitter = 0.035
Opening = 634 mV
Connectors
Board
Attach
ROGERS 4350
Jitter = 0.034 UI
Opening = 736 mV
Z
Results
ROGERS 4350
ARLON CLTE
ARLON CLTE
Jitter = 0.020 UI
Opening = 788 mV
10 Gbps
-The output waveforms shown
result from a 1-volt, 32-bit
inverting K28.5 input bit
pattern (5 Gbps, 60ps
edges) that is applied to a
12 mil, 50 Ohm stripline
trace that is 18” long.
4
Adding HS3 Connectors
5 Gbps
Trace Loss
• 50 Ω impedance throughout
matches board impedance
AMP
Connectors
Z-PACK HS3
Board
Attach
Z
Results
10 Gbps
test point
test point
~1”, 12 mil,
~1”, 12 mil,
50 Ohms
50 Ohms
~16”, 12 mil, 50 Ohms
5
5 Gbps System Eye Patterns
5 Gbps
FR4
GETEK
FR4:
Jitter = 0.25 UI
Opening = 218 mV
Trace Loss
GETEK:
Jitter = 0.24 UI
Opening = 227 mV
Connectors
Board
Attach
ROGERS 4350:
Jitter = 0.19 UI
Opening = 378 mV
Z
Results
ROGERS 4350
ARLON CLTE
10 Gbps
ARLON CLTE:
Jitter = 0.12 UI
Opening = 516 mV
-The output waveforms shown
result from a 1-volt, 32-bit
inverting K28.5 input bit
pattern (5 Gbps, 60ps
edges) that is applied to a
system with two throughholes, two AMP HS3
connectors, and a 12 mil,
50 Ohm stripline trace
that is ~18” long.
.
6
Connector Performance
5 Gbps
• Comparison of HS3 connector to trace
Trace Loss
Connectors
Z
Voltage (V)
Results
50 Ω
50 Ω
0.50
0.50
0.40
0.40
0.30
0.30
0.20
0.20
0.10
0.10
Voltage (V)
Board
Attach
10 Gbps
50 Ω
Trace
50 Ω
0.00
-0.10
50 Ω
0.00
-0.10
-0.20
-0.20
-0.30
-0.30
-0.40
-0.40
-0.50
0.00
HS3
Connector
-0.50
0.06
0.12
0.18
0.24
0.00
0.05
0.10
0.15
0.20
Time (ns)
Time (ns)
769 mV Opening, 6.25% Jitter
754 mV Opening, 6.25% Jitter
7
Adding the Via
5 Gbps
Trace Loss
50 Ω
Connectors
VIA
Board
Attach
50 Ω
VIA
0.60
Z
0.40
Results
0.20
Voltage (V)
10 Gbps
HS3
Connector
0.00
-0.20
-0.40
-0.60
0.00
0.06
0.12
0.18
Time (ns)
218 mV Opening, 34.4% Jitter
8
0.24
-The output waveform shown
results from a 1-volt, 32bit inverting K28.5 input
bit pattern (5 Gbps, 60ps
edges) that is applied to a
system with two throughholes, two AMP HS3
connectors, and a 12 mil,
50 Ohm stripline trace
that is ~18” long.
.
Challenge: The Via Culprit
5 Gbps
Trace Loss
•
•
Vias introduce capacitive discontinuities
Connector and traces are about 50 Ω
Connectors
HS3 connector
Board
Attach
Test parameters
•All traces 12 mils
•6” backplane trace
(ROGERS 4350 dielectric)
Z
Results
via
•3” daughtercard traces
(FR4 dielectric)
via
•HS3 6 row connectors
10 Gbps
9
System Insertion Loss
5 Gbps
Trace Loss
• Comparison of trace and system
reveals performance hit vs. frequency
1.00
Connectors
Board
Attach
0.90
System
0.80
Trace Only
Test/simulation parameters
•All traces 12 mils
Z
Results
10 Gbps
Amplitude (V)
0.70
•6” backplane trace
(ROGERS 4350 dielectric)
0.60
•3” daughtercard traces
(FR4 dielectric)
0.50
0.40
•HS3 6 row connectors
0.30
0.20
0.10
0.00
0.00
1.00
2.00
3.00
4.00
5.00
Frequency (GHz)
10
6.00
7.00
8.00
Multilayer Boards Require Vias
5 Gbps
Trace Loss
Connectors
Board
Attach
• Vias are required to reach the interior of
any multilayer board
• Both pressfit and SMT attachment
techniques require vias
Z
Results
10 Gbps
11
SMT vs. Press-fit
• Board thickness determines
potential for SMT
• Thick boards may be worse
5 Gbps
Trace Loss
Connectors
Board
Attach
1.2
1.1
Z
10 Gbps
Capacitance (pF)
Results
Simulation parameters
1
•25 mil SMT pad
0.9
•150 mil board thickness
0.8
•9 planes
0.7
•FR4 board material
•7 mil SMT pad-to-plane
dielectric thickness
0.6
SMT Total Cap
0.5
Via Only
0.4
10
12
14
16
18
20
22
24
26
Finished hole size (mils)
12
28
30
Via Capacitance Factors
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
10 Gbps
• Via diameter
• Board stackup
– Board thickness (Length of cylinder)
– Number of planes
– Spacing of planes
• Pads*
• Anti-pad size*
• Signal layer attachment location*
13
Remove Non-Functional Pads
5 Gbps
Trace Loss
Connectors
Board
Attach
• Non-functional pads are not necessary
– Surface pads required
– Keep internal pad for trace connection
• Removal can improve via capacitance
Z
Results
10 Gbps
pads kept
pads removed
14
Antipad Capacitance Effect
5 Gbps
Trace Loss
• Capacitance of via decreases as
antipad grows
54.00
Connectors
Simulation parameters
•HS3 pinfield
Board
Attach
Results
•Via only (no connector)
Impedance (Ohms)
Z
50.00
•60 ps edge
46.00
42.00
10 Gbps
52 mil Antipad
38.00
63 mil Antipad
34.00
3.50
3.65
3.80
3.95
4.10
4.25
Time (ns)
15
4.40
4.55
4.70
HS3 Antipad Example
5 Gbps
• AMP HS3 supports large antipads
0.60
Trace Loss
•52 mil antipad diameter
•166.1 mV opening
•25 % jitter
0.20
Voltage (V)
Connectors
0.40
0.00
-0.20
Board
Attach
-0.40
-0.60
0.00
0.06
0.12
0.18
0.24
0.18
0.24
Time (ns)
0.60
Z
10 Gbps
0.40
•63 mil antipad diameter
•301.6 mV opening
•18.75 % jitter
0.20
Voltage (V)
Results
0.00
-0.20
-0.40
-0.60
0.00
0.06
0.12
Time (ns)
•5Gbps
•K28.5 pattern
•HS3 6 row connectors
Simulation parameters
•Backplane
•12” ROGERS 4350
•200 mils thick
16
•Daughtercard
•3” FR4
•100 mils thick
Pinfield Routing
5 Gbps
Trace Loss
• Routing through HS3 pinfield with 63 mil
antipads does not decrease performance
1.00
Connectors
0.90
Board
Attach
Results
10 Gbps
0.70
Amplitude (V)
Z
0.80
0.60
0.50
0.40
0.30
0.20
S21 Magnitude
No Pinfield
0.10
S21 Magnitude
Through Pinfield
Test parameters
•12“ ROGERS 4350 BP,3“ FR4 DC
•HS3 6 row connectors
•12 mil traces
0.00
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (GHz)
17
9.0
10.0
•Pinfield routing through 12 connectors
Layer Attachment Location
5 Gbps
Trace Loss
• Two layer connection extremes are
possible
Connectors
Board
Attach
Z
Results
10 Gbps
Transmitting
across the via
Transmitting
through the via
18
Stub Via Performance
5 Gbps
Trace Loss
• Transmitting across the via introduces
the largest discontinuity
Connectors
Board
Attach
Test parameters
•HS3 pinfield
Z
•Optimized antipad
Results
10 Gbps
•Via only (no connector)
across
the via
through
the via
19
Stub Removal Technique #1
5 Gbps
Trace Loss
Connectors
• Blind vias can be
used to eliminate the
stub capacitance
Board
Attach
Z
Results
• Pros
– Via stub is completely removed
10 Gbps
• Cons
– Can double fabrication cost of bare board
– May not support pin-in-hole soldering
techniques
20
Stub Removal Technique #2
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
• Counterboring is an
alternative technique
that removes via stub
capacitance
• Pros
– Via stub is almost completely removed
10 Gbps
• Cons
– Can add 25% to bare board fabrication cost
– Counterbore drill depth tolerance requires
that a small stub remain
21
Counterboring Performance
5 Gbps
Trace Loss
• Transmitting across the via now
introduces almost no discontinuity
Connectors
Board
Attach
across the via
w/ counterboring
Test parameters
•HS3 pinfield
Z
•Optimized antipad
Results
•Via only (no connector)
through the via
10 Gbps
across the via
no counterboring
22
Via Connections with Pins
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
Counterbored
Top of Via Connection
Not Counterbored
Top of Via Connection
10 Gbps
Not Counterbored
Bottom of Via Connection
23
Counterboring and HS3
5 Gbps
Trace Loss
HS3 connector
Connectors
Board
Attach
Z
Results
across the via
w/ counterboring
across the via
no counterboring
10 Gbps
Test parameters
•HS3 6 row connector
•Optimized antipad
24
Design Technique Summary
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
10 Gbps
• Remove unused pads
• Antipad size
– Decreases excess capacitance
– No added cost
– Limited by trace routing considerations
• Stub removal
– Significantly decreases excess capacitance
– At least two techniques can be used
– Adds additional costs
25
Gigabit System Testbed
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
• HS3 Connectors
• ROGERS 4350 &
FR4 materials
• 8 and 12 mil trace widths
• 12, 18, and 24 inch system
trace lengths
• Top of via layer connection
–
–
10 Gbps
•
•
•
Counterbored
Not counterbored
Bottom of via layer connection
Optimized antipads
Non-functional pads removed
26
Test Configuration
5 Gbps
Trace Loss
Connectors
•
•
•
HP 8722ES 40 GHz Vector Network Analyzer
HP 8152 Digitizing Oscilloscope and TDR
Advantest D3186 12 Gbps Pulse Pattern
Generator
Board
Attach
Z
Results
10 Gbps
27
ROGERS 4350 System @ 5 Gbps
5 Gbps
Test parameters
•24” system (ROGERS 4350)
•No Counterboring
Trace Loss
•Top of board layer connection
•12 mil traces
Connectors
•HS3 6 row, Optimized antipads
39 % Eye Opening
Board
Attach
13.5 % UI Jitter
Z
Results
Test parameters
•24” system (ROGERS 4350)
10 Gbps
•Counterboring
•Top of board layer connection
•12 mil traces
•HS3 6 row, Optimized antipads
54 % Eye Opening
9.5 % UI Jitter
28
FR4/ROGERS 4350 System @5 Gbps
5 Gbps
Test parameters
•3” FR4 DCs, 18” ROGERS 4350 BP
•No Counterboring
Trace Loss
•Top of board layer connection
•12 mil traces
Connectors
•HS3 6 row, Optimized antipads
31 % Eye Opening
Board
Attach
15.5 % UI Jitter
Z
Results
Test parameters
•3” FR4 DCs, 18” ROGERS 4350 BP
10 Gbps
•Counterboring
•Top of board layer connection
•12 mil traces
•HS3 6 row, Optimized antipads
49 % Eye Opening
12.5 % UI Jitter
29
8 mil Trace, 2 ft System Comparison
5 Gbps
2 Gbps
3.125 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
64 % Eye Opening, 7.2% UI Jitter
59 % Eye Opening, 10.0% UI Jitter
5 Gbps
Test parameters
•3” FR4 daughtercards
•18” ROGERS 4350 backplane
10 Gbps
•No Counterboring
•Top of board layer connection
•8 mil trace width
•HS3 6 row connectors
•Optimized antipads
35 % Eye Opening, 13.5% UI Jitter
30
Trace Width Comparison
100%
5 Gbps
90%
12 mil trace
80%
8 mil trace
Connectors
Board
Attach
Z
Results
10 Gbps
Eye opening (% Launch)
Trace Loss
70%
60%
50%
Test parameters
•3” FR4 daughtercards
40%
•18” ROGERS 4350 backplane
•Counterboring
30%
•Top of board layer connection
20%
•HS3 6 row connectors
•Optimized antipads
10%
0%
1.0
2.0
3.0
Bit rate (Gbps)
31
4.0
5.0
6.0
7.0
8.0 9.0 10.0
Layer Connection Comparison
100%
5 Gbps
Top Counterbore
90%
Trace Loss
Top No Counterbore
Connectors
Board
Attach
Z
Results
10 Gbps
Eye opening (% Launch)
80%
Bottom No Counterbore
70%
60%
50%
40%
Test parameters
•3” FR4 daughtercards
30%
•18” ROGERS 4350 backplane
•12 mil traces
20%
•HS3 6 row connectors
10%
•Optimized antipads
0%
1.0
2.0
3.0
Bit rate (Gbps)
32
4.0
5.0
6.0
7.0
8.0 9.0 10.0
5 Gbps Using AMCC Devices
5 Gbps
Trace Loss
Connectors
• AMCC S2018 Crosspoint Switch
• Designed for 2.5 Gbps
operation
Board
Attach
Z
Results
Test parameters
10 Gbps
•All traces 12 mils
•24” ROGERS 4350 System
•HS3 6 row connectors
•Optimized antipads
•Top layer connection, counterbored
33
Summary of 5 Gbps Techniques
5 Gbps
Trace Loss
Connectors
Board
Attach
Z
Results
10 Gbps
• Low-loss dielectrics are prudent
• Unused pads can be removed to
decrease capacitance
• Increasing antipad size further reduces
via capacitance
• Via stubs and associated capacitive
discontinuities may be removed
– Blind vias
– Counterboring
34
10 Gbps Trace Eye Patterns
5 Gbps
FR4
GETEK
FR4:
Jitter = 0.30 UI
Opening = 238 mV
Trace Loss
GETEK:
Jitter = 0.28 UI
Opening = 268 mV
Connectors
Board
Attach
ROGERS 4350:
Jitter = 0.20 UI
Opening = 426 mV
Z
Results
ROGERS 4350
ARLON CLTE
ARLON CLTE:
Jitter = 0.19 UI
Opening = 520 mV
10 Gbps
-The output waveforms shown
result from a 1-volt, 32-bit
inverting K28.5 input bit
pattern (10 Gbps, 60ps
edges) that is applied to a
12 mil, 50 Ohm stripline
trace that is 18” long.
35
10 Gbps System Eye Patterns
5 Gbps
FR4
GETEK
All Materials:
Trace Loss
Zero Crossover jitter is
indistinguishable
Connectors
The eye is closed (no
open amplitude)
Board
Attach
Z
Results
ROGERS 4350
ARLON CLTE
10 Gbps
-The output waveforms shown
result from a 1-volt, 32-bit
inverting K28.5 input bit
pattern (10 Gbps, 60ps
edges) that is applied to a
system with two throughholes, two AMP HS3
connectors, and a 12 mil,
50 Ohm stripline trace
that is ~18” long.
36
The Roadmap to 10 Gbps
5 Gbps
Trace Loss
• 5 Gbps techniques will be required
• Further improvements are necessary
Test parameters
Connectors
•All traces 12 mils
•3” FR4 DCs, 6” ROGERS 4350 BP
Board
Attach
•HS3 6 row connectors
•Optimized antipads
Z
•Top layer connection, counterbored
Results
10 Gbps
37
Recommended Resources
• AMP Circuits & Design
System
Analysis
System
Design
Prototype
Production
• For further information, contact:
– AMP simulation services - simulation@amp.com
– AMP modeling services - modeling@amp.com
• Presentation information and additional
paper copies can be obtained from:
Brent Rothermel
(717) 986-7835
brothermel@amp.com
Dave Helster
(717) 986-5686
dave.helster@amp.com
38
Alex Sharf
(717) 986-5447
alex.sharf@amp.com