Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
1
2. Chapter: Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
Time of study: 6 hours
Goals:
•
definition of the quiescent points set for the above tripoles
•
definition of the BJT admittance model
•
definition of the FET admittance model
•
definition of the triode admittance model
Text
THE QUIESCENT POINT OF A BJT (BIPOLAR JUNCTION TRANSISTOR) – an
example
Basic description of BJT principle
A transistor can be considered as two diodes with a shared region (base). In typical operation,
the emitter-base junction is forward biased and the base-collector junction is reverse biased.
In NPN transistor, for example, positive voltage applied to the base-emitter junction injects
electrons into the base (type P) region. These electrons wander (diffuse) through the base
towards the collector (type N). The collector- base junction is reverse biased → electrons that
diffuse through the base are swept into the collector by the electric field in the depletion
region of the collector-base junction. The base region of the transistor must be made thin, so
that carriers (electrons in the NPN structure) can diffuse across it in much less time than the
semiconductor’s minority carrier lifetime, to minimize recombination.
EMITTER
INJECTION
DRIFT CURRENT
FORCE DIRRECTION
N
P
N+
COLLECTOR Schematic
IE
IC
E
C
+UCB
B
UBE +
IB
DEPLETION
REGION
ELECTRIC FIELD
diagram showing the
flows of electrons within n+-p-n
bipolar junction transistor. The
conventions for the electrical
currents are shown. Since only a
small portion of electrons will be
recombined within base, we can use
a small injection current (IB) to
control a much bigger current (IC).
β = IC / I B
α = I C / I E = I C /( I C + I B ) =
= ( I C / I B ) /( I C / I B + 1) = β /( β + 1)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
2
UN
I1
IC
RC
R1
Ri
UC
CV2
IB
CV1
RE
UCE
R´E
0, 6 V
ui
R2
(a)
IE
RE
UR2
Re = RE//R´E
RZ
UE
(b)
Fig. 1 A basic common emitter configuration (CE) – voltage divider biasing – a); a
capacitor in fig. b) transfers AC signals through R´E to the earth (reference
point), too – parallel connection RE//R´E gives Re for the AC signal
Example – the circuit in the Fig. 1 – quiescent point
1. It uses voltage negative feedback to stabilize the quiescent point – this is provided by RE.
2. Since there is a ± 50 mV spread in UBE for defined IC value and about a -2 mV/°C
temperature dependency on UBE it is best to allow UBE to be much larger than this variation.
We therefore make UBE between 1 V and 3 V (the larger the better from the point of view of
quiescent point stability).
3. The fixed DC bias is guaranteed by the divider action of R1 and R2. Since IB is drawn from
this, it is usual to allow the voltage divider current I1 to be (5-10) x IB → the BJT load (base)
current does not pull the bias voltage UR2 down to much.
4. RE introduces negative (DC) feedback. If the temperature increases, UBE (circa 0, 6 V)
decreases (influence of temperature transistor properties) and IC increases and therefore UE
increases, too. Since UR2 is fixed, this causes UBE to fall (influence of RE feedback properties),
which causes IC to fall back to its original value.
Biasing is determined by following steps (generally):
1. Choose the required IC (DC) value for the circuit – assume IE ≈ IC.
2. For a CE circuit, allow about 1 V (UE) to be dropped across RE – calculate it (you know its
voltage and current – Ohm’s law).
3. For a CE circuit (and CB), the rest of the power supply must be dropped approximately
equally across BJT and RC – calculate RC (you know its voltage and current – Ohm’s law).
For a CC circuit, the rest of the power supply must be dropped across BJT only.
4. The quiescent base voltage UR2 is simply the emitter voltage UE plus UBE (assume 0, 6 V).
5. Find the lowest guaranteed β for the BJT used and calculate IB = IC/ β.
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
3
6. The voltage divider circuit of R1 and R2 must provide the required UR2.
6.1. Assume that the lower resistor R2 carries (5-10) times the IB value. Calculate R2 (you
know its voltage and current).
6.2. The upper resistor R1 therefore carries the R2 current plus IB (Kirchhoff’s current law).
This means that R1 carries
(5-10) x IB + IB = (6-11) IB
The voltage across R1 is found from the Kirchhoff’s voltage law (KVL): (UN – UR2) –
calculate R1 (you know its voltage and current).
---------------------------------------------------------------------------------------Example 1
Design the voltage divider bias for a CE BJT circuit- Fig. 1, where β >>1, the power
supply UN = 12 V and the load resistance RZ = 100 kΩ (given, known).
Solution (steps are slightly modified because we know the load resistance now)
It is known (thereinafter) that the resistance RC defines (approximately) an output resistance
of the CE circuit. Thus we must choose RC << RZ - or else it will degrade voltage gain of the
circuit (Thévenin´s theorem).
Thus we choose RC = 10 kΩ.
We choose UE = 0, 6 V.
We choose UC = 6 V (≈ UCE = 5, 4 V).
Now we can calculate IC = UC/RC = 0, 6 mA.
We suppose IE ≈ IC = 0, 6 mA.
From this we can calculate RE = UE/IC = 1 kΩ.
Now UR2 = UE + UBE ≈ 0, 6 + 0, 6 = 1, 2 V.
Suppose that the lowest value of β is 150. Therefore IB = IC/ β = 0, 0006/150 = 4 μA.
→ The voltage divider must provide 1, 2 V at 4 μA.
Assume that R2 carries 40 μA (= 10 x IB). Therefore R2 = 1, 2 V/ 40 μA = 30 kΩ.
→ Now R1 carries 11 x IB = 44 μA and drops (UN – UR2) = (12 – 1, 2) V. Therefore
R1 = 10, 8 V/ 44 μA = 245, 5 kΩ.
Practically we can choose R2 = 27 kΩ and R1 realize by means two resistors: the first part is
“invariable” 220 kΩ and the other part is “variable” 68 kΩ - trimming resistor.
-------------------------------------------------------------------------------------------------------THE BJT SIPMLEST AC MODEL – common emitter
The UBE and IC of the BJT are related by the equation
I E ≅ I S ⋅ (eU BE / U th − 1) ≈ I S ⋅ eU BE / U th
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
4
where Uth is thermal voltage (of about 26 mV at room temperature) – Shockley equation. For
β >>1 we can write
I C ≅ I S ⋅ eU BE / U th
(1)
We can easy derive that a signal conductance is
g BE = 1 / re =
dI C
1
I
I
= I S ⋅ eU BE /U th ⋅
= C ≈ E
dU BE
U th U th U th
(2)
We can model this property (in the given quiescent point IC, of course) as shown in Fig. 2.
C
ib ≈ uBE/(βre)
B
uBE
EXTERNAL
(SIGNAL)
VOLTAGE
iC ≈
uBE/re
INTERNAL EMITTER OF AN IDEAL
TRANSISTOR – ZERO VOLTAGE BETWEEN
BASE AND EI (SIGNAL MODEL)
0
EI
re = 1/gBE = Uth/IC – intrinsic (internal)
ie =
uBE/re
re
E
emitter resistance (signal); it is not a resistor
planted in the transistor; it only models the
real conductance of the device – the signal
collector current changes as a function of the
input signal voltages uBE – accord in eq. (2);
dIC → iC ; dUBE → uBE – signal changes
Fig. 2 The simplest signal model of BJT in the quiescent point IC; β - current gain;
all voltages referred to E
Now we can easy determine signal equations of the BJT – see Fig. 2 (E – common point)
iB = iC/β + 0.uCE = ((uBE/re )/β + 0.uCE ⇒
iC= uBE/re + uCE.0
⇒
yBB = 1/(β.re);
yCB = 1/re;
That easy way we get the simplest admittance model of the BJT.
yBC= 0
yCC = 0
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
5
THE BJT MORE KOMPLEX AC MODEL – common emitter
Base-width modulation - BJT
As the applied collector-base voltage (UCB) varies, the collector-base depletion region varies
in size. An increase in the collector-base voltage causes a greatest reverse bias across the
collector-base junction, increasing the collector-base depletion region width, and decreasing
the width of the base – Early effect. Narrowing of the base width has two consequences:
- There is a lesser chance for recombination within the “smaller” base region.
- The charge gradient is increased across the base, and consequently, the current of minority
carriers injected across the emitter junction increases.
In the forward active region the Early effect modifies the collector current IC and the forward
common emitter current gain β as given by the following equations:
I C ≅ I S ⋅ eU BE / U th ⋅ (1 + U CB / U A )
(3)
β ≅ β 0 ⋅ (1 + U CB / U A )
(4)
where
UCB is the collector – base voltage (≈ UCE always)
UA is the Early voltage (15 to 150 V)
β0 is forward common-emitter current gain when UCB = 0
We can easy derive that a signal conductance is now
g BE = 1 / re =
1
I
I
δI C
= I S ⋅ eU BE /U th ⋅
⋅ (1 + U CB / U A ) = C ≈ E
δU BE
U th
U th U th
(5)
and
gCE = 1 / rCE =
δI C
δI
I
I
≈ C = I S ⋅ eU BE /U th ⋅ (1 / U A ) ≈ C ≈ E
δU CE δU CB
UA UA
We can model this more complex property (in the given quiescent point IC, of course) as
shown in Fig. 3.
(6)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
6
iC
C
ib ≈ uBE/(βre)
uCE/rCE
≈
uBE/re
rCE = 1/gCE = UA/IC - emitter –
B
uBE
EXTERNAL
(SIGNAL)
VOLTAGE
0
EI
rCE
ie =
uBE/re
re
collector resistance (signal); it is not
a resistor planted in the transistor; it
only models the real conductance of
the device – the signal collector
current changes as a function of the
signal voltages uCE , too – accord in
eq. (6) – ideally is infinite
E
Fig. 3 The more complex signal model of BJT (extended) in a quiescent point IC;
it models the Early effect, too; all voltages referred to E
Now we can easy determine more complex signal equations of the BJT – see Fig. 3:
iB = iC/β + 0.uCE = ((uBE/re )/β + 0.uCE ⇒ yBB = 1/(β.re);
iC= uBE/re + uCE/ rCE
⇒ yCB = 1/re;
yBC= 0
yCC =1/ rCE
We don’t reason about influence of equation (4) –we suppose β constant.
Thus the BJT matrixes are:
B
C
B YBB YBC
C YCB YCC
Y- matrix model (ordinary) of the BJT; common emitter connection
(7)
B
C
E
B YBB
YBC
-YBB –YBC
(8)
C YCB
YCC
-YCB –YCC
E -YBB-YCB -YBC-YCC +Σ
Σ =YBB+YBC +YCB +YCC
extended Y- matrix model of the BJT – derived from the common emitter connection
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
7
THE BJT AC MODEL – Collector Capacitance
Most of the potential difference between base and collector is distributed over a thin region at
the PN junction, within which the voltage gradient is very high. Consequently, in the vicinity
of the junction there are two sets of electric charges (one on either side). The junction acts in
much the same way as a capacitor in which charges are separated by a thin sheet of dielectric
– for small-signal analysis the effect is closely equivalent to that of a capacitance shunted
across the junction. The magnitude of this capacitance depends on the collector-base potential
difference, being greatest at low voltages. This “depletion layer” capacitance is the dominant
capacitance at the collector -we can model this capacitance CCB (in the given quiescent point
IC, UCB of course) as shown in Fig. 4.
iCCB
iC
CCB
C
uBE/(βre)
ib
B
uBE
EXTERNAL
(SIGNAL)
VOLTAGE
uCE/rCE
≈
uBE/re
EI
0
rCE
ie =
uBE/re
re
Fig. 4 A signal model of BJT (extended) with
capacitance CCB in a quiescent point IC,
UCB; all voltages referred to E
E
Now we can easy derive (harmonic steady state: p = jω; or Laplace transform):
ICCB = (UBE - UCE).p.CCB;
IB = ((UBE/re )/β + ICCB = ((UBE/re )/β + (UBE - UCE).p.CCB
IB =(1/(βre) + p.CCB). UBE - p.CCB. UCE
⇒
YBB = 1/(β.re) + p.CCB; YBC= - p.CCB
(9)
IC= UBE/re + UCE/ rCE - ICCB = UBE/re + UCE/ rCE - (UBE - UCE).p.CCB
IC= (1/ re - p.CCB). UBE + (1/ rCE + p.CCB). UCE
⇒
YCB = 1/re - p.CCB;
see the equations (7) and (8).
YCC =1/ rCE + p.CCB
(10)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
8
We could add base-emitter capacitance CBE, further – current that flows through CBE is not
amplified by the transistor. CBE changes so rapidly with base current that it is not even
spcified on transistor datasheets; fT (unity frequency is given instead).
THE QUIESCENT POINT OF A FET (FIELD EFFECT TRANSISTOR)
Basic description of FET principle
The FET controls the flow of electrons (or holes) from the source to drain by affecting the
size and shape of a "conductive channel" created and influenced by voltage (or lack of
voltage) applied across the gate and source terminals. This conductive channel is the "stream"
through which electrons flow from source to drain.
A) Consider an n-channel "depletion-mode" device. (It exists conducting channel between
S and D for UGS = 0 V).A negative gate-to-source voltage causes a depletion region to
expand in width and encroach on the channel from the sides, narrowing the channel. If the
depletion region expands to completely close the channel, the resistance of the channel from
source to drain becomes large, and the FET is effectively turned off like a switch. Likewise a
positive gate-to-source voltage increases the channel size and allows electrons to flow easily –
principle see Fig. 5 to Fig. 6.
metal
G
S
D
SiO2
N
N+
N+
P
Fig. 5 A principle of depletion mode device – MOSFET;
S – source; G – gait; D – drain; N - channel
metal
S
G
N+
D
P
N+
N
Fig. 6 A principle of depletion mode device; junction FET –
JFET; UGS < 0; N – channel; S–source; G–gait; D–drain;
Do not forward bias the JFET gate. Forward gate current
will burn out the JFET.
If drain-to-source voltage is increased, this creates a significant asymmetrical change in the
shape of the channel due to a gradient of voltage potential from source to drain – see Fig. 7 to
Fig. 11.
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
D
UDS
ID
P
DEPLETION
REGIONS
9
PINCH OFF
POINT – the first
PINCH OFF
POINT – the other
G
UDS
or
Si
O2
UGS = 0
ID
ID
UGS = 0
N
IDSS
UGS = 0
S
.
|UPINCH|
Fig. 7 An effect of UDS on depletion region, UGS = 0; N - channel
UDS = 0;
UDS = 0, 5 V;
UDS = 1 V;
UDS = |UPINCH|= 2 V for example; ID = IDSS
UDS > |UPINCH|; ID ≈ IDSS
UGS
D
ID
P
DEPLETION
REGIONS
G
UDS = 0
UGS
or
Si
O2
N
UGS
S
Fig. 8 An effect of UGS on depletion region, UDS = 0; N - channel
UGS = 0;
UGS = - 0, 5 V;
UGS = -1 V;
UGS = UPINCH = - 2 V for example; ID = 0 for any UDS
UDS < UPINCH; ID = 0 for any UDS
UDS
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
10
The shape of the conductive region (channel) is “pinched-off” near the drain end of the
channel. If drain-to-source voltage is increased further, the pinch-off point of the channel
begins to move away from the drain towards the source. The FET is said to be in saturation
mode
UDS - UGS
D
ID
PINCH OFF
POINT – the first
P
DEPLETION
REGIONS
PINCH OFF
POINT – the other
G
UDS
or
Si
O2
UGS = 0
UGS = 0
ID
|UPINCH|
IDSS
UGS = 0 V
IDP
ID
N
S
UGS = -0,5 V
UDS
|UPINCH| - |UGS|
Fig. 9 An effect of UDS and UGS on depletion region - superposition, UGS = - 0, 5 V;
UDS = 0 V; UDS - UGS = 0, 5 V
UDS = 0, 5 V; UDS - UGS = 1 V
UDSP - UGS = 2 V = |UPINCH| →
UDSP = |UPINCH| + UGS = |UPINCH| - |UGS| = - UPINCH + UGS generally
= 2 - 0, 5 = 1, 5 V; IDP < IDSS
UDS > UDSP; ID ≈ IDP < IDSS
UDSP = |UPINCH| - |UGS|
OHMIC
(LINEAR)
MODE
ID
SATURATION MODE
(ACTIVE MODE)
UGS>0
MOSFETs only
UGS=0;
UGS<0; JFETs,
MOSFETs
IDSS
UA – EARLY VOLTAGE
0
UDSQ
Fig. 10 There is I – U characteristics of depletion FETs in this figure,
UGS – parameter; N - channel
U
– quiescent voltage; N - channel
UDS
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
11
ID
MOSFET
N-channel
JFET
N-channel
UPINCH
IDSS
0
UDS = UDSQ
invariable
UGS
Fig. 11 There is I – U characteristics of depletion FETs in this figure,
UDSQ – constant quiescent voltage; N - channel
B) Consider an n-channel "enhancement-mode" device. (No conducting channel between
S and D for UGS = 0 V).A positive gate-to-source voltage is necessary to create a conductive
channel, since one does not exist naturally within the transistor. The positive voltage attracts
free-floating electron within the body towards the gate, forming conductive channel. But first
enough electrons must be attracted near the gate to counter the dopant ions added to the body
of the FET; this forms a region free of mobile carriers called a depletion region, and the
phenomenon is referred to as the threshold voltage UT of the FET. Further gate-to-source
voltage will attract even more electrons towards the gate which are able to create a conductive
channel from source S to drain D; this process is called inversion; principle - see Fig. 12, 13.
metal
G
S
D
SiO2
N+
N+
P
Fig. 12 A principle of enhancement mode device – MOSFET;
S – source; G – gait; D – drain; N – channel – no induced now
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
UDS
12
ID
UDS - UGS
UGS
S
G
D
SiO2
N+
N+
INDUCED
CHANNEL – N type
P
Fig. 13 A principle of enhancement mode device – MOSFET;
UGS >UT ; N – channel – induced now
Now is valid for the induced channel the same thing as for depletion channel - see Fig. 7 to
Fig. 11 – superpositon of influence of UGS >UT and UDS; positive voltage UDS narrows the
induced channel close the D; etc. The induced channel is “pinched off“ if UDS - UGS → 0, too.
We have no current if UGS = 0 V; thus it is no defined IDSS, see Fig. 14 to Fig. 15.
UDSP = UGS – UT
OHMIC
(LINEAR)
MODE
ID
UA – EARLY VOLTAGE
0
SATURATION MODE
(ACTIVE MODE)
UDSQ
UGS = 4 V
UGS = 3 V
UGS > UT ≈ 2 V
for example
UDS
Fig. 14 There are I – U characteristics of enhancement FETs in this figure,
UGS – parameter; N – channel induced if UGS > UT
U
– quiescent voltage; N - channel
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
13
ID
MOSFET
N-channel
induced
UDS = UDSQ
invariable
UT
0
UGS
Fig. 15 There are I – U characteristics of enhancement FETs in this figure,
UDSQ – constant quiescent voltage; N – channel – induced if UGS > UT
For either enhancement-or-depletion-mode devices, at drain-to-source voltages much less
than gate-to-source voltages, changing the gate voltage will alter the channel resistance, and
drain current will be proportional to drain voltage (referenced to source voltage). In this mode
FET operates like a variable resistor and the FET is said to be operating in a linear mode
(ohmic mode).
For reference, here is the universal FET drain-current formula (UT → UPINCH≡ UP for the
depletion type FETs):
[
2
I D = 2k (U GS − U T ) ⋅ U DS − U DS
/2
]
(11)
- it is valid in linear region.
If just U DS = U GS − U T than I D ”saturates” (pinch-off) and will be approximately constant
further – saturation mode (region):
[
]
[
]
2
I D = 2k (U GS − U T ) ⋅ U DS − U DS
/ 2 = 2k (U GS − U T ) ⋅ (U GS − U T ) − (U GS − U T ) 2 / 2
I D = k ⋅ (U GS − U T ) 2
(12)
- it is valid in saturation mode (region).
The channel-length modulation effect (as a function of drain voltage UDS) causes the
characteristics to converge at a common intersection – UA – Early voltage – see Fig. 10, 14 –
models current dependence on drain voltage – equations (11) and (12) are modified:
[
]
2
I D = 2k (U GS − U T ) ⋅ U DS − U DS
/ 2 ⋅ (1 + U DS / U A )
LINEAR REGION
(11a)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
I D = k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A )
14
(12a)
SATURATION REGION
For the depletion mode device we know that
I D (U GS = 0) = k ⋅ (0 − U P ) 2 ⋅ (1 + U DS / U A ) ≅ k ⋅ U P2 = I DSS ;
⇒ k = I DSS / U P2
Thus in the saturation mode we can rewrite equation (12a):
I D = ( I DSS / U P2 ) ⋅ (U GS − U P ) 2 ⋅ (1 + U DS / U A )
→
I D = I DSS ⋅ (1 − U GS / U P ) 2 ⋅ (1 + U DS / U A )
(12b)
SATURATION REGION –DEPLETION TYPES
Some FET symbols
Comparison of different enhancement-mode and depletion-mode MOSFET symbols, along
with JFET symbols:
P-channel
N-channel
JFET(it has
conductive channel, too)
MOSFET enhancement
MOSFET
depletion
(N)MOSFET - depletion
D
(N)MOSFET - enhancement
G
S
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
15
Example 2
A depletion type MOSFET has a UP = - 2 V, IDSS = 5 mA and UA = 120 V. Derive a quiescent
point of the FET – see Fig. 16 (ignore Early effect influence, now – UA →∞); UDD = 10 V;
Rd = 5,1kΩ; RS = 1kΩ
UDD
Rd
ID
G
UGS
D
UDS
S
RS
RG
Fig. 16 Basic autobias circuit of depletion type FETs
(JFETs); RG usually from 500 kΩ to 5 MΩ
1. We suppose that (Fig. 10)
UDS > UDSP = UGS - UP = UGS - (-2) = UGS+2V
Thus the quiescent is in the saturation region and we can use eq. (12b), UDS/UA →0:
I D = I DSS ⋅ (1 − U GS / U P ) 2 ⋅ (1 + 0) = I DSS ⋅ (1 − U GS / U P ) 2
(12c)
2. The gate voltage URG is 0 V because no significant current flows through RG. Thus it is
valid (resistor RS generates the UGS)
UGS = - RSID
3. We establish UGS = - RSID into (12c):
ID = IDSS.(1 + ID.1000/UP)2 = 5.10-3(1+ID1000/(-2))2 =
= 5.10-3.(1 -500ID)2 = 5.10-3(1 - 1000ID + 2,5.105 I 2D );
ID = 5.10-3(1 - 1000ID + 2,5.105 I 2D )
We easy get equation of the form
2,5.105 I 2D - 1200ID + 1 = 0
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
16
This has a solution ID = 1, 07 mA (and ID = 3, 73 mA). We take the only physically solution
ID = 1, 07 mA which gives UGS = - RSID = - 1000. 0, 00107 = - 1, 07 V. No physically
solution 3, 73 mA gives UGS = - 3, 73 V – thus FET is would be fully “off”.
4. We determine a voltage drain-source UDS = 10 – (5100 + 1000) .1, 07.10-3 = 3, 47 V
(Kirchhoff’s voltage law) and UDSP = -1, 07 - (-2) = 0, 93 V. It is valid
UDS = 3, 47 V > UDSP = 0,93 V.
Thus the quiescent point (1, 07 mA; 3, 47 V) is really in the saturation region as was
supposed. Assumption in design is right.
Example 3
A depletion (N) MOSFET (or JFET) in Fig. 16 has a UP = -3, 5 V, IDSS = 10 mA; UDD = 15 V.
Calculate the component values if we need quiescent point (5 mA; 5 V).
1. We first suppose that (Fig. 10) UDS > UDSP – saturation (active) function region.
Thus we can use the equation (12c) – ignored Early effect:
ID = IDSS.(1 - UGS/UP)2
2. For the given values we get from this equation
5.10-3= 10.10-3.(1- UGS/(-3,5))2
=>
1+UGS/3,5 = ±1 / 2 .
This has a solution UGS = -1,025 V (and -5,975 V). We take the only physically solution UGS
= -1,025 V (UP = -3, 5 V). No physically solution is UGS = - 5, 975 V – thus FET is would be
fully “off”.
3. It is valid UGS = - RSID (no significant current flows through RG) =>
RS = -(-1,025)/5.10-3 = 205 Ω.
4. It is valid UDD = RdID + UDS + RSID (Kirchhoff’s voltage law). Thus we can rearrange this
formula: Rd = (UDD-UDS)/ID - RS = (15 - 5)/5.10-3- 205 Ω = 1,795.103 Ω = 1,795 kΩ
5. We determine UDSP = UGS - UP = –1, 025 – (–3, 5) = 2, 475 V - the quiescent point (5 mA;
5 V) is really in the saturation region.
6. We choose RG = 1 MΩ.
Component values are: RS = 205 Ω; Rd = 1, 795 kΩ; RG = 1 MΩ
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
17
Example 4
Suppose the component values gained in the example 3 (Fig. 16; UDD = 15 V, Rd = 1,795 kΩ,
RS = 205Ω). Now we use other FET - IDSS = 12 mA, UP = - 4 V (selected at random).
Determine a new quiescent point.
1. It is valid now UGS = - 205 ID and ID = IDSS .(1 - UGS/UP)2 (Early effect is ignored).
2. We establish UGS = - RSID into ID and easy get equation of the form
I
(205 ⋅ I D ) 2 2 ⋅ 205 ⋅ I D
+
− D +1 = 0
2
UP
I DSS
UP
3. This has a solution ID = 5, 869 mA (and ID = 64, 89 mA). We take the only physically
solution ID = 5, 869 mA which gives UGS = - RSID = - 205. 0, 005869 = - 1, 20 V. No
physically solution 64, 89 mA gives UGS = - 13, 3 V – thus FET is would be fully “off”.
Example 5
An enhancement (N) MOSFET in Fig. 17 has a k = 2, 96 mA/V2, UT = 2 V, UA = 156 V.
Derive a quiescent point (ignore Early effect).
UDD = 10 V
RD
1kΩ
RG1
240kΩ
D
ID
G
RG2
150kΩ
UGSQ
RS
UG 100Ω
RZ
1kΩ
S
US
ID
Fig. 17 Basic bias circuit of enhancement type FETs
1. We suppose that (Fig. 14)
UDS > UDSP = UGS – UT = UGS - (2) = UGS- 2V
Thus the quiescent is supposed in the saturation region and we can use eq. (12a), UDS/UA →0:
I D = k ⋅ (U GS − U T ) 2 ⋅ (1 + 0) = k ⋅ (U GS − U T ) 2
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
18
2. It is valid (voltage divider, supposed zero gait current):
UG = UDDRG2/(RG1+RG2) =10.150/(240+150) = 3,846 V.
3. It is valid (Ohm’s law)
US = RSID
4. It is valid (Kirchhoff’s voltage law)
UGS = UG - RSID
5. We establish US = RSID and UGS = UG - RSID into ID and easy get equation of the form
I D = K [(U G − RS I D ) − U T ] = K [(U G − U T ) − RS I D ]
2
2
5. Rearranging this equation for given values gives us equation
I 2D 10 4 − I D .707 + 3,41 = 0
This has solutions ID = 5, 2 mA (and 65, 5 mA) - whereas the second value is not right value
(why not?).
6. Now we can calculate
UDS = UDD - ID(RD + RS) = 10 -5,2.1,1 = 10-5,72 = 4,28 V
UGS = UG - RSID = 3, 846 – 100. 5,2 . 10-3 = 3, 326 V
UDSP = UGS – UT = UGS - (2) = 3, 326 – 2 = 1, 326 V =>
UDS = 4,28 > UDSP = 1, 326 V; thus the FETs quiescent point (5, 2 mA; 4, 28 V) is
really (and correctly) in the saturation (active) region – as was supposed.
Example 6
An enhancement (N) MOSFET in Fig. 18 has a k = 0, 25 mA/V2, UT = 2, 5 V.
Derive a quiescent point (ignore Early effect).
RG (510kΩ)
UDD = 15 V
RD
(1,5 kΩ)
D
G
UDS ID
UGS
S
Fig. 18 Another bias circuit of enhancement type FETs
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
19
1. We can ignore gate current (in practice). Thus it is valid UDS = UGS, and
ID = k(UGS - UT)2 = k(UDS - UT)2 = UDS = UDD- RDID= k [(UDD- RDID) - UT]2
2. Rearranging this formula we get easy
ID2 RD2 - [2RD(UDD - UT) + 1/k]ID + (UDD - UT)2 = 0
This gives for known values
2,25.106 ID2 - 41500 ID + 156,25 = 0
This has solutions ID = 5, 27 mA (and 13, 17 mA) - whereas the second value is not right
value.
If it is ID = 5, 27 mA - UDS = UDD - RDID = 15 - 7, 905 = 7, 095 V = UGS – suitable voltage.
If it is ID = 13, 17 mA - UDS = UDD - RDID = 15 – 19, 76 = - 4, 76 V = UGS – bad voltage.
UDSP = UGS – UT = UGS - (2, 5) = 7, 095 – 2, 5 = 4, 59 V => the FET is really in the active
region.
THE FET AC MODEL – common source (in the active = saturation region)
The UGS and ID of the FET (in the saturation region) are related by the equations (12a) –
general description - and (12b) – depletion types (UT → UP and k = IDSS/(UP)2 for the
depletion type FETs):
We can easy derive now that a “GS” signal conductance is now (equivalent rearranging are
used only)
g GS = 1 / rm =
= 2 ⋅ k ⋅ (U GS − U T ) ⋅ (1 + U DS
=
[
]
δI D
δ
=
⋅ k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A ) =
δU GS δU GS
2 ⋅ k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A )
/U A ) =
=
(U GS − U T )
2⋅ ID
= OR another way = 2 ⋅
(U GS − U T )
[
[k ⋅ (U GS − U T ) ⋅ (1 + U DS / U A )]2
]
= 2 ⋅ k ⋅ k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A ) ⋅ (1 + U DS / U A ) =
= 2 ⋅ k ⋅ I D ⋅ (1 + U DS / U A ) = 2 ⋅
I DSS ⋅ I D ⋅ (1 + U DS / U A )
U P2
If we suppose (in practice rightly) that UDS/UA << 1, we get known formulas:
=
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
20
g GS = 1 / rm = 2 ⋅ k ⋅ (U GS − U T )
=
2 ⋅ ID
(U GS − U T )
(13)
= 2 ⋅ k ⋅ ID
appropriate for enhancement types
g GS = 1 / rm =
2 ⋅ ID
(U GS − U P )
= 2⋅
I DSS ⋅ I D
U P2
(14)
appropriate for depletion types
(and JFETs)
Further we derive a “DS” signal conductance (equivalent rearranging is used only):
g DS = 1 / rd =
= k ⋅ (U GS
=
[
]
δI D
δ
=
⋅ k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A ) =
δU DS δU DS
k ⋅ (U GS − U T ) 2 ⋅ (1 + U DS / U A )
− UT ) / U A =
=
(1 + U DS / U A ) ⋅ U A
2
ID
(1 + U DS / U A ) ⋅ U A
If we suppose (in practice rightly) that UDS/UA << 1 again, we get known formulas:
g DS = 1 / rd =
ID
UA
We can model these known (derived) properties (in the given quiescent point ID, UDS of
course) as shown in Fig. 19.
(15)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
external iD
iCGD
G
uGS
D
CDG
uGS/rm
0
0
INTERNAL SOURCE OF AN IDEAL FE
TRANSISTOR – ZERO VOLTAGE
BETWEEN GATE AND SI (SIGNAL MODEL)
uDS/rd
rd
SI
rm
uGS/rm
S
21
rd = 1/gDS = UA/ID - drain –source resistance
(signal); it is not a resistor planted in the
transistor; it only models the real conductance
of the device – the signal drain current changes
as a function of the signal voltages uDS
rm = 1/gGS – intrinsic (internal) source resistance
(signal); it is not a resistor planted in the transistor; it
only models the real conductance of the device – the
drain current changes as a function of the input
signal voltages uGS ; dID → iD ; dUGS → uGS – signal
changes
Fig. 19 A signal model of FET in a quiescent point ID, UDS; all voltages referred to S
Now we can easy determine signal equations of the FET – see Fig. 19:
iG = 0.uGS + 0.uDS
iD= uGS/rm + uDS/rd
⇒ yGG = 0 ; yGD= 0
⇒ yDG = 1/rm = gm ; yDD = 1/ rd = gd
If we impeach a gate-drain capacitance CDG (see Fig. 19 – green line; harmonic steady state:
p = jω; or Laplace transform), we can easy derive
ICGD = (UGS - UDS).p.CDG;
IG = 0 + ICGD = 0 + (UGS - UDS).p.CDG
IG = p.CDG. UGS - p.CDG. UDS
⇒
YGG = p.CDG;
YGD= - p.CDG
(16)
ID= UGS/rm + UDS/ rd - ICGD = UGS/rm + UDS/ rd - (UGS - UDS).p.CDG
ID= (1/ rm - p.CDG). UGS + (1/ rd + p.CDG). UDS
⇒
YDG = 1/rm - p.CDG;
YDD =1/ rd + p.CDG
(17)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
Thus the FET matrixes are:
G
D
G YGG YGC
D YDG YDD
Y- matrix model (ordinary) of the FET; common source connection
G
D
S
G
D
S
YGG
YGD
-YGG –YGD
YDG
YDD
-YDG –YDD
-YGG-YDG -YGD-YDD +Σ
Σ =YGG+YGD +YDG +YDD
22
(18)
(19)
extended Y- matrix model of the FET – derived from the common source connection
---------------------------------------------------------------Note to the FET model
A simple FET model we can get another way. Suppose that instantaneous gate – to – source
voltage is u GSI = U GSQ + u GS ; where UGSQ is the DC component and uGS is the AC component
2
(signal voltage). The instantaneous drain current is i DI ≅ k ⋅ (u GSI − U T ) .
Substituting u GSI into iDI produces
i DI ≅ k ⋅ (u GSI − U T ) 2 = k ⋅ (U GSQ + u GS − U T ) 2 = k ⋅ (U GSQ − U T + u GS ) 2 =
2
= k ⋅ (U GSQ − U T ) 2 + 2 ⋅ k ⋅ (U GSQ − U T ) ⋅ u GS + k ⋅ u GS
The first term in equation is the DC (or quiescent) drain current ID (or IDQ), the second term is
the time – varying drain current component that is linearly related to the signal u GS , and the
third term is proportional to the square of the signal voltage u GS . For a sinusoidal input signal
u GS , the squared term produces harmonics (nonlinear distortion) in the output current, thus
output voltage, too. To minimize these harmonics (distortion), we require
u GS << 2 ⋅ k ⋅ (U GSQ − U T ) ⋅ u GS
this means that the third term will be much smaller than the second term. The last equation
represents the small – signal condition that must be satisfied for linear amplifier.
2
Neglecting the u GS
term we can write
i DI ≅ k ⋅ (U GSQ − U T ) 2 + 2 ⋅ k ⋅ (U GSQ − U T ) ⋅ u GS = I DQ + i D
The total current can be separated into a DC component (IDQ) and an AC component
i D ≅ 2 ⋅ k ⋅ (U GSQ − U T ) ⋅ u GS .
The small – signal drain current is related to the small – signal gate – to – source voltage by
the transconductance
g GS = g m = 1 / rm ≅ 2 ⋅ k ⋅ (U GSQ − U T ) ;
see equations. (13) and (14), etc.
2
The term u GS
we must not neglect if we solve problems of a distortion (parasite non –
linearities) or modulation (functional non - linearities).
----------------------------------------------------------------
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
23
TRIODE – VACUUM TUBES
Basic description of triode principle
- Underlying all tube operation is the fact that any hot metal is continuously emitting electrons
(for an oxide-coated cathode under typical operating conditions, a 10% increase in
temperature increases emission by about a factor of 3; current passing through the filament
heats it).
- Electrons, being negatively charged, are attracted to the positive plate – anode.
- The number of electrons depends on the current flow - the higher the current, the greater the
number of electrons and therefore the greater the charge. Since the cathode feels the influence
of the plate through the negatively-charged electrons between them, the increasing current
reduces the attractive force of the plate until the two reach a balance. At this point of balance,
the effective field at the surface of the cathode is reduced to zero. Moving away from the
cathode, the electrons accelerate. If we have just one anode and one cathode (vacuum diode)
it is valid Child – Langmuir law
I a = k ⋅ U a3 / 2
(Ua – an anode – cathode voltage; Ia – an anode current; k – constant – dependent on the tube
construction).
- A grid of wires between the cathode and the plate (fig. 20) is negative (normally always),
which decelerates the electrons and hence controls the current to the plate – triode. Making
some simplifying assumptions, he showed that the electric field as seen at the cathode is
equivalent to a plate voltage of:
U ef = U a / µ + U g ;
µ is a constant for a given electrode geometry. In other words, the actual plate voltage is
divided by µ to get the effective voltage. For example, in a typical medium-µ triode under
normal operating conditions, the effective voltage as seen at the cathode is only around 5V,
even though the plate is at 100V or more. An idealized formula is
3/2
3/ 2
I a = k ⋅ (U a + µU g ) = k ′ ⋅ (U a / µ + U g )
(Ug – a grid – cathode voltage; µ is a constant for a given electrode geometry).
- If we add the second grid, we get tetrode (double grid tube).
- If we add the third grid, we get pentode (triple grid tube).
Fig. 20 A construction principle
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
UB
Ia
Ia
Ra
A
(a)
G
∆Ug = Ug 1 - Ug3;
UaQ = const.
Ug=0
Ug 1< 0
Ua
Ug
Ug 2<Ug1
C
Rg
Rk
∆Ia;
UaQ=
const.
Ck
Ug 3<Ug2
IaQ
∆Ug; ∆Ua
IaQ= const
Ia
Ig
A
G
Ug
24
SUg
Ri
∆Ia; ∆Ua if
Ug = const.
Ua
K
(b)
(c)
UaQ
Ua
Fig. 21 a) An triode amplifier; b) A-V characteristic; c) small - signal model
There is a basic connection of the triode amplifier in the Fig. 21a. The behavior of a triode
is fully described by its plate curves, as shown in Fig. 21b. These show the anode (plate)
current as a function of anode voltage (on the horizontal axis) and the grid voltage, becoming
more negative as we move to the right of the family of curves. The used signal model is
shown in Fig. 21c. Data sheets usually give a tube quiescent point as well as tube’s
parameters in Fig. 21c. The gate voltage URg is 0 V because no significant current flows
through Rg (if grid voltage is negative). Thus it is valid (resistor Rk generates the Ug –
compare depletion FET – N channel): Ug = - RkIa. A capacitance Ck shorts out Rk - shorts AC
signals.
Quiescent point example
Triode ECC83 (double triode) – it is indicate: UA = 250 V, Rk = 1600Ω, IA = 1, 2 mA,
S = 1, 6 mA/V, µ = 100, Ri = 62, 5 kΩ. If we require Ra = 100 kΩ for example and this
quiescent point, we can calculate a supply voltage UB = UA + (Ra + Rk).Ia =372 V.
Small - signal model (parameters) and small-signal triode model
Mutual transconductance is the slope of the transfer characteristic
gm= 1/rm = S = ∆I a
∆U g
Ua =const
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
25
It relates the mutual changes between anode current and voltage changes in grid circuit – see
Fig. 21b, too – the transfer characteristic Ia = f(Ug; Ua = UaQ = const.) we can derive, if we
need it, from Fig. 21b.
Plate (anode, internal, output) resistance represents the change in voltage associated with a
change in current in the anode circuit – see Fig. 21b, too.
Ri = 1/Gi =
∆U a
∆I a
Ug = const
Gain coefficient represents the change in voltage in the anode circuit associated with change
in voltage in the grid circuit – see Fig. 21b, too.
µ=
∆U a
∆U g
Ia = const
Barkhausen formula
It is evident that for small – signal changes is valid
S . Ri = µ
“More physical model” is in the fig. 22.
A
uAC/Ri
0
ia= iC
Ri - anode – cathode resistance (signal); it is not
CI
a resistor planted in the triode; it only models the
real conductance of the device – the signal anode
current changes as a function of the signal
voltages uAC
G
0
uGC
Ri
iC =
uGC/rm
rm =
1/S
C
INTERNAL CATHODE OF AN IDEAL TRIODE
– ZERO VOLTAGE BETWEEN GATE AND CI
(SIGNAL MODEL)
rm=1/S – intrinsic (internal) cathode resistance
(signal); it is not a resistor planted in the triode; it only
models the real conductance of the device – the anode
current changes as a function of the input signal
voltages uGC
Fig. 22 Small – signal triode model; in the appropriate quiescent point;
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
26
TRIODE ADMITTANCE MODEL
If we consider now just signal changes, thus from Fig. 21c or Fig. 22 we can easy derive
formulas (common cathode)
Ig = 0.Ug + 0.Ua
Ia = S.Ug + Gi.Ua
Thus we easy get (harmonic steady state) ordinary matrix model
G
A
G
0
S
A
0
Gi
Ug
Ua
= Ig
Ia
If we take into account a capacity anode – gate (CAG), we easy determine more complex
triode ordinary admittance matrix (compare FET matrix models)
G
G p.CAG
A S - p.CAG
A
- p.CAG
Gi + p.CAG
Ug
Ua
You can get ordinarily extended matrix.
= Ig
Ia
(20)
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
27
ADMITTANCE MODEL OF GENERAL ACTIVE THREE – TERMINAL DEVICE
(We will suppose that input current is not function of a voltage u23; i1 << i and the device
quiescent point is correct).
All was described we can generally sum into Fig. 23 and two matrices and Table 1– we
need just one general model.
C21
iC12
i2
2
u23/r21
u12/(βr)
i1 1
u12I
=0
i≈
u13/r
2I
i=
u13/re
r
u13
EXTERNAL
(SIGNAL)
VOLTAGE
r23
3
u23
2I – internal point of the ideal element
(zero voltage u12I)
i1 – input current
r – defines the i2 changes as a function
of the u13
r23– defines the i2 changes as a function
of the u23
1
2
- pC21
1 g/β + pC21
2 g - pC21
g23+ pC21
Ordinary admittance matrix – common terminal 3
1
2
3
- pC21
1 g/β + pC21
- g/β
- g – g23
2 g - pC21
g23+ pC21
- g23
3 - g/β - g
g/β + g+ g23
Extended adm. matrix – external common terminal
Fig. 23 A signal model of general active three-terminal device with capacitance C21; all
voltages referred to the terminal 3; input current is not function of a voltage;
i1 << i and the device – see Table 1
quiescent point is correct
general
bipolar
field effect transistor;
triode
tripole
transistor;
FET
device
BJT
terminal 1
≡Base
≡Gate
≡Grid
terminal 2
≡Collector
≡Drain
≡Anode
terminal 3
≡Emitter
≡Source
≡Cathode
input
i/β
iG → 0
iG → 0
current i1
it
means
it means that model β→ ∞
that model
β→ ∞
g = 1/r
ge = 1/re =
S = 1/rm =
g GS = g m = 1 / rm = 2 ⋅ k ⋅ (U GS − U T )
=IC/Uth
gm
2⋅ ID
I DSS ⋅ I D
=
= 2⋅ k ⋅ ID = = 2⋅
(U GS − U T )
U P2
r23 = 1/g23 rCE = UA/ IC
rd = UA/ ID
Ri
C21
CCB
CDG
CAG
Table 1. Sum of „all“ as mentioned above; y12 = 0 if input current is no function of u23
and parasitic capacitance is neglected. UT → UP – if depletion type
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
28
BJT versus FET
The FET transconductance is g m = 1 / rm = 2 ⋅ k ⋅ I D = 2 ⋅ I DSS ⋅ I D / U P2 . It increased only
as the square root of ID and is well below the transconductance ge = 1/re = IC/Uth of a bipolar
transistor at the same operating current. We will derive later that a low transconductance
means a low voltage gain. The problem of low voltage gain in FET amplifiers can we solve
by means a current – source (active) load, but once again the bipolar transistor will be better
in the same circuit. For this reason you seldom see FETs used as simple amplifiers, unless it is
important to take advantage of their unique input properties – extremaly high input resistance
and low input current.
AC EQUIVALENT CIRCUIT (SMALL-SIGNAL EQUIVALENT CIRCUIT)
Understanding and designing circuits can be made much easier if we can replace real
devices by simplified mathematical models of the same thing. We know signal models (and
their matrix models) of BJT, FET and TRIODE, now (“signal” active components of a
circuit). We must be able to determine a signal model of whole electronic circuit.
Capacitors
A capacitor has frequency-dependent impedance Z C = 1 /( jωC ) = − j ⋅ X C ; X C = 1 /(ωC ) .
We will ignore the phase-changing property as this is not relevant to our discussion here. As
ω = 2πf reduces to DC, then ω = 2πf = 0 and we have X C = 1 /(ωC ) → ∞ . As
ω = 2πf increases towards infinity, then we have X C = 1 /(ωC ) → 0 . This gives us two rules
for capacitors in equivalent circuits:
1. Capacitors in DC equivalent circuits (determination of a quiescent point): replace
capacitors by an open circuit.
2. Capacitors in AC equivalent circuits: replace capacitors by a short circuit.
In fact, the designer usually chooses values of C which make XC negligible at all
frequencies likely to be encountered for the amplifier. If we solve frequency properties of a
circuit, the problem is more complex – capacitors must not be neglected (parasitic frequency
properties of amplifiers, filters – functional capacitors).
Coupling capacitors (vazební)
Capacitors are used in this way to couple AC circuits together (without any steady DC bias
conditions being affected) - XC must be small compared with other resistances in the circuit –
at the minimum frequency specified for the circuit. This is an example of worst case design.
Example 7
Find a suitable input coupling capacitor for an amplifier with a frequency response of 50 Hz
to 15 kHz and RIN = 50 kΩ (Fig. 24), driven from a voltage source with ROUT = 50 kΩ.
Referring to Fig. 24, we would choose X C = 1 /(2 ⋅ π ⋅ f min ⋅ C ) = ( RIN + ROUT ) / 10 .
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
[
29
]
Therefore C = 10 /[2 ⋅ π ⋅ f min ( RIN + ROUT )] = 10 / 2 ⋅ π ⋅ 50 ⋅ (50 + 50) ⋅ 10 3 = 0,3 µF
ROUT
UOUT
C is coupling capacitor;
(any left side DC component)

RIN
UQ =
“left side”
DC component
Fig. 24 A model circuit with a coupling capacitor C
For some designs this can generate enormous C values, so designers opt for a more realistic
X C = 1 /(2 ⋅ π ⋅ f min ⋅ C ) = ( RIN + ROUT ) value.
Bypass capacitors (“přemosťovací”)
In Fig. 25 we can see the bypass capacitor C transfers AC signal directly to earth, thus
bypassing R. For AC, R is short circuited (and therefore its action is ignored), whereas for DC
R comes into play and C is considered as an open circuit.
DC
MODEL
DC
MODEL
R
R1
OR
R
R1
AC
MODEL
R
R2
R = R1//R2
AC
MODEL
R1
R2
Fig. 25 A model circuits with a bypass capacitor
Example 8
Choose a capacitor to create an AC bypass across a 1 kΩ resistance at all frequencies in the
range 25 Hz to 10 kHz.
Using X C = 1 /(2 ⋅ π ⋅ f min ⋅ C ) = R / 10 , where R = 1 kΩ and fmin = 25 Hz, we have
C = 10 / [2 ⋅ π ⋅ f min R ] = 10 /[2 ⋅ π ⋅ 25 ⋅ 1000] = 63 µF
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
30
Equivalent circuits of (power) supplies
All active circuits require some form of energy sources. Usually we do not want a power
supply the output of which varies with variation in load current drawn from it, thus we need
an ideal DC voltage (power) source – its output resistance is zero. Therefore, the rules are:
RULE 1. For power supplies (sources) in DC equivalent circuits: show all power supply
voltages and currents in full.
RULE 2. For power supplies (voltage sources) in AC equivalent circuits: replace all voltage
sources with a short circuit – see Figs. 26, 28 and 29.
If we use an ideal current source (with infinite internal resistance), another rule is valid:
RULE 3. For current sources in AC equivalent circuits: replace all current sources with an
open circuit – see Fig. 27.
UN
I1
I1
IC
RC
R1
UC
IC
RC
R1
CV2
IB
CV1
Ri
UN
IB
UCE
UCE
0, 6 V
ui
R2
(a)
UC
0, 6 V
IE
RE
UR2
RZ
R2
UE
IE
RE
UE
UR2
(b)
UN
R1
Ri
RC
CV1
ui
SIGNAL
(c)
R1
RC
ui
SIGNAL
R2
RE
CV2
Ri
R2
RE
RZ
RZ
(d)
Fig. 26 a) A basic common emitter configuration (CE) – voltage divider biasing;
b) a DC equivalent circuit – all capacitors are opened; c) AC - all capacitors
and voltage power supply source are shorted; d) an AC equivalent circuit –
ui - signal voltage we must not omit
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
UN
RI
≈1, 2 V
RD
ID
CV1
Ri
UN
≈1 mA
0, 6 V
0, 6 V
T2; β2; UAT2
IC
RB
IB
RAT2
≈ UAT2/1 mA
RF
IB
CV1
Ri
T1 UCE
UCE
0, 6 V
ui
0, 6 V
ui
(b)
T1; β1; UAT1
(a)
RAT2
≈ UAT2/1 mA
RF
31
RF
Ri
Ri
T1
RAT2
≈ UAT2/1 mA
T1
ui
(d)
ui
(c)
Fig. 27 a) A common emitter configuration (CE) – current source as collector resistor
(active): T2 (PNP), diodes, RI and RD create current source: it is evident that
voltage across resistance RI is ≈ 0, 6 V; thus I C ≈ 0,6 / RI = 1 mA if RI = 600 Ω; we
must choose ID >> IC/β2; b) a model of current source – RAT2 ≈ UAT2/IC – describes
influence of T2 Early voltage; c) AC equivalent circuit and d) the rearranged AC
equivalent circuit.
Resistance RB defines a T1 base current. It is valid I B ≈ (U CE − 0,6) / RB = I C / β 1 .
We choose (properly) U CE = U N / 2 than RB ≈ β1 ⋅ (U N / 2 − 0,6) / I C - attention, it
creates negative feedback!!
(2)
(1)
RG
D
I1
(2)
G
(1)
U1
RG1 RG2 S
RS
S
RD
(3)
RD
RZ
U2
Ui1
Fig. 28 AC equivalent circuit of the
structure in Fig. 18
Fig. 29 AC equivalent circuit of the
structure in Fig. 17
U2
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
32
Basic texts
Other text
Questions
' Answers you find in this text
1. Explain basic principle of BJT.
2. Explain basic principle of FET.
3. Explain basic principle of triode.
4. Explain relationship between ordinary and extended matrices.
5. Explain a stabilization of transistor quiescent current (basic principle).
Problems
1. Determine an admittance matrix of a BJT in Fig. 1. Suppose that Early voltage is
infinite (= neglect influence of Early voltage), neglect capacity collector – base.
2. Determine an admittance matrix of a FET in Fig. 17, neglect parasitic capacity.
3. a) Determine a quiescent point of the NJFET in Fig. 30; UP = - 5 V, IDSS = 6 mA, UA =
100 V – we demand UGSQ = - 2 V. Determine UDD and all resistances; we suppose load
resistance 10 kΩ.
b) Determine an admittance matrix of a FET, neglect parasitic capacity.
c) Draw AC equivalent circuit.
4. Suppose the component values gained in the example 3 (Fig. 16; UDD = 15 V, Rd =
1,795 kΩ, RS = 205Ω). Now we use other FET - IDSS = 8 mA, UP = - 3 V (selected at
random). Determine a new quiescent current.
UDD
IDQ
RD
RZ
UDSQ
D
G
RG
510kΩ
UGSQ
RS
IDQ
S
Fig. 30 Amplifier with RS
Punčochář, Mohylová: TELO, Chapter 2, Quiescent point of basic active tripoles
(BJT, FET, triode); their admittance models
33
Problems key
Ad 1) We know – example 1 – that IC = 0, 6 mA and β is 150. Thus
re = 1/y21 ≅ UT/IC = 26 mV/(0,6 mA) = 43 Ω
1/y11 ≅ β re = 6500 Ω.
If we neglect the Early voltage than y22 = 0; y12 = 0 – we suppose that input current is no
function of the voltage across collector and emitter.
Ad 2) We know – example 5 – that if k = 2,96 mA/V2, UT = 2 V, UA = 156 V than ID = 5,2
mA. We easy determine gm =2. K. I D = 2 ⋅
1/gd = UA/ID = 156/5,2.10-3 = 30 kΩ.
2,96 ⋅ 10 −35,2 ⋅ 10 −3 = 7,846 mS and also rd =
Ad 3 a) It is known that in a quiescent point: IDQ = IDSS(1-UGSQ/UP)2 = 6.10-3(1-(-2)/(-5))2 =
2,16 mA and RSIDQ = + 2V – from this equation we get RS = 2/(2,16 .10-3) = 926 Ω. Further
UDD = RDIDQ + UDSQ + RSIDQ . We suppose load resistance 10 kΩ. Thus we must choose RD
<< 10 kΩ - or else it will degrade voltage gain of the circuit (Thévenin´s theorem). Thus we
choose RD = 2, 2 kΩ. We determine UDSP = UGSQ - UP = - 2 - (-5) = 3 V – fig. 10. We choose
UDD = 12 V – then UDSQ = UDD - RDIDQ -RSIDQ = 12 - 2, 2 .103. 2, 16 .10-3- 2 = 5, 25 V – it is
greater value than 3 V – the transistor is in the active (saturated) region – that is right
quiescent point.
Ad 3 b) Now we can derive:
rd =1/gd = UA/IDQ = 100/(2,16 .10-3 )= 46,3 kΩ ⇒ gd = 21,6.10-6 S
gm = 2IDQ/(UGSQ - UP) = 2.2, 16.10-3/(-2-(-5)) = 1,44 mS
Ad 3 c) Equivalent AC you can see in fig. 31.
(2)
D
I1
(1) G
S
G
(3)
RG
RS
RD
RZ Fig. 31 Equivalent AC circuit
of the amplifier in the
fig. 30
Ad 4) ID = 4,125 mA – see solution in the example 4.
Recommendation
If you can solve and answer more than circa 60 % of the problems and questions, you
may continue your study.
3. 2. 2009