Design and optimization of LC oscillators
Maria del Mar Hershenson1
Ali Hajimiri
California Institue of
Stanford University
1 currently with Barcelona Design
Technology
Sunderarajan S. Mohan1 , Stephen P. Boyd, Thomas H. Lee
Stanford University
Abstract
Vdd
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program,
a special type of optimization problem for which very efficient
global optimization methods have recently been developed. The
synthesis method is therefore fast, and determines the globally
optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible),
and infeasible specifications are unambiguously detected. We
can rapidly compute globally optimal trade-off curves between
competing objectives such as phase noise and power.
1
MP1
MP2
L
Cvar
Cload
L
Vcontrol
Cvar
MN1
MN2
Cload
Introduction
LC oscillators are commonly used in CMOS radio-frequency integrated circuits (RF-ICs) because of their good phase noise characteristics and their ease of implementation [1, 2, 3, 4, 5]. However,
no systematic design methodology exists to account for the many
specifications (phase noise, power dissipation, voltage swing, tuning range . . . ). Typical design strategies have tried to achieve a low
phase noise by using the largest possible inductance value [3], or by
using inductors with the lowest possible series resistance [4]. However, an optimal design requires the simultaneous consideration of
both active and passive devices.
In this paper, we propose a new method for the design of LC
oscillators. We illustrate our technique for the specific architecture
of Figure 1. The method is easily extensible to other LC oscillator
architectures. We formulate the design problem as a special type
of optimization problem, called geometric programming (GP). We
provide an overview GP in §2 and then outline the design variables in §3. In §4, we obtain the equivalent circuit model for the
LC oscillator using the inductor model presented in [6] and simple
transistor models. In §5, we use these models and the phase noise
model of [5] to show how the design specifications can be posed in
a way suitable for geometric programming.
This geometric program formulation allows us to obtain globally optimal designs very efficiently, thereby permitting the designer to spend more time exploring design trade-offs rather than
sizing inductors and devices. We illustrate our method with design
examples in §6 and optimal performance tradeoff curves in §7.
Ibias
Figure 1: Complementary LC oscillator.
2
Geometric Programming
Let f be a real-valued function of n real, positive variables x1 , . . . , xn .
It is called a posynomial function if it has the form
f (x1 , . . . , xn ) =
t
X
1k α2k
nk
ck xα
x2 · · · xα
,
n
1
k=1
where cj ≥ 0 and αij ∈ R. When t = 1, f is called a monomial
function. A geometric program (see [7]) has the form
minimize f0 (x)
subject to fi (x) ≤ 1, i = 1, 2, . . . , m,
gi (x) = 1, i = 1, 2, . . . , p,
xi > 0, i = 1, 2, . . . , n,
(1)
where fi are posynomial functions and gi are monomial functions.
The most important feature of geometric programs is that they
can be globally solved with great efficiency, with no initial point
needed, using newly developed interior-point methods [8, 9, 10].
To carry out the designs described in this paper we implemented
in MATLAB a very simple (primal barrier) method for solving the
convex form of a GP [10]. Despite the simplicity of the method,
and the inefficiency of our implementation, all the design problems
in this paper were solved under one second on a personal computer.
3
Design variables
To design the oscillator we specify the following twelve variables:
• Spiral inductor: number of turns n, turn width w, turn spacing s and outer diameter dout .
0-7803-5832-X /99/$10.00 ©1999 IEEE.
• Transistors: width (Wn and Wp ) and length (Ln and Lp ).
• Varactor: maximum value Cv,max and minimum value Cv,min .
g
• Transconductance m : A simple model for the transconductance of short-channel devices is [16],
gm = µCox W Esat /2,
• Load capacitance: Cload .
• Bias current: Ibias . Since the thermal noise of the tail current
source in the vicinity of the frequency of oscillation does not
affect the phase noise of the oscillator due to its differential
operation [5], we use Ibias as a design parameter rather than
the bias transistor dimensions.
4
4.1
Model for the LC oscillator
Inductor model
In this paper, we consider planar spiral inductors. One can easily
extend the method to other inductors such as bond wires [1], autotransformers [3] and non-standard spiral inductors [2].
A spiral inductor is characterized by the number of turns n, the
turn width w, the turn spacing s, and the outer diameter dout . The
inductor can be implemented with or without a patterned ground
shield (PGS) [11] (a grounded polysilicon shield broken regularly
in the direction perpendicular to the inductor current flow).
Figure 2 shows a commonly used circuit model for the inductor
(with or without PGS) (see [6]). This model is accurate for lightly
doped substrates as long as the assumption of a lumped model is
valid. In [12], it is shown that the inductor circuit element values
are posynomial functions of the design variables (n, dout , w and
s). The inductance L can be modeled by a monomial function of
the design variables with typical errors of only 3% (see [13]).
where µ is the mobility of the carriers in the channel, Cox is
the oxide capacitance, W is the transistor width, and Esat is
the field at which the carrier velocity reaches half its saturation velocity.
g
• Output conductance d : We use a simple monomial model
for the short-channel transistor output conductance that was
used in [15],
(3)
gd = λI 0.6 L−1 W 0.4 ,
where λ is a fitting parameter, I is the transistor drain current
and L is the transistor channel length.
• Capacitances: We model the gate-to-drain (Cgd ), the drainto-bulk (Cdb ) and the gate-to-source (Cgs ) capacitances with
posynomial expressions in the transistor width and length
(see [16, 15]).
4.4
Tank model
−gm,p
Cdb,p
+Cgs,p
Cs
L
Rs
2
4Cgd,p
CL
CL
Rp
Rp
Rs
Rs
Cv
Cload
−gm,p
4Cgd,p
L
1
Rv
Cp
Rp
Figure 2: Simplified inductor model.
Varactor model
There are several varactor options for frequency tuning [14] such
as junction diodes, MOS capacitors and accumulation mode capacitors. In this paper, we use a generic varactor model although models specific to a particular implementation can also be used. The
varactor capacitance ranges from some minimum value Cv,min to
some maximum value Cv,max . The ratio Cv,max /Cv,min is limited
due to physical limitations of the varactor. The varactor quality factor Qv depends on the frequency of operation. For simplicity, we
assume a constant quality factor value equal to its minimum value
across the tuning range. We model the varactor as an ideal capacitor in series with a resistor Rv = Qv / (Cv ω). We will see that this
simplification is not critical since the varactor contributes little to
the total oscillator phase noise (see §6).
4.3
Cv
Cload
4Cgd,n
Cp
−gm,n
Cdb,n
+Cgs,n
4.2
Cdb,p
+Cgs,p
L
Rv
4Cgd,n
Rp
(2)
Transistor model
We now describe an analytical model for short-channel devices.
More accurate models for transistors that are still compatible for
geometric programming are available [15].
−gm,n
Cdb,n
+Cgs,n
Figure 3: Complementary LC oscillator.
We model the tank with the equivalent small signal differential mode circuit shown in Figure 3, where the dashed lined is an
effective AC ground for differential operation. We now define:
• Tank inductance (
L
tank )is
given by the monomial,
Ltank = 2L.
• Tank capacitance (
Ctank =
C
tank )is
(4)
given by,
1
(4Cgd,n + Cgs,n + Cdb,n + 4Cgd,p
2
+Cgs,p + Cdb,p + CL + Cv ),
(5)
which is a posynomial function of the design variables since
it is a sum of posynomial functions.
• Tank load conductance (
g
tank )
is given by,
gtank = (gd,n + gd,p + gv + gL ) /2,
(6)
where gv , the effective parallel varactor conductance, and
gL , the effective parallel inductor conductance, are given by
the posynomial expressions (see [12]),
gv =
Cvar ω
,
Qv
gL =
1
1
+
.
Rp
(Lω)2 /Rs
Since gd,n and gd,p are also given by posynomial functions
of the design variables, expression (6) for gtank is a posynomial function of the design variables.
Transistor channel thermal noise. In [5], it is shown
that the total differential thermal current noise density due to
the active devices is given by the posynomial expression,
g
• Tank effective negative conductance ( neg;tank ) is determined by the transconductance of the cross-coupled transistor pairs. To improve the 1/f 3 corner of the phase noise it is
convenient to have a symmetric tank (gm,n = gm,p ) [5]. For
symmetric tanks, gneg,tank is given by the monomial expression,
gneg,tank = −(gm,n + gm,p )/2 = −gm,n .
5
i2M,dT
1
=
∆f
2
We now show that the design specifications for the LC oscillator
can be expressed as either monomial equality constraints, or posynomial inequality constraints, and therefore can be handled by GP.
Quiescent power
i2M,d
∆f
(8)
i2M,gT
1
=
∆f
2
The amplitude of the differential voltage across the tank is determined by whether the oscillator is operating in current limited
mode or in voltage limited mode. It can be expressed as,
Vamp = min{Ibias /gtank , Vdd }.
Vamp,min ≤ Ibias Rtank .
i2
M,dp
∆f
i2
M,gp
∆f
MP1
Rp
In the 1/f 2 region of the phase noise spectrum, the single sideband
phase noise at an offset frequency (foff ) is given by [5]
L(foff ) =
L
P
·
i2n /∆f
2
qmax
,
i2M,gn
i2M,gp
+
∆f
∆f
!
,
(15)
(16)
Vdd
Phase noise model
Γ2rms
2
8π 2 foff
(14)
where the parameter δ takes a value close to twice γ (see [16])
and Cgs is the gate to source capacitance. Since Cgs is given
by a posynomial expression, equation (16) is also posynomial.
(9)
(10)
4kT γIbias
,
Esat L
=
2
i2M,g
4kT δω 2 Cgs
Esat L
=
,
∆f
5Ibias
We can impose a minimum swing (Vamp ≥ Vamp,min ) with the two
monomial constraints,
Vamp,min ≤ Vdd
(13)
where for short-channel devices,
Since equation (8) is monomial, we can bound the maximum quiescent power with a monomial constraint (P ≤ Pmax ).
Differential voltage amplitude
,
where k is Boltzman constant, T is the temperature in Kelvin
and γ ≈ 2 for short channel transistors. This simple model
agrees well with measurements [5].
Transistor gate noise. Since the gate noise sources are
in parallel with the drain noise sources, they add in the same
way [5]. Therefore, the total differential transistor gate current noise density is given by the posynomial expression,
The quiescent power is given by the product of the supply voltage
Vdd and the bias current Ibias ,
P = Ibias Vdd .
!
where for short-channel devices,
(7)
Design specifications
i2M,dn
i2M,dp
+
∆f
∆f
Rs
i2
M,gp
∆f
v2
Rp
∆f
v2
Rp
∆f
Rp
v2
Rs
∆f
v2
Rs
∆f
Rs
MP2
i2
M,dp
∆f
MN2
i2
M,dn
∆f
L
(11)
Cv Rv
v2
Cv
∆f
v2
Cv
∆f
Rv Cv
where
• Γrms ≈ 1/2 for differential noise sources.
• qmax is the total charge swing of the tank and is given by the
monomial expression,
qmax = Ctank Vamp =
•
Vsw
.
2
Ltank ωres
i2
M,dn
∆f
MN1
i2
M,gn
∆f
Ibias
(12)
P
i2n /∆f is the sum of the current noise densities of the differential equivalent of individual noise sources: the transistor
channel thermal noise (i2M,dT /∆f ), the transistor gate noise
(i2M,gT /∆f ), the inductor thermal noise (i2RL /∆f ) and the
varactor thermal noise (i2CV /∆f ), as depicted in Figure 4.
i2
M,gn
∆f
Figure 4: Noise sources in the LC oscillator.
Inductor noise. There are two noise sources from the inductors: the ohmic losses in the winding and the losses in the
substrate,
i2RL
4kT
≈ 8kT
=2·
∆f
RL,p
1
1
+
.
Rp
(Lω)2 /Rs
(17)
Since Rp , L and Rs are given by monomial expressions
(see [12]), equation (17) is a posynomial function of the design variables.
Varactor noise. The varactor noise can be modeled with
the monomial expression,
i2CV
4kT
8kT Cv ω
=2·
≈
,
∆f
Rv,p
Qv
(18)
where Rv,p is the equivalent varactor parallel resistance.
Since Γrms is a constant, qmax is monomial in the design
variables and the noise sources i2n /∆f are posynomial in
the design variables, expression (11) is a posynomial equation of the design variables. Therefore, we can minimize the
phase noise at a given frequency. To guarantee a minimum
phase noise over the entire tuning range, we can impose the
constraint (L(foff ) ≤ Lmax (foff )) over several frequencies
within the tuning range.
Resonance frequency
We can impose a constraint on the maximum resonance frequency
ωres,max . This constraint together with a constraint on the tuning
range is equivalent to specifying a center resonance frequency. The
maximum tank resonance frequency is given by the posynomial
expression:
ωres,max =
1
.
Ltank Ctank,min
(19)
We can therefore impose a minimum required ωres,max with the
posynomial constraint ωres,max ≥ ωres,max,req . This constraint
is always active (i.e., it is practically an equality). If it were not
active the inductor could contribute additional capacitance to the
tank, which would translate into a higher QL .
Tuning range
The tuning range is specified with two constraints
Ltank Ctank,min
Ltank Ctank,max
2
≤ 1/ωmax
≥
2
1/ωmin
.
(20)
(21)
Constraint (21) is not posynomial and cannot be handled directly by GP. Since constraint (20) is always tight at the optimum,
we can handle constraint (21) indirectly. We rewrite constraint (21)
as,
2
2
Ctank,max ≥ ωmax
Ctank,min .
ωmin
2
2
Now we let r = ωres,max
/ωres,min
, and obtain
(r − 1)
Ctank,min
Cv,min
+r
≤ 1.
Cv,max
Cv,max
(22)
Thus, we can substitute (21) by the posynomial constraint (22).
Inductor constraints
It is shown in [12] that many inductor specifications have the form
of posynomial inequalities. For example, specifications on minimum and maximum inductance, on maximum area, on minimum
turn spacing and width are monomial while specifications on minimum quality factor and minimum self-resonance frequency are
posynomial.
Geometry constraints
We can require that the width and length of the devices be constrained within some range using monomial constraints,
Wmin ≤ W ≤ Wmax
Lmin ≤ L ≤ Lmax .
(23)
We can also limit the inductor area by imposing the monomial constraint d2out ≤ Amax .
Loop gain
For a complementary LC oscillator, the loop gain condition is
(gm,n + gm,p ) /2 ≥ αg gtank ,
where αg is the excess gain and it is typically ≈ 2 − 3. Since we
have gm,n = gm,p the loop gain condition is given by a posynomial
constraint,
gm,n ≥ αg gtank .
Varactor tuning range
Although the absolute value of the varactor capacitance is typically
not limited, the maximum tuning ratio βv = Cv,max /Cv,min is
limited. We impose a maximum βv with the monomial constraint
Cv,max ≤ βv Cv,min .
6
Design examples
In this section, we show two oscillator designs. The LC oscillators
are designed in a standard 0.35µm five metal layer 2.5V CMOS
process.
Constraint
Phase Noise 600kHz
ωres
Cload
Itail
Vsw
Tuning range
dout
Excess loop gain αg
Specification
minimize
1.8GHz
≥ 0.2nF
≤ 5mA
≥ 2V
≥ 10%
≤ 300µm
≥3
Achieved
−124.2dBc/Hz
1.8GHz
0.83nF
5mA
2.5V
10%
300µm
3
Table 1: Specifications for example 1.
The objective in the first example is to minimize phase noise in
an LC oscillator built using spiral inductors with PGS. The desired
and achieved specifications are shown in Table 1. We note that
many of the constraints are tight, i.e., power, voltage swing, tuning
range and area are all set to the limit specified. Table 2 shows the
optimal oscillator design obtained. It is important to note that significant phase noise is contributed by both the transistors (≈ 52%)
and the inductors (≈ 44%). This shows that a design solely based
on maximizing the inductor or its quality factor will not be optimum.
In the second design example we limit Ibias to only 1.6mA.
Table 3 shows the desired and achieved specifications. The differential swing voltage constraint is now tight. In table 4 we show the
optimal design for the second example. The phase noise is around
7dB worse than in the first example and the relative contributions
from the inductor and the transistors are ≈ 50% and ≈ 46%, respectively.
This result is consistent with our intuition: increasing Ibias results in significant improvements in phase noise only if the oscillator operates in current limited mode. We cannot achieve a significant increase in the charge swing, qmax , in the voltage limited
mode. Therefore, if the available power is low, it is necessary to to
operate in deep current limited regime. This corresponds to smaller
average transistor currents which results in smaller noise current
density. Optimization of the inductor Q is more helpful in this
case.
Inductor
3.9nH
4
300µm
23.2µm
1.8µm
6.5Ω
0.3pF
332Ω
Varactor
Cv,max 0.81pF
Cv,min
0.41pF
Rv,p
4.2kΩ
Transistors
17.0/0.35µm
52.7/0.35µm
0.07pF
0.21pF
2mS
5.5kΩ
1.7kΩ
Tank
Rtank
500Ω
Ctank
1.1pF − 0.9pF
qmax
2.3pC
i2M,d /∆f 117.7pA2 /Hz
L
n
dout
w
s
Rs
CL
RL,p
Wn /Ln
Wp /Lp
CNMOS
CPMOS
gm
1/gds,n
1/gds,p
i2RL /∆f
i2CV /∆f
99.2pA2 /Hz
7.9pA2 /Hz
Table 2: Oscillator design for example 1.
Constraint
Phase Noise 600kHz
ωres
Cload
Itail
Vsw
Tuning range
dout
Excess loop gain αg
Specification
minimize
1.8GHz
≥ 0.2nF
≤ 1.6mA
≥ 2V
≥ 10%
≤ 300µm
≥3
Achieved
−118.5dBc/Hz
1.8GHz
0.2nF
1.6mA
2V
10%
300µm
3
Inductor
10.0nH
6
300µm
13.0µm
1.8µm
17.4Ω
0.24pF
804Ω
Varactor
Cv,max 0.32pF
Cv,min
0.16pF
Rv,p
10.7kΩ
Transistors
6.8/0.35µm
21.0/0.35µm
0.03pF
0.08pF
2.4mS
15.8kΩ
5.0kΩ
Tank
Rtank
1250Ω
Ctank
0.43pF − 0.36pF
qmax
0.71pC
i2M,d /∆f 38.0pA2 /Hz
Wn /Ln
Wp /Lp
CNMOS
CPMOS
gm
1/gds,n
1/gds,p
i2RL /∆f
i2CV /∆f
41.0pA2 /Hz
3.1pA2 /Hz
Table 4: Oscillator design for example 2.
−121
Phase noise (dBc/Hz)
In this paper, we have shown how a commonly used LC oscillator
can be optimized rapidly and globally by posing the design problem
as a geometric program. This formulation permits the designer to
quickly explore globally optimal tradeoff curves between different
specifications. The method allows the simultaneous optimization
of all passive and active components.
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−124
−125
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Figure 5: Minimum phase noise versus power limit for different tuning ranges.
7
Conclusions
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Table 3: Specifications for example 2.
L
n
dout
w
s
Rs
CL
RL,p
mal trade-off curves for the LC oscillator. In Figure 5 we show the
trade-off curves of the minimum achievable phase noise versus quiescent power for different three tuning ranges. The rest of the specs
are set to the values in table 2. As an RF designer might suspect, the
phase noise decreases with higher power and smaller tuning range.
What is difficult to know, without using the tool described in this
paper, is exactly how these parameters trade off.
Trade-off curves
By repeatedly solving optimal design problems as we sweep over
values of some of the specifications, we can obtain globally opti-
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accurate expressions for planar spiral inductances. IEEE Journal of
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