EE134
Digital Integrated Circuit (IC) Layout and
Design - Week 3, Lecture 5
! http://www.ee.ucr.edu/~rlake/EE134.html
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Reading and Prelab
" Week
1 - Read Chapter 1 of text.
" Week 2 - Read Chapter 2 of text.
" Week 3 - Read Chapter 3 of text.
" Prelab - Lab 1.
! Read insert A of text, pp. 67 - 71.
! The lab will make more sense if you read this
before lab.
! There is nothing to turn in.
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Agenda
" Last
!
!
!
!
!
Lecture
Design rules
Layout and Design
Ties to VDD and GND
Padframes
Pin Packages
" Today’s
!
!
!
!
Lecture
Contacts
Basic MOS transistor operation
Large-signal MOS model for manual analysis
The CMOS inverter
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Course Emphasis / Design Styles
" Physical
design of CMOS digital ICs
" Application Specific IC (ASIC)
! Full Custom (What we are doing)
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– Most flexible approach
– Higher speed
– Smaller designs
– Expensive
– Requires device-level (i.e. transistor level) knowledge
– Push limits of a technology - must understand
parasitics: stray C, L, pn jns., BJTs, breakdown,
stored charge, latch-up, etc.
– Used for high-volume chips - µ−processors &
memory
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Design Styles (cont.)
" ASIC
(cont.)
! Standard Cell
– Logic gate level
– Low volume
– Quick turnaround
– Lower density
! Gate Array (FPGA)
– Lowest density - speed - cost.
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Define circuit specs
Flowchart
Circuit Schematic
Circuit Simulation
Meet Specs?
No
Layout
Parasitic Extraction (R,C)
Re-simulate with Parasitics
No
Meet Specs?
Prototype Fabrication
Test and Evaluate
No
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Meet Specs?
Yes
Production
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Tie n-well to VDD and Substrate to
Ground
In
GND
VD D
A
A’
Out
(a) Layout
V
VDD
A
A’
n
p-substrate
p+
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n+
n+
p+
n+
Field
Oxide
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Reason for GND and VDD Ties
Parasitic Diodes
Vout
p+
n
p-substrate
n+
VDD
n+
p+
n+
p-substrate
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Contacts to Silicon
" Ohmic
Contacts
! Metal on highly doped n+ or p+ Si.
! What you want to pin the substrate to ground or
the n-well to VDD.
" Schottky
Contacts (we won’t use these)
! Metal on lightly doped n or p Si.
! Creates a Schottky diode which has an I-V curve
similar to a p-n junction diode.
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Ohmic contact
" Metal
on n+ or p+ Si.
" Simple picture:
" Need
heavy doping to get the ultra short
screening length needed for an OHMIC
contact.
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Schottky Contact
" Metal
on n or p Si.
" Simple picture:
" Light
n or p doping gives long screening
length giving Schottky Barrier.
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Ohmic Contacts for Voltage Pinning
" Ohmic
" You
contact to the n-well
need the
! Active and Select to
define the n+
region.
! Contact to put hole
in thick passivation
oxide / nitride so
that the metal
contacts the Si.
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Ohmic Contacts for Voltage Pinning
" Ohmic
" You
contact to the p-substrate
need the
! Active and Select to define
the p+ region.
! Contact to put hole in
thick passivation oxide /
nitride so that the metal
contacts the Si.
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Pin n-well to VDD and p-substrate to GND
n+
VDD
M1
p+
PMOS
p+
NMOS
n+
n+
p+
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Power
Bus
n-well
M1
Ground
Bus
GND
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The Active Layer
" Cut
in the Field Oxide (FOX) to get down to
the Si.
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Active and Select Layers
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Active and Select Layers (cont)
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4 Concepts to Remember:
" Need
to put down an n+ region on the n-well
to make an ohmic contact to the n-well.
" Need
to put down a p+ region on the psubstrate to make an ohmic contact to the
p-substrate.
" These
are your active / select layers.
" Finally,
you need a contact layer to drill
through the thick oxide / nitride passivation.
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BAD MOS Layout
" DO
NOT DO THIS!!!!!!!
poly-gate
active - hole cut in FOX
n+ select
• Self-aligned process
• The Poly gate serves as an implant mask during the n+
implant.
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There is no gap between the source/gate and drain/gate.
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Outline
" MOS
Ch. 3
Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
" CMOS
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Inverter
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What is a Transistor?
An MOS Transistor
VGS
A Switch!
VGS ≥ VT
G
S
Ron
D
S
D
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Switch Model of CMOS Transistor
VGS
S
G
D
Ron
S
D
|VGS| < |VT|
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S
D
|VGS| > |VT|
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Transistor Circuit Symbols
" NMOS
We always want
Drain
D
Body (p-Si substrate)
Gate
B
G
Source
S
D
D
B=S
G
G
#
Body tied to Source
S
S
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NMOS Body Terminal (B)
• A transistor is a 4
terminal device.
n+
VDD
M1
p+
Circuit
Schematic
D
PMOS
Layout
B = S = GND
S
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n-well
D
NMOS
G
p+
S
B
n+
n+
p+
M1
GND
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Transistor Circuit Symbols
We always want
" PMOS
Source
Body (n-well)
Gate
B
G
Drain
D
S
S
G
VDD
S
B=S
G
#
Body tied to Source
D
D
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PMOS Body Terminal (B)
S = VDD
G
n+
M1
p+
B = S = VDD
PMOS
D
Layout
p+
n-well
D
NMOS
S
B
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VDD
n+
n+
p+
M1
GND
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NMOS and PMOS
" PMOS
is complementary to NMOS
" Turn it upside down and switch all signs of
voltages, VSD # VDS, VGS # VSG.
NMOS
PMOS
D
+
>0 S
+ G
VGS > 0
- S
VSG
- G
D
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Outline
" MOS
Ch. 3
Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
" CMOS
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Inverter
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Threshold Voltage: Concept
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The Threshold Voltage
Fermi Potential
⎛ NA
⎝ ni
φF = - φT ln⎜⎜
φT =
⎞
⎟⎟
⎠
kBT
q
2φF ≈ -0.6V for p-type substrates
γ is the body factor
VT0 = 0.76 V (NMOS)
0.95 V (PMOS)
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AMI C5 process
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The Body Effect
0.9
VT(V)
0.8
0.7
0.6
reverse body bias
0.5
0.4
-2.5
VTO
-2
-1.5
-1.0
-0.5
0
VSB
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The Drain Current
" Charge
in the channel is controlled by the
gate voltage:
Qi ( x ) = −Cox [VGS − V ( x ) − VT ]
Cox =
ε ox
tox
" Drain
current is proportional to charge x
velocity:
ID = −v n ( x ) ⋅ Qi ( x ) ⋅ W
v n ( x ) = − µn ⋅ ξ ( x ) = µn
dV
dx
vn = velocity; W = channel width; ξ = electric field; µn = mobility
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The Drain Current
" Combining
velocity and charge:
I D ⋅ dx = µn ⋅ Cox ⋅ W ⋅ (VGS − V − VT ) ⋅ dV
" Integrating
along the length of the channel
from source to drain:
LG
VDS
0
0
∫ ID ⋅ dx = ∫ µn ⋅ Cox ⋅ W ⋅ (VGS − V − VT ) ⋅ dV
I D = µn ⋅ Cox ⋅
k n′ = µn ⋅ Cox
⎡
V2 ⎤
⋅ ⎢(VGS − VT ) ⋅ VDS − DS ⎥
2 ⎦
⎣
µ ⋅ε
= n ox
t ox
W
L
S
VGS
VDS
G
n+
–
V(x)
n+
+
L
x
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Outline
" MOS
ID
D
Ch. 3
Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
" CMOS
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Inverter
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Transistor in Linear Mode
VGS > VDS + VT
Device turned on (VGS > VT)
VDS < VGS - VT
VGS
S
VDS
G
n+
– V(x)
ID
D
n+
+
x
L
p-substrate
B
I D = µn ⋅ Cox ⋅
W
L
⎡
V2 ⎤
⋅ ⎢(VGS − VT ) ⋅ VDS − DS ⎥
2 ⎦
⎣
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Transistor in Saturation
VT < VGS < VDS + VT
VDS > VGS - VT
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
2 ⎤
VDS
W ⎡
(
)
I D = µn ⋅ Cox ⋅ ⋅ ⎢ VGS − VT ⋅ VDS −
⎥
2 ⎦
L ⎣
ID =
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µn ⋅ Cox W
2
⋅
L
+
n+
Pinch-off
⋅ (VGS − VT )2
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Saturation
" For
VDS > VGS - VT, the drain current
saturates:
-4
6x 10
5
2
⋅
L
4
⋅ (VGS − VT )
ID(A)
ID =
µn ⋅ Cox W
2
3
2
1
00
" Including
ID =
2
1
1.5
VDS(V)
2
2.5
channel-length modulation:
µn ⋅ Cox W
⋅
0.5
L
⋅ (VGS − VT )2 ⋅ (1 + λVDS )
slope = λ VDS
= VDS/VA
VA = 1/λ = Early voltage
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Modes of Operation
" Cutoff:
ID = 0
VGS < VT
" Resistive
or Linear:
VDS < VGS - VT &
VGS > VT
I D = µn ⋅ Cox ⋅
W
L
⎡
V2 ⎤
⋅ ⎢(VGS − VT ) ⋅ VDS − DS ⎥
2 ⎦
⎣
" Saturation
VDS > VGS - VT
VGS > VT
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ID =
µn ⋅ Cox W
2
⋅
L
⋅ (VGS − VT )2
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Current-Voltage Relations
A good ol’ Transistor
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VDS = VGS - VT
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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A model for manual analysis
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Outline
" MOS
Ch. 3
Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
" CMOS
Inverter
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Current-Voltage Relations
The Deep-Submicron Era
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
1
0.5
0
Linear
Relationship
VGS= 1.5 V
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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υ n (m/s)
Velocity Saturation
υsat = 105
Constant velocity
Constant mobility (slope = µ)
ξc = 1.5
ξ (V/µm)
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Velocity Saturation
ID
Long-channel device
VGS = VDD
Short-channel device
Saturates sooner
V DSAT
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VGS - V T
VDS
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ID versus VGS
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ID versus VDS
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Including Velocity Saturation
µn chosen empirically
so that µ ξ
n c
= v sat
2
# µn depends on the
SPICE model.
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Simple Cheesy Derivation for Velocity
Saturation and Linear Dependence on
VGS
dV
′
ID = W µn
Cox (VGS − VTH − V ( x ))
1444424444
3
12dx
3 ρ (charge density)
velocity
2D
I D = W v ρ 2D
By definition,
ID = W
µn ≡
v
ξ
=
v
dV dx
v sat dV
C ′ (V − VTH − VDS,sat )
dV dx dx ox GS
′ (VGS − VTH − VDS,sat )
I D = W v sat Cox
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ID versus VDS
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Regions of Operation
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A Unified Model for Manual Analysis
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Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
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A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
VGS = -2.0V
-0.6
-0.8
Assume all variables
negative!
VGS = -2.5V
-1
-2.5
-2
-1.5
-1
-0.5
0
VDS (V)
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Sub-Threshold Conduction
(Cut-off)
The Slope Factor
VDS = VDD
ID ~
-2
10
Linear
qVGS
I 0e nkT
, n = 1+
CD
Cox
-4
10
S is ∆VGS for ID2/ID1 =10
-6
Quadratic
ID (A)
10
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
Typical values for S:
60 .. 100 mV/decade
1
1.5
VGS (V)
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2
2.5
S = inverse subtheshold slope
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Subthreshold
" Inverse
sub-threshold slope (S)
! Ideal value @ T=300K, n=1,
S=
k BT
mV
ln(10 ) = 60
q
decade
! For each 60 mV of VGS, the current drops by a
factor of 10. This is the best that you can do.
! For VDD = 0.4V, the maximum on-off current ratio
that you can have at T=300K is
! At 373K, the ratio is
400
10 60
= 4.6 × 106
400
10 74
= 2.3 × 105
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Subthreshold
" Current
in subthreshold
I D = IS e
" Inverse
VGS ⎛
nkBT / q ⎜
⎜⎜ 1 − e
⎝
VDS
k BT / q
⎞
⎟
⎟⎟(1 + λVDS )
⎠
subthreshold slope definition
⎛ d (log10 I DS ) ⎞
⎟⎟
S ≡ ⎜⎜
dVGS
⎝
⎠
nk T
S = B ln 10
q
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−
−1
⎛ 1
1 dIDS ⎞
⎟⎟
= ⎜⎜
⎝ ln 10 IDS dVGS ⎠
−1
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Subthreshold Concepts
" FETs
turn off exponentially.
" Inverse
subthreshold slope, S (mV/dec), is
the figure of merit that tells how well they
shut off. S = nkBT ln(10 ) = ⎧ 60 mV/dec @ 27o C
q
{ ⎨
n =1⎩74 mV/dec
@ 100 o C
n ≥ 1 and typically ≈ 1.5
" The
maximum possible on-off current ratio
is
Ion
|max = 10VDD
Ioff
S
" 2018
ITRS node has VDD = 0.4V - hence the
static power problem.
Know this if you are in an interview with a semiconductor co.
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Transistor Model
for Manual Analysis
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