4. Combinational CMOS Logic Circuits
Combinational logic or gates, which perform Boolean operations on multiple input
variables and determine the outputs as Boolean functions of the inputs are the basic
building blocks of all digital systems. This chapter will examine the static and dynamic
characteristics of CMOS logic circuits.
CMOS Logic Circuits
This section examines a CMOS two input NOR gate, a CMOS two input NAND gate and
then extends the discussion to arbitrary function CMOS gates.
CMOS NOR2 (Two-input NOR) Gate
Fig. 4.1 shows the circuit diagram of a two-input CMOS NOR gate. When either one or
both inputs are high, the nMOS transistor(s) creates a conducting path between the output
node and ground, and the pMOS transistors are cut-off. When both input voltages are
low, the nMOS transistors are cut-off and the pMOS transistors create a conducting path
between the output node and the supply voltage V DD .
The output voltage of a CMOS NOR2 gate will attain a logic-low voltage of VOL  0
and a logic-high voltage of VOH  V DD . For circuit design purposes, the switching
threshold voltage Vth of a CMOS gate emerges as an important design criterion. This
section derives Vth , for a two-input CMOS NOR gate.
Figure 4.1 A CMOS two-input NOR gate and its complementary operation
Assuming that both input voltages switch simultaneously, i.e. V A  V B ; the device sizes
in each block are identical, (W / L) n, A  (W / L) n, B and (W / L) p, A  (W / L) p, B ; and the
substrate-bias effects for the pMOS transistor (M4) is neglected for simplicity. By
definition, the output voltage is equal to the input voltage at the switching threshold
V A  V B  Vout  Vth
(4.1)
The two parallel nMOS transistors are saturated at this point, since VGS  V DS . The
combined drain current of the two nMOS transistors is
I D  K n (Vth  VT , n ) 2
(4.2)
Thus the first equation for the switching threshold Vth is
V th  VT , n 
ID
(4.3)
Kn
Examining the pMOS transistors of Fig. 4.1 shows that M3 operates in the linear region,
while M4 operates in the saturation region when (4.1) occurs. Thus
I D3 
Kp
2
ID4 
2(V
Kp
2
DD
2
 Vth  | VT , p |)V SD 3  V SD
3
VDD  Vth  | VT , p | V SD3 2

(4.4)
(4.5)
Note the drain current of both pMOS transistors are identical (i.e. I D3  I D 4  I D ), thus
combining (4.4) and (4.5), yields
V DD  Vth  | VT , p | 2
ID
Kp
(4.6)
Combining (4.3) and (4.6), yields
VT , n 
V th ( NOR) 
1
2
Kp
Kn
1
1
2
(V DD  | VT , p |)
Kp
(4.7)
Kn
The threshold voltage of the NOR Vth (NOR) provided by (4.7) is compared with the
threshold voltage of the inverter (2.17), rewritten as
Kp
V T 0, n 
V th ( INV ) 
Kn

1 


(V DD  VT 0 , p )
K p 
Kn 

(4.8)
If K n  K p and VT ,n | VT , p | , the switching threshold of the CMOS inverter is equal to
V DD / 2 . Using the same parameters, the switching threshold of the NOR2 gate is
V th ( NOR2 ) 
V DD  VT ,n
3
(4.9)
which is not equal to V DD / 2 . For example, if V DD  5V and VT ,n | VT , p | 1V the switching
voltages of the NOR2 gate and the inverter are Vth ( NOR 2)  2V and Vth ( INV )  2.5V .
The switching threshold voltage of the NOR2 gate can also be obtained by using the
equivalent-inverter approach. When both the inputs are identical, the parallel connected
nMOS transistors can be represented by a single nMOS transistor with 2 K n . Similarly,
the series-connected pMOS transistors are represented by a single pMOS transistor with
K p / 2 . The resulting equivalent CMOS inverter is shown in Fig. 4.2.
Using the inverter switching threshold of (4.8) for the equivalent inverter circuit of Fig.
4.2, results
VT , n 
V th ( NOR) 
Kp
4K n
1
(V DD  | VT , p |)
Kp
4Kn
Figure 4.2 A CMOS NOR2 gate and its inverter equivalent
(4.10)
The expression of (4.10) is identical to (4.7). Equation (4.7) can be used as simple design
guidelines for the NOR2 gate. For example, in order to achieve a switching threshold
voltage of V DD / 2 , the following parameters are set to VT ,n | VT , p | and K p  4 K n .
Note that the equivalent inverter approach can also be used to calculate V IL and V IH to
estimate the noise margins of CMOS gate. Thus once the equivalent inverter of the NOR2
gate is determined, (2.8) and (2.10) can be used to calculate V IL and (2.12) and (2.14) can
be used to calculate V IH .
Fig. 4.3 shows the CMOS NOR2 gate with the parasitic device capacitances and the
corresponding lumped output load capacitance. In the worst case, the total lumped load
capacitance is assumed to be equal to the sum of all internal parasitic device capacitances
as
C load  C wire  C gd ,1  C db,1  C gd , 2  C db, 2  C gd ,3  C db,3  C gd , 4  C db, 4  C gs , 4  C sb, 4
(4.11)
Note that the load capacitance of the NOR gate is larger than the inverter, hence the NOR
gate will always be slower than that of the equivalent inverter. The dynamic
characteristics of the NOR2 gate are calculated using the same equations provided in
Chapter 3 using (4.11) for the load capacitance.
Figure 4.3 Parasitic device capacitances of the CMOS NOR2 circuit and the simplified
equivalent with the lumped output load capacitance.
CMOS NAND2 (Two-input NAND) Gate
Fig. 4.4 shows a two-input CMOS NAND (NAND2) gate. The two series connected
nMOS transistors creates a conducting path between output node and the ground only if
both input voltages are set to VOH . In this scenario, both the parallel pMOS transistors
will be off. For all other input combinations, either one or both of the pMOS transistors
will be turned on, while the path of the nMOS transistors will be cut-off, thus creating a
current path between the output node and the power supply voltage.
The threshold voltage for the CMOS NAND2 gate can be calculated using a similar
procedure followed for the NOR2 gate. Assuming the device sizes in each block are
identical, (W / L) n, A  (W / L) n, B and (W / L) p, A  (W / L) p, B , and using the inverter equivalent
method shown in Fig. 4.4, the switching threshold for the NAND2 gate is found using
VT , n  2
V th ( NAND ) 
Kp
Kn
1 2
(V DD  | VT , p |)
Kp
(4.12)
Kn
Using (4.12), to achieve a switching threshold of V DD / 2 when simultaneous switching
occurs, the parameters are set to VT ,n | VT , p | and K n  4 K p .
Since the mobility of electrons is greater then the mobility of holes, the area occupied
by NOR gates will be greater than the NAND gates. For this reason, NAND gates are
generally preferred for implementing combinational logic functions in CMOS circuits.
Figure 4.4 A CMOS NAND2 gate and its inverter equivalent
Complex Logic Circuits
The CMOS logic gate consists of two networks: the pull-down network (PDN)
constructed of nMOS transistors and the pull-up network (PUN) constructed of pMOS
transistors as shown in Fig. 4.5. The PDN and PUN networks each utilize transistors in
parallel to form an OR function, and transistors in series to form an AND function. In this
discussion, the OR and AND notation refer to current flow or conduction. Fig. 4.6 shows
examples of PDNs. The functions derived from Fig. 4.6 are:
Y  ( A  B) 
Fig 4.6a:
Y  A B
or equivalently
Y  ( AB ) 
Fig 4.6b:
Y   AB
or equivalently
Y  ( A  BC ) 
Y   A  BC
Fig 4.6c:
or equivalently
Next consider the PUN examples shown in Fig 4.7. The functions derived from Fig.4.7
are
Fig 4.7a:
Y  A  B 
Fig 4.7b:
Y  A B 
Y  A' B ' C '
Fig 4.7c:
Figure 4.5 Representation of a three-input CMOS logic gate. The PUN comprises
PMOS transistors, and the PDN comprises NMOS transistors.
Figure 4.6 Examples of pull-down networks.
Figure 4.7 Examples of pull-up networks.
Thus to create a NOR2 gate requires combining Fig. 4.6a with Fig. 4.7b, to realize
Y  ( A  B )'  A' B '
(4.13)
Similarly, to create a NAND2 gate requires combining Fig. 4.6b with Fig. 4.7a, to realize
Y  ( AB )'  A' B'
(4.14)
This approach can be used to create more complicated functions. For example, the logic
function
Y  ( A( B  CD ))'
(4.15)
is implemented in Fig. 4.8. The PDN and PUN functions to realize (4.15) are
Y '  ( A( B  CD ))
PDN
Y  A'( B ' (C ' D' )) (using DeMorgan’s theorem)
PUN
Note the transistors are placed in parallel to form the OR functions and transistors are
placed in series to form the AND functions.
Transistor Sizing of Complex Logic Circuits
The derivation of the equivalent W/L ratio is based on the fact that the resistance of a
MOSFET is inversely proportional to W/L. For example, when the input voltage of the
inverter is Vin  0 or VOL , then the nMOS transistor is in cutoff region and the pMOS
transistor is in linear or triode region (as illustrated in Fig. 4.9a). The current through the
pMOS transistor is
Figure 4.8 CMOS realization of Y  ( A( B  CD))'
(a)
(b)
Figure 4.9 Operation of the CMOS inverter (a) Vin  0 or VOL , with equivalent circuit (b)
Vin  V DD or VOH , with equivalent circuit
1 2 
W  
I D   p C ox    (VGS , p  VT 0 , p )V DS , p  V DS
,p 
2
 L p

(4.16)
The voltage V DS , p is very small when the inverter is operating as shown in Fig. 4.9a.
Therefore, the resistance rDSP of Fig. 4.9a can be expressed as
r DSP 
V DS , p
ID

1
W 
 p C ox   (V GS , p  VT 0 , p )
 L p
(4.17)
Similarly, when the input voltage of the inverter is Vin  V DD or VOH , then the pMOS
transistor is in cutoff region and the nMOS transistor is in linear or triode region (as
illustrated in Fig. 4.9b). The resistance rDSN of Fig. 4.9b is written as
r DSN 
V DS ,n
ID

1
W 
 n C ox   (VGS ,n  VT 0 ,n )
 L n
(4.18)
Note that for the example shown in Fig. 4.9, the resistance of the transistor is inversely
proportional to W/L. Next, suppose a number of MOSFETs having ratios of (W / L)1 ,
(W / L) 2 , … are connected in series as illustrated by the four input NOR gate shown in
Fig. 4.10. Neglecting the substrate- bias effect, assuming that the threshold voltages of all
transistors are the same, and that all input voltages switch simultaneously, the equivalent
series resistances will be
R series  rDS1  rDS 2  ....

K
K

 ....
(W / L ) 1 (W / L ) 2
(4.19)


1
1
K
 K 

 ....  
 (W / L ) 1 (W / L ) 2
 (W / L ) eq
Figure 4.10 Proper transistor sizing for a four-input NOR gate. Note that n and p denote
the (W/L) ratios of QN and QP, respectively, of the basic inverter.
resulting in the following expression of (W / L) eq for transistors connected in series
(W / L ) eq 
1
1
1

 ....
(W / L ) 1 (W / L ) 2
(4.20)
Similarly, for parallel connected transistors the (W / L) eq expression becomes
(W / L) eq  (W / L)1  (W / L) 2  ....
(4.21)
As an example of proposer sizing, consider the four-input NOR gate in Fig. 4.10. Here,
the worst case (the lowest current) for the PDN is obtained when only one of the nMOS
transistors is conducting. The W/L of each nMOS transistor is set to be equal to that of a
nMOS transistor of a basic inverter, namely n. For the PUN, however, the worst case
situation is when all inputs are low and the four series pMOS transistors are conducting.
Hence using (4.20), the pMOS transistors of Fig. 4.10 are set to be four times that of the
pMOS transistor of a basic inverter. The proposer sizing of a four input NAND gate is
also provided in Fig 4.11, using (4.20) and (4.21).
Figure 4.11 Proper transistor sizing for a four-input NAND gate. Note that n and p
denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.
Layout of Complex CMOS Logic Gates
This section investigates the problem of constructing a minimum area layout for complex
CMOS logic circuits. Fig. 4.12 and Fig 4.13 show a sample layout of a CMOS NOR2 and
NAND2 gate, respectively, using single-layer and single layer polysilicon.
Contact
Metal
Polysilicon
Figure 4.12 Sample layout of the CMOS NOR2 gate
Figure 4.13 Sample layout of a CMOS NAND2 gate
Figure 4.14 Stick diagram layout of CMOS NOR2 gate.
In both examples, the p-type diffusion area for the pMOS transistors and the n-type
diffusion area for the nMOS transistors are aligned to allow simple routing of the gate
signals via two parallel polysilicon lines running vertically. This layout style allows the
so-called feedthrough of signals in standard cell layouts and provides area savings in
signal routing. Fig. 4.14 shows a simplified (stick diagram) view of the CMOS NOR2
gate layout given in Fig. 4.12. Here, the diffusion areas are depicted by rectangles, the
metal connections and contacts are represented by a solid lines and circles, respectively,
and the polysilicon columns are represented by cross-hatched strips. The stick diagram
layout does not carry any information on the actual geometry relations of the individual
features, but it conveys valuable information on the relative placement of the transistors
and their interconnections.
Next, consider the problem of constructing a minimum-area layout for the following
function
Z   A( D  E )  BC  '
(4.22)
The CMOS logic circuit to realize (4.22) is shown in Fig. 4.15. Fig. 4.16 shows the stickdiagram layout of a “first attempt” using an arbitrary ordering of the polysilicon gate
column. Note that in this case, the separation between the polysilicon columns must allow
for one diffusion-to-diffusion separation and two metal-to-diffusion contacts in between.
This certainly consumes a considerable amount of extra silicon area.
A simple method for finding the optimum gate ordering is the Euler-path approach: find
a Euler path in the pull-down and pull-up graph with identical ordering of the output
labels; i.e., find a common Euler path for both graphs. The Euler path is defined as an
uninterrupted path that traverses each edge (branch) of the graph exactly once. Fig. 4.17
shows the construction of a common Euler path for both graphs for (4.22).
Figure 4.15 A complex CMOS logic gate realizing the Boolean function
Figure 4.16 Stick-diagram layout of a complex CMOS logic gate, with an arbitrary
ordering of polysilicon gate columns
Figure 4.17 Finding a common Euler path in both graphs for n-net and p-net provides
gate ordering that minimizes the number of diffusion breaks and, thus, minimizes the
logic gate layout area, in both cases, the Euler path starts at (x) and ends at (y).
It is seen that there is a common Euler path sequence (E-D-A-B-C) in both graphs. The
polysilicon gate columns can be arranged according to this sequence, which results in
uninterrupted p-type and n-type diffusion areas. The stick diagram of the new layout is
shown in Fig 7.22. The advantages of this new layout are more compact (smaller) layout
area, simple routing of signals, and consequently, less parasitic capacitance.
AOI and OAI gates
AND-OR-INVERT (AOI) gates enable the sum-of-products realization, while the ORAND-INVERT (OAI) gates enable product of sums realizations. Examples of AOI and
OAI gates are shown in Fig. 4.19 and Fig. 4.20, respectively
Figure 4.18 Optimized stick-diagram layout of the complex CMOS logic gate
Figure 4.19 An AND-OR-INVERT (AOI) gate and the corresponding pull-down net.
Figure 4.20 An OR-AND-INVERT (OAI) gate, and the corresponding pull-down net
CMOS Full-Adder Circuit
The one-bit full adder is one of the most widely used building blocks in all data
processing arithmetic architectures. The sum_out and carry_out signals of the full adder
are defined as
sum _ out  A  B  C  ABC  AB' C ' A' B ' C  A' C ' B
carry _ out  AB  AC  BC
(4.23)
The gate-level realization of these two functions is shown in Fig. 4.21 and the transistor
realization is shown in Fig. 4.22. The mask layout of the full-adder circuit where all
nMOS and pMOS transistors are the same size (same W/L ratio) is shown in Fig. 4.23.
Figure 4.21 Gate level schematic of one-bit full-adder circuit
Figure 4.22 Transistor level schematic of one-bit full-adder circuit
In order to improve the transient time-domain performance of the circuit, it is usually
necessary to adjust the dimensions of each transistor as illustrated by the inverter example
of the previous chapter. By varying the sizes of transistors at strategic points, a circuit can
be made to run much faster than when all its transistors have the same size. The issue of
selecting transistor sizes of complicated circuits is a challenging task, often performed by
automated logic optimization programs. Fig. 4.24 shows an optimized mask layout of the
full-adder. The transient responses between of the same size transistor layout and
optimized layout are shown in Fig. 4.25. Note that the propagation delay of the optimized
circuit is about 1 ns, a reduction of 50% when compared to the same size transistor
layout.
Figure 4.23 Mask layout of the CMOS full-adder circuit using minimum-size transistors
Figure 4.24 Mask layout of the optimized CMOS full-adder circuit
(a)
(b)
Figure 4.25 Simulated output waveforms of the full-adder circuit showing one of the
worst-case transitions (a) with minimum transistor dimensions (b) with optimized
transistor dimensions
Super Buffer Design
The logic delay increases as the capacitance attached to the logic’s output becomes larger.
In many cases, one small logic gate is driving an equally small logic gate, roughly
matching driving capability to the load. However, there are several situations in which the
capacitive load can be much larger than that presented by a typical gate:
 driving a signal connected off-chip
 driving a long wire
 driving a clock wire which goes to many points on the chip
One solution to driving large capacitive loads is to increase current by making wider
transistors. However, wider transistors result in large capacitive loads to the gate which
drives them, pushing the problem back one level of logic. One way to drive large
capacitive loads and minimize the delay along the path is to use a sequence of
successively large drivers as illustrated in Fig. 4.26, where
 C g is the minimum-size load capacitance at the first stage.
 C d is the drain capacitance at the first stage.
 The inverters in the chain are scaled up by a factor of  per stage.
N 1
 C load   C g
 All inverter have identical delay of  o (C d  C g ) /(C d  C g )
where  o represents the per-gate delay of the inverter with load capacitance of (C d  C g ) .
Thus the total delay time from the input terminal to the load capacitance node becomes
Figure 4.26 Scaled super buffer circuit consisting of N inverter stages
 C d  C g
 total  ( N  1) o 
 Cd  Cg





(4.24)
There are two unknowns in (4.24). To solve for these unknowns, the following
expression C load   N 1C g is rewritten as
C
ln load
 Cg

N 1 
ln 




(4.25)
Combining (4.24) and (4.25), yields the following delay relationship
 total
C
ln load
 Cg


ln 




 C d  C g
o
 Cd  Cg





(4.26)
To minimize the delay, the derivative of (4.26) with respect to  is set to zero
C
 total
  o ln load
 Cg


1


  
 (ln  ) 2


 C d C g

 Cd  C g


 Cg
 1 
 ln   C d  C g




  0



(4.27)
Solving for (4.27) gives the following scaling factor
 (ln   1) 
Cd
Cg
(4.28)
A special case of (4.28) occurs when the drain capacitance is neglected (i.e. C d  0 ). In
this case the optimal scaling factor becomes the natural number
  e  2.718
(4.29)
However, in reality the drain parasitics cannot be ignored and (4.28) should be used.
Transistor Sizing using Logical Effort
The theory of logical effort provides a clear and useful foundation for transistor sizing.
Logical effort computes d , the delay of a gate, in units of  , the dealy of a minimum size
inverter. The model for a gate’s delay consists of two components:
d f p
(4.30)
where
 f is the effort delay and related to the gate’s load
 p is the parasitic delay fixed by the gate’s structure
The effort delay can be expressed in terms of its components as
f  gh
(4.31)
where
 h is the electrical effort and is determined by the gate’s load.
 g is the logical effort determined by the gate’s structure.
The electrical effort is given by the relationship between the gate’s capacitive load and
the capacitance of its own drivers (which is related to the drivers’ current capacity)
h
C out
Cin
(4.32)
The logical effort of a gate is defined as the ration of the input capacitance of the gate to
the input capacitance of an inverter that can deliver the same out current. Fig. 4.27 shows
an inverter, NAND and NOR gates with transistor widths chosen to achieve unit
resistance, assuming pMOS transistors have twice the resistance of the nMOS transistors.
The inverter presents 3 units of input capacitance. The NAND presents 4 units of
capacitance on each input, so that the logic effort is 4/3. Similarly, the NOR gate presents
5 units of capacitance, so the logical effort is 5/3. Table 4.1 lists the logical effort for
multi-input NOR and NAND gates.
Using (4.31), equation (4.30) can be rewritten as
d  gh  p
(4.33)
The path logical effort of a chain of gates is
n
G   gi
i 1
(4.34)
The electrical effort along a path is the ratio of the last stage’s load to the first stage’s
input capacitance
H
C out
(4.35)
Cin
Branching effort takes fanout into account. The branching effort b at a gate is defined as
b
Conpath  C offpath
(4.36)
C onpath
The branching effort along an entire path is
n
B   bi
(4.37)
F  GBH
(4.38)
i 1
The path effort F is defined as
The path delay of a multistage network is calculated as the sum of the delays of the gates
along the path
D
n
n
n
i 1
i 1
i 1
 d i   g i hi   p i  D F  P
(4.39)
The path delay is minimized by ensuring that each stage bears the same effort fˆ as
fˆ  g i hi  F 1 / n
(4.40)
Thus the minimum possible delay of an n-stage path with path effort F and path parasitic
delay P is
D  NF 1 / n  P
(4.41)
Using (4.31) and (4.32), the calculated input capacitance for a gate given the output
capacitance it drives is
C in, i 
g i C out ,i
fˆ
(4.42)
Thus the ratios of each stage are determined by starting from the last gate with a known
load and working backward to the first gate.