CMOS Logic Circuit Design
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Logic Design for Speed (Logical Effort)
• 4 Common Design Techniques of Fast Complex Gates
• Logical Effort Description of the Gate Delay
– Definition of Logical Effort, Electrical Effort and Parasitic (Intrinsic) Delay
– Logical Effort and Parasitic Delay of Typical Gates
• Logical Effort Description in Combinational Circuits
– Efforts and Delays of a Signal Path
– Optimum Number of Stages in the Signal Path
– Summary of the Logical Effort Method for Optimized Delay and Stage
Number of a Signal Path
Mattausch, CMOS Design, H20/5/23
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Fast-Gate Design (1): Transistor Sizing
• Increase the transistor width
¾ Good as long as load capacitance dominates
• Progressive sizing for MOSFETS connected in series
InN
CL
MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Distributed RC line
M1 > M2 > M3 > … > MN
(the MOSFET closest to the
output has the smallest width)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
The most common method of decreasing the delay of a logic
gate is to increase the width of its transistors.
Mattausch, CMOS Design, H20/5/23
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Fast-Gate Design (2): Transistor Ordering
critical path
In3 1 M3
charged
CL
In2 1 M2
C2 charged
In1
M1
0→1
C1 charged
Delay determined by
time to discharge CL, C1
and C2
critical path
0→1
In1
M3
CLcharged
In2 1 M2
C2 discharged
In3 1 M1
C1 discharged
Delay only determined
by time to discharge CL
The load capacitance of critical path signals is minimized by
placing related MOSFETs closest to the output node.
Mattausch, CMOS Design, H20/5/23
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Fast-Gate Design (3): Change of Logic Structure
Desired Logic Function
F = ABCDEFGH
Solution 1
Slow gate with large fan-in
Solution 3
Only gates with fan-in equal 2
Solution 2
Reduced fan-in, but NOR at output
Slow gates with large fan-in can be avoided by changing the
logic structure for realizing the logic function.
Mattausch, CMOS Design, H20/5/23
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Fast-Gate Design (4): Isolate Fan-in from Fan-out
CL
CL
Isolating gates with large fan-in from an output node with
high fan-out or large load capacity can reduce signal delay.
Mattausch, CMOS Design, H20/5/23
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Logical Effort Description of
the Gate Delay
-
Definition of Logical Effort, Electrical
Effort and Parasitic (Intrinsic) Delay
Logical Effort and Parasitic Delay of
Typical Gates
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Logical Effort View of the Gate Delay
Formula for date delay:
tdf,NAND = m⋅ (m⋅ t fin + k⋅ t fex )
⇒ τ inv ⋅ d = τ inv ⋅ ( p + h )
(see lecture 3)
d=p+h
Gate delay:
(Units of minimum
inverter delay)
intrinsic delay
effort delay
(parasitic delay)
Effort delay:
h = le • fo
logical
effort
effective fanout
= Cout/Cin = “electrical effort”
The logical effort is only a function of gate topology. Delay is
measured in units of the minimum-size inverter delay.
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How to Calculate the Logical Effort of a Gate ?
• Formula for the gate delay
¾ dgate = (le · fo) + p = effort delay + parasitic delay
• Options to find the logical effort (le) of a logic gate
a) Set the current drive (Rdrive) of the gate equal to the minimum inverter
current drive. Then compare the input capacitances (Cin)
b) Set the input capacitance (Cin) of the gate equal to the minimum inverter
input capacitance. Then compare the current drives (Rdrive)
c) Use the ratio of the products between Rdrive and Cin
legate
τ gate ( Rdrive ⋅ Cin ) gate
=
=
τ inv
( Rdrive ⋅ Cin )inv
Mattausch, CMOS Design, H20/5/23
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Determination of Logical Efforts with Method a)
A
A
2
2
B
F
2
F
A
A
VDD
VDD
VDD
B
4
A
4
Transistor
Width (W)
in Units of the
Minimum n-MOSFET
Value
2
F
1
A
B
B
1
1
2
Inverter
2-input NAND
2-input NOR
leinv = 1
leNAND2 = 4/3
leNOR2 = 5/3
The logical effort is only a function of gate topology. Delay is
measured in units of the minimum-size inverter delay.
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Catalog of Logical Efforts (le) of Important Gates
With increasing fan-in the logical effort (le) of NOR gates
becomes much larger than the logical effort of NAND gates.
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Parasitic (Intrinsic) Delay of Gates
• The parasitic delay p is technology and gate dependent
• For the inverter pinv between 0.5 and 1 is typical
• Once pinv is known, the parasitic delay of other gates pgate
can be estimated
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Graphical View of le and p for Typical Gates
• From the graph:
normalized delay: dgate
– pinv is assumed as 0.5
– slope is equal to le
– y-axis intercept is
equal to pgate
• More complex gates:
– have larger le
– have larger pgate
electrical effort: fo = Cout/Cin
Knowledge of the logical effort (le) and the parasitic delay (p)
are sufficient to estimate the gate delay for any load.
Mattausch, CMOS Design, H20/5/23
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Logical Effort Description in
Combinational Circuits
-
Efforts and Delays of a Signal Path
Optimum Stage Number in Signal Path
Summary of the Logical Effort Method for
Optimized Stage Number and Delay of a
Signal Path
Mattausch, CMOS Design, H20/5/23
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Multi-stage Logic Path
• Example of a 4-stage signal path:
1
le = 1
fo = a
a
le = 5/3
fo = b/a
c
b
5
le = 5/3
fo = c/b
le = 1
fo = 5/c
Stage effort: hi = lei •foi
Path electrical effort: FO = Cout /Cin = 5
Path logical effort: LE = le1•le2•…•le4
How can we determine the path effort? H = LE • FO ?. How
can we design the best intermediate electrical fan-outs fo ?
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Adding of the Branching Effort
Branching effort:
b=
Con − path + Coff − path
Con − path
Branch example
Branching effort:
B = b1•b2•…•bN
Path effort:
H = LE•FO•B
An important additional feature in combinational circuits is
the possibility of signal branches.
Mattausch, CMOS Design, H20/5/23
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General Signal Path with N Stages
N
Delay = ∑ ( pi + lei ⋅ foi )
i =1
Stage effort: hi = lei •foi
Stage-effort for minimum
signal-path delay
Path electrical effort: FO = Cout /Cin
lei •foi = H1/N
Path logical effort: LE = le1•le2•…•leN
Branching effort: B = b1•b2•…•bN
Path effort: H = LE•FO•B
Minimum path delay
Path delay Dpath=Σdi =Σpi +Σhi = P+DH
N • H1/N + P
Key result of logical-effort approach: The shortest possible
path delay can be found without detailed path design.
Mattausch, CMOS Design, H20/5/23
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Logical Effort Description in
Combinational Circuits
-
Efforts and Delays of a Signal Path
Optimum Stage Number in Signal Path
Summary of the Logical Effort Method for
Optimized Stage Number and Delay of a
Signal Path
Mattausch, CMOS Design, H20/5/23
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Derivation of the Optimum Stage Number
Combinational logic block with n1 stages
and N-n1 inverters for output buffering
H
n1
D path = N ⋅ H + ∑ pi + ( N − n1 ) pinv
1
N
Path Delay:
i =1
Minimum N:
∂D path
∂N
1
N
1
N
1
N
= − H ln( H ) + H + pinv = 0
H =ρ
1
N
pinv + ρ (1 − ln ρ ) = 0
For determining the optimum stage number, an equation with
no explicit solution has to be solved.
Mattausch, CMOS Design, H20/5/23
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Normalized Delay (D/Dbest)
Sensitivity of Mistakes in the Optimum N
Normalized Stages (N/Nbest)
• Factor 2 mistaken
stage number N has
less than <51% effect
on delay time.
• It is better to use too
many than too few
stages.
• 2.4<ρ <6 gives only
15% change in delay
time.
The generally accepted best choice for ρ is 4. Therefore the
stage number N is determined by Nbest=log4H
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Summary of Definitions for Logical Effort Method
le
LE
fo
FO
lei
b
h
le•fo
h
H LE•FO•B
DH
hi
= log4 H
d
h
DH
Mattausch, CMOS Design, H20/5/23
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Application of the Logical-Effort Method
•
•
•
•
•
Compute the path effort: H = LE•FO•B
Find the best number of stages: Nbest ~ log4 H
Compute the stage effort: h = H1/N
Sketch the path with this number of stages
Work either from 1st or last stage; find size for
stage i with equation:
best
Cin ,i = Cout ,i
lei
hi
Reference: Sutherland, Sproull, Harris, “Logical Effort”, Morgan-Kaufmann 1999.
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