Novel Three-Phase AC-DC-AC Sparse Matrix Converter
Part I: Derivation, Basic Principle of Operation, Space Vector Modulation, Dimensioning
J.W. Kolar, M. Baumann*, F. Schafmeister, H. Ertl*
ETH Zurich
Power Electronic Systems Laboratory
ETH Zentrum/ETL H22
Physikstr. 3, CH-8092 Zurich/Switzerland
kolar@lem.ee.ethz.ch
*Vienna University of Technology
Dept. of Electrical Drives
Gusshausstr. 27/E 372
A-1040 Vienna/Austria
martina.baumann@tuwien.ac.at
Abstract. A novel three-phase AC-DC-AC Sparse Matrix Converter
(SMC) having no energy storage elements in the DC link and
employing only 15 IGBTs as opposed to 18 IGBTs of a functionally
equivalent conventional AC-AC matrix converter (CMC) is proposed. It is shown that the realization effort could be further reduced
to only 9 IGBTs (Ultra Sparse Matrix Converter, USMC) in case the
phase displacement of the fundamentals of voltage and current at the
input and at the output is limited to ±π/6. The dependency of the
voltage and current transfer ratios of the systems on the operating
parameters is analyzed and a space vector modulation scheme is
described in combination with a zero current commutation procedure. Furthermore, a safe multi-step current commutation concept is
treated briefly. Conduction and switching losses of the SMC and
USMC are calculated in analytically closed form. Finally, the
theoretical results are verified in Part II of the paper by digital
simulations and results of a first experimental investigation of a
10kW/400V SMC prototype are given.
a
A
b
B
c
C
(a)
I. INTRODUCTION
Three-phase matrix converters are capable of providing simultaneous amplitude and frequency transformation of a three-phase
voltage system and do need only small switching frequency ac filter
components as opposed to conventional two-stage AC/DC/AC
conversion by back-to-back connection of current or voltage DC link
PWM converter systems. Furthermore, matrix converters are
inherently bi-directional and therefore can regenerate energy back
into the mains from the load side where the mains current is sinusoidal and the displacement factor seen by the mains can be adjusted by
proper modulation irrespective of the type of load. In consequence
matrix converters show a high power density and due to lacking
electrolytic capacitors a potentially high reliability. Accordingly,
there is considerable interest in the application of matrix converters
for the realization of highly compact three-phase AC drives [1] for
industrial and military marine and avionics systems.
A conventional matrix converter does employ 9 bidirectional
bipolar (four-quadrant) switches which, based on available power
semiconductor technology have to be formed by 18 unipolar turn-off
power semiconductors (IGBTs) and 18 diodes as shown in Fig.1(a).
The combination of 2 IGBTs and 2 anti-parallel diodes per fourquadrant switch does allow a selective turn-on of the switch for each
current direction as required for the implementation of a safe multistep commutation strategy avoiding the short circuiting of an input
line-to-line voltage or an abrupt interruption of an output phase
current [2, 3].
Research on the matrix converter so far has been mainly focused
on modulation schemes and digital generation of the PWM
switching patterns. The derivation of alternative topologies showing
identical functionality but a lower count of unipolar turn-off power
semiconductors has not been paid much attention.
a
A
b
B
c
C
(b)
Fig. 1: (a): Conventional matrix converter (CMC) shown for common
emitter arrangement of the power transistors of a four quadrant switch cell; a
common collector arrangement does allow to reduce the number of isolated
gate drive power supplies from nine to six (cf. Tab.1) and therefore is
employed in a new matrix converter power module [4],[5]. (b): indirect
matrix converter (IMC) as proposed in [6] and also analyzed in [7].
In this paper novel matrix-equivalent three-phase AC-DC-AC
converter topologies are developed based on the structure of an
indirect matrix converter (IMC, cf. Fig.1(b)) which has been
proposed in [6] (cf. Section II). The novel converter topologies do
show a reduced number of power transistors as compared to the
CMC or IMC and are therefore denoted as Sparse Matrix Converter
(SMC) and/or Ultra Sparse Matrix Converter (USMC). In Section
III a safe multi-step commutation concept for the SMC is treated
and a zero current commutation procedure featuring low complexity
is described. In Section IV a space vector modulation scheme is
proposed which naturally does provide zero current commutation
and ohmic fundamental mains behavior. Furthermore, in Section V
the operating range of the SMC and of the USMC is analyzed and
the dependency of the current and voltage transfer ratio of a matrix
converter on the phase displacement of voltage and current fundamentals at the input and at the output side is clarified. In Section VI
the average and rms current stress on the IGBTs and diodes as
required for the dimensioning of the power circuit of the SMC and of
the USMC are calculated for ohmic fundamental mains behavior in
dependency on the modulation depth and on the load power factor.
In Section VII the theoretical considerations are verified by digital
simulations and in Section VIII results of a first experimental
investigation of the reduced complexity matrix converter are presented. There, the theoretical considerations are verified by digital
simulations and do provide the basis for the dimensioning of a
10kW/400Vrms line-to-line input SMC prototype supplying a passive
load. Finally, in Section IX topics of the continuation of the research
are identified and a novel three-level output stage SCM (SMC3) is
proposed.
II. DERIVATION OF THE SMC TOPOLOGY
In the following the derivation of the circuit topology of the SMC
and the equivalence to the CMC concerning controllability and/or
modulation range shall be treated. The topology of the CMC is
shown in Fig.1(a) where, with reference to a three-phase AC motor
drive application the converter input voltages and the output currents
are assumed to be impressed. Modulation schemes for the CMC as
given in the literature can be classified in direct frequency conversion schemes [8, 9] and indirect frequency conversion schemes
[10, 2]. For the indirect frequency conversion scheme the CMC is
fictitiously divided into a voltage-fed rectifier input stage and an
inverter output stage with impressed output currents which are
directly connected on the DC side (see Fig.2 in [2]). The physical
implementation of this basic idea does result in the converter
topology depicted in Fig.1(b) [6] which is functionally equivalent to
a CMC and will be denoted as indirect matrix converter (IMC) in the
following (cf. Fig.2).
AC-AC Converter
DC Link Energy Storage
Converter
Type
CMC
IMC
SMC
VSMC
USMC
Transistors
Diodes
18
18
15
12
9
18
18
18
30
18
Isolated Driver
Potentials
6
8
7
10
7
TABLE I: Realization effort of different matrix converter topologies (for
VSMC see Section III.).
The DC link voltage of the IMC shows a fixed polarity, but the
IMC four-quadrant switch current-source-type rectifier could operate
with both DC link voltage polarities. Therefore, it is near at hand to
consider ways of reducing the rectifier stage circuit complexity. The
actual possibility of a reduction of the number of unipolar turn-off
power semiconductors of the current-source-type rectifier stage is
verified step-by-step in Fig.3 for a single bridge leg.
For spa=sap=1 (a switching function si=1 does denote a turn-on
state of the corresponding power transistor Si, si=0 does denote the
turn-off state) for the bridge leg topology Fig.3(a) input a is
connected bidirectionally to p. There, in case of upn>0 transistor San
is blocking voltage, a voltage upn<0 is taken over by Sna. Restricting
the operation to upn>0, therefore a blocking of Sna within the turn-on
interval of Sap is not required and both transistors could be combined
in a single transistor Sa (cf. Fig.3(b)) which has to be turned on for
connection of a to p as well as for connecting a to n. However, the
resulting bridge leg topology (cf. Fig.3(c), [11],[12]) for upn>0 still
does provide the independent controllability of both current
directions as required for the implementation of a safe commutation
strategy [3]. Consequently, for upn>0 the functionality of an IMC
and/or CMC can be realized by the novel converter topology
depicted in Fig.4(a) which does employ only 15 IGBTs as opposed
to 18 IGBTs of the IMC and does require a lower number of isolated
gate drive power supplies and therefore shall be denoted as Sparse
Matrix Converter (SMC) in the following.
No DC Link Energy Storage − Matrix Converter
VSR/VSI CSR/CSI
Conventional (Direct)
Sparse
Very Sparse
Inv. Link
Indirect
Ultra Sparse
Fig. 2: Classification of AC-AC converter topologies. Systems pointed out
are treated in more detail in this paper.
For the IMC a conventional (two-quadrant switch) voltagesource-type inverter is fed by a four-quadrant switch current-sourcetype rectifier which is able to operate with positive and negative DC
current for unipolar DC link voltage as required by the inverter
stage. There, the input capacitor of the inverter has to be thought to
be realized by the AC-side (voltage impressing) filter capacitors of
the rectifier stage and the output inductor of the rectifier is realized
by the current-impressing inductance of the load. The IMC does
employ 18 unipolar turn-off power semiconductors and 18 diodes
(cf. Tab.1) and therefore basically shows the same realization effort
as the CMC. However, the inverter stage could be realized by a
conventional six-pack power module what slightly reduces the realization effort as compared to a fully discrete realization of a CMC.
Fig. 3: Modification of the structure of a bridge leg of the current-sourcetype rectifier input stage of the IMC (a) (cf. Fig.1(b)) into the SMC bridge
leg topology (c) (cf. Fig.4(a)).
The functional equivalence of CMC/IMC and SMC are proven
by Tab.2 [2] and Tab.3 where the CMC and SMC line-to-line
output voltages and input phase currents resulting for the different
switching state combinations are compiled. In case, e.g., uab>0, ubc,
uca < 0 (as given in a π/3-wide interval of a mains period) is valid,
due to the restriction upn>0 the SMC switching states pointed out in
Tab.3 are not available. However, the remaining switching states to
be employed for space vector modulation [2] are identical to the
switching states of the CMC concerning output voltage and input
current formation (cf. Tab.2). Therefore, the controllability and the
operating range of the SMC is not restricted as compared to the
CMC despite the reduced number of unipolar turn-off power
semiconductors. As a result the SMC represents a highly interesting
alternative to the CMC for industrial applications.
i
p
b
B
c
C
n
(a)
a
A
b
B
c
C
(b)
Fig. 4: Proposed Matrix Converter Topologies; (a): Sparse Matrix Converter
(SMC), (b):Ultra Sparse Matrix Converter (USMC).
No. A
1 a
2 b
3 c
4 a
5 b
6 b
7 c
8 c
9 a
10 c
11 c
12 a
13 a
14 b
15 b
16 c
17 c
18 a
19 a
20 b
21 b
22 a
23 a
24 b
25 b
26 c
27 c
B
a
b
c
c
c
a
a
b
b
a
b
b
c
c
a
c
c
a
a
b
b
b
c
a
c
a
b
C
a
b
c
c
c
a
a
b
b
c
c
a
a
b
b
a
b
b
c
c
a
c
b
c
a
b
a
sAa
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
sAb
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
sAc
0
0
1
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
sBa
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
sBb
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
sBc
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
1
0
1
sCa
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
0
1
sCb
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
0
1
0
0
1
0
sCc
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
uAB
0
0
0
-uca
ubc
-uab
uca
-ubc
uab
uca
-ubc
uab
-uca
ubc
-uab
0
0
0
0
0
0
uab
-uca
-uab
ubc
uca
-ubc
uBC
0
0
0
0
0
0
0
0
0
-uca
ubc
-uab
uca
-ubc
uab
uca
-ubc
uab
-uca
ubc
-uab
ubc
-ubc
-uca
uca
uab
-uab
uCA
0
0
0
uca
-ubc
uab
-uca
ubc
-uab
0
0
0
0
0
0
-uca
ubc
-uab
uca
-ubc
uab
uca
-uab
-ubc
uab
ubc
-uca
ia
0
0
0
iA
0
-iA
-iA
0
iA
iB
0
-iB
-iB
0
iB
iC
0
-iC
-iC
0
iC
iA
iA
iB
iC
iB
iC
ib
0
0
0
0
iA
iA
0
-iA
-iA
0
iB
iB
0
-iB
-iB
0
iC
iC
0
-iC
-iC
iB
iC
iA
iA
iC
iB
1
10
19
25
31
37
38
39
40
41
42
43
44
45
46
47
48
iA A
ia
a
No. A B C spa spb spc san sbn scn sA sB sC uAB uBC uCA
ic
0
0
0
-iA
-iA
0
iA
iA
0
-iB
-iB
0
iB
iB
0
-iC
-iC
0
iC
iC
0
iC
iB
iC
iB
iA
iA
TABLE II. Switching states and corresponding line-to-line output voltages
and input phase currents of the CMC.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
p
n
X
X
X
a
a
b
b
b
b
c
c
c
c
a
a
c
c
c
c
a
a
a
a
b
b
b
b
c
c
c
c
a
a
a
a
b
b
b
b
p
n
X
X
X
c
c
c
c
a
a
a
a
b
b
b
b
a
a
b
b
b
b
c
c
c
c
a
a
c
c
c
c
a
a
a
a
b
b
b
b
p
n
X
X
X
c
c
c
c
a
a
a
a
b
b
b
b
c
c
c
c
a
a
a
a
b
b
b
b
a
a
b
b
b
b
c
c
c
c
a
a
X
X
1
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
X
X
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
1
X
X
0
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
X
X
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
X
X
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
1
0
X
X
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
X
X
X
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
-uca
-uca
ubc
ubc
-uab
-uab
uca
uca
-ubc
-ubc
uab
uab
uca
uca
-ubc
-ubc
uab
uab
-uca
-uca
ubc
ubc
-uab
-uab
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-uca
-uca
ubc
ubc
-uab
-uab
uca
uca
-ubc
-ubc
uab
uab
uca
uca
-ubc
-ubc
uab
uab
-uca
-uca
ubc
ubc
-uab
-uab
0
0
0
0
0
uca
-uca
-ubc
-ubc
uab
uab
-uca
-uca
ubc
ubc
-uab
-uab
0
0
0
0
0
0
0
0
0
0
0
0
-uca
-uca
ubc
ubc
-uab
-uab
uca
uca
-ubc
-ubc
uab
uab
u
0
0
0
-uca
uca
ubc
-ubc
-uab
uab
uca
-uca
-ubc
ubc
uab
-uab
-uca
uca
ubc
-ubc
-uab
uab
uca
-uca
-ubc
ubc
uab
-uab
-uca
uca
ubc
-ubc
-uab
uab
uca
-uca
-ubc
ubc
uab
-uab
ia ib ic
0
0
0
0
0
iA
iA
0
0
-iA
-iA
-iA
-iA
0
0
iA
iA
iB
iB
0
0
-iB
-iB
-iB
-iB
0
0
iB
iB
iC
iC
0
0
-iC
-iC
-iC
-iC
0
0
iC
iC
0
0
0
0
0
0
0
iA
iA
iA
iA
0
0
-iA
-iA
-iA
-iA
0
0
iB
iB
iB
iB
0
0
-iB
-iB
-iB
-iB
0
0
iC
iC
iC
iC
0
0
-iC
-iC
-iC
-iC
0
0
0
0
0
-iA
-iA
-iA
-iA
0
0
iA
iA
iA
iA
0
0
-iB
-iB
-iB
-iB
0
0
iB
iB
iB
iB
0
0
-iC
-iC
-iC
-iC
0
0
iC
iC
iC
iC
0
0
TABLE III. Switching states and corresponding line-to-line output voltages
and input phase currents of the CMC. The switching states pointed out are
not available for uab>0, ubc, uca < 0 due to the restriction upn>0 given by the
SMC inverter output stage. The switching state of a bridge leg of the input
stage is denoted by switching functions spi and sin, i=a,b,c, only, switching
functions si are omitted for the sake of brevity and redundancy.
With reference to an unidirectional buck-type PWM rectifier
system as described in [13] and [14] one now could further reduce
the realization effort of the SMC by omitting the power transistors
Spi and Sin in each bridge leg i=a,b,c, which do provide a reversibility of the DC link current.
This basically does restrict the circuit operation to unidirectional
power flow (upn > 0, i > 0). As a more detailed analysis shows (cf.
Section V) the controllability of the phase displacement of input
voltage and input current fundamental then is limited to ± π/6.
Furthermore, the phase displacement of load current and load
voltage fundamental is not allowed to exceed ±π/6. However, due to
the low number of power transistors the novel circuit topology which
is denoted as Ultra Sparse Matrix Converter (USMC) in the
following is of high interest and will be treated in detail in a future
paper.
III. COMMUTATION SCHEME
A. Multi-Step Commutation
For a given switching state of the rectifier input stage the commutation of the inverter output stage has to be performed identical to the
commutation of a conventional voltage DC link converter where a
dead time between turn-off and turn-on of the power transistors of a
bridge leg has to be considered in order to avoid a short circuit of the
DC link voltage.
For the changing of the switching state of the SMC rectifier
input stage for given inverter switching state one has to ensure that
no bidirectional connection between two input lines, i.e. not shortcircuiting of an input line-to-line voltage does occur. There, multistep commutation schemes, i.e. voltage independent and current
independent commutation as known for the CMC (cf. e.g. [3]) can be
employed (cf. Fig. 5). Both commutation strategies have been analyzed extensively in the literature (cf. e.g. [15-17]), we therefore would
like to omit a detailed description here for the sake of brevity.
(a)
(b)
Fig. 6: Zero current commutation of indirect matrix converter topologies
shown for the SMC. (a): Control of the power transistors of a bridge leg of
the SMC, for the VSMC (cf. Fig.7(a)) the switching functions have to be
applied directly to the corresponding power transistors (e.g. sapa has to be
connected to the gate terminal of switch Sapa). (b): Switching state sequence
(s0,s7=1 does indicate a free-wheeling operation of the inverter stage) and DC
link current i for changing the connection of the positive DC link voltage bus
p from input a to input b.
a
A
b
B
c
C
(a)
Fig. 5: Application of multi-step commutation to the SMC rectifier input
stage; (a): Basic structure of the commutating bridge legs; switching state
sequence given for changing the connection of the positive DC link voltage
bus p from input a to input b, (b): voltage independent commutation
assuming a positive DC link current, i.e. i>0, (c): current independent
commutation assuming uab>0.
B. Zero DC Link Current Commutation
The obvious drawback of multi-step commutation is complexity.
However, AC-DC-AC (two-stage) matrix converters do provide a
degree of freedom for control which is not available for the CMC
and can be utilized for alleviating the commutation problem. As
proposed in [18], in advance to rectifier stage commutation the
inverter stage could be switched into free-wheeling operation and the
rectifier stage then could commutate at zero DC link current, i.e. no
continuity of the DC link current flow during commutation has to be
considered and the switching losses of the input stage are reduced.
One only has to ensure that no overlapping of turn-on intervals of
power transistors in a bridge half does occur which would result in a
short circuit of an input line-to-line voltage (cf. Fig. 6). All further
considerations in this paper will be restricted to this straightforward
and potentially more reliable commutation concept.
It is interesting to note that for employing the zero DC link
current commutation strategy the topology of the IMC could be
reduced to the circuit structure shown in Fig.7(a) which will be
denoted as Very Sparse Matrix Converter (VSMC [19, 20]) in the
following.
a
A
b
B
c
C
(b)
Fig. 7: Topology of the Very Sparse Matrix Converter (VSMC) (a) and of
the Inverting Link Matrix Converter (ILMC) (b).
Zero DC link current commutation also would allow employ the
circuit topology shown in Fig.7(b) for three-phase AC-AC power
conversion. There, the bidirectional current carrying capability of the
input stage is achieved by combining a conventional current DC link
rectifier and a voltage and/or current inverting switching section
formed, e.g., by two power transistors and two diodes [21].
Accordingly, this converter shall be denoted as Inverting Link Matrix
Converter (ILMC). As compared to the SMC, the ILMC does show
an about equal number of power transistors. However, the inversion
of the inverter output stage input current has to be performed with
switching frequency for a phase displacement of load current and
load voltage fundamental larger than ± π/6 what does result in high
switching losses and complex control. Therefore, the ILMC will not
be considered in more detail in this paper.
Finally, it should be pointed out that the commutation of the
USMC can be performed irrespective of the switching state of the
output stage in case a free-wheeling diode is provided in the DC link
(cf. Fig.4(b)). However, commutating the input stage at non-zero DC
link current does cause additional switching losses. Therefore, a
coordination of the switching state changes of the input and output
stage is advantageous also in this case. Employing a free-wheeling
diode also for zero current commutation does potentially increase the
circuit reliability because a path for the DC link current is provided
in case of missing turn-on of an input stage power transistor, e.g. due
to an gate drive failure. As is obvious from Fig.6(a), the switching
function of the power transistors of the USMC can be derived from
the switching functions of the power transistors of a bridge leg of the
SMC by an OR gate.
IV. SPACE VECTOR MODULATION
The modulation concept derived in the following should be
applicable to the SMC, VSMC and USMC, i.e. should facilitate zero
DC link current commutation of the rectifier (input) stage. In order
to make a maximum voltage available for the formation of the output
voltage, a phase input is clamped to the positive or negative DC link
bus in π/3-wide intervals when the corresponding phase voltage does
show the highest absolute value (cf. Tab.4 and Fig.8). Thereby, the
required operating condition upn>0 of the SMC, VSMC, and USMC
is inherently satisfied.
we will limit our considerations in the following to ϕ1 = 0...π/6
where phase a remains clamped to the positive DC bus p.
Furthermore, we assume a constant average value i of the DC link
current i for each rectifier switching state. The formation of i and i
within a pulse period tµ=0...TP (tµ denotes a local time running
within a pulse period) will be treated in detail, once the converter
modulation scheme has been defined.
The DC link voltage u is defined by segments of the input lineto-line voltages uab and uac according to the rectifier switching state.
Therefore, the voltage employed by the inverter for output voltage
formation does show two different levels within each pulse half
period (cf. Fig.9). In case the switching of rectifier and inverter stage
is coordinated as shown in Fig.9 the switching over of the rectifier
always does occur in the free-wheeling interval of the inverter and
zero DC link current commutation is naturally achieved.
A free-wheeling of the rectifier stage, which could be realized by
turning on the power transistors of a bridge leg simultaneously, e.g.
sapa=sana=1, would be equivalent to an inverter free-wheeling state
concerning the formation of the input currents ia, ib, ic and the
formation of the output voltages uA, uB, uC; in both cases ia=ib=ic=0
and uAB=uBC=uCA=0 is given. Therefore, aiming for a modulation
scheme of low complexity (each change of the rectifier switching
state is linked to switching the inverter into free-wheeling mode),
free-wheeling operation is limited to the inverter stage, i.e.
(2)
dab + dac = 1.
up
un
u
ϕ1=ω1t
ua
ub, uc
uab, uac
0 ... π/6
ua, ub
uc
uac, ubc
π/6 ... π/2
ub
ua, uc
uba, ubc
π/2 ... 5π/6
ub, uc
ua
uba, uca
5π/6 ... 7π/6
uc
ua, ub
uca, ucb
7π/6 ... 3π/2
ua, uc
ub
uab, ucb
3π/2 ... 11π/6
ua
ub, uc
uab, uac
11π/6 ... 0
TABLE IV. Intervals of an input voltage period, and corresponding potentials
of the positive and negative DC link bus up and un (given with reference to
the mains star point) and DC link voltage levels u; clamping of a phase input
to p or n is pointed out by a dotted area.
ur
d
2.0
uac,r ubc,r
1.5
uab,r
Ur
ub,r
1.0
ur
uc,r
dapa
0
ua,r
-1.0
0
π/3
2π/3
π
4π/3
ϕ1
Fig. 8: Time behavior of
the input phase voltage
ua, ub, uc, and of the local
average ū of the DC link
voltage u; Ū does denote
the global average value
of u; voltages are normalized (index r) to the
phase voltage amplitude
Û1. Furthermore shown:
Duty cycle dapa of power
transistor Sapa, where for
the clamping of phase a
2π
to p, dapa =1 is valid.
With reference to the symmetry of the circuit topology and an
assumed symmetry of the three-phase input voltage system,
u a = Uˆ 1 cos(ω1t )
ub = Uˆ 1 cos(ω1t − 2π / 3)
(1)
u c = Uˆ 1 cos(ω1t + 2π / 3)
Fig. 9: Formation of the DC link voltage u and DC link current i within a
pulse period and corresponding switching functions of the rectifier and
inverter stage being characteristic for ϕ1∈(0...π/6). Switching state changes
of the input stage do occur at zero DC link current. The DC link current does
show a constant average value i within τac and τab. The switching frequency
ripple of the input line-to-line voltages uac and uab and of the output phase
currents iA and iC is neglected for the sake of clarity.
Therefore, we have in the considered interval ϕ1= 0...π/6 in which
input a is clamped to the positive DC link bus
ia = (d ab + d ac ) i ,
ib = d ab i ,
ic = d ac i
(3)
where dab and dac do denote the relative on-time of the switching
states being characterized by u=uab and u=uac. In order to achieve an
ohmic fundamental input behavior of the rectifier,
cos Φ1 = 1
(4)
we now have to guarantee a proportional relationship between the
local average value (related to a pulse period) of an input phase
current and the corresponding input phase voltage
ia ~ u a ;
ib ~ u b ;
ic ~ u c
(5)
what does result in
i
u
d ac = − c = − c ;
ia
ua
d ab = −
ib
u
=− b
ia
ua
(6)
where ua+ub+uc = 0 has been considered.
At the inverter output a voltage space vector u2 of given absolute
value |u2| and given phase ϕ2 = ω2 t has to be formed in the average
over half a pulse period ½TP (reference values are denoted by a
superscript * ). For analyzing the voltage formation we will limit our
considerations to ϕ2 = ω2 t = 0...π/6. Based on this the relations for
further intervals of the output period can be derived by symmetry
considerations.
In ϕ2 = 0...π/6 the formation of the output voltage is by the active
voltage space vectors u2,(100) and u2,(110) and by the free-wheeling
state (111) or (000), where u2,(111)= u2,(000)=0 is valid. (The inverter
output voltage space vectors are denominated by the corresponding
combinations (sAsBsC) of the bridge leg switching functions.)
In the time intervals τac = dacTP/2 and τab = dabTP/2 we have for
the DC link voltage u = uac and/or u = uab, accordingly the absolute
value of the inverter output voltage space vector will show a
different value. In order to fully utilize the voltages uac and uab for
the formation of u2 the output voltage space vectors have to show
identical phase in τac and τab (cf. Fig. 10), what is achieved by
identical values of the duty cycle of the active switching states (100)
and (110) in τac and τab.
τ (100),ac
τ (100),ab
δ (100),ac =
= δ (100),ab =
= δ (100)
(7)
τ ac
τ ab
δ (110),ac =
τ (110),ac
τ (110),ab
= δ (110),ab =
= δ (110) .
τ ac
τ ab
With u (100) = 23 u and u (110) = 23 ue
j
π
3
(8)
for DC link voltage u we then
have for the voltage space vector formed in the average over ½TP
u *2 =
2
3
TP
2
(u acτ (100),ac + u abτ (100),ab + u ac e
j
π
3τ
(110 ),ac
+ u ab e
j
π
3τ
(110 ),ab )
(9)
and considering Eq.(7) and Eq.(8)
u *2
=
=
=
π
π
2
j
j
3
(u acτ ac δ (100) + u abτ bc δ (100) + u acτ ac δ (110) e 3 + u abτ bc δ (110) e 3
TP
2
π
j
τ ac
τ
τ
τ
2 (u
+ u ab 1 ab )δ (100) + 23 (u ac 1 ac + u ab 1 ab ) e 3 δ (110)
ac 1
3
T
T
T
T
2 P
2 P
2 P
2 P
π
j
2
2
3δ
(110) .
3 (u ac d ac + u ab d ab )δ (100 ) + 3 (u ac d ac + u ab d ab ) e
With the local average value ū of the DC link voltage
u = u ab d ab + u ac d ac
(10)
(11)
this results in
u *2 = 23 u δ (100) + 23 u e
j
π
3δ
(110 )
.
(12)
Therefore, for calculating the on-times of the active switching states
we could directly refer to the local average value ū of the DC link
voltage and could omit the detailed consideration of the line-to-line
input voltages uac and uab in τac and τab. We then have
δ (100) =
3
2
| u *2 |
cos(ϕ 2* + π6 )
1u
2
δ (110) =
3
2
| u *2 |
sin ϕ 2*
1u
2
(13)
and, therefore for the absolute turn-on times τ(100),ac τ(100),ab and
τ(110),ac τ(110),ab of the output voltage space vectors u2,(100) and u2,(110)
in τac and τab.
Uˆ *
τ (100),ac = − 2 TP 22 u c cos(ϕ 2* + π6 )
3 3
Uˆ
1
τ (100),ab
Uˆ *
= − 2 TP 22 u b cos(ϕ 2* + π6 )
3 3
Uˆ
τ (110),ac
Uˆ *
= − 2 TP 22 u c sin ϕ 2*
3 3
Uˆ
τ (110),ab
Uˆ *
= − 2 TP 22 u b sin ϕ 2*
3 3
Uˆ
1
(14)
1
1
As can be seen from Eq.(11) the local average value ū of the DC link
voltage shows a variation with six times the input frequency
1
u = 32 Uˆ 1
(15)
cos(ω1t )
(cf. Fig.8) and a minimum of
u
= 3 2 Uˆ
min
1
(16)
(cf. Fig. 10). This does allow the formation of an output phase
voltage system
u ∗ = Uˆ * cos(ω t + ϕ )
2
A
2
0
uB
∗
= Uˆ 2* cos(ω 2 t − 23π + ϕ 0 )
uC
∗
= Uˆ 2* cos(ω 2 t +
2π
3
(17)
+ ϕ0 )
(ϕ0 = 0 is selected here for the sake of simplicity what, however,
does not restrict the general validity of the analysis) having a
maximum fundamental amplitude Û2* of 3/2 Û1. Therefore, we
have the relation for the voltage transfer ratio M of the matrix
converter as also known, e.g. from [2]
Uˆ *
3
M = 2 ≤
.
(18)
ˆ
2
U1
For given constant output voltage amplitude Û2* and/or given
absolute value |u2*| = Û2* of the output voltage space vector the
variation of ū does make necessary a variation of the inverter
modulation index,
| u * | 4 Uˆ 2*
cos(ω1t ) .
(19)
m2 = 1 2 =
3 Uˆ 1
u
2
In order to ensure, that the free-wheeling state of the inverter does
remain for a minimum time τmin (in ϕ2* = 0...π/6 we have
τmin = min(τ(111),ac + τ(111),ac), as required for changing the rectifier
switching state at zero DC link current, the modulation index of the
inverter and/or the output voltage reference amplitude has to be
limited to
τ
3 ˆ
U1 (1 − 4 min ) .
2
TP
Uˆ 2* ≤
(20)
Therefore, the achievable maximum system voltage transfer ratio
will be slightly lower than the theoretical maximum Mmax = 3/2 (cf.
Eq.(18)).
For the sake of minimizing the inverter switching losses, in
ϕ2* = 0...π/6 only the free-wheeling state (111) is incorporated into
the switching state sequence. Accordingly, output phase A remains
clamped within the whole interval to the positive DC link bus (cf.
Fig.19). The clamping intervals of all phases over an output voltage
period can be seen in Tab.5. Each output phase remains clamped
within a π/3−wide interval which is arranged symmetrically in time
around the maxima and minima of the corresponding phase voltage.
Accordingly, minimum switching losses will result for ohmic load.
In case the system is supplying an inductive load, the phase
currents and the corresponding phase voltages will show a phase
displacement Φ2,
i A = Iˆ2 cos(ω 2 t + Φ 2 )
(21)
i = Iˆ cos(ω t − 2π + Φ ) .
B
2
2
iC = Iˆ2 cos(ω 2 t +
3
2π
3
2
+ Φ2 )
The clamping intervals then should be shifted accordingly in order to
maintain low switching losses. E.g., phase A then should be clamped
in ϕ2 = 0...π/3 (clamping of A to p) and ϕ2* = π...4π/3 (clamping of A
to n). A detailed analysis of minimum switching loss clamping of
DC voltage link inverters has been given in [22]. We therefore
would like to omit here a further discussion for the sake of brevity.
In connection with the formation of the input current (cf. Eq.(3))
we still have to prove that the local average i of the DC link current
i shows a constant value. With Eqs.(7) and (8) we have
iac = τ 1 (i Aδ (100),acτ ac − iC δ (110),acτ ac ) = i Aδ (100) − iC δ (110)
(22)
iab = τ 1 (i Aδ (100),abτ ab − iC δ (110),abτ ab ) = i Aδ (100) − iC δ (110)
(23)
ac
Analogous to referring the analysis of the formation of the inverter
output voltage to the local average value ū of the DC link voltage,
one could give a description of the rectifier input current formation
based on the local average value i of the DC link current.
There, the variation of i results in a variation of the diameter of
the hexagon which is defined by the input current space vectors
resulting for the different rectifier switching states. For controlling
the rectifier according to Eq.(2) the tip of the input current space
vector i 1 being formed in the average over a pulse period will move
along the side µ of the hexagon (cf. Fig.11). In the interval
ϕ1= 0...π/6 considered, this results in a variation of the modulation
index of the rectifier
|i |
1
m1 = 1 =
,
(25)
i
cos ω1t
i.e. would not lead to a space vector i 1 of constant absolute value
i 1 and constant angular frequency ω1 and/or to sinusoidally shaped
local average values of the input phase currents for a constant value
of i . However, due to the variation of i according to Eq.(24) the
hexagon diameter does change such that the tip of i 1 actually does
move along a circular trajectory and/or sinusoidal local average
values of the input phase currents are generated,
i = Iˆ cos(ω t )
a
1
1
ib = Iˆ1 cos(ω1t −
2π
3
)
ic = Iˆ1 cos(ω1t +
2π
3
)
(26)
This can be verified immediately by combining Eqs.(24) and (25)
Uˆ *
1
(27)
| i 1 | = i m1 = Iˆ2 2 cos Φ 2 cos(ω1t )
= Iˆ1 .
ˆ
cos ω1t
U1
Fig.11: Rectifier input current space
vectors resulting in the average over
a pulse half period and trajectory of
the space vector i 1 within the input
voltage fundamental. The diameter
of the space vector hexagon is determined by the local DC link current
average value i varying over the fundamental period. The considerations
are limited to ϕ1=0...π/6. The range
of variation of the hexagon is shown
by a dotted area.
and
ab
Accordingly, in τac and τab an equal average value
Uˆ *
i = iac = iab = 43 m2 Iˆ2 cos Φ 2 = Iˆ2 2 cos Φ 2 cos(ω1t )
Uˆ
(24)
1
of i is available for input current formation as assumed in Eq.(3).
The variation of i is inverse to the variation of ū what does result in
a constant local average value of the DC link power flow p = u i ,
and or of the power taken from the input and/or supplied to the load.
(a)
(b)
(c)
Fig. 10: Inverter output voltage space vectors u(100) and u(110) and average
output voltage vector in τac (a) and τab (b) (the range of variation of and uac
and uab is shown by a dotted area). Furthermore shown: Formation of the
inverter output voltage space vector reference value u2* based on the average
value ū of the DC link voltage u over half a pulse period (c). The minimum
value of ū does define a maximum available inverter output phase voltage
amplitude of 3 /2 Û1.
ϕ2=ω2t
uA
uB
uC
0 ... π/6
π/6 ... π/2
π/2 ... 5π/6
5π/6 ... 7π/6
7π/6 ... 3π/2
3π/2 ... 11π/6
11π/6 ... 0
up
up , un
up , un
un
un , up
un , up
up
up , un
up , un
up
up , un
up , un
un
un , up
up , un
un
up , un
up , un
up
up , un
up , un
TABLE 5. Intervals of an output voltage period, and corresponding potentials
of the inverter output phases; clamping of an output phase to the positive DC
bus p (potential up) or to the negative DC bus n (potential un) is pointed out
by a dotted area.
As is clear form Fig. 9, the inverter switching frequency is two times
the rectifier switching frequency,
f P ,1 = 2 f P , 2 ,
(28)
as a full switching cycle of the inverter is contained in each rectifier
pulse half interval. Basically, also a different ratio of the pulse
frequency could be selected as long as it is ensured that the
commutation of the rectifier stage is at zero DC link current, i.e. is
placed in the inverter free-wheeling interval.
V. OPERATING RANGE OF SMC, VSMC AND USMC
In the following we will briefly show which space vectors are
available for output voltage and input current formation for the
SMC, VSMC and USMC and/or which restrictions of the operating
range have to be accepted in consequence of a simplification of the
circuit structure.
A. Admissible Converter Switching States
A.1 SMC and VSMC
For space vector description of input voltage and input current we
have for the instantaneous active power supplied to the DC link
p = 32 ℜ{u 1∗ i1 (n)} = u i
(29)
*
(u1 does denote the complex conjugate of u1). The DC link current i
as impressed by the inverter does define the absolute value of the
input current space vectors i1(n) resulting for the different rectifier
switching states n. The voltage u(n) occurring at the rectifier output
then can be determined with reference to Eq.(29) by projection of the
current space vectors along the input voltage space vector u1 (cf.
Fig.12(a), [18]). The condition u(n)>0 there is met only by such
switching states for which the corresponding current space vector
shows a component in the direction of u1 and/or is located in the
half-plane defined by the direction of u1. Therefore, three switching
states are not available as they would result in a negative DC link
voltage.
If now i does change its sign what could be achieved by inverting the switching state of the output stage, e.g., by changing form
(100) to (011), such switching states and/or current space vectors
i1(n) are admissible which do result negative DC link power, p<0,
i.e. do show a negative projection onto u1. As by changing the sign
of i also the current space vectors are inverted, such switching states
are identical to admissible switching states for i>0. In summary, all
current space vectors available for the CMC can be formed also by
the SMC or VSMC despite always only three out of six active rectifier switching states are employed (cf. also Tab.3, lines 37 - 72).
Fig.12: Input current space vectors and/or rectifier switching states admissible for a given angular position ϕ1 of the input voltage space vector u1.
Current space vectors not available are shown by broken lines. The rectifier
switching states n are denoted by a combination of transistors switching
functions in matrix form, where each row does characterize the switching
state of a bridge leg. (a): DC link current i>0, (b): DC link current i < 0.
A.2 USMC
For the USMC besides the restriction u>0 according to the
unidirectional connection of the input stage bridge legs to the DC
bus also i > 0 has to be guaranteed. Therefore, as shown in Section
A.1 for the formation of the input current only three space vectors
are available which are defined by the instantaneous angular position
of u1 (cf. Fig. 12(a)). As can be seen immediately, therefore, the
phase displacement of the input current fundamental i 1 and of the
input voltage u1 is limited to
Φ1 ∈ ( − π6 , + π6 ) .
(30)
For the formation of an input current of higher phase displacement
current space vectors would not be continuously available over the
fundamental period. However, this restriction is of low importance
as in most cases ohmic mains behavior will be required and Eq.(30)
will allow a compensation of the capacitive reactive power of the
input filter capacitors at rated load.
However, as will be shown in the following, by i > 0 also the
admissible load power factor is restricted. We have for the inverter
stage in analogy to Eq.(29)
p = 23 ℜ{u ∗2 (m) i 2 } = u i
(31)
*
where u2 (m) does denote the complex conjugate of the output
voltage space vector being present for a switching state m. In order
to ensure i(m)>0, only output voltage space vectors and/or switching
states m are admissible which are located in the half-plane defined
by the output current space vector i2 (cf. Fig.13). We therefore have
for the output stage analogous to the input stage the requirement
Φ 2 ∈ (− π6 , + π6 )
(32)
(cf. Fig.14). For supplying heavily inductive loads this limitation
could be satisfied by compensating capacitors.
Fig.13: Output voltage space vectors
and/or inverter switching states admissible for the USMC for a given
angular position ϕ2*+Φ2 of the output
current space vector i2. Voltage space
vectors not available are shown by
broken lines. The inverter switching
states m are denoted by the combination of the bridge leg switching
functions.
Fig.14: Input current space vectors (a) and output voltage space vectors (b)
available for the USMC for ua>0, ub, uc<0 (corresponding angular interval of
u1 pointed out by a dotted area) and ia>0, ib, ic<0 (corresponding angular
interval of i2 pointed out by a dotted area). Only current space vectors
showing a phase displacement Φ2 of less than π/6 to the input voltage can be
formed; furthermore, the voltage space vectors u2* to be formed at the output
have to remain within ± π/6 phase displacement to the output current i2 in
order not to generate a negative DC link current.
B. Voltage and Current Transfer Ratio
With reference to Eqs.(19), (24), and (25) we have for the amplitude
of the input current fundamental
Iˆ = m i = 3 m m Iˆ cos Φ
(33)
1
1
4
1
2 2
2
output, i.e. for i ≠ 0 and could be limited by the required voltage
transfer ratio. Based on Eqs.(37) and (39) there follows for the
maximum admissible phase displacement
cos Φ1,max =
2
3
M
Φ1 ≤ arccos(
2
3
M) .
M ≤ 3 2
(40)
and/or
and accordingly for the current amplitude transfer ratio of the matrix
converter
Iˆ1 3
(34)
= 4 m1m2 cos Φ 2 .
Iˆ2
Accordingly, with reference to
Q 2 = ( 3 Uˆ Iˆ ) 2 − P 2
Considering the input and output power balance
3 Uˆ Iˆ = u i = 3 Uˆ * Iˆ cos Φ ,
where P denotes the active power, we have for the maximum fundamental reactive power Q1 which could be generated at the input
1 1
2
2 2
2
2
(35)
where losses are neglected and cos Φ1 = 1 is assumed, there follows
for the voltage amplitude transfer ratio
Uˆ 2* Iˆ1
1
=
= 43 m1m2 .
(36)
Uˆ 1 Iˆ2 cos Φ 2
Voltage and current transfer of the system therefore are
characterized by a transfer ratio
M = 34 m1m2
(37)
where M ∈ (0, 3/2); introducing Eq.(37) into Eqs.(34) and (36)
there follows
Uˆ 2* = M Uˆ1
(38)
Iˆ = M Iˆ cos Φ
1
2
2
(cf. Eq.(18)).
The basic function of the system concerning the conversion of
voltage and current can be shown with reference to the amplitudes
Û1, Û2 of the input voltage and of the output reference voltage and
the amplitudes Î1, Î2 of the input current fundamental and the output
current (phase difference cos Φ2) as depicted in Fig.15.
In case a phase difference Φ1 of input current and voltage would
be set by proper control of the input stage we would have
Uˆ 2* = M Uˆ 1 cos Φ1
(39)
Iˆ = M Iˆ cos Φ
1
2
2
It is important to point out that therefore the maximum voltage
transfer ratio (Û2*/Û1)max = 3/2 is only available for cos Φ1 = 1.
Another interesting property of the matrix converter is that the
formation of an output voltage, i.e. Û2*/Û1 ≠ 0 is not connected to the
formation of an input current fundamental, i.e. Î1/Î2 = 0 could be
valid. This can be explained by the fact that only active power is
transferred via the DC link, accordingly, for a fundamental
displacement factor of the output current of cos Φ2 = 0 in the
average of a pulse period no current flow does occur in the DC link,
i.e. i = 0 , where a finite value of i is a requirement for the
formation of an input current.
On the other hand, Û2*/Û1 = 0 is possible for Î1/Î2 ≠ 0 in case
the control of the input stage is according to cos Φ1 = 0 where the
segments of the line-to-line input voltages occurring at the rectifier
output do not form a local average value ū of the DC link voltage
and therefore no voltage is available for a formation of an output
voltage fundamental, i.e. Û2*= 0.
Furthermore, we would like to note that input and output side are
basically decoupled concerning the formation of fundamental
reactive power, however, the generation of reactive power at the
input side is possible only in case active power is transferred to the
1
2
(41)
(42)
1 1
Q1,max = P
3
4M 2
−1 .
(43)
m1 = cos-1(ω1t)
m*2 =
3
2
*
*
U2 4 U2
cos(ω1t)
= 3
1
2 u
U1
1
2
u
U1
*
U2
3
4
I1
(cos(Φ1) = 1)
I2 cos(Φ2)
i
Matrix Converter
Fig. 15: Voltage and current transfer of a matrix converter shown with
reference to the amplitudes of the fundamentals of the input and output
voltages and currents.
VI. GUIDELINES FOR DIMENSIONING OF THE SMC, VSMC AND USMC
In the following analytical formulae for the current stresses on the
power semiconductors will be derived. There, the basic idea is to
define an average modulation index of the output stage and/or a
global average value Ū of the DC link voltage. Thereby, the matrix
converter is transferred into a constant DC link voltage system and
the relation of input and output frequency is not longer of
importance. Considering the limited range of variation of the local
average value ū of the DC link voltage (cf. Fig. 8) we could expect a
sufficiently accurate approximation of the actual circuit behavior
despite this drastic simplification.
The current stresses will be given for Φ2 ∈ (0...π/2). Based on
this, stresses on the components occurring for other phase
displacement values can be determined by symmetry considerations.
A. Global Average Modulation
Based on Eq.(15) we have for the global average value of the DC
link voltage
(44)
U = π9 ln( 3 )Uˆ 1 .
As is immediately clear, the current stress on the input stage power
semiconductors is determined by the DC link current average and
rms value. We therefore will calculate the characteristic DC link
current values in the following.
Corresponding to Eq.(24), the global average value of the DC
link current results in
I = 3 M Iˆ cos Φ
(45)
4
2 2
2
(output current ripple neglected) where
U
M2 = 1 2
U
2
(46)
does define a global average modulation index. With reference to
[23] we furthermore have for the global rms value of the DC link
current
I rms 2 = π3 M 2 Iˆ2 2 ( 14 + cos 2 Φ 2 ) .
(47)
The DC link current i is determined by the output phase currents and
by the inverter switching state and/or switching functions
i = i A s A + i B s B + iC s C .
(48)
In the angle interval ϕ2 = ω2t = 0...π/3 the active switching states
sABC = (100) and (110) are employed where the DC link current is
for s ABC = (100)
ì+ i A
i=í
(49)
for s ABC = (110).
îi A + i B = −iC
Accordingly, for Φ2 = π/6...π/2 the DC link current i will show a
negative component due to iA < 0 for ϕ2 ∈(π/2−Φ2...π/3) (cf.
Eq.(21)) in the interval ϕ2 = 0...π/3 which is considered in the
following. The sign of i is of importance for splitting the DC link
current to the respective power semiconductors of the input stage
which are denominated as given in Fig.16.
Dap
p
p
...
Spa
...
Dap
Dpa
Sapa
p
a
Dpa
Dap
Dna
Dan
a
a
Dapn
=
3
π
Dna
n
...
n
(a)
(b)
I = I + −I −
is valid.
A.2 Global DC Link Current RMS Value
A.2.1 PHASE DISPLACEMENT Φ2 ∈ (0...π/6)
As is immediately clear from the considerations in Section VI.A.1.1
we have for the global rms value of the DC link current components
(55)
I −,rms 2 =
Dna
n
...
=
(c)
components i+ of i, i− does denote the negative components). Due to
i>0 the diodes Dap will not be involved in the current conduction.
A.1.2 PHASE DISPLACEMENT Φ2 ∈ (π/6...π/2)
For the global average value of the positive DC link current
component i+ which is carried by the diodes Dap we have
π 2− Φ 2
ò i Aδ (100) dϕ 2 ] =
0
(( π6 − Φ 2 ) sin( π3 + Φ 2 ) + sin(Φ 2 − π6 ))]
where
3
π
3
π
π 2− Φ 2
ò
2
3
4
(56)
sin( 2Φ 2 − π3 )]
δ (100) dϕ 2 =
M 2 I 2 2 [ 43 + 14 sin(2Φ 2 + π6 ) − sin(Φ 2 + π3 )]
I rms 2 = I + ,rms 2 + I −,rms 2
(57)
(58)
is valid due to the fact that i+ and i− do not overlap in time.
B. Stresses on the Components of the Output Stage
As given in [23] we have for the current stresses on the output stage
power transistors and diodes
I = 1 Iˆ ( 1 + 1 M cos Φ )
2 2 π
2
4
I DA = 12 Iˆ2 ( π1 − 14 M 2
I SA,rms 2 = Iˆ2 2 ( 18 + 31π
2
cos Φ 2 )
M 2 cos Φ 2 )
(59)
I DA,rms 2 = Iˆ2 2 ( 18 − 31π M 2 cos Φ 2 ).
C. Stresses on the Power Semiconductors of the Input Stage
C.1 Phase Displacement Φ2 ∈ (0...π/6)
C.1.1 CURRENT AVERAGE VALUES
Due to the symmetric average distribution of the DC link current i to
the rectifier bridge legs we have
I
= 1 I = 1 M Iˆ cos Φ
Dap
(51)
0
M 2 Iˆ2 [sin(Φ 2 + π3 ) −
iA
π 2− Φ 2
2
ò i A δ (100) dϕ 2 ] =
2
π 3
3
π
SA
is valid ( I + does denote the global average value of the positive
3
π
I −, rms 2 = 0
and
=
For Φ2 ∈ (0...π/6) the DC link current is comprised of only positive
components and/or output current segments, i.e. we have within the
whole pulse period i > 0, accordingly
I + = I and I − = 0
(50)
0
(54)
0
A.1.1 PHASE DISPLACEMENT Φ2 ∈ (0...π/6)
= 34 M 2 Iˆ2 [cos Φ 2 +
I rms 2 = I + ,rms 2
π 3
A.1 Global DC Link Current Average Value
All findings described in the following are shown in graphical form
in Fig. 17.
π 3
(53)
I + ,rms 2 = π3 [ ò iC 2δ (110) dϕ 2 +
Dpna
Fig.16: Structure of a bridge leg of the VSMC (a), SMC (b) and USMC (c)
and denomination of the diodes and power transistors. Identical denomination
of components for the different bridge leg topologies does indicate an equal
current stress, e.g. the average and rms current stress of diode Dpa of the
VSMC is identical to the current stress on diode Dpa of the USMC.
I + = π3 [ ò ( −iC )δ (110) dϕ 2 +
M 2 Iˆ2 [( π6 + 3 − Φ 2 ) sin(Φ 2 + π3 ) − 2 cos Φ 2 ]
where
Dapn
...
(52)
In analogy to Section VI.A.2.1 we have
San
Dan
ò ( − i A )δ (100) dϕ 2 =
π 2 −Φ 2
3 3
4π
Sana
Dna
π 3
A.2.2 PHASE DISPLACEMENT Φ2 ∈ (π/6...π/2)
Sa
Dpna
I− =
...
Dap
Sa
and for the global average value of the negative component i− (cf.
Fig. 16)
3
4
2 2
I Sapa = I Dpna = I ap
I Sa = 2 I Dap .
2
(60)
1.0
1.0
Ir
Irms,r
Irms,r
Fig. 17: Graphical representation of the normalized (index r)
dependency of (a): the global
average value of the DC link
current i and of the current
components i+ and i− (cf.
Section VI.A.1) on the output
current phase displacement Φ2;
normalization basis: M2Î2; and
(b): the global rms value of the
DC link current i and of the
current components i+ and i−
(cf. Section VI.A.2) on the
output current phase displacement Φ2; normalization basis
M2Î2.
Ir
0.6
0.6
0.4
0.4
I+,rms,r
0.2
I−,rms,r
Ir
0.2
0
I−,r
I−,r = 0
π/6
0
I+,r
π/3
Φ2 π/2
0
I−,rms,r = 0
π/6
0
According to i>0 the diodes Dpa, Dan and the switches Spa, San do not
participate in the current conduction, i.e. iDpa = iSpa = 0 and/or
I Dpa = I Spa = 0 .
(61)
is valid.
C.1.2 CURRENT RMS VALUES
In analogy to Section VI.C.1.1 we have
I Dap ,rms 2 = 13 I rms 2 = 1 M 2 Iˆ2 2 ( 14 + cos 2 Φ 2 )
3π
2
2
I Sapa,rms = I Dpna,rms = I Dap ,rms 2
The analytical expressions given in Sections VI.C and VI.D have
been verified with excellent consistency by digital simulations (cf.
Section VII.) irrespective of the relation of input and output
frequency, output stage modulation index and output current phase
displacement. The simulation results are compiled in Fig. 18 where
results of the analytical approximation are shown in brackets.
(63)
Positive components i+ of i are carried by diodes Dap, negative
components i− of i are taken over by diodes Dpa. Accordingly, there
results for the global average current stress on the devices
I Dap = 13 I + =
10
I Sapa = I Dpna = ( I Dap + I Dpa )
(1.05) (0.95) (1.27)
Dap
Dpa
Sapa
DA
SA
(2.09)(2.27)
100
10
(c)
(0.033) (0.67)(0.70) (1.11) (1.52)
(0.21) (0.48)
100
(64)
I Sa = 2 I Dap
(0.32)
(2.41)
RMS
f2
Hz
(( π6 − Φ 2 ) sin( π3 + Φ 2 ) + sin(Φ 2 − π6 ))]
M 2 Iˆ2 [( π6 + 3 − Φ 2 ) sin(Φ 2 + π3 ) − 2 cos Φ 2 ]
(2.12)
(1.33) (1.53)
f2
Hz
10
I Spa = I Dpa
(d) (0.024) (0.50) (0.56) (1.03) (1.31) (1.45) (2.03)
In analogy to Section VI.C.2.1 we have
I Dap ,rms 2 = 13 I + ,rms 2 = 1 M 2 Iˆ2 2 [sin(Φ 2 + π3 ) − 43 sin(2Φ 2 − π3 )]
3π
2
1
1
I Dpa ,rms = 3 I −,rms =
M 2 I 2 2 [ 34 + 14 sin( 2Φ 2 + π6 ) − sin(Φ 2 + π3 )]
3π
I Sapa ,rms 2 = ( I Dap ,rms 2 + I Dpa ,rms 2 ) = 13 I rms 2 =
3
π
M 2 Iˆ2 2 ( 14 + cos 2 Φ 2 )
(65)
(1.32)
(0.18) (0.53)
100
C.2.2 CURRENT RMS VALUES
I Sa ,rms 2 = I Dpa ,rms 2 .
(1.27) (1.43)
f2
Hz
C.2.1 CURRENT AVERAGE VALUES
I Spa ,rms 2 = I Dpa ,rms 2
(0.65)
AVG
(b)
C.2 Phase Displacement Φ2 ∈ (π/6...π/2)
3
4π
(0.16)
100
I Dpa ,rms = I Spa ,rms = 0 .
I Dpa = 13 I − =
π/2
D. Comparison to Digital Simulation
(a)
and
3
π
Φ2
π/3
(62)
I Sa ,rms 2 = 2 I Dap,rms 2
= 14 M 2 Iˆ2 [cos Φ 2 +
Irms,r
f2
Hz
10
0
0.5
1.0
1.5
I; Irms / A 2.5
Fig.18: Average and rms current stresses on the power semiconductors as
determined by simulations and analytical approximations (shown in
brackets): Modulation index M = 0.8 in (a), (c) and M = 0.6 in (b), (d); output
phase displacement Φ2 = 0 in (a), (b) and Φ2 = π/3 in (c), (d). Input
frequency f1 = 50 Hz; amplitude of the output current fundamental Î2 = 5 A,
input line-to-line voltage U1,l-l = 400 V.
Part II: Experimental Analysis of the Very Sparse Matrix Converter
M. Baumann*, F. Stögerer*, J.W. Kolar
VII. SIMULATION RESULTS
VIII. PRACTICAL REALIZATION
In this section the theoretical considerations of Section IV are
verified by digital simulation using CASPOC®. The simulation
parameters are defined with reference to the operating conditions of
the experimental investigations described in Section VIII
A prototype of the Very Sparse Matrix Converter (VSMC) having
the following rated operating parameters
U 1,l −l = 400 V
P = 2 kW
f1 = 50 Hz
U 2 = 95 V
f P ,1 = 15.625 kHz
f 2 = 100 Hz
(66)
For the sake of simplicity no LC input filter was considered but the
input voltage has been assumed to be directly applied to the
converter input. There, the time behavior of the mains phase currents
iN,i, i.e. of the input filter inductor currents of a practical system was
obtained by averaging the discontinuous rectifier input currents over
one pulse half period. The simulation results are compiled in Fig.19,
where (d) shows the purely sinusoidal behavior of input and output
quantities. The local average ia of the rectifier stage input phase
current ia is lying in phase with the corresponding mains phase
voltage ua , accordingly the system shows ohmic fundamental mains
behavior (cf. Eq.(4)) As Fig.19(a) clearly shows, each power
transistor is clamped within a π/3-wide interval of an input and/or
output fundamental period what is indicated by a voltage across the
power transistors of u Sbpb = 0 and/or u S Bn = 0. In Fig.19(f) the time
behavior of the DC link current i is given where i>0, and/or i=i+, i−
is valid (cf. Eq.(50)), according to the output power factor of
cos Φ2=0.961 (cf. Fig.19(d), load phase displacement of Φ2 < π/6).
u,u
ucb
i=a
b
P = 10 kW
f1 = 50 Hz
U 1,l −l = 400 V
f P ,1 = 15.625 kHz
has been realized using standard power semiconductors, i.e.
• IGBTs: IXYS FII 50-12E in ISOPLUS i4-PACTM package
[24]. The package does contain a full IGBT bridge leg, i.e. two
power transistors of latest IGBT technology which can be
directly employed in the output stage. For the realization of the
input stage only one transistor per package has been utilized,
due to the fact that no package containing only a single IGBT
of latest technology is currently available.
• Diodes: IXYS DSEP 29-12A in TO220 [25].
An isolated package containing a four-quadrant switch (cf. Fig. 20)
consisting of one IGBT of type FII 50-12E and of four diodes of
type DSEP 29-12A rated for 50 A/1200 V is currently under development in collaboration with IXYS Semicond. GmbH [26]. This
switch will be employed in the experimental system in a next step.
Furthermore, we would like to point out that for realizing the
input stage of the USMC a power module VUI 30-12N1 containing
the power semiconductors of one bridge leg is available (cf. [27,
28]).
c
j=A
B
uA
C
ij
uSBn
(a)
0.01
0.02
iA,uA
iN,i
uSbpb
0
(67)
u
(b)
0
0.01
ia
ia,ua
0.02
iB
(c)
0
0.005
j=A
iB,ia
0.01
B
C
ij
iB,uB
iSapa
i
i
(f)
u0N
(d)
0
0.01
0.02
(e)
0
0.01
0.02
0
0.01
0.02
Fig. 19: Simulation results for operating conditions given in Eq.(66), (a) DC link voltage u and local average value ū, line-line voltage ucb, voltage across input
stage power transistor Sbpb and voltage across output stage power transistor SBn; (b) mains phase currents iN,i, i=a,b,c, and output currents ij; j=A,B,C; (c) output
current iA, output voltage (local average value ūA and discontinuous behavior uA) and DC link voltage u; (d) local average īa of input phase current ia and input
voltage ua and output current and voltage (local average value) in phase B; (e) input and output currents in phases a (local average) and B, current through
input power transistor Sapa and voltage between input and output neutral point u0N; (f) output currents and DC link current (discontinuous behavior i and local
average value ī). Voltage scales: 500 V/div in (a), (e); 250 V/div in (b): uA, u; (d): uA; 100 V/div in (c): ūA; (d): ūB. Current scales: 20 A/div in (c); 10 A/div in
(d): iB; (e); 5 A/div in (b); (d): ia; (f).
1
3
5
(a)
4
2
Fig. 20: Structure and
package style of the
novel
four-quadrant
VSMC switch FIO 5012BD: (a) sectional view
(b) and (b) internal structure.
In Fig.21 the prototype of the VSMC is shown. The overall dimensions of the system are 20.0×24.0×8.5cm³ (i.e. 7.9×9.45×3.45 in³),
the total weight is 3.6 kg. The LC input filter was realized employing
• 3 iron powder core inductors, L = 270 µH @ zero current
(diameter: 60 mm, height: 30 mm), and
• 3×4 foil capacitors in ∆-connection, C = 1µF (dimensions:
(21×26×15)mm³) [29].
Fig. 21: Prototype of the 10kW VSMC. The control unit (realized using a
floating point digital signal processor ADSP-21061 SHARC [14] in
combination with programmable logic devices MAX 7000S) is not shown.
A. Switching Behavior of Input Stage Power Transistors
The switching behavior of the input stage power transistors for the
transition from switching state un=uc, up=ua → un=uc, up=ub, and
vice versa has been investigated in detail for the following operating
conditions
U2,l-l = 86 V
P0 = 700 W.
(68)
UN,l-l = 440 V
According to Section IV (cf. Fig. 9) the commutation of the input
stage is placed in the free-wheeling interval of the output stage,
therefore, basically no switching losses are expected for the input
stage. In Fig. 22(a) the time behavior of the DC link voltage u and of
the current via the power transistor Sbpb within a part of a pulse
period TP are shown for the transition from a higher to a lower DC
voltage level (and vice versa); due to the free-wheeling operation of
the output stage we have zero current via Sbpb. In Fig. 22(b) the gate-
to-emitter voltages of the switching power transistors are depicted
(power transistor Sbpb is turned on and power transistor Sapa is turned
off) where a delay-time td ≈ 700ns between turn-off of a transistor
and turn-on of the subsequent transistor is provided in order to avoid
a short circuit between the mains phases during a commutation.
However, when Sbpb is turned on a current peak occurs which results
from
• the charging current of the parasitic DC link capacitance, and
• the tail-current of the IGBT which has been carrying current in
the prior switching state.
This current peak has been found to be approximately independent
from the load conditions and does result in switching losses of the
input power transistors. In Fig.22(c) the transition from a lower to a
higher DC voltage level is depicted where the behavior is basically
identical to Fig.22(b). One has to point out that power transistor Sbpb
is taking over the blocking voltage only when the gate-to-emitter
voltage of power transistor Sapa has reached the threshold-voltage,
i.e. when Sapa is turned on. Furthermore, we want to note that due to
the low-inductance biplanar wiring of the power semiconductors the
measurement of the power semiconductor currents was partly
obtained by subtracting and/or adding currents through neighboring
diodes by a clip-on type current probe.
B. Three-Phase Operation
The simulation results given in Section VII are verified by the
experimental analysis as derived from the VSMC prototype shown
in Fig.21 for the operating parameters given in Eq.(66), cf. Figs.23
and 24. An excellent consistency of the simulation results and of
experimental results has been found, as can be seen immediately by
comparing Figs. 19, 23 and 24 . Insignificant differences are due to
the fact that
• input and output frequency of the prototype are not
synchronized what does result in a varying phase displacement
of the fundamentals of the input and output phase quantities,
• the output frequency for the experimental investigation has not
been set to exactly twice the input frequency, accordingly the
envelope of, e.g., the voltages across the output power transistor
SBn does show a slightly different shape for the simulation and
the experimental analysis (cf. Figs.19(a) and 23(a)), and
u
(b)
(c)
iSbpb
uSapa
uSbpb
(a)
uGE,Sbpb
uGE,Sapa
uSbpb
iSbpb
uGE,Sapa
uGE,Sbpb
uSbpb
iSbpb
pSbpb
pSbpb
(b)
(c)
Fig. 22: Results of the experimental investigation of the switching behavior of the input stage power transistors for a mains phase condition corresponding to
ϕ1=π/12 for the operating parameters given in (68): (a): Global behavior of the current via input power transistor Sbpb, DC link voltage u and corresponding
voltages across power transistors Sbpb and Sbpb being involved in the switching actions considered. (b): Transition from higher to lower DC link voltage level:
gate-to-emitter voltages uGE of involved power transistors, voltage across power transistor Sbpb and current through the power transistor, calculated power loss
p occurring for Sbpb. (c):Transition from lower to higher DC link voltage level, cf. (b). Current scales: 5 A/div, voltage scales: 100 V/div in (a); 50 V/div for
the voltage across the power transistor Sbpb in (b),(c); 10 V/div for the gate-to-emitter voltages in (b) and (c).
i=a
u
ubc
b
c
iN,i
j=A
B
C
iA;uA
uA
uSbpb
uSBn
ij
(a)
(b)
u
(c)
Fig. 23: Experimental results for operating parameters (66): (a): DC link voltage u and corresponding local average value ū as determined by a two-stage
switching frequency RC filter, line-line voltage ucb, voltage across input stage power transistor Sbpb and output stage power transistor SBn; (b): mains phase
currents iN,i , i=a,b,c, and output currents ij; j=A,B,C. (c) output current iA, output voltage (local average value ūA and actual discontinuous voltage uA) and DC
link voltage u. Voltage and current scales: cf. Fig. 24.
ia;ua
Fig. 24: Fig. 25 conti-
iB;uB nued: (d) input filter in-
(d)
ia
iB
iB;ia
iSbpb
u0N
(e)
ductor current and voltage in phase a and output current and voltage
(local average value) in
phase B; (e) input current
in phase a and output
current in phase B, current through input power
transistor Sbpb and voltage
between input neutral
point 0 and output neutral
point N, u0N. Voltage
scales: 500 V/div in (a),
(e); 250 V/div in (b): uA,
u; (d): uA; 100 V/div in
(c): ūA; (d): ūB. Current
scales: 20 A/div in (c);
10 A/div in (d): iB; (e);
5 A/div in (b); (d): ia.
• due to the dead-times which have to be considered for the
switching state change of the power transistors of each output
stage bridge leg, the local average of the output voltage (as
determined by a two-stage switching frequency RC-filter) does
show a low-frequency distortion (cf. Fig.23(c)), this effect could
be avoided by a proper pre-control which will be implemented in
a next step.
IX. CONCLUSIONS
As proposed in this paper, the functionality of a conventional threephase AC-AC matrix converter (CMC) could be achieved by
employing only 15 IGBTs based on the Sparse Matrix Converter
Concept (SMC). There, a zero DC link current commutation scheme
does provide lower control complexity and potentially higher
reliability as known multi-step commutation strategies. Zero DC link
current commutation also would allow to realize the input stage of
an Indirect Matrix Converter (IMC) by four-quadrant switches
resulting in the Very Sparse Matrix Converter topology (VSMC)
comprising only 12 IGBTs. An isolated four-quadrant switch will be
available commercially in near future, therefore, the SMC and the
VSMC are of high interest to the industry as alternative to the CMC
concept.
In case a limitation to essentially unidirectional power flow
could be accepted, the Ultra Sparse Matrix Converter (USMC)
should be considered for three-phase AC-AC energy conversion.
There, only 9 IGBTs are required in total for the system realization
where a bridge leg of the input stage is available in form of an
isolated power module.
The dimensioning of the power semiconductors of the SMC,
VSMC and USMC can be based on analytical approximations of
excellent accuracy as given in the paper. Furthermore, the current
stresses on the input filter capacitors and the output current ripple
could be calculated analytically what has been omitted here for the
sake of brevity and will be shown in a future paper. Further topics of
research will be
• the transfer of minimum switching loss strategies known for
DC voltage link and DC current link converters to the SMC,
VSMC and USMC,
• a comparison of the proposed matrix converter topologies to the
CMC concerning conduction and switching losses and/or
efficiency, where the realization of the CMC will be by
unipolar IGBTs and reverse blocking IGBTs of type IXRH
50N80 [30]
• pre-correction of pulse pattern distortions introduced by the
output stage dead-times and by the power semiconductor
conduction voltage drops,
• analysis of the operation of the SMC under unbalanced mains
condition,
• application of the SMC and VSMC for feeding a permanent
magnet synchronous machine and application of the INFORM
concept for sensorless control, where also a novel concept for
emergency braking of the machine which does allow to
dissipate the mechanical energy in the stator resistance will be
tested [31]. This concept is of special interest in connection
with the matrix converter in case a failure of the mains does
occur while the machine is operating in braking mode. The
research in this area will be in collaboration with the
Department of Electrical Drives and Machines at the Vienna
University of Technology.
Finally, we would like to point out, that the input stage of the SMC
also could be connected to a three-level voltage DC link inverter
output stage. The resulting topology is depicted in Fig. 25 and will
also be investigated in the course of future research.
a
A
b
B
c
C
Fig. 25: Basic structure of the power circuit of a novel Three-Level-OutputStage Sparse Matrix Converter (SMC3).
ACKNOWLEDGEMENT
The authors are very grateful to Dr. Andreas Lindemann, IXYS
Semiconductor GmbH, Lampertheim, Germany, for his efforts in
connection with the design and practical realization of the novel
four-quadrant switch IXYS FIO 50-12BD.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
REFERENCES
Klumpner, C., Blaabjerg, F., and Nielsen, P.: Speeding-up the
Maturation Process of the Matrix Converter Technology. Proceedings
of the 32nd IEEE Power Electronics Specialists Conference,
Vancouver, Canada, Vol. 2, pp. 1083-1088 (2001).
Huber, L., and Borojevic, D.: Space Vector Modulation with Unity
Input Power Factor for Forced Commutated Cycloconverters. Record
of the 26th IEEE Industry Applications Society Annual Meeting,
Dearborn, USA, Sept. 28 – Oct. 4, Vol. I, pp. 1032-1041 (1991).
Wheeler, P., Clare, J., Empringham, L., and Bland, M.: Technology
and Potential of Matrix Converters. Power Electronics Europe, No. 3,
pp. 25-28 (2001).
Hornkamp, M., Loddenkötter, M., Münzer, M., Simon, O., and
Bruckmann, M.: EconoMAC the First All-in-One IGBT Module for
Matrix Converters. Proceedings of the 43rd International Power
Electronics Conference, Nuremberg, June 19-21, pp.417-421 (2001).
Mahlein, J., Weigold, J., and Simon, O.: New Concepts for Matrix
Converter Design. Proceedings of the 27th IEEE International
Conference on Industrial Electronics, Control and Instrumentation,
Denver, U.S.A., Nov. 29 - Dec. 2 (2001).
Iimori, K., Shinohara, K., Tarumi, O., Fu, Z., and Muroya, M.:
New Current-Controlled PWM Rectifier-Voltage Source Inverter
without DC Link Components. Proceedings of the Power Conversion
Conference, Nagaoka, Japan, Aug. 3-6, Vol.II, pp. 783-786 (1997).
Zwimpfer, P., and Stemmler, H.: Modulation and Realization of a
Novel Two-Stage Matrix Converter. Proceedings of the 6th Brazilian
Power Electronics Conference, Florianópolis, Brazil, Nov. 11-14, vol.2,
pp. 485-490 (2001).
Alesina, A., and Venturini, M.G.B.: Analysis and Design of OptimumAmplitude Nine-Switch Direct AC-AC Converters. IEEE Transactions
on Power Electronics, Vol. 4, No. 1, pp.101-112 (1989).
Ishiguro, A., Furuhashi, T., and Okuma, S.: A Novel Control Method
for Forced Commutated Cycloconversion Using Instantaneous Values
of Input Line-to-Line Voltages. IEEE Transactions on Industrial
Electronics, Vol. 38, No. 3, pp.166-172 (1991).
Ziogas, P.D., Khan, S.I., and Rashid, M.H.: Analysis and Design of
Forced Commutated Cycloconverter Structures with Improved Transfer
Characteristics. IEEE Transactions on Industrial Electronics, Vol. IE33, No. 3, pp. 271-280 (1986).
Rahim, N.A., Green, T.C., and Williams, B.W.: Three-Phase StepDown Reversible AC-DC Power Converter. Proceedings of the 26th
IEEE Power Electronics Specialists Conference, Atlanta, USA, Vol. 2,
pp. 973-978 (1995).
Kolar, J.W.: Vorrichtung zur quasi-direkten pulsbreitengesteuerten
Energieumformung zwischen Dreiphasennetzen. Austrian Patent
Application (in German), filed July 2001.
Malesani, L., and Tenti, P.: Three-Phase AC/DC PWM Converter
with Sinusoidal AC Currents and Minimum Filter Requirements. IEEE
Transactions on Industry Applications, Vol. IA-23, No. 1, pp. 71-77
(1987).
[14] Baumann, M., Drofenik, U., and Kolar, J.W.: New Wide Input
Voltage Range Three-Phase Unity Power Factor Rectifier Formed by
Integration of a Three-Switch Buck-Derived Front-End and a DC/DC
Boost Converter Output Stage. Proceedings of the 22nd IEEE
International Telecommunications Energy Conference, Phoenix,
Arizona, U.S.A., Sept. 14-18, pp. 461-470 (2000).
[15] Cittadini, R., Huselstein, J.J., and Glaize, C.: A Matrix Converter
Switching Controller for Low Losses Operation Without Snubber
Circuits. Proceedings of the 7th European Conference on Power
Electronics and Applications, Trondheim, Norway, Sept. 8-10, pp.
4.199-4.202 (1997).
[16] Schuster, A.: A Matrix Converter without Reactive Clamp Elements for
an Induction Motor Drive System. Proceedings of the 29th IEEE Power
Electronics Specialists Confernce, Fukuoka, Japan, May 17-22, Vol. 1,
pp. 714-720 (1998).
[17] Ziegler, M., and Hofmann, W.: A New Two Steps Commutation
Policy for Low Cost Matrix Converters. Proceedings of the 41st
International Power Electronics Conference, Nuremberg, June 6-8,
pp.445-450 (2001).
[18] Holtz, J., and Boelkens, U.: Direct Frequency Converter with
Sinusoidal Line Currents for Speed-Variable ac Motors. IEEE
Transactions on Industrial Electronics, Vol. 36, No. 4, pp. 475-478
(1989).
[19] Kolar, J.W.: Dreiphasiger Hybrid-Wechselspannungs-Wechselspannungs-Direktumrichter minimaler Komplexität und hoher Kommutierungssicherheit. Austrian Patent Application (in German), filed Aug.
2001.
[20] Wei, L., and Lipo, T.A.: A Novel Matrix Converter Topology With
Simple Commutation. Record of the IEEE Industry Applications
Society Annual Meeting, Chicago, Sept. 30-Oct. 4, Vol. 3, pp. 17491754 (2001).
[21] Kolar, J.W.: Status of the Techniques of Three-Phase PWM Rectifier
Systems with Low Effects on the Mains. Professional Education Tutorial
Workbook (Tutorial 4) of the 31st IEEE Power Electronics Specialists
Conference, Galway, Ireland, June 18-23 (2000).
[22] Kolar, J.W., Ertl, H., and Zach, F.C.: Influence of the Modulation
Method on the Conduction and Switching Losses of a PWM Converter
System. IEEE Transactions on Industry Applications, vol. 27, No.6, pp.
1063 – 1075 (1991).
[23] Kolar, J.W., Ertl, H., and Zach, F.C.: Calculation of the Passive and
Active Component Stresses of Three-Phase PWM Converter Systems
with High Pulse Rate. Proceedings of the 3rd European Conference on
Power Electronics and Applications, Aachen, Germany, Oct. 9-12, Vol.
3, pp. 1303-1311 (1989).
[24] IXYS Corporation: FII 50-12E IGBT Phaseleg. Advanced Technical
Information (2000).
[25] IXYS Corporation: DSEP29-12A HiPerFRED Epitaxial Diode with
soft recovery. Datasheet (2000).
[26] IXYS Corporation: FIO 50-12BD Bidirectional Switch with IGBT and
fast Diode Bridge. Advanced Technical Information (2001).
[27] Baumann, M., Stögerer, F., Kolar, J.W., and Lindemann, A.:
Design of a Novel Multi-Chip Power Module for a Three-Phase
Buck+Boost Unity Power Factor Utility Interface Supplying the
Variable Voltage DC Link of a Square-Wave Inverter Drive.
Proceedings of the 16th IEEE Applied Power Electronics Conference,
Anaheim, California U.S.A., March 4-8, Vol. 2, pp. 820-827 (2001).
[28] Baumann, M., and Kolar, J.W.: Experimental Analysis of a 5kW Wide
Input Voltage Range Three-Phase Buck+Boost Power Factor
Corrector. Proceedings of the 23rd IEEE International
Telecommunications Energy Conference, Edinburgh, U.K., Oct. 14-18,
pp. 146-153 (2001).
[29] Evox Rifa: PHE844 EMI Suppressor. Datasheet (2001).
[30] Lindemann, A.: A New IGBT With Reverse Blocking Capability.
Record of the 9th European Conference on Power Electronics and
Applications, Graz, Austria, Aug. 27-29 (2001).
[31] Robeischl, E. and Schrödl, M.: Direct Axis Current Utilization for
Intelligent Sensorless Permanent Magnet Synchronous Drives.
Proceedings of the IEEE Industry Applications Conference, 36th Annual
Meeting, Chicago, Illinois, U.S.A., Sept. 30 – Oct. 4 (2001).
[32] Holmes, D.G., and Lipo, T.A.: Implementation of a Controlled
Rectifier Using AC-AC Matrix Converter Theory. Proceedings of the
IEEE Power Electronics Specialists Conference, pp. 353-359 (1989).
[33] Kang, J., Hara, H., Yamamoto, E., Watanabe, E., Hava, A., and
Kume, T.J.: The Matrix Converter Drive Performance Under
Abnormal Input Voltage Conditions. Proceedings of the 32nd IEEE
Power Electronics Specialists Conference, Vancouver, Canada, Vol. 2,
pp. 1089-1095 (2001).