a
FEATURES
High Speed
41 MHz, –3 dB Bandwidth
125 V/␮s Slew Rate
80 ns Settling Time
Input Bias Current of 20 pA and Noise Current of
10 fA/√Hz
Input Voltage Noise of 12 nV/√Hz
Fully Specified Power Supplies: ⴞ5 V to ⴞ15 V
Low Distortion: –76 dB at 1 MHz
High Output Drive Capability
Drives Unlimited Capacitance Load
50 mA Min Output Current
No Phase Reversal When Input Is at Rail
Available in 8-Lead SOIC
APPLICATIONS
CCD
Low Distortion Filters
Mixed Gain Stages
Audio Amplifier
Photo Detector Interface
ADC Input Buffer
DAC Output Buffer
Low-Cost, General-Purpose
High-Speed JFET Amplifier
AD825
CONNECTION DIAGRAMS
8-Lead Plastic SOIC (R) Package
NC 1
–IN 2
8 NC
AD825
7 +VS
TOP VIEW
+IN 3 (Not to Scale) 6 OUTPUT
–VS 4
5 NC
NC = NO CONNECT
16-Lead Plastic SOIC (R-16) Package
NC 1
16
NC
NC 2
15
NC
NC 3
14
NC
AD825
+VS
TOP VIEW
+INPUT 5 (Not to Scale) 12 OUTPUT
–INPUT 4
–VS 6
13
11
NC
7
10
NC
NC 8
9
NC
NC
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD825 is a superbly optimized operational amplifier for
high speed, low cost, and dc parameters, making it ideally suited
for a broad range of signal conditioning and data acquisition
applications. The ac performance, gain, bandwidth, slew rate
and drive capability are all very stable over temperature. The
AD825 also maintains stable gain under varying load conditions.
The unique input stage has ultralow input bias current and
ultralow input current noise. Signals that go to either rail on
this high performance input do not cause phase reversals at the
output. These features make the AD825 a good choice as a buffer
for MUX outputs, creating minimal offset and gain errors.
The AD825 is fully specified for operation with dual ± 5 V and
± 15 V supplies. This power supply flexibility, and the low supply current of 6.5 mA with excellent ac characteristics under
all supply conditions, make the AD825 well suited for many
demanding applications.
Figure 1. Performance with Rail-to-Rail Input Signals
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD825–SPECIFICATIONS (@ T = 25ⴗC, V = ⴞ15 V unless otherwise noted)
A
S
Parameter
Conditions
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Bandwidth for 0.1 dB Flatness
–3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
Total Harmonic Distortion
Differential Gain Error
(RLOAD = 150 Ω)
Differential Phase Error
(RLOAD = 150 Ω)
Gain = +1
Gain = +1
RLOAD = 1 kΩ, G = 1
0 V–10 V Step, AV = –1
0 V–10 V Step, AV = –1
FC = 1 MHz, G = –1
NTSC
Gain = +2
NTSC
Gain = +2
INPUT OFFSET VOLTAGE
VS
Min
± 15 V
± 15 V
± 15 V
± 15 V
± 15 V
± 15 V
± 15 V
± 15 V
23
18
44
125
AD825A
Typ
Max
26
21
46
140
150
180
–77
1.3
± 15 V
2.1
± 15 V
1
180
220
± 15 V
TMIN
TMAX
15
40
pA
pA
pA
700
± 15 V
20
30
5
TMIN
TMAX
440
VOUT = ± 10 V
RLOAD = 1 kΩ
VOUT = ± 7.5 V
RLOAD = 1 kΩ
VOUT = ± 7.5 V
RLOAD = 150 Ω
(50 mA Output)
± 15 V
COMMON-MODE REJECTION
VCM = ± 10 V
± 15 V
INPUT VOLTAGE NOISE
f = 10 kHz
INPUT CURRENT NOISE
f = 10 kHz
pA
pA
pA
70
76
dB
70
76
dB
72
74
dB
71
80
dB
± 15 V
12
nV/√Hz
± 15 V
10
fA/√Hz
± 15 V
± 13.5
V
± 13.3
± 13.2
V
V
mA
mA
± 15 V
± 15 V
INPUT COMMON-MODE
VOLTAGE RANGE
OUTPUT VOLTAGE SWING
mV
mV
µV/°C
5
INPUT OFFSET CURRENT
OPEN LOOP GAIN
2
5
10
INPUT BIAS CURRENT
MHz
MHz
MHz
V/µs
ns
ns
dB
%
Degrees
TMIN to TMAX
Offset Drift
Unit
± 15 V
± 15 V
± 15 V
± 15 V
RLOAD = 1 kΩ
RLOAD = 500 Ω
Output Current
Short-Circuit Current
13
12.9
50
100
11
INPUT RESISTANCE
5 × 10
Ω
INPUT CAPACITANCE
6
pF
8
Ω
OUTPUT RESISTANCE
Open Loop
POWER SUPPLY
Quiescent Current
± 15 V
± 15 V
TMIN to TMAX
6.5
7.2
7.5
mA
mA
NOTES
All limits are determined to be at least four standard deviations away from mean value. .
Specifications subject to change without notice.
–2–
REV. D
AD825
SPECIFICATIONS (@ T = 25ⴗC, V = ⴞ5 V unless otherwise noted)
A
S
Parameter
Conditions
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Bandwidth for 0.1 dB Flatness
–3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
Total Harmonic Distortion
Differential Gain Error
(RLOAD = 150 Ω)
Differential Phase Error
(RLOAD = 150 Ω)
Gain = +1
Gain = +1
RLOAD = 1 kΩ, G = –1
–2.5 V to +2.5 V
–2.5 V to +2.5 V
FC = 1 MHz, G = –1
NTSC
Gain = +2
NTSC
Gain = +2
INPUT OFFSET VOLTAGE
VS
Min
±5 V
±5 V
±5 V
±5 V
±5 V
±5 V
±5 V
±5 V
18
8
34
115
AD825A
Typ
Max
21
10
37
130
75
90
–76
1.2
±5 V
1.4
±5 V
1
90
110
±5 V
TMIN
TMAX
±5 V
TMIN
TMAX
30
pA
pA
pA
15
25
5
280
±5 V
COMMON-MODE REJECTION
VCM = ± 2 V
±5 V
INPUT VOLTAGE NOISE
f = 10 kHz
INPUT CURRENT NOISE
f = 10 kHz
INPUT COMMON-MODE
VOLTAGE RANGE
OUTPUT VOLTAGE SWING
10
600
VOUT = ± 2.5 V
RLOAD = 500 Ω
RLOAD = 150 Ω
OPEN LOOP GAIN
mV
mV
µV/°C
5
INPUT OFFSET CURRENT
Offset Current Drift
2
5
10
INPUT BIAS CURRENT
RLOAD = 500 Ω
RLOAD = 150 Ω
pA
pA
pA
64
64
66
66
dB
dB
69
80
dB
±5 V
12
nV/√Hz
±5 V
10
fA/√Hz
±5 V
± 3.5
V
± 3.4
± 3.2
V
V
mA
mA
±5 V
±5 V
±5 V
Output Current
Short-Circuit Current
MHz
MHz
MHz
V/µs
ns
ns
dB
%
Degrees
TMIN to TMAX
Offset Drift
Unit
3.2
3.1
50
80
11
INPUT RESISTANCE
5 × 10
Ω
INPUT CAPACITANCE
6
pF
8
Ω
OUTPUT RESISTANCE
Open Loop
POWER SUPPLY
Quiescent Current
±5 V
±5 V
TMIN to TMAX
POWER SUPPLY REJECTION
VS = ± 5 V to ± 15 V
NOTES
All limits are determined to be at least four standard deviations away from mean value.
Specifications subject to change without notice.
REV. D
–3–
6.2
76
88
6.8
7.5
mA
mA
dB
AD825
ABSOLUTE MAXIMUM RATINGS 1
PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Small Outline (R) . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . See Derating Curves
Storage Temperature Range (R, R-16) . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
NC 1
8 NC
AD825
–IN 2
7 +VS
TOP VIEW
+IN 3 (Not to Scale) 6 OUTPUT
–VS 4
5 NC
NC = NO CONNECT
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
8-lead SOIC package: θJA = 155°C/W
16-lead SOIC package: θJA = 85°C/W
MAXIMUM POWER DISSIPATION – Watts
2.5
TJ = 150ⴗC
2.0
16-LEAD SOIC PACKAGE
1.5
1.0
0.5
8-LEAD SOIC PACKAGE
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – °C
80 90
Figure 2. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD825AR
AD825ACHIPS
AD825AR-REEL
AD825AR-REEL7
AD825AR-16
AD825AR-16-REEL
AD825AR-16-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic SOIC
Die
13" Tape and Reel
7" Tape and Reel
16-Lead Plastic SOIC
13" Tape and Reel
7" Tape and Reel
SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD825 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
SO-8
SO-8
R-16
R-16
R-16
WARNING!
ESD SENSITIVE DEVICE
REV. D
Typical Performance Characteristics–AD825
20
100
15
OUTPUT IMPEDANCE – ⍀
OUTPUT SWING – Volts
10
5
RL = 150⍀
0
RL = 1k⍀
–5
–10
10
1
0.1
–15
0
2
4
6
8
10
12
SUPPLY VOLTAGE – Volts
14
0.01
100
18
16
TPC 1. Output Voltage Swing vs. Supply
10M
1M
35
80
BANDWIDTH
30
UNITY GAIN BANDWIDTH – MHz
10
VS = ⴞ15V
OUTPUT SWING – Volts
10k
100k
FREQUENCY – Hz
TPC 4. Closed-Loop Output Impedance vs. Frequency
15
5
VS = ⴞ5V
0
–5
VS = ⴞ15V
–10
–15
1k
25
60
20
PHASE MARGIN
15
40
10
PHASE MARGIN – ⴗC
–20
5
0
100
200
300 400 500 600 700
LOAD RESISTANCE – ⍀
800
900
0
–60
1000
TPC 2. Output Voltage Swing vs. Load Resistance
20
–40
–20
0
60
20
40
80
TEMPERATURE – ⴗC
100
120 140
TPC 5. Unity Gain Bandwidth and Phase Margin vs.
Temperature
7.0
180
80
VS = ⴞ15V
135
70
OPEN-LOOP GAIN – dB
SUPPLY CURRENT – mA
6.5
+85ⴗ
6.0
5.5
60
VS = ⴞ5V
90
50
45
40
0
30
20
10
5.0
0
2
4
6
8
10
12
14
SUPPLY VOLTAGE – ±V
16
18
0
1k
20
TPC 3. Quiescent Supply Current vs. Supply Voltage for
Various Temperatures
REV. D
10k
100k
1M
FREQUENCY – Hz
10M
100M
TPC 6. Open-Loop Gain and Phase Margin vs.
Frequency
–5–
OPEN-LOOP PHASE – Degrees
–40ⴗ
+25ⴗ
AD825
80
30
OUTPUT VOLTAGE – Volts p-p
OPEN-LOOP GAIN – dB
RL = 1k⍀
75
VS = ⴞ15V
70
VS = ⴞ5V
65
60
100
1k
LOAD RESISTANCE – ⍀
20
RL = 150⍀
10
0
10k
10k
TPC 7. Open-Loop Gain vs. Load Resistance
100k
1M
FREQUENCY – Hz
10M
TPC 10. Large Signal Frequency Response; G = +2
10
200
0
180
–10
160
–PSRR
SETTLING TIME – ns
PSR – dB
–20
–30
+PSRR
–40
–50
–60
140
0.01%
100
40
20
100k
0
10
10M
1M
FREQUENCY – Hz
TPC 8. Power Supply Rejection vs. Frequency
0.1%
60
–80
10k
0.1%
80
–70
–90
0.01%
120
8
6
4
2
0
–2
–4
OUTPUT SWING – 0 to ⴞV
–6
–8
–10
TPC 11. Output Swing and Error vs. Settling Time
130
–50
120
–55
110
CMR – dB
DISTORTION – dB
–60
100
VS = ⴞ15V
90
80
VS = ⴞ5V
70
60
2nd
–65
3rd
–70
–75
50
–80
40
30
10
100
1k
100k
10k
FREQUENCY – Hz
1M
–85
100k
10M
TPC 9. Common-Mode Rejection vs. Frequency
1M
FREQUENCY – Hz
10M
TPC 12. Harmonic Distortion vs. Frequency
–6–
REV. D
AD825
160
ⴞ15V
140
+VS 10␮F
ⴞ5V
SLEW RATE – V/␮s
120
0.01␮F
100
80
HP
PULSE (LS)
OR FUNCTION
(SS)
GENERATOR
60
40
–
VOUT
AD825
VIN
+
TEKTRONIX
P6204 FET
PROBE
0.01␮F
RL
50⍀
10␮F
20
0
–60
–VS
–40
–20
0
20
40
80
60
TEMPERATURE – ⴗC
100
120
140
TPC 13. Slew Rate vs. Temperature
TPC 16. Noninverting Amplifier Connection
2
1
0
–1
GAIN – dB
–2
–3
–4
VOUT
VIN
VS
0.1dB FLATNESS
ⴞ5V
10MHz
ⴞ15V
21MHz
–5
–6
–7
–8
1k
10k
100k
1M
FREQUENCY – Hz
10M
TPC 17. Noninverting Large Signal Pulse
Response, RL = 1 kΩ
TPC 14. Closed-Loop Gain vs. Frequency, Gain = +1
2
1
0
GAIN – dB
–1
–2
–3
VIN
1k⍀
–4
1k⍀
VOUT
–5
VS
0.1dB FLATNESS
ⴞ5V
7.7MHz
ⴞ15V
9.8MHz
–6
–7
–8
1k
10k
100k
1M
FREQUENCY – Hz
10M
TPC 18. Noninverting Small Signal Pulse
Response, RL = 1 kΩ
TPC 15. Closed-Loop Gain vs. Frequency, Gain = –1
REV. D
TEKTRONIX
7A24
PREAMP
–7–
AD825
TPC 19. Noninverting Large Signal Pulse
Response, RL = 150 Ω
TPC 22 . Inverting Large Signal Pulse
Response, RL = 1 kΩ
TPC 20. Noninverting Small Signal Pulse
Response, RL = 150 Ω
TPC 23. Inverting Small Signal Pulse
Response, RL = 1 kΩ
1k⍀
+VS
10␮F
0.01␮F
HP
PULSE
GENERATOR
RIN
VIN 1k⍀
VOUT
–
50⍀
AD825
+
TEKTRONIX
P6204 FET
PROBE
TEKTRONIX
7A24
PREAMP
0.01␮F
10␮F
CL
1000pF
–VS
TPC 21. Inverting Amplifier Connection
–8–
REV. D
AD825
VPOS
DRIVING CAPACITIVE LOADS
The internal compensation of the AD825, together with its high
output current drive, permits excellent large signal performance
while driving extremely high capacitive loads.
NEG
1k⍀
POS
10␮F
+VS
CF
0.01␮F
HP
PULSE
GENERATOR
RIN
VIN 1k⍀
50⍀
VOUT
AD825
TEKTRONIX
P6204 FET
PROBE
VOUT
TEKTRONIX
7A24
PREAMP
0.01␮F
CL
10␮F
VNEG
–VS
Figure 4. Simplified Schematic
Figure 3a. Inverting Amplifier Driving a Capacitive Load
The capacitor, CF, in the output stage, enables the AD825 to
drive heavy capacitive load. For light load, the gain of the output buffer is close to unity, CF is bootstrapped and not much
happens. As the capacitive load is increased, the gain of the
output buffer is decreased and the bandwidth of the amplifier is
reduced through a portion of CF adding to the dominant pole.
As the capacitive load is further increased, the amplifier’s bandwidth continues to drop, maintaining the stability of the AD825.
INPUT
Input Consideration
The AD825 with its unique input stage assures no phase reversal for signals as large or even larger than the supply voltages.
Also, layout considerations of the input transistors assure functionality even with a large differential signal.
OUTPUT
The need for a low noise input stage calls for a larger FET transistor. One should consider the additional capacitance that is added
to assure stability. When filters are designed with the AD825,
one needs to consider the input capacitance (5 pF–6 pF) of the
AD825 as part of the passive network.
Figure 3b. Inverting Amplifier Pulse Response
While Driving a 400 pF Capacitive Load
THEORY OF OPERATION
The AD825 is a low cost, wide band, high performance FET
input operational amplifier. With its unique input stage design,
the AD825 assures no phase reversal even for inputs that exceed
the power supply voltages, and its output stage is designed to
drive heavy capacitive or resistive load with small changes relative to no load condition.
Grounding and Bypassing
The AD825 is a low input bias current FET amplifier. Its high
frequency response makes it useful in applications such as photo
diode interfaces, filters and audio circuits. When designing high
frequency circuits, some special precautions are in order. Circuits
must be built with short interconnects, and resistances should
have low inductive paths to ground. Power supply leads should
be bypassed to common as close as possible to the amplifier
pins. Ceramic capacitors of 0.1 µF are recommended.
The AD825 (Figure 4) consists of common-drain common-base
FET input stage driving a cascoded, common base matched NPN
gain stage. The output buffer stage uses emitter followers in a
class AB amplifier that can deliver large current to the load
while maintaining low levels of distortion.
REV. D
–9–
AD825
Second Order Low-Pass Filter
A second order Butterworth low-pass filter can be implemented
using the AD825 as shown in Figure 5. The extremely low bias
currents of the AD825 allow the use of large resistor values, and
consequently small capacitor values, without concern for developing large offset errors. Low current noise is another factor in
permitting the use of large resistors without having to worry
about the resultant voltage noise.
With the values shown, the corner frequency will be 1 MHz.
The equations for component selection are shown below. Note
that the noninverting input (and the inverting input) has an
input capacitance of 6 pF. As a result, the calculated value of
C1 (12 pF) is reduced to 6 pF.
C3
0.1␮F
R2
9.31k⍀
VIN
C2
6pF
VOUT
AD825
–5V
Figure 5. Second Order Butterworth Low-Pass Filter
0
0.707
C2 ( farads) =
2π f CUTOFF R1
(
+5V
C4
0.1␮F
1.414
2π f CUTOFF R1
R1= R2 = user selected typically10kΩ to 100 kΩ
R1
9.31k⍀
HIGH FREQUENCY REJECTION – dB
C1=
C1
24pF
)
A plot of the filter frequency response is shown in Figure 6;
better than 40 dB of high frequency rejection is provided.
–10
–20
–30
–40
–50
–60
–70
–80
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 6. Frequency Response of Second Order
Butterworth Filter
–10–
REV. D
AD825
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8ⴗ
0.0098 (0.25) 0ⴗ 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
16-Lead Plastic SOIC
(R-16)
0.413 (10.50)
0.398 (10.10)
16
9
0.299 (7.60)
0.291 (7.40)
1
PIN 1
0.050 (1.27)
BSC
0.010 (0.25)
0.004 (0.10)
REV. D
0.419 (10.65)
0.404 (10.26)
8
0.107 (2.72)
0.089 (2.26)
0.018 (0.46) SEATING
0.015 (0.38)
0.014 (0.36) PLANE
0.007 (1.18)
–11–
0.364 (9.246)
0.344 (8.738)
0.045 (1.15)
0.020 (0.50)
AD825 –Revision History
Location
Page
PRINTED IN U.S.A.
C00876c–0–2/01 (rev. D)
Changed from REV. C to REV. D.
Addition of 16-lead SOIC package (R-16) Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Addition to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Addition to Ordering Guide (R-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Addition of 16-lead SOIC package (R-16) Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
–12–
REV. D