An Overview of the IPEM-Based Modular Implementation for
Distributed Power Systems
P. Barbosa, F.C. Lee, J.D. van Wyk, D. Boroyevich, E. Scott1, K. Thole1, H. Odendaal, Z. Liang, Y. Pang1, E.
Sewall1, J. Chen, R. Chen, and B. Yang
The Bradley Department of Elec. & Computer Engineering
Center For Power Electronics Systems – Virginia Tech
Blacksburg, VA 24061-0179
Abstract
Power electronics systems are typically designed
and manufactured using non-standard parts, which results in
labor-intensive manufacturing processes and increased cost. As
a possible way to overcome these problems, this paper provides
an overview on how to realize integrated systems via Integrated
Power Electronics Modules (IPEMs) to improve performance,
reliability and cost of power electronic equipment. Technology
barriers, existing industry practice and necessary
advancements to realize integrated power systems are discussed
in the paper, along with results from the active and passive
IPEM design optimization processes.
I.
INTRODUCTION
Power electronics and related power processing technologies
constitute an “enabling infrastructure technology” with a
significant potential impact on industrial competitiveness. This
is manifested through the increased energy efficiency of
equipment and processes using electrical power, and through
higher industrial productivity and higher product quality, which
results from the ability to control precisely the electrical power
for manufacturing operations. Industrial firms are under
constant pressure to produce power electronics products that are
more powerful, durable, smaller, lighter, and less costly to the
consumer. Despite all these requirements, power electronics
products, to date, are essentially custom-designed and
manufactured using non-standard parts, which increase labor
and ultimately cost of power electronic equipment.
Over the last twenty years, the fundamental approach to
power conversion has steadily moved toward “high-frequency
synthesis”, resulting in huge improvements in converter
performance, size, weight and cost. However, in some high
frequency power conversion technologies, fundamental limits
are being reached that will not be overcome without a radical
change in the design and implementation of power electronics
systems.
To address some of these issues, this paper briefly discusses
the technology barriers that limit the rapid growth of power
electronics, as well as the technology advancements needed to
improve the characteristics of power electronics systems. The
technologies being developed for the realization of integrated
systems include planar metalization to allow three-dimensional
This work was supported by the ERC Program of the National Science
Foundation under Award Number EEC-9731677.
1
Department of Mechanical Engineering
Virginia Tech
Blacksburg, VA 24061-0179
integration of power devices and integration of power passives
to increase power density. This paper presents the design and
implementation results of active and passive Integrated Power
Electronics Modules (IPEMs) needed to realize integrated
power electronics systems.
II.
TECHNOLOGY BARRIERS
A. Power Semiconductor Devices
It is well recognized within the industrial sector that the
performance of power electronics systems were driven by
improvements in semiconductor components during the last five
decades. The power device industry has undergone a
revolutionary change, from bipolar technology-based devices,
such as bipolar power transistors, power thyristors, and gate
turn-off thyristors, to MOS-based devices, such as power
MOSFETs, Insulated-Gate-Bipolar-Transistors (IGBTs) and
MOS-controlled thyristors [1] [2]. Moving from bipolar to
MOSFET technology has resulted in speed increases that,
today, test the limits of packaging inductance and thermal
handling. Thus, an order of magnitude increase in switching
speed, which is possible with new device technologies, will
require substantial reductions in structural capacitances and
inductances associated with device and system-level packaging.
B. Passive Components
The inadequate performance of passive components at high
switching speeds is evident. High current and voltage rates
often produce frequency components in the megahertz range,
which results in a situation in which capacitors behave as
inductors and inductors behave as capacitors. This forms
another critical barrier to future developments, because the
major reason for further increases in switching speed in most
applications is the size reduction of passive components, as
long as thermal de-rating is not implied. Even continued efforts
at developing cost-effective and volume-efficient capacitors and
magnetic components with significantly improved performance
do not solve the problems of high frequency interconnection
impedance (parasitics) in future developments.
C. Power Electronics Modules
The lack of standardization of a modular approach to power
electronics systems is a major barrier for future advancements
in power electronics, especially for DPS applications that can
be implemented with numerous topologies. Many power
electronics companies still perceive that utilizing a proprietary
circuit topology is a major value added to the product.
However, with the system-oriented thinking, optimization of the
overall system performance, cost, and time to market inevitably
will lead to standardization of power modules. These modules
must not only contain the power semiconductors, but as an
efficient system integration tool, all other necessary
standardized functions such as passive power components and
the necessary level of intelligence for sensing and control.
D. Power Electronics Packaging
For a typical power electronics system, individual power
devices are mounted on the heat sink, and the drivers,
sensors, and protection circuits are implemented on a printed
circuit board and mounted near the power devices. The
manufacturing process for such equipment is labor-intensive,
high cost, and low reliability. However, some manufactures
have taken a more aggressive approach in recent years,
developing a high level of integration where power
semiconductors in the die form are mounted on a common
substrate with wire bonding. The associated drivers,
protection, and sensors are still realized in the form of a
high-density printed circuit board, using surface-mount
components and then packaged together with the power
devices to form a power module. Although the wire bonding
technology has seen many improvements, this approach still
limits the possibilities of three-dimensional integration, as
well as having electromagnetic layout constraints. The
thermal management in this type of packaging is essentially
limited to one-dimensional heat flow. In addition, the
reduction of structural inductance associated with bonding
wires and terminations have limitations, which impairs the
electrical performances of the power module, restraining its
application to the low frequency range.
components are distributed on the printed circuit board and Cu
traces are routed to distribute power and control signals to all
devices. This type of layout approach presents severe
limitations from the electrical and thermal viewpoints. Fig. 2(b)
shows the top view of the 3-D solid-body model. Major
components are identified in the figure, as well as critical paths
defining which components must be placed next to each other
in order to reduce parasitic inductance, and consequently
voltage ringing during switching events. For instance, in the
PFC stage the critical path consists of the connection between
power switch, boost diode and output filter capacitor. The loop
inductance formed by this connection is critical because it will
generate voltage overshoot across the power switch during its
turn-off, which impairs the electrical performance of the PFC
circuit. Another critical path verified in the system appears
between the bus capacitor and the two switches of the halfbridge DC/DC converter. Any inductance in this loop generates
overshoot across the DC/DC switches due to high di/dt flowing
through the parasitic inductance during switch turn-off.
On-board
Converter
Power
Factor
Correction
DC/DC
Converter
High Volt
VRM
On-board
Converter
Low Volt
VRM
Fig. 1. Distributed power system.
III. POWER ELECTRONICS SYSTEMS & CURRENT PRACTICE
(a)
MOSFETs
Fan
Out. Rectifiers
Integrated
Magnetics
Bus
Cap
Fan
The increasing use of distributed power systems (DPS) for
computer and telecommunication applications has opened up
the opportunity to develop a standardized modular approach to
power processing, which will improve the design and
manufacturing processes significantly, as well as enhance the
electrical system performance. For this reason, a DPS has been
chosen to demonstrate the advantages of implementing
integrated power electronics systems. A typical DPS
configuration is shown in Fig. 1. Currently, the power supply
industry uses discrete components to design and manufacture
front-end converters for DPS applications. A three-dimensional
solid-body representation for this type of system is shown in
Fig. 2(a), which illustrates both front-end PFC and DC/DC
converters. As observed, the current approach to implementing
DPS front-end converters requires using a large number of
parts, which makes difficult the optimization of space usage,
limiting the power density of the entire system. The
Blocking
Caps
Heat Sinks
Out
Cap
Boost Diode MOSFET
Snubber
Diodes
Control
Bus
Cap
EMI
Filter
Boost Inductor
Out
Cap
IV. NECESSARY TECHNOLOGY ADVANCEMENTS
In order to provide significant improvements in
performance, reliability, and cost of power electronic
systems, it is essential to develop an integrated systems
approach to standardize power electronics components and
packaging techniques in the form of IPEMs. The IPEM
approach makes possible increased levels of integration in
the components that comprise a power electronics system –
devices, circuits, controls, sensors, and actuators − integrated
into standardized manufacturable subassemblies and
modules that are customized for a particular application.
The basic functions in electronic power conversion are
easy to identify: (1) active control of energy transfer using
semiconductor switches and switch assemblies, (2) passive
energy transfer and storage using transformers, inductors
and capacitors, and (3) control and protection using signal
processing circuits. However, the integration of these
components in a manufacturing process is not readily
available due to the inadequate electromagnetic
characteristics of semiconductor materials, incompatibility
of materials and processing methods used in fabrication, and
due to the high energy levels that these components must
handle. All these considerations lead essentially to a hybrid
integration technology as the only alternative to integration.
Integrated power electronics modules in the form of hybrid
packaging are quite feasible. Passive integration technologies
must be developed as well, since the required physical volume
of power electronic equipment is large, especially for passive
energy transfer and storage components.
Active IPEM
C1
+
C2
Gate drivers,
protection and
sensors
Although bringing devices closer to each other is feasible and
helps reduce the parasitic inductance, there is a clear limitation
to this packaging approach because the space between
components is limited by form factors. Moreover, electrical and
thermal issues are conflicting entities, which means that
improving electrical performance by bringing components
closer to each other does deteriorate thermal performance
because the heat has to be dissipated in a smaller area. Thermal
issues are more stringent for integrated power electronics
modules because the devices are closer. However, integration
creates new opportunities to exploring novel thermal
management approaches, such as 3-D thermal flow.
The parasitic inductance is a limiting factor to increasing
switching frequency and power level of systems based on the
packaging approach shown in Fig. 2(a). Therefore, the only way
to overcome this problem is to minimize parasitic inductance of
critical paths by seeking integrating approaches for power
devices and components. Such an integrated power electronics
approach requires advances in power electronics technologies,
which depend on finding solutions to deal with the multidisciplinary issues in materials, electromagnetic compatibility
and thermal management.
Passive IPEM
+
Fig. 3. Asymmetrical half-bridge DC/DC converter (AHBC) used to
demonstrate active and passive IPEMs.
V. DEVELOPING AN INTEGRATED SYSTEMS APPROACH
Although the objective is to integrate functions and
components for both front-end PFC and DC/DC converters, the
results reported in this paper are only related to the work that
has been accomplished in integrating the front-end DC/DC
converter.
The PWM asymmetrical half-bridge DC/DC converter
(AHBC) was chosen as the demonstration vehicle to show the
application of active and passive IPEMs, as illustrated in Fig. 3.
In the same figure, two blocks are defined as active and passive
IPEMs. The active IPEM represents the integration of power
MOSFETs and gate drivers, while the passive IPEM represents
the electromagnetic integration of the DC blocking capacitor,
transformer and output inductors of the current doubler
configuration used in the AHBC. Although the system
represented in Fig. 2(b) is the discrete approach to DPS
applications, one can already verify some level of integration in
the magnetic components of the DC/DC AHBC [3]. This
represents by itself an advanced approach to integrating
functions in power electronics systems. The passive IPEM
represented in Fig. 3 is a step further to integrate not only
magnetic parts, but also capacitive components into a single
electromagnetic device. Therefore, one of the main purposes of
increasing the level of integration is to reduce the parts count in
the system, increase the power density and develop a modular
approach to manufacturing power electronics systems, as well
as reduce the overall number of interconnections needed to
realize such systems.
The next subsections in this paper discuss the design
process used to implement the active and passive IPEMs for
the AHBC.
A. System Specifications and IPEM Requirements
Steps were taken towards defining specifications at the
system level, as well as the requirements for the active and
passive IPEMs. Table 1 shows specifications for the DC/DC
converter, which was simulated at 200kHz in order to define
the requirements for the active and passive IPEMs, as
described in Table 2 and Table 3.
Table 1. System-level (DC/DC converter) specifications.
Parameter
Input voltage
Output voltage
Output voltage ripple (pk-pk)
Isolation (output to ground)
Output power
Ambient temperature
Air flow at 5000ft
Safety
EMI system-level
Specification
300 V – 415 V
48 V ± 10%
480 mV
>10kΩ
1 kW
50oC
20 CFM at 50oC amb.
15 CFM at 35oC amb
UL 60950
EN55022 Class B
Metalization
layer
Gate
drive
r
ic
ram
Ce
Device
Device
Etched
Cu
Etched
Cu
Ceramic
Cu layer
Table 2. Active IPEM requirements.
Specification
400V
415V
25A
150oC
125 oC
-20 oC -100 oC
at
He
r
de
ea
spr
(a)
Gate driver
Ceramic
Parameter
DC bus voltage (500 device)
Surge of DC Bus voltage
Power terminal current
Junction temperature (max.)
Maximum operating junction temperature
Operating case temperature
Isolation voltage (case-to-terminal at
60Hz)
Power terminal leakage current
Maximum switching frequency
Metalization
layer
>2500V
<500µA
500kHz
Table 3. Passive IPEM requirements.
Parameter
DC blocking capacitance
Leakage inductance (ZVS range 50%100%)
Magnetizing inductance
Turns
Specification
>2 µF
2 µH
45 µH
Np1=4, Ns1=3, Np2=8 and
Ns2=6
B. Active IPEM Design and Implementation Using Planar
Metalization Technology
Some approaches have been developed for integrated
packaging of power modules. Previous work reported a
MCM-D package for power applications [4]. In that
structure, the silicon chip with one power transistor was used
as a MCM-D substrate onto which the gate driver was
mounted using flip-chip technology. The technique
accomplishes high integration levels of multiple power and
signal chips. However, the power bus is still interconnected
to the base substrate with bond wires. This also occurred in
the IPM packaging technology, where power chips were
mounted and interconnected with bond wires onto a highdensity substrate [5]. In addition, the concepts of embedded
chips and bump-less bonding were investigated for
microelectronics packaging applications [6].
Since the use of wire bonding inhibits three-dimensional
structural integration and has limitations in reducing structural
packaging inductance, a planar metalization technology was
developed, namely embedded power [7]. Embedded power is a
3-D multi-layer integrated packaging technology that
sandwiches power bus structure and integrated circuitry. The
principle of this technology is shown in Fig. 4(a), while a
module for the DPS-IPEM is shown in Fig. 4 (b). Note that
since one of the main structural elements of this planar
Metalization
(b)
Fig. 4. (a) Three-dimensional view of the active module using embedded
power technology and (b) Top view after metalization and assembly of gate
driver.
technology is a ceramic carrier, the structure is suitable to
mounting passive devices and advanced control functions in 3D fashion directly on the carrier.
Fig. 4(a) shows several layers used to implement the active
IPEM. The heat spreader is used not only for thermal purpose,
but also to provide mechanical stability to the entire module.
Mounted on the top of the heat spreader is the DBC, which is
comprised of Cu layer, ceramic and etched Cu traces. The
devices are then soldered on the top of the etched Cu and
another ceramic carrier is used to confine the devices. The
metalization layers connect the devices from the top of the
ceramic carrier. Gate driver and circuitry are also mounted on
the top of the same carrier.
In the design process of the active IPEM, different layouts
were proposed to reduce the geometric footprint based on
electrical limitations. Bringing devices closer, as well as
reducing the Cu area of the planar metalization reduced the
footprint of the IPEM. Analyses were conducted on these
layouts to determine the best design based on electrical
performance. A parametric study was then carried out on the
best layout to determine how ceramic thickness, ceramic
material and heat spreader thickness affect the thermal
performance of the power module [8]. A set of models for DPS-
Table 4. Summary of modeling, analysis and design results.
Generation II DPS-IPEM
(Preliminary design)
Generation II DPS-IPEM
(Proposed design)
Inductance
10nH
3nH
3nH
Overshoot
70V
50V
10V
CM capacitance
4pF
60pF
20pF
Parameter
Design
Version
Generation I DPS-IPEM
5
extraction, while the thermal models were implemented in IDEAS thermal.
*
*
. .
5
8
E core
8
a
im
pr
(a)
b
hy
T1
nd
co
se
ry
ing
ind
w
rid
ary
in
nd
wi
ar
n
pla
I core
T1
g
T2
p
(b)
y
ar
nd s
co ing
e
d
& swin
arynar
rimpla
T2
Ec
e
or
(c)
Fig. 5. Components of the passive IPEM: (a) equivalent circuit, (b) core
structure and (c) exploded view of passive IPEM.
Fig. 6. Prototype of passive IPEM.
IPEMs based on three-dimensional geometry was developed,
including both electrical and thermal models. The electrical
models were implemented in Maxwell Q3D for parameter
Table 4 summarizes the results obtained from the design
optimization. The first design shown in the table used wire
bonding, while the other two used embedded power
technology. The proposed design achieved 37% in footprint
reduction, as compared to Generation I wire bonding
version, and approximately 5% reduction in comparison
with Generation II preliminary design. The device
interconnects using planar metalization with embedded
power reduced the structural inductance by a factor of 3
when compared to the wire bonding technology (Table 4
shows the largest structural packaging inductance only, but
other paths also presented similar reduction ratio). The
embedded power technology using planar metalization helps
reduce the structural inductance, but the common-mode
(CM) capacitance is increased by a factor of 5, as compared
to wire bonding. The parametric thermal study concluded
that factors such as reduction in footprint, increase in
ceramic thickness and increase in heat spreader thickness
deteriorate thermal performance. The temperature rise,
however, is less sensitive to increase in ceramic and heat
spreader thickness than reduction in footprint. AlN substrate
resulted in slightly better thermal performance and 10% less
CM capacitance than Al2O3. Ceramic thickness does not
affect temperature rise to a great extension, then it should be
chosen according to cost and CM capacitance impacts at the
module level. The proposed design recommended 25milthick Al2O3 ceramic substrate and 3mm-thick heat spreader
to improve thermal and mechanical managements.
C. Design and implementation of passive IPEMs Using
Hybrid Winding Technology
The electromagnetic structure of any capacitor or
inductor already includes both types of electromagnetic
energy storage. Instead of attempting to produce “pure”
components, it has long been realized that enhancing the
capacitive element in inductors can lead to an integrated
component [9]. However, in terms of 3-D integration, it
remained for the combination of all the well-known
technologies for planar magnetic components, multi-layer
planar capacitors and the process technologies for making
micro-inductors to be combined into a viable planar
technology for the integration of high density, high power
planar passives into modules [10]. The development of this
technology was first applied to resonant and resonant
transition converters as offering a natural proving ground to
combine a resonant function and a transformer.
In the front-end DC/DC converter, the size and
dimensions of the passive components strongly affects the
total size and volume of the converter. To further increase
the power density and reduce the profile, there is a demand
for the integration of passive components into one planar
module. The original work of an integrated inductorcapacitor structure [9] led to the development of a planar
technology to integrate inductors, capacitors and
transformers (L-C-T) for resonant applications [11]. The
integration of passive components for PWM AHBC is an
application of L-C-T technology to PWM converter.
For the design of the passive IPEM, constraints and
parameters for all components are obtained from the system
requirements and circuit analyses, as illustrated in Table 3. A
design program was developed and an optimal design result
was obtained from the design process. Because of the
current doubler configuration, the structure of the passive
IPEM has been realized by stacking two transformers, as
illustrated in Fig. 5(a). The transformers are built with two
E-planar cores that share a common I core, as shown in Fig.
5(b) and further detailed in Fig. 5(c). The DC blocking
capacitor is implemented in transformer T1 by using the
hybrid winding technology [12], The hybrid winding is
implemented using Cu traces on both sides of the winding
and a dielectric layer placed in the middle to enhance the
capacitive component of the winding. The transformer T2 is
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