. WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W THS7347 W C . W W .T WW .100Y M.T .100 .TW 100 M . O W M O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O O .................................................................................................................................................. WW SLOS531A W www.ti.com Y.C– MAY 2007.T– W WW 00Y.CO .TW C . 0 W W REVISED SEPTEMBER 2008 W 0 Y W W M .1 W.1 Y.COM W M.T .100 O W O W W C . W 2 W W .T W W 00Y Buffer RGBHV WW .100Y.C M.T3-Channel .1002:1 Input M.T with I C™ Control, .1Video OM Mux, W O W C . O W W C W Y W Y. .TW WW .100Y.C M.TW MonitorWPass-Through, and SelectableWInputWBias M.T .100 Modes 100 M . O O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W W FEATURES APPLICATIONS .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW WW • .3-Video 00Y Amplifiers O 1 for CVBS, S-Video, OM W W .CO .T• WProjectorsWWW 00Y.C WW EDTV, C . Y W W 0 Y W 1SystemsOM.T 0 W T HDTV and R'G'B' Video • Professional Video . 1 00 Y'P'BP'M R, .G'B'R', M . 1 W . O O W Y.C WW 00Y.C WW Input •.TW LCD/DLP®/LOCS .TW • H/V Sync WAdjustable 00Buffering Y.CPaths with WSchmitt 1 0 WW T M . . 1 0 M . O 1 W O W OM Trigger W. WW .100Y.C M.TW W Y.C WW .100Y.C M TW . 0 W•W2:1 Input T . 0 DESCRIPTION .1 Mux M WW 00Y.CO .TW WW 00Y.CO .TW W W2 W 00Y.CO .TW W W M .1 using the W revolutionary • I C Control of AllM Functions on Each Channel M Ocomplimentary .1 W.1 Y.COFabricated C . O W W Y W C W . silicon-germanium (SiGe) BiCom3 process, 0 W W .TW the W • WUnity-Gain Buffer Path for ADC Buffering: .T M .10 .TW 100 00Y M . O 1 W M . THS7347 is a low-power, single-supply 2.7-V to 5-V O W C . W W WRate 00Y.C3-channel WintegratedW .CO .TW 0Ywith –W 500-MHz Bandwidth, 1200-V/µs Slew TW (H) . 0 Y W T . video buffer horizontal 1 0 W M . O 10 W OMvertical (V) sync signal W.1 OM Function: W.Pass-Through • Monitor and W a YIt.Cincorporates W 0 WW paths. 0 WW .100Y.C T . 1 WW .100Y.C M.TW M.T ideal . unity-gainObuffer M 500-MHz bandwidth, 1200-V/µs W O – 500-MHz Bandwidth, 1300-V/µs Slew Rate W C W .C driving Y. WW converters WW 00Y.CO .TW analog-to-digital 0Yfor WW .TW M.Tand .100 (ADCs) M – W 6-dB Gain with SAGMCorrection Capable W.10 videoOdecoders. O 1 W . In parallel W with the unity-gain buffer, O W C W Y.C W .Tthe WDisable State 00for Y.C WW .100aY.monitor TW . 1 – High Impedance in 0 WWOutput T M . pass-through path allows passing . 0 M O 1 W M . O W C . O W W systems. • Selectable .TaW 00Ypath has 0Y.C signal Y.C Modes: WW .10input .TonWto other W 1This WW Input M . .TW 00Bias M O 1 W M . 6-dB gain, 500-MHz bandwidth, 1300-V/µs slew rate, O W O W with Sync-Tip .C – AC-Coupled Clamp Y.C WW .TW WW .1SAG capability, and high output .TW 100 impedance 00Y correction WW .100Y.C M.TW M . M O W W – AC-Coupled BiasO .CO .TW WW .100Y.C M.TW WW with W 0Ydisabled. Y.C WW .while 0 0 W T . 1 0 M O – DC-Coupled with W M WEach Ychannel W.1 OffsetOShift .CO .TofW the THS7347 0Y.C M.TW WW is.10individually 0 WW I2.C-configurable 0 WW .100Y.C M.TW – DC-Coupled 1 controlling M for all functions, including .CO .TW O WW stage W .CO mux..TIts Yallows WW C W . the 2:1 input rail-to-rail output 0 Y W W W • +2.7-V to +5-V Single-Supply Operation 0 0 Y W 1 0 W M . .T 1 ac- and 00 M applications. W.both OMmW at 3.3 V WW 00Y.CO .TW W.1 Y.C265 .CO dc-coupling Wfor • Total Power Consumption: W Y W W W 0 W T . 0 W .T 00 W.1 Y.COM W W.1 Y.COM W • Disable Function Reduces OM to 0.1 µA W W.1 YCurrent W C . W W W .T 0 W M.T .100 .TW 100 M . O W • Rail-to-Rail Output:W.10 M O W C . O WW .100Y .TW W WW .100Y.C M.TW 0Y.VCof the WWWithin M .T – Output Swings Rails, 00.1 O 1 W M . O W O W WW .100Y.C M.TW Allowing AC-W orWDC-Output Coupling W Y.C WW .100Y.C M.TW 0 T . 0 1 . OM WW 00Y.CO .T WPackage • Lead-free, RoHS TQFP WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W 3.3 V WW 00Y.CO .T W.1 Y.COM W W Input 1 W W W 0.1 00 WmFIn A .100 M.T W.1 Y.COM M.T W.1 Y.CO O W W W C 0.1 m F W . W W 2:1 00Y X1 .TW +W .T ADC In B W M .100 100 M . 1 W M . O W 75 W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T AC 0 W DC .100 Sync .T W.1 W.1 Y.COM W Input 2 OM W W DC Y.C 0.1 mF W +Offset TIP W W W W + 10047 mF OM.T 00 Clamp M.TW .Out .1ACW O W .C 75 W .TW W C DisableW . W675 W .10330mY 75 W WW BIAS = OPEN .T 00Y F M 1 M . SAG O W CO WW Y.Monitor 0 W 0 WW .100Y.C M.T1W 75 W kW 878 W 150 W Output W.1 O W W C . W W Y W SCL WSDA .100 .T 3.3 V OM W C . W Y W .TW with Monitor Pass-Through 3.3 V Single-Supply Projector MSystem .100 Input O W C (One of Three R'G'B' Channels Shown) . WW .100Y W WW 1 2345 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. DLP is a registered trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW 0Y.C M.TW CONTINUED WW .10DESCRIPTION, O W O WacW WW W .CO 0Y.C Minputs. Y.Cinput can part of the T THS7347 flexibility, the device be selectedW for or dc-coupled .TW The ac-coupled W 0 0 Y W T . 1 0 0 WW .1As . . 1 0 M . O W M O W forY.CVBS/Y'/G'B'R' include a sync-tip clampWoption with syncWor a fixedY.bias C'/P' /P'R/R'G'B' C for the O W modes .TW for Ba full W 00 shift toMallow 0 Cinclude Y.C without W input .options TaWdc input orWa dc+Offset . 1 0 0 WW channels T sync. The dc sync . . 1 0 M .1 OM at the output with 0-V WW 00Y.CO .TW Wdynamic range input. 0Y.CO WW C W . W W W Y W T . 1 0 W M .T .100 OM TQFP package.WW. W.1RoHS-compliant .CO .TW OM W C The THS7347 is available in a lead-free, . Y W C W . 0 Y W W W 0 Y W .T W .100 W.1 Y.COM W M.T .100 OM W O W W C . W C W Y W .T W 00 W WW .100Y. M.T .100 W.1 Y.COM W M.T O W O W W C . .C Y W 00 WW by .ESD. .TW recommends WW .1This TW can be damaged M.Tbe handled with .circuit 100 Texas OInstruments 00Yintegrated M that W all.1 integrated circuits O M W C . O W cause 0damage. W W Y Failure to observe handling .C precautions. Y.C and installation Wcan WW proper .TW procedures WW .appropriate M.T .1 0 .TW 100 00Y M . O 1 W M O W W ESD damage from subtle performance degradation complete failure. Precision integrated W be more Y.C circuits.Tmay W device .COcan range Y.C tocould WW 00published WWparametric .Tcause 00changes WW susceptible because very small the device not to meet.1its specifications. M .TW 1 00Y to damage M . O 1 W M . O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O (1) W O W PACKAGING/ORDERING W WW .100Y.C M.TW WW .100Y.C INFORMATION T . WW .100Y.C M.TW O W QUANTITY OM PACKAGED DEVICES PACKAGE W W Y.C WW TYPE W TRANSPORT .CO .TW 0 Y.C WWMEDIA, 0 0 Y W T . 1 0 0 WW THS7347IPHP M.T . 1 0 M . O Tray, 250 1 W M . O W C . W PowerPAD™Y.C .CO .TW HTQFP-48 WW .TW 00Y WW .TW Tape and Reel,.11000 00 WWTHS7347IPHPR M 1 00Y M . O 1 W M . O W .C O W W WofWthis document, W information, 00Y or see M 0Y.COptionMAddendum Y.C and.ordering WW TW at the end (1) For W theW most current package see the Package the.T TI . 1 0 0 T . 1 0 . O 1 W M . O W C web site at www.ti.com. . O W WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW(1) ABSOLUTE MAXIMUM RATINGS O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W Wfree-air .temperature M .1 .T (unless otherwise noted). 00 Over operating range W.1 Y.COM W WW 00Y.CO .TW W 1 Y.COM W W W W W .T THS7347 00 W W.1 UNITY.COM W M.T .100 W.1 Y.COM W O W W W C . W W VSS Supply voltage, GND toY to VW W .T 5.5 W M.T .10V0 .T DD 100 00 VA or GND M . O 1 W M . O W C O W VI Input voltage W –0.4 to V or V V Y. .TW WW .100Y.C M.TW A DD W 100 WW .100Y.C M.TW M . O IO Continuous output current ±80 mA W O W .C O W W W DissipationW WWdissipation W 00Y Y.C WW .100Y.C M.TSee 1 0 Continuous Rating Table Wpower T M.T . . 0 O 1 W M . O W C . Ocondition (2) W W .Cany TJ Maximum junction +150 WW °C .100Y .TW WW .100Y.C M.T WW temperature, M .TW 00Y O 1 W M . (3) O W TJ Maximum junction temperature, continuous operation, long term reliability +125 O W W WW°C .100Y.C M.TW W Y.C WW .100Y.C –65 T+150 . 0 WW range T . 0 M Tstg Storage temperature to °CW 1 W .CO .T OM W W. .CO .TW Y W C . 0 Y W W W 0 0 Y W Lead temperature 300 °C 0 W 1,6 mm .(1/16 .T for 10 seconds 00 inch) from case W.1 Y.COM W.1 Y.COM W W 1 Y.COM W W HBM 1500 V W W W W W M.T .100 M.T .100 O W M.T .100 O W C ESD ratings CDM 1500 V . O W W Y .C W WW .100Y.C 100M.TW WW M .100 .TW 00Y MM V 1 W M . O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .TThese are stress ratings W.1 0 to the device. (1) Stresses above those listedW under absolute ratings cause permanent damage M.T mayconditions .100maximumO OM recommended W.1 indicated C . W only, and functional operation of W theW device at these or any other beyond those under operating C W . Y WW W 0may degrade Y W T . 0 0 W to absolute T . 1 0 conditions is not implied Exposure maximum rated conditions for extended periods device reliability. M . M .1 O Ocondition WW 0of0the (2) The absolute maximum junction temperature any is limited by the constraints silicon process. .C Y.C WW 0under W Y W .TW above this 0 W T . 1 (3) The absolute maximum junction temperature MOperation . constraints. Moperation is limited by theWpackage .1 for continuous O W O W C temperature may result in reduced reliability lifetime device. .C of the Y. W WW .and/or .TW 100 00Y . 1 M W O W WW DISSIPATION RATINGS WW .100Y.C M.TW O W POWER RATING (1) (2) WW .100Y.C M.TW (TJ = +125°C) O W θJC Y.C θJA 0 WW (°C/W) PACKAGE (°C/W) T = +25°C TA = +85°C 0 A .1 W1.2 W HTQFP-48 with PowerPAD (PHP) 35 2.85 W 1.14 W W (1) (2) 2 This data was taken with a PowerPAD standard 3-inch by 3-inch, 4-layer printed circuit board (PCB) with internal ground plane connections to the PowerPAD. Power rating is determined with a junction temperature of +125°C. This temperature is the point where distortion starts to substantially increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and reliability. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . W O W .CO .TW WW .100Y.C M.TW WW .CONDITIONS 00Y 0Y.C M.TW OPERATING WW .10RECOMMENDED 1 M O W O W O W NOM MAX UNIT WW .100Y.C MINM.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O 2.7 5 V O supply voltage W VDD Digital WW WW .100Y.C M.TW 0Y.C .TW WW .V1A00Y.C .TWvoltage. MustW AnalogM supply be equal to.1or0greater thanM VDD V 5 V DD W O WW 00Y.CO .TW WT .CO .TW W C . Y W W W 0 Ambient temperature –40 +85 °C Y W A 00 0 W M .1 .T W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W W .T M.TV .1A0=0 VDD =O3.3 W.1 Y.COM W M .100 ELECTRICAL CHARACTERISTICS, V W O W W C . W C W W .T 00 Y. 00Y WWRL = 150 .TWfor MonitorW Output, 19.1kΩ || 8 pFO Load shorted M.Tto GND for Buffer Output, OM to Monitor W.1SAG pin MGND .100Ω 5 pFOto W C . W W C . .C otherwise Output Pin, Y unless W .TW W noted. WW .100Y 00Y TW . 1 0 WW T M . . 0 M O 1 W O W OM W. TYP 0Y.C M.TW WW OVER 0TEMPERATURE WW .100Y.C M.TW 1 WW .100Y.C M.TW . 0°C W to O MIN/MAX/ O W W to –40°C W WCONDITIONS TEST +25°C +85°C W +25°C W+70°C .CO .TW 0Y.C UNIT Y.C TW TYP . 0 0 Y W T . 1 0 0 WW .1PARAMETER M . 0 M .1 AC PERFORMANCE OM WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 output.T MHz Typ M500 .1 Small-signal M .100 BufferO V = 0.2 V WW 00Y.CO W W WW 00Y.CO 450.TW bandwidth (–3 dB) C . W T Monitor output MHz Typ W . W Y W W .1 M .1 OM Typ W M.T .100 Buffer output O W C 425 MHz . O W W C W Y W –1 dB flatness WW .100Y. .TW 0Y.C outputM.TVW= 0.2 V WW .10Monitor .100 MHzOM.TTyp 375 M W O W C W CO WW .100Y.MHz M.Typ TW V =1V WW .100Y.C 475M.TW Large-signal 0Y.output WW .1Buffer TW . 0 O W M O bandwidth (–3 dB) W .C 240 MHz Typ W W MonitorYoutput .CO V = 2 V WW .100Y .T WW .100Y.C1050 M.TW WW .Buffer M 00 output MV.T=W 1V V/µs Typ O 1 W O W C . O W Slew rate Y .C V .=T2W WW .100V/µs .TW WW .100Y.C output V 1050 Typ .TW WW Monitor M 00Y M O 1 W M . O W Buffer output.CO .C Group delay at WW WW .10ns0Y.C TypM.TW W Y WW .100Y1.2 TW . 0 W Monitor T . 0 100 kHz M 1 output 1.2 Typ OM WW ns00Y.CO W. W .CO .TW WW 00.05/0.05 C . Y W W W 0 Y W Buffer output % Typ M.T W .1 .T 1 00 M . O 1 W Differential gain NTSC/PAL M . O W C W outputY.CO Monitor WW .%100Y. Typ M.TW W 0Y.C M.TW WW .100.1/0.1 0 WW T . 0 1 M . Buffer output degrees CO O WW W W .CO .TW Y.Typ WW 0.1/0.15 C Differential phase NTSC/PAL . 0 Y W W W 0 0 Y W 1 0 WMonitor output 0.15/0.2 degrees Typ M.T . .T 1 00 M . O 1 W M . O W C . O .C Buffer output V.C =1V Typ WW dB .100Y WW Total harmonic .TW WW .–58 .TW 00Y W M 1 00YV = 2 V M.TW M O 1 distortion f = 1 MHz Monitor output W . O dB Typ .C W–57 O W W Y WWdB .100Typ WW 63.100Y.C M.TW WWoutput .100Y.C M.TW M.T Buffer O W O W Signal-to-noise ratio No weighting, up to 100 MHz C . O W 0Y MonitorW dB WW .TW WW 65 .100Y.C M.TW 10Typ W output .100Y.C M.TW M . O W O W –40 Channel-to-channel Buffer outputW CO WdBW .1Typ00Y.C M.TW W f = 100 W Y.MHz WW–36 .100Y.C M.TW 0 Woutput T crosstalk . 0 Monitor dB Typ 1 OM WW Typ00Y.CO .T W. W64W 00Y.CO .TW C . W W Buffer output dB W Y W W 00 MHz M.T MUX isolation f.=1100 W.1 Y.COM W.1 Y.COM W O Monitor output W 66 dB W Typ W C . W W W Y V = 1 V .T W0 100 W M.T 00kHz; M.T .100 Buffer output f =.100 dB Typ. O 1 W M O W C . O W W Gain Y Y.C Monitor output dB W Min/Max.100 W6 W 5.8/6.25 TW .5.75/6.35 0YV.C= 2 V M.TW WW f = 100 M 100 5.75/6.3 0kHz; M . 1 W . O W .CO O W C Buffer output 6 W ns WW Typ . Y C W . 0 Y W W 0 0 Y W Settling time .T 0 W V = 1.V10;00.5% settlingM.T .1 Monitor output 6 TypW W.1 Y.COM W ns O W W W C . W W W Y Buffer output W 0.3W Ω Typ .T .100 Output impedance f = 10 MHz M.T .100 OM W O W C . Monitor output 0.4 Ω Typ W C W .TW 00Y WW .100Y. .TW 1 M . M DC PERFORMANCE O W WW 00Y.CO .TW 0Y.C ±85 WW 0 Buffer output 15 ±80 ±85 mV Max W 1 . 1 M Output offset voltage Bias = dc W. W O W C Monitor output 20 ±120 ±125 ±125 mV Max W WW .100Y. .TW M Buffer output 20 µV/°C Typ Average offset W CO Bias = dc . W W Y voltage drift 0 W T Monitor output 20 µV/°C Typ . 0 OM W.1 Bias = dc W + shift, V = 0 VY.C 255 175/335 165/345 160/350 mV Min/Max W Buffer output 00 Bias = ac 1.0 0.85/1.15 0.8/1.2 0.8/1.2 V Min/Max W.1 W Bias output voltage W+ shift, V = 0 V Bias = dc 235 145/325 135/335 130/340 mV Min/Max O PP O PP O PP O PP O PP O PP O PP O PP IN O PP O PP PP IN Monitor output Sync tip clamp voltage Buffer output Monitor output IN Bias = ac Bias = ac STC, clamp voltage 1.7 1.55/1.85 1.5/1.9 1.5/1.9 V Min/Max 290 200/380 195/385 190/390 mV Min/Max 300 200/400 195/405 190/410 mV Min/Max Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 3 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW =W 3.3 V (continued) WW .100YV.C A = VDD.T 0Y.C M.TWCHARACTERISTICS, WW .10ELECTRICAL M W Output, CO pin shorted to GND for Monitor Output, 19 kΩO|| 8 pF Load Buffer W RL =Y150 WW W to GND for .COΩ 5 .pF 0Y.SAG Y.C WW .TW to Monitor W 0 0 W T . 1 0 0 WW .1Output T M . 1 0 Pin, unless otherwise noted. M . O W M O W .C O W W WW .100YOVER WW .100Y.C M.TW TYP TEMPERATURE WW .100Y.C M.TW M.T O W O W C O W W Y. to.TW MIN/MAX/ 0Y.C M.TW +25°C W+25°C .0°C WW TEST 100to –40°C 0CONDITIONS WW .100Y.CPARAMETER M .TW +70°C +85°C UNIT TYP 1 . O W M O W .C O continued W WDC PERFORMANCE, C W . Y W C W . 0 Y W T W . W 0 W .T W 00Y .100 OM µA W.1 Y.C M.T .1bias OM Input current Bias = dc;W (–)W implies I out .of the pin –1.3 –3.0 W –3.5 –3.5 Max O W C C W . 0 Y W TW . W 0 0 Y W T . 1 0 0 WWAverage T M . . 1 0 bias current drift Bias = dc Typ M . W CO nA/°C .10 OM W.1 W Min/Max .CO .TW2.3 WW WW0.8/3.8.100Y0.7/3.9 T . Bias = ac low bias00Y 0.9/3.6 µA WSTC, WW .100Y.C M.TW M M .1 O µA W Wbias O SyncW tip clamp bias.C current Bias = ac STC, 5.8 3.8/8.0 W 3.7/8.2 3.6/8.3 W Min/Max .CO .TW Y.C Wmid 0 Y W W W 0 0 Y W W .1 5.5/11.1 OMµA.T Min/Max .T 10 00 M . Bias = ac STC, highW bias 8.1 5.7/10.8 5.6/11.0 1 W M . O .CO .TW WW .100Y.C M.TW WW WW .100Y.C M.TW INPUT CHARACTERISTICS W 00Y 1 M . WW 00Y.CO V .TWTyp W range Y.CO InputW voltage Bias = dc WW 00Y.CO 0.toT2W W W W W M .1 .T Bias = ac bias mode W.1 00 M Typ WW 00Y.COkΩ .TW W.1 Y.COM W .CO 25.TW Input resistance W Y W W 0 W Bias = dc, dc + shift, ac STC 3 MΩ Typ 1 0 0 W T M . . 0 O W.1 Y.COM1.5 W WW 00Y.CpF W.1 Y.COM W W W Input capacitance Typ W T W W .T W M. .1 .T OUTPUT 100 00 M . O 1 W M . OUTPUT CHARACTERISTICS: MONITOR O W C O W WW 2.8.100Y. V M.Min TW WW .100Y.C 3.15M.TW2.9 WW .100Y.C M.RTW = 150 Ω to 1.65 V 2.8 O W O W W2.75 00YV.C 150 Ω to GND WW 2.75 W Min W WWswing00Y.CO R.T= W .TW 0Y.C3.05 M.T2.85 0 Wvoltage .1 V OMTyp High output 1 . 1 W M . O W R = 75 Ω to 1.65 V 3.05 C . O W WW .100VY .TW WW .100Y.C2.9 M.TW WW .100Y.C M M .T75W R = Ω to GND Typ O W O W .C Max .TW O = 150 Ω to 1.65 V W W .C 0.25 WW .100Y0.15 .TW 0.28 W0.29 W.10V0Y O WW .100Y.C RM M .TW M W R = 150 Ω to GND 0.1.CO 0.18 0.21 0.22 V Y.C Max O W W W W C W . Y W Low output voltage W W W swing .100Y R =M TtoW1.65 V M.T .1V00 1000.25 OM.T 75.Ω Typ . O W W C O W WW .V100Y. Typ M.TW to W GND 0Y.C M.TW WW .100.08 WW .100Y.CR = 75MΩ.T CO O WWmA 00Y.Min W Sourcing 45 WW 0800Y.CO50 .TW47 C . W W .TW W Output current R = 10 Ω to 1.65 V Y W 1 WSinking .100 .T 1 75 . 50M 47 45 mA. Min OM W M O W C W .CO WW .100Y. .TW WW .100Y.C M.TW OUTPUT CHARACTERISTICS: WW BUFFER M 00YOUTPUT M.TW O 1 W . O W WV High output voltage swing WW W Y.C .CO .TW 1.75 W 00Min WW 2.100Y.C1.8 M.1.75 TW 1 (Limited by input range W and G = 0 dB) 00Y M.T . O 1 W M . O Load = 19 kΩ 8 pF to 1.65 V W C . O W W .C Low Output voltage swing 0Y .TW Y.C WW 0.05.100Y0.12 .TW 0.14 W V W.10Max 0.13 WGW M .TW (Limited by input range and = 0 dB) .100 M O M O W O W .C 47 .TW 45 WmAW .1Min00Y.C M.TW Sourcing 50 Y.ΩCto GND .TW WW 80 .100Y WW .1R0=010 M Output Current W Min Y.CO OMV W R = 10YΩ.C Sinking to 1.65 mA W W75W 0050Y.CO 47 .TW 45 W W .T W 00 W W M .1 POWER SUPPLY: ANALOG W.1 Y.COM M.T .100 O W O W W C . W W3.3 Maximum operating voltage VW Max.100 00Y 5.5 M.TW5.5 WW V .100Y.C M.TW M.T .15.5 O W O W C . O W W Minimum operating voltage V 3.3W 2.7 Y.C2.7 2.7 V W Min Y W .C W 0Ymode, WW V , dc.1+0shift TW M .100 .100 100 103OM.T105 . W Maximum quiescent current V = mV 80 100 mA Max M W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T55 Minimum quiescent current 80 60 0 57 mA Min W V , dc .+1shift 00 mode, V = 100.TmV W.1 W.1 Y.COM W dB W Woutput Y.COM W W Power supply rejection (+PSRR) Buffer 50 Typ W W W .T W .100 M.T .100 POWER SUPPLY: DIGITAL OM W O W C . W C W V Y W WVW .100Y. Maximum operating voltage 3.3 W 5.5 .1005.5 5.5.T Max M M.T O W O W C . W C . Minimum operating voltage V W 3.3 2.7 2.7 2.7 V Min Y Y W .TW 0.65 W 1.2 W.101.30 M .100 Maximum quiescent current V , V =W 0V 1.4 mA Max O W W Y.C .TW 0.65 W0.35 Minimum quiescent current VW , V = 0 V 100 0.3 0.25 mA Min M . O W DISABLE CHARACTERISTICS: ALL CHANNELSW DISABLED Y.C W W M.T .100 Quiescent current All channels disabled 0.1 µA Typ O W C . W Y 0 W 0 Turn-on time delay (t ) 5 µs Typ 1 of final value Time for l to reach.50% W after I C control is initiated W Turn-on time delay (t ) 2 µs Typ W B L L L L L L L L L L L A A A IN A IN DD DD DD IN DD IN ON S 2 OFF 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW =W 3.3 V (continued) WW .100YV.C A = VDD.T 0Y.C M.TWCHARACTERISTICS, WW .10ELECTRICAL M W Output, CO pin shorted to GND for Monitor Output, 19 kΩO|| 8 pF Load Buffer W RL =Y150 WW W to GND for .COΩ 5 .pF 0Y.SAG Y.C WW .TW to Monitor W 0 0 W T . 1 0 0 WW .1Output T M . 1 0 Pin, unless otherwise noted. M . O W M O W .C O W W WW .100YOVER WW .100Y.C M.TW TYP TEMPERATURE WW .100Y.C M.TW M.T O W O W C O W W Y. to.TW MIN/MAX/ 0Y.C M.TW +25°C W+25°C .0°C WW TEST 100to –40°C 0CONDITIONS WW .100Y.CPARAMETER M .TW +70°C +85°C UNIT TYP 1 . O W M O W .C O W WDIGITAL CHARACTERISTICS C W . Y W C W . 0 Y W T W . W 0 W .T W 00Y .100 W.1 Y.COM W M.T .1level OM W High input C voltage V 2.3 Typ O W W C . W W . 0 Y W TV . W 0 0 Y W T . 1 0 0 WWLow level T M . . 1 0 input voltage V 1.0 V Typ M . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W H/V SYNC CHARACTERISTICS: R = 1 kΩ ToW GND 1 0 WW T M . . O V 10 adjust pin W 1.27/1.68 W.1trigger Y.COM W OM W.trigger Schmitt voltage Reference forW Schmitt 1.47 1.35/1.6 W 1.3/1.65 W Min/Max Y.C C . 0 W W W 0 0 Y W T . WSchmitt trigger MV.T .1 .T 10 trigger adjust 00threshold range M . Allowable range forW Schmitt 0.9 to 2 Typ O 1 W M . O W W Y.C WW .100Y.C M.TW WW 00Y.CO .TW Positive-going 0 W T input voltage0threshold . W Schmitt trigger VT+ V Typ trigger W.1thresholdY.COM 0.25W WW 00Y.CO .TW W.1 Y.COM Wrelative to SchmittW W W 0 W T . 0 W M .1 .T Negative-going input voltage 00 M .1threshold Schmitt trigger.1 Typ relative to Schmitt trigger WW 00Y.COV .TW W VT– Y.COM W .CO –0.3.TW WWthreshold Y W W 0 W 1 0 0 W T M . . 1 Schmitt trigger threshold O W .10 pin input M Input resistance into Control OM10 W.pin W resistance WW .100Y.CkΩ M.TTyp WW 00Y.CO .TW WW .100Y.C M.TW W O 1 W M . H/V Sync input impedance 10 MΩ Typ O W C .CO .1TkΩ WW 3.0.100Y. V M.Min TW WW Wto GND WW .100Y.C 3.15M.TW3.05 H/V Sync output voltage 3.0 Whigh 00Y O 1 W M . O W .C O 1 kΩ to GND W H/V Sync lowW 0.1 WW 0.1 Max W .TW W 00YV Y.C WW .100Y.C0.01 M.T0.05 1 0 W output voltage T MMin . . 0 O 1 W M . O H/V Sync source current 10 Ω to GND 50 35 30 30 mA W C . O Y WW21 .100mA WW 00Y.C 10 Ω.TtoW .TW WW .100Y.C35 M.T25W Wcurrent M H/V Sync sink 3.3 V 23 Min O 1 W M . O W O W .C H/V Delay from WW .10ns0Y.C TypM.TW WInput to outputWW .100Y6.5 TW . WW .100Y.C Delay T . M H/V to buffer output skew Typ OM WW ns00Y.CO W W WW 00Y5.CO .TW C . W W W Y W 1 0 W T M.T . . 1 0 M . O 1 W M . O (1) Standard CMOS logic. W C W .CO (VT+ WW .100Y. .TW (2) Schmitt trigger threshold is0defined WW .100Y.C M.TW WW M .T–WVT–)/2. 0 Y by M O 1 W . O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W .T W 00 W WW .100Y M.T .100 W.1 Y.COM M.T O W O W W C . W W WW .100Y WW .100Y.C M.TW M.T .100 M.T O W O W C . O W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M .100 W O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW (1) IH IL Load (2) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 5 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW =W 5V WW .100YV.C A = VDD.T 0Y.C M.TWCHARACTERISTICS, WW .10ELECTRICAL M O O W WW to GND for Monitor 19kΩ Buffer Output,0SAG W RL =Y150Ω Y.C pin shorted WOutput, Wto GND for W .CO || 5pF Y.C|| 8pF Load .TWto Monitor Output W 0 0 W T . 1 0 0 WW .1Pin, T M . . 1 0 unless otherwise noted. M . O W M O W .C O W W WW .100YOVER WW .100Y.C M.TW TYP TEMPERATURE WW .100Y.C M.TW M.T O W O W C O W W Y. to.TW MIN/MAX/ 0Y.C M.TW +25°C W+25°C .0°C WW TEST 100to –40°C 0CONDITIONS WW .100Y.CPARAMETER M .TW +70°C +85°C UNIT TYP 1 . O W M O W .C O W WAC PERFORMANCE C W . Y W C W . 0 Y W T W . 0 Y W .T W .TW .100 W.1 Y.COM MHz M .100 OM W Buffer output 550 Typ O W W C Small-signal . W C W 0 Y W TW V =W 0.2 V . W 0 0 Y.dB) Monitor T . 1 0 0 WWbandwidth T (–3 M . . 1 0 500 MHz Typ M . M output WW 00Y.CO .MHz W.1 Y.COBuffer W Typ WW 00Y.CO .TW450 W T output W W 1 0 WW T M . 0 M .1 –1 dB flatness V = 0.2 V M. WW 00Y.CO MHz W.1 Y.CO Monitor output 400 WW 00Y.CO .TW W W .TW Typ W W WLarge-signal MMHz .1 .T 1 00 M . Buffer output V =1V 525 Typ O 1 W M . O W O W WW .100Y.C MHz WW (–3 0dB)0Y.CMonitor bandwidth .TW Typ W V = 2 V WW .100Y.C M.T325 output W T M . M Ooutput WW 00Y.COV/µs .TWTyp W.1 YBuffer V =1V WW 00Y.CO 1200 C W . W W W W T Slew rate . W M .1 .T V = 2 V 00 Monitor output V/µs Typ W.1 Y.COM1350 W OM WW 00Y.CO W.1 Y W C . W TW W . W 0 W T . 1.15 ns Typ 1 0 W delay at .100 Buffer outputM.T M . Group W W.1 Y.COM .CnsO .TTyp O W W 100 kHz W Y W Monitor output 1.15 C W . 0 W W W .T 0Y output M.TW W M Typ .10 100 0Buffer M . O 1 W . 0.05/0.05 % O W C W Differential W NTSC/PAL .CO WW .100Y. % M.Typ TW WW .100Y.C 0.1/0.1 .TW W gain .1Monitor 00Y output M.TW M O W O W Y.C output 0.05/0.05 TW .CO NTSC/PAL WW .100degrees WW Buffer .TW W Y WW .100Y.C . 0 Wphase T MTyp Differential . 0 M O 1 W M . O W Monitor output 0.05/0.05 degrees Typ C . O W WW .100dBY .TW Y.C V .=T1W WW .100Y.C–71 M.TW WW Buffer M V Typ 00output Total harmonic O 1 W M . O W O W .C distortion f = 1 MHz WW .10dB0Y.C TypM.TW output Y.C V = .2TVW WW .100Y–67 TW . 0 WW Monitor 0 M 1 Buffer 63.CO Typ WW dB00Y.CO W. outputY.CONoMweighting, W WW 00Y W W Signal-to-noise ratioW up to 100 MHz W W T . 1 W Monitor.1output T M.T . . 1 00 65 dB Typ M . O W M O W C O W W Y. WW dB Buffer output0Y.C 0Y.C M.TW WW .10–40 Channel-to-channel 100 TypOM.T WW TW . . 0 f = 100 MHz 1 W M . O W –36 crosstalk C Monitor W WW dB.100Y.Typ WWoutput00Y.CO .TW WW .10640Y.C M.TW WBuffer M.T output dB Typ O 1 W M . O W C . OMHz MUX Isolation WW dB .100Y WWoutput 00Yf =.C100 .TW WW .16600Y.C M.TW Monitor Typ W M .TW O 1 W M . O W O W Buffer f = 100 V W Y.C WWdB .100Typ Woutput Y.C kHz; V .=T1W WW 0.100Y.C M.TW Gain 0 W M.T 0 1 Monitor output. f = 100 kHz;M V =2V 6 5.8/6.25 5.75/6.3 5.75/6.35 dB W Min/Max CO O W . 0Y WW WW 00Y.CO .TW .TW WW 6 .100Y.C M.TW Buffer ns 10Typ Woutput M . O 1 W M . Settling time V =1V O ; 0.5% settling O W Monitor output WnsW .1Typ00Y.C M.TW WW 00Y.C W WW 6 .100Y.C M.TW W T . O 1 Buffer output W. 0.3W Ω WW Typ OM .CO .TW Y.C W C Output impedance f = 10 MHz . 0 Y W W .T W 0 0 Y W MonitorW output 0.4 Ω .1 M .10 OM WTyp M.T .100 O W C . O W W C . Y DC PERFORMANCE W W WW .100Y WW .100Y.C M.TW M.T .100 M.T ±85 O W O Buffer output 15 ±80 ±85 mV Max W C . O W W W W Output offset voltage Y.C W Max .100Y W WW Bias .=1dc00Y.C M.TW M Monitor output 20 ±120 mV 100 ±125OM.T±125 . W W .CO O WTyp W C . Y W C W . 0 Y W W Buffer output 20 µV/°C W 0 0 Y W Average offset .T 0 W Bias = .dc100 .1 .T voltage drift W.1 Y.COM 20 W µV/°C Monitor output TypW OM W W W C . W W W 185/345.100175/355 M .T 0YV = 0 VM.TW W Bias = dc.1+ 0shift, 265 mV Min/Max O 170/360 W Buffer output O W C . W C W . Y W Bias = ac 1.5 1.3/1.65 1.25/1.7 1.25/1.7 V Min/Max W 0 Y W T W Bias output voltage M. .10135/335 O130/340 .100 0 VOM.T W Bias = dc + shift, V = C 235 145/325 mV Min/Max W C W W W 2.65 W2.5/2.8 Monitor output 0Y. 2.45/2.85 Y. 0 0 W T . 1 0 . Bias = ac 2.45/2.85 V Min/Max 1 OM W. WW 200/390 195/395 C . W W Y W Buffer output 295 205/385 mV Min/Max Sync tip clamp W Bias = ac STC,.clamp 100 voltageOM.T voltage W Monitor output 300 200/400 195/405 190/410 mV Min/Max .C W WW .10I0Y T . Input bias current Bias = dc; (–) implies out of the pin –1.4 –3.0 –3.5 –3.5 µA Max OM W C . Y Average bias current drift Bias =W dc W 10 nA/°C Typ 100 . W Bias = ac STC, low bias 2.4 0.9/3.9 0.8/4.0 0.7/4.1 µA Min/Max WW Sync tip clamp bias current Bias = ac STC, mid bias 6.2 3.9/8.4 3.8/8.6 3.7/8.7 µA Min/Max O PP O PP O PP O PP O PP O PP O PP O PP IN O PP O PP PP IN IN B Bias = ac STC, high bias 6 8.6 Submit Documentation Feedback 6/11.2 5.8/11.4 5.7/11.5 µA Min/Max Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW =W 5 V (continued) WW .100YV.C A = VDD.T 0Y.C M.TWCHARACTERISTICS, WW .10ELECTRICAL M O O W WW to GND for Monitor 19kΩ Buffer Output,0SAG W RL =Y150Ω Y.C pin shorted WOutput, Wto GND for W .CO || 5pF Y.C|| 8pF Load .TWto Monitor Output W 0 0 W T . 1 0 0 WW .1Pin, T M . . 1 0 unless otherwise noted. M . O W M O W .C O W W WW .100YOVER WW .100Y.C M.TW TYP TEMPERATURE WW .100Y.C M.TW M.T O W O W C O W W Y. to.TW MIN/MAX/ 0Y.C M.TW +25°C W+25°C .0°C WW TEST 100to –40°C 0CONDITIONS WW .100Y.CPARAMETER M .TW +70°C +85°C UNIT TYP 1 . O W M O W .C O W WINPUT CHARACTERISTICS C W . Y W C W . 0 Y W T W . 0 W .T W 00Y range M.TW .100 W.1 Y.COM W .1voltage OM Input Bias = dcWW 0 to 3.4 Typ O W W C . C W 0 Y W TV . W 0 0 W T . 1 0 WW .100Y. T M . . 1 Bias = ac bias mode 25 kΩ Typ O W OM W. Input Wresistance OM W3 Y.C WW .100Y.C M.MΩ TW Typ Bias = dc, STC 0 WdcW+ shift,.ac T . 0 WW .100Y.C M.TW 1 M WW 00Y.CO pF.TW Typ InputW capacitance .CO 1.5 WW 00Y.CO .TW W W W Y W WOUTPUT .CHARACTERISTICS: M .1 .T 00 OUTPUT W.1 Y.COM W WW 00Y.CO .TW W 1 Y.COM MONITOR W W W W R = 150 Ω W to 2.5 V 4.65 4.6 4.6 V Min .T4.8 00 W W.1 4.5 Y.COM M.T R = 150 Ω to GND .100 W.1 Y.COM 4.7 W 4.55 O W W 4.5 V Min W W C . 0 W T Y W T High output voltage .4.7 WW M. Typ .10 .TWR = 75 Ω to 2.5 100 00swing M . O 1 W V V M . O W C O W WW .100Y. V M.TW WW .100Y.C M4.6.TW R = 75 Ω to GND Typ WW .100Y.C M.TW O 0.2 W O WW0.30 00Y.CO W C W . RW = 150 Ω to 2.5 V W 0.25 0.28 V Max C W . Y W T W .T W M. Max .1 .TR = 150 Ω to GNDW W.100 00Y M O 1 W M . 0.1 0.19 0.23 0.24 V O C W .C W Low outputW .CO .RTW WW .100Y. V M.Typ TW 00Y 0.24M.TW W voltage swing = 75 Ω to 2.5 V W 1 00Y . O 1 W M . O W O W 75 Ω to GND WW .100YV.C MTyp .TW WW .100Y.C0.085 M.TW WW .100Y.C MR.T= W O W O W Sourcing 110 85 80 75 mA Min C . O W Y .C R =.T10W Output current W Ω to 2.5 V WW75 .100mA .TW WW .100Y.C110 M.T85W W M Sinking 80 Min 00Y O 1 W M . O W O W WW .100Y.C M.TW OUTPUT CHARACTERISTICS: W Y.C OUTPUT WW .100Y.C M.TW WW .100BUFFER T . W O 3.1 High output voltage swing .CO OM W W WW 00Y C 3.4.C 3.0 3.0W V00Y Min W . W W W Y W T (Limited by input range and G = 0 dB) . W T M.T .1 1 00 M . O 1 Load = .19 kΩ 8 pF to 2.5 V W M . O W C O W Low output voltage swing WW .V100Y. Max M.TW 0.14 0Y.C 0.12 WW .100.05 .TW0.13 0Y.C M.TW WWand G =.100dB) (Limited by input range M CO O WWmA 00Y.Min W W .CO85 .TW80 WW 110 C . Sourcing R = 10 Ω to GND 75W Y W W 0 Y W 1 0 W M.T . .T2.5 V Output current 1110 00 R = 10 M M . O W O W C SinkingW.1 Ω to 85 80 75 mA Min O WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M POWER SUPPLY: ANALOG O W O W O W W Y.C WWV .100Max Maximum operating voltageW VY.C 5.5 W WW 5.0.100Y.C5.5 M.5.5 TW 0 W T M.T . 0 O 1 W M . O W C . Minimum operating voltage 2.7 2.7 V MinY O W W V W .C W 5.0 00Y2.7 0 .TW 117 W mA W.10Max WW .10V0,Ydc.C M.T .TVW= 100 mV W W Maximum quiescent current + shift mode, 90 .1 112 OM 115 O M O W V , dcY+.C .C 65 .TW 63 WmAW .1Min00Y.C M.TW W Minimum quiescent current WW shift mode, V = 100 mV 68 WW 90 .100Y 0 T . 0 M 1 W Typ Y.CO OM W. Buffer Output Power supply rejection (+PSRR) dB W W46W 00Y.CO .TW C . W W .T W 00 Y W W M .1 POWER SUPPLY: DIGITAL W.1 Y.COM M.T .100 O W O W W C . W W5.0 Maximum operating voltage VW Max.100 00Y 5.5 M.TW5.5 WW V .100Y.C M.TW M.T .15.5 O W O W C . O W W Minimum operating voltage V 5.0W 2.7 Y.C2.7 2.7 V W Min Y W .TW WW V , .V10=00YV.C M.TW M .100 12 00 M . W Maximum quiescent current 1 3 3 mA Max O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T0.4 Minimum quiescent current 1 0.5 0 0.4 mA Min W V , V .1=000V .T W.1 W.1 Y.COM W OM W W W C DIGITAL CHARACTERISTICS . W W W Y W .T WV .100 M.T .100 High level input voltage 3.5 V Typ OM W O W C . W C W V Y W 0 T . 0 WVW .100Y. T Low level input voltage 1.5 W Typ . 1 OM W. OM W C . W DISABLE CHARACTERISTICS: ALL CHANNELS DISABLEDY.C Y W W W W .100 M.T .100 W Quiescent current All channels disabled 1 µA Typ O W W C . W W Y W 0 W T . Turn-on time delay (t ) 5 µs Typ 0 Time for l to reach 50% of final value OM W.1is initiated C after I CW control . Turn-on time delay (t ) 2 µs Typ W .TW 00Y 1 M . O W (1) Standard CMOS logic. WW .100Y.C W WW L L L L L L L L L L L A A A IN A IN DD DD DD IN DD IN (1) IH IL ON S 2 OFF Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 7 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW =W 5 V (continued) WW .100YV.C A = VDD.T 0Y.C M.TWCHARACTERISTICS, WW .10ELECTRICAL M O O W WW to GND for Monitor 19kΩ Buffer Output,0SAG W RL =Y150Ω Y.C pin shorted WOutput, Wto GND for W .CO || 5pF Y.C|| 8pF Load .TWto Monitor Output W 0 0 W T . 1 0 0 WW .1Pin, T M . . 1 0 unless otherwise noted. M . O W M O W .C O W W WW .100YOVER WW .100Y.C M.TW TYP TEMPERATURE WW .100Y.C M.TW M.T O W O W C O W W Y. to.TW MIN/MAX/ 0Y.C M.TW +25°C W+25°C .0°C WW TEST 100to –40°C 0CONDITIONS WW .100Y.CPARAMETER M .TW +70°C +85°C UNIT TYP 1 . O W M O W .C O W WH/V SYNCYCHARACTERISTICS: C W . Y W C W . 0 Y W T W R = 1 kΩ To GND . W .T 0 W .10 .TW .100 OM V W M .10trigger OM C Schmitt adjust pin voltage Reference forW Schmitt trigger 1.54 1.43/1.65 1.38/1.7 Y 1.35/1.73 . O W W C . W C W . 0 Y W TW Min/Max . 0 0 W T . 1 0 WWSchmitt.1trigger M . .TW 1 00Y thresholdMrange Allowable range for. Schmitt trigger adjust 0.9 to 2 V Typ M W WW 00Y.CO .TW W .CO .TW Winput CO . Y W Positive-going voltage threshold W 0 Y W 1 0 0 WW T M . . Schmitt trigger V Typ 0 VT+ .1 threshold OM 0.25 trigger W WW 00Y.CO .TW W.1 Y.COM W relative to Schmitt .C W W Y W W 0 W T . Negative-going input voltage 0 threshold M –0.3 WSchmitt trigger M .1 .T 00 O W.1 threshold trigger WW 00Y.CO V .TW Typ W.1 VT–Y.COM W relative to Schmitt C . W W Y W W W .T 00 0 W Schmitt trigger pin input W.1 Y.COM M.T Input resistance into .10threshold Control kΩ Typ W.1 pin Y.COM 10 W O W W resistance W C . W W .TW W 00 0 Y W T . 1 0 0 W T M . . 1 0 M . H/V Sync input.1 10 Typ M WW 00Y.COMΩ .TW W impedance WW 00Y.CO 4.8.TW 4.7 .CO .TW W Whigh Y W H/VW Sync output voltage 1 kΩ to GND 4.6 4.6 V Min 1 0 M . W .10 W.1 Y.COM CO OM 1 kΩ to GND W W H/V SyncW lowW output voltage 0.01 0.05 0.1 0.1 0Y. V Max W C W . W T .T W M. Min .10 .T10WΩ to GND W W.100 00Y M O 1 W M . H/V Sync source current 90 60 55 55 mA O C .CO .10 WW 25 .100Y.mA M.Min TW WW WW .100Y.C 50M.TW30 H/V Sync current 00Y Ω to 5 V 27 Wsink TW O 1 W M . O O Delay from input to outputWW H/V Delay WW WW .100Yns.C MTyp .TW W 0Y.C 6.5 M.TW Y.C W 0 0 W T . 1 0 . O 1 W M . O H/V to buffer outputW skew 5 ns Typ W C . O WW .100Y .TW W Y.C WW .100Y.C M.TW WW threshold M .T(VT+ O W M .100 is defined (2) Schmitt triggerW by – VT–)/2. O W O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T W .100 W.1 Y.COM W M.T .100 OM W O W W C . W C W Y W .T W W WW .100Y. .100 M.T .100 OM W M.T O W C . O W W C W Y W WW .100Y. .TW WW .100Y.C M.TW M.T .100 M O W O W C . O W WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .T W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Load 8 (2) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O (1) (2) W Y.C WW .100Y.C M.TW FOR I2C W 0INTERFACE WW TW . 0 0Y.C REQUIREMENTS WW .10TIMING T . 1 M . O W MV to 5 V. O W 2.7 W At VDD = O WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O WMODE W W Y.C FAST.MODE WW 00Y.CO .TW STANDARD C . 0 W W W 0 Y W 1 0 W MT . .T 1 0 PARAMETER MIN MAX MIN MAX UNIT M . O 1 W M . O W C . O W W W .C Y W C W . 0 Y W T W . W 0 0 Y W f Clock frequency, SCL 0 100 0 400 kHz T SCL00 W .1 .T M. .10 OM 1 W M . O W C . O W W C Y 0.6 .TW t Pulse duration, SCL high 4 W µs WW .100Y. .TW WW w(H).100Y.C M.TW M .100 M O W O tW Pulse duration, SCL low 4.7 1.3 µs W C w(L) . O WW .100Y .TW300 ns WSDA Y.Ctime, SCL.Tand WW .100Y.C M.TW WWtr .100Rise M 1000 O W M W300 W FallYtime, W Y.C WW 00Y.CO .TW .COSCL and 0 W .T300 W tf SDA ns 0 W 1 0 WW T M . . 1 0 M . O 1 W M to SCL . Setup time,OSDA O W C . W C W . tW 250 100 ns Y W C su(1)W W . W W W .T 00Y 0Ytime, SCLMto.T Wt .100 0 OM.T 1 0 M . 1 W . Hold SDA 0 O W h(1) W W W ns .C Y.C W W .CO .TW 0 Y W T W . 0 0 Y W T . 1 0 0 W M . t(buf) Bus between 4.7 1.3 µs M .1 M stop and start conditions .10free time O WW 00.60Y.CO .TWµs WSetup WW 00Y.CO .TW C . W W tsu(2) time, SCL to start condition 4.7 W Y W W M .1 M .1 M.T .100 O WW 0.600Y.CO .TW th(2) WW Hold time, start condition to SCL 4 µs WW 00Y.CO .TW C . W W Y W 10.6 W Setup.1time, M . .Tcondition 1 00 SCL to stop M . O W M tsu(3) 4 µs W W W Y.C WW 00Y.CO .TW CO . 0 W T W . W 0 Y W 1 0 W T M pF . Cb Capacitive 400 400 .bus line 1 0 load for each M . O 1 W M . O W C O .C W WW .100Y. WW I20C0address .TW Y.C = 01011(A1)(A0)(R/W). W .TW 00Y Information (1) The See the Applications section for more information. WTHS7347 M .TW 1 M . O 1 W M . 2 O W I C specification. O to comply with version 2.1 W (2) The THS7347 of the W was designed .C WW .100Y.C M.TW W .TW 00Y WW .100Y.C M.TW 1 M . O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W W.1 Y.COM W M.T .100 W.1 Y.COM W O W W W C . W .T 00 W .T WW .100Y t w(H) M.TW t w(L) tO tf .100 r M W.1 Y.COM W W O W W C . W W Y W W .T W Y.C W WSCL .100 M.T .100 OM W M.T .100 O W C . O W W C W Y W WW .100Y. .TW WW .100Y.C M.TW M.T .100 M O W O W C O W WW .100Y. .TW WW .100Y.Ct h(1) M.TW WW .100Y.C t su(1) M .TW O W M O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W SDA W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W Timing .T 00 W Figure W.1 Y.COM M.T 1. SCL and SDA .100 W.1 Y.COM W O W W W C . W .T W 00 W WW .100Y M.T .100 W.1 Y.COM M.T O W O W W C . W W WW .100Y SCL WW .100Y.C M.TW M.T .100 M.T O W O W C . O W W Y W WW .100Y.C M.TW WWt .100Y.C t M.TW M .100 W t t O W su(2) h(2) su(3) (buf) .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W SDA .100 M.T .100 OM W O W C . W C W Y W W Y. W Stop.Condition WStart 100 M.T Condition M.T .100 O W O W C .C WW .100Y. WW Figure .TWStop Conditions 00Y2. StartMand 1 . W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 9 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W W O W .CO .TW WW .100Y.C M.TW BLOCK DIAGRAM WW .1FUNCTIONAL 00Y WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W 0 W .1 W.1 Y.COM W M1 .T .10 Channel OM W O W W C . W C Y W .T W2:1 .TW WW .100Y. Input AM.TW .100 M .100 OM + X1 W O W C . O W W C C 2 TW W .TW1 Buffer Channel 00Y Y.Input WW .100Y. .TW WW .100Channel M - W.1 M A M. O O Output (To ADC) W C . O AC W W Y.CSync WW .100Y TW . 0 WW T DC . 0 0Y.C 3 M.TW WW .10Channel M 1 . OM +OffsetW DC InputC AO WW 00Y.CO .TW W CTIP .Clamp W W Y W W 0 Y. W T + . 0 WW .100H-Sync T ACOM 1 Monitor W.1 Y.CChannel M. OM W.1BIAS O W W C W . W C W . Disable Y W W .T= OPEN 10W0 Output 0YA WW .10Input M.T .675 .TW 100 M . O W M O W W V-SyncY.CO WW .100Y.C .TW WW .100Y.C M.TW WW .Input Channel 1 SAG M .TW 00 A O 1 W M O W O W 150 W 0Y.C W WW WW .100Y.C M.TW 1 kW 878W WW .100Y.C M.TW M.T .10 O W O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W W 2:1 0Y.C M.TW 0Channel WW .1X100Y.C M.TW + W 1 WW .100Y.C M.TW . Buffer C2 O O WW Output W Y.(To WW AC 00Y.CO .TW C . ADC) .TW 0 W W W 0 Y W 1 W M . .T 1 00 M . 1 W M . DC Sync O W .CO .TW O W W C . Y W C W . 0 Y W W +Offset TIP 00 W DC 0 Y W .T + W .1 W.1 Y.COM W M.T .100 Clamp OM W O W W C AC. W C W Channel Y W .T W W WW .100Y. BIAS .100 2 Monitor M.T .100 Disable Output OM W M.T O W C . O W W C 675 W = OPEN . Y W .TW WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W 2 SAG.C O W W WW WWChannel 00Y WW .100Y.C 1 kWM.T878 1 WW .100Y.C M.TW 150 W M.T . O W O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W WW 00Y.CO .TW WW .100Y.C M.TW W WW .100Y.C 2:1 M.TW X1 + 1 M . O W .CO .TW O WW3 Buffer W Channel W W 00Y WW .100Y.C M 1 - .T WW .100Y.C M.TW . Output (To WADC) Y.COM W AC O W O DC W W C . W C W . Y W W Sync W .T W M.T .100 .TW 100 00Y +Offset M . O 1 TIP W DC M . O W C . O W .C Clamp WW WW .100Y .TW 00Y + M.TW WW .100Y.C M.TW ACM 1 . Channel 3 Monitor O W O W BIAS O W Disable W W OutputWW .100Y.C M.TW Y.CWW .T675 WW .100Y.C M.TW = OPEN .100 M O WW 00Y.CO .T W WW 00Y.CO .TW ChannelW C . W W Y W 3 SAG W M .1 .T 00 M 150 W W1.1kW Y878 WO WW 00Y.CO .T W.1 Y.COM W C . W W Channel 1 W W W .T 1 00 W .T Input B M .12:100 W.1 Y.COM W Horizontal SyncWW. 0Y.COM + O W W C . W W Channel 2 WW .100Y M .TW M.T Buffer OUTPUT WW.10 .100 -M O W Input B .CO O W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .T 00 Channel 3 W.1 W.1 Y.COM W W W.1 Y.COM W W Input B W W W .T Horizontal Sync W .100 M.T .100 OM Monitor OUTPUT W O W H-Sync C . W C W Y W W Input B WW .100Y. M.T .100 M.T O W O W C .C 2:1 V-Sync WW .100Y. Vertical Sync WW .TW 00Y+ 1 M . Input B W Buffer OUTPUT O W W C W W WW .100-Y. T . M W .CO .TW Y kW 0 WW .10 Vertical Sync 0 VOM W 1 +1.4 Monitor OUTPUT C . W Y W 00 1 . WW W MUX MUX I2C, I2C, PUC SCHMITT SDA SCL MODE SELECT TRIGGER ADJUST A1 A0 +VDD DGND +VA AGND NOTE: The I2C address of the THS7347 is 01011(A1)(A0)(R/W). 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 +VA AGND CH. 1, MONITOR OUTPUT CH. 1, SAG CH. 2, MONITOR OUTPUT CH. 2, SAG CH. 3, MONITOR OUTPUT CH. 3, SAG H-SYNC MON. OUTPUT V-SYNC MON. OUTPUT +VA AGND 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 AGND SCHMITT-TRIGGER ADJ. MUX MODE MUX SELECT I2C, A1 I2C, A0 SDA SCL PUC VDD DGND V-SYNC BUFFER OUTPUT . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW CONFIGURATION WW .100Y.CPIN M .TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW THS7347IPHP WW .100Y.C M TW . WW .100Y.C M.TW (PHP) O WW 00Y.CO .TW W WW 00Y.COHTQFP-48 C W . W W (Top View) W Y W T . 0 W .1 W.1 Y.COM W M.T .10 OM W O W W C . W C W Y W .T W W WW .100Y. .100 M.T .100 OM W M.T O W C . O W W C W Y W WW .100Y. .TW WW .100Y.C M.TW M.T .100 M O W O W C . O W WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W W.1 Y.COM W M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M.T .100 .TW 100 M . O W M O W C O W Y. WWCH. 1,.BUFFER .TW 36 Y.C A 1 WW .100Y.C M.TW 100 OUTPUT WW CH. M .TW 01,0INPUT O 1 W M . O W .C O W WW CH. 1, BUFFER 00YOUTPUT M.TW WW .100Y.C M.TW 35 1 0Y.CA M.T2W WW CH..12,0INPUT . O 3 WW 00Y.CO .TW W WW 00Y.CO .TW 34 C AGND CH. 3, INPUT A . W W W Y W W 00 W.1 Y.COM W M.4T W.1 Y.COM W 33 W.1INPUT Y +VAW H-SYNC, A .CO W W W W .T W M.T .100 .TW 100 00 M . O 1 W M . O W C . 32 CH. 2, BUFFER OUTPUT 5 O V-SYNC, WINPUT A WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O 31 6 CH. 2, BUFFER OUTPUT W AGND THS7347 WW .100Y.C M.TW WW 00Y.CO .TW WW .100Y.C M.TW W PowerPAD O 1 W 7 30 AGND CH. 1, INPUT W W. B Y.COM W W Y.C WW 00Y.CO .TW 0 W W 0 W W 2, INPUT.B100 M.T .1 1 M . 8 M.T 29 CH. +VA O W O W C O W Y. WW OUTPUT .TW Y.C9 WW .100Y.C M28.TW CH. 3, BUFFER 100 W3,W M . .TW CH. INPUT B.100 O W M O W .C W W CH. 3, BUFFER WWOUTPUT WWB 00Y.10CO .TW 00Y WW .100Y.C M 1 27 .T WINPUT H-SYNC, M.T . O 1 W M . O W C W Y. CO WW .TW WW .100Y.C 26M.TW AGND W 11. V-SYNC, W INPUT B 100 M . .TW 00Y O 1 W M . O W .C W WW WW 0012Y.CO .TW OUTPUT 100Y AGND WW .100Y.C 25 M.TWH-SYNC BUFFER W M.T . O 1 W M . O W C . O W WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .T W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W W 0Y W WW .100Y. M.T M.T FUNCTIONS WW.10 O TERMINAL O W C Y. W WW .100Y.C M.TW 100 . TERMINAL W O I/O W DESCRIPTION NAME NO. WW WW .100Y.C M.TW O W Input Channel CH. 1, INPUT A 1 I A WVideo W Y.C 1, Input.T 0 W 0 1 CH. 2, INPUT A 2 I Video Input Channel 2, Input MA . O W C . CH. 3, INPUT A 3 I WW Video Input 0 Channel 0Y 3, Input A .1Sync, W H-SYNC, INPUT A 4 I Horizontal Input A W W V-SYNC, INPUT A 5 I Vertical Sync, Input A CH. 1, INPUT B 7 I Video Input Channel 1, Input B CH. 2, INPUT B 8 I Video Input Channel 2, Input B CH. 3, INPUT B 9 I Video Input Channel 3, Input B Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 11 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W W O W .CO FUNCTIONS WW .100Y.C M.TW (continued) WW .1TERMINAL .TW 00Y WW .100Y.C M.TW M W O W .CO .TW O TERMINAL W WW 00Y WWI/O .100Y.C M.TW DESCRIPTION 1 WW .100Y.CNAMEM.TW M . W NO. O W .CO .TW O W W C . Y W C W . 0 Y W W 0 Y W I Horizontal B .TW 10 Input B.T W M .100 Sync, O 100 INPUT W.1 Y.COM W M .H-SYNC, W O W W C . W V-SYNC, INPUT B 11 I Vertical Sync, Input B C W 0 Y W .T W WW .100Y. M .110preset .TW M.TBit A1. Connect to V forWa logic .100Address O O W M I C Slave Control value or GND for a logic 0 preset W C . O W C 17 I C, A1 W .TW 00Y WI Wvalue..100Y. .TW 1 WW .100Y.C M.TW M . M O W O O W I CW Slave Address Connect to V W for aW logic 1 preset0value logic 0 preset Y.Cor GND for W Y.CControl Bit.A0. IWW .TaW 0 T 1 WWI C, A0.100Y.C M.TW 18 value. .100 M . M O W O O W W .CI C bus. Pull-up Y.C= 2 kΩ and.TaW WW line00ofYthe have a minimum W19 00value Y.C TWresistor shouldW . SDA I/O WSerial data 1 1 0 WW T M maximum value . . 0 M . = 19 kΩ. Pull up to V . O 1 W M . O W C . O W Ya maximum .value W Y.C resistor.should WW WW 00Y.C W 00and W TW have a minimum I C bus clock1 line. value = 2.1 kΩ 00Pull-up WSCL M T = 19 -kΩ. .T20 I M . O 1 W M . O W Pull up to V . O W .C Y.C W WW power-up. .TW WW .100Y .Tfor 100 Connect WW .100Y.C M.TW M . Power-Up Condition. Connect toM GND all channels disabled upon to V (logic O W O and monitor outputs ON withW .C O 21 W PUC I high) toW setW buffer outputs to OFF W1 to 3 .C W ac-bias configuration 00Y on Channels 1 00Yenabled.M.TW WW .100Y.C M.TW andW both H-Sync/V-Sync M.T . 1 . O W O W C WSelect (pin016) C Connect .control. Y. of the .MUX. W configuration MUX Wto logic low for W TW WW 00Y.CO 15 .TW I Sets the WMUX .TMUX. MUX 1 0 control O 0for0Y WMODE M . 1 M . Connect to logic high I C control of the 1 W M . .C W W .CO WW 00Ywhen WW 00Y.CO 16 .TW I ControlsW 00Yto logic lowM TW(pin 15) is set toW the MUX selection MUX MODE logic low. Connect for.T MUX . 1 . 1 MUXW SELECT M . O 1 W M . selector set to Input A. Connect to logic high for MUX selector set to Input B. O W C O W W W .C Y. .T WW1 from.1either .ATorWCH. 1, INPUT B.WConnectW 100 00Y WW .100Y.C35, 36M.TWO Output Channel CH. 1, INPUT to .ADC/Scalar/Decoder. Both M M O CH. 1, BUFFER OUTPUT O W together pins should be connected on the PCB. O W Y.C WW .100Y.C M.TW WW .TW 00CH. WW .100Y.C M.TW Output Channel 1 2 from either 2, INPUT A or CH. 2, INPUT B. Connect toW M . OPCB. CH. 2, BUFFER OUTPUT 31, 32 O .CO Both.TW O W ADC/Scalar/Decoder. W .Cthe pins should be connected on Y WW together C W . 0 Y W W W 0 0 Y W T . W 00 .10CH. 3, INPUT W.1 Y.COM M.T Output Channel 3 from W either to ADC/Scalar/Decoder. Both OAMor CH. 3, INPUT B. ConnectW W.1 27, CH. 3, BUFFER OUTPUT 28 O O C . W C W . 0 Y pins should be connected together on the PCB. W W .TW W 0 0 Y W T . 1 0 0 W T M . . 1 0 M . O 1 W W H-SYNC BUFFER OMO Horizontal Sync BufferW W. .CO .TH-sync W input. WW .100Y.C M.TW W Output. .Connect OUTPUT 00Yto ADC/Scalar WW .10025Y.C M .TW 1 M O W V-SYNC BUFFER WW .CO .TWinput. WW .CO O .Vertical Y WW .100Y.C M.TW 24 Sync BufferW Output. Connect to ADC/Scalar V-sync W 0 Y 0 0 W T OUTPUT 0 M O W.1 Channel WW 00Directly W.1 Y.COM VideoW .C1 O Y.C to .TW WOutput Monitor Pass-Through SAG Correction pin. If SAG isW not used, connect W Y W 0 W T CH. 1, SAG 45 O . 1 0 W M . .T1, OUTPUT pin 46. 00 CH. M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W CH. 1, MONITOR W W .TMonitor Pass-Through Output 46 00 O Video INPUT M CH. 1, INPUT A or CH. 1,W .1 1 fromOeither W.B.1 Y.COM W OUTPUT WChannel W.1 Y.COM W C . W W Y W W 00 to M.T WOutput Channel .T pin. If SAG is not used, connect Monitor Pass-Through 0 O Video W .1Directly .T 1002 SAG Correction M . CH. 2, SAG 43.10 W M O W CH. 2, OUTPUT pin 44. .CO .TW O W W .C Y W C W . 0 Y W W W 0 0 Y W T . 0 W 44 .100 O VideoMMonitor M .1 .T Pass-Through Output Channel CH. 2, MONITOR W either CH. 2, INPUT A or CH. 2, INPUT B. OM W.1 2 from .CO .TW O W W C OUTPUT . Y W C W . 0 Y W W Y W .T 00 W .10 .TW OM 100O Video Monitor Pass-Through Output Channel Directly to W M OMpin. If SAG is not used, connect W.13 SAGYCorrection C . O CH. 3, SAG 41 W. W C . Y W C CH. 3, OUTPUT pin 42. W . W .T 00 W WW .100Y .TW M.T .100 W.1 Y.COM M O W CH. 3, MONITOR O W W C . 42 O Video Monitor Pass-Through Output Channel either A or CH. 3, INPUT W Y CH. 3, INPUT WB. OUTPUT WW 3 .from WW .100Y.C M.TW M.T .100 100 M.T O W O W C . O W W H-SYNC MONITOR Y W .C Sync.Monitor Y.C W 40 W O Horizontal WOutput. .TW OUTPUT W TW Pass-Through M .100 100 00Y M . 1 W M . O W .CO O W W C . Y W C V-SYNC MONITOR W . 0 Y W W W 0 0 Y W 39W O Vertical Sync Monitor Pass-Through Output. .T 0 OUTPUT W.1 M.T .100 W.1 Y.COM W O W W W C . W W 6, 12, 13,W 26, Ground pin Internally, these pins connect to DGND, although it is Wanalog signals.W AGND I .Tfor 00Y Reference M.Tfor best results. .10to0the properOsignals 30, 34, 37, 47 toM have the AGND and DGND connected .1recommended W O W C . W C Y W Y. Power.T W .TW +V 29, 33, 38, W 48 WI Analog 2.7 1 to or greater than VDD. . V0to05 V. MustObeMequal M Supply Input pins. ConnectWtoW .100 PositiveO W C . C V 22 I Digital Positive Supply pin for I C circuitry and H-Sync/V-Sync outputs. Connect to 2.7 V to 5 V. . Y W W 0Y W .TW 100 0GND . 1 M . W DGND 23 I Digital pin for HV circuitry and I C circuitry. W .CO .TW WW WIW Defaults 0to0Y 1.45 V (TTLM compatible). Connect to external voltage reference to adjust H-Sync/V-Sync input 1 . Schmitt Trigger Adjust 14 W from 0.9 O thresholds V to 2 V range. WW .100Y.C M.TW O W WW .100Y.C W WW 2 2 DD 2 2 DD 2 DD 2 DD DD 2 A 2 DD 2 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW 0Y.C M.TW INFORMATION WW .10APPLICATIONS WW .100Y.C M.TW WW 00Y.CO .TW W WW 00Y.CO .TW .CO .TisWtargeted for W Y W 0 WW .1The M for numerous other THS7347 RGB+HV video buffer applications. Although 0 M W.1it canY.be Ovideo W.1 ofY.the COused OMthe needs and requirements W W applications, C W C signal were the most important design parameters of the W . 0 W W .TW W T .silicon-germanium W .10 BiCom3OM .TonWthe revolutionary 100 00Y Built M . 1 W THS7347. complementary (SiGe) process, THS7347 M . O W C O W W the W W video parts 0Y. Y.C WW Tlow . W 0 0 Y.C many T features notW typically found in integrated while consuming very power. Each . 1 0 0 WW incorporates T M . . 1 0 . WThis architecture .1 OM W .CO .Tallows OM W W channel configuration is completely independent of theWother channels. for any C W . Y W C . 0 Y W W W 0 Y for each W .T W configuration M the configuration part what .100by the end W.1dictating M.T channel to be dictated .100 OMuser, rather than the W .CO O W W C . Y W C W . 0 Y W W must be—resulting in a highly flexible system. .TW W 0 0 Y W T . 1 0 W M . .T 1 00 M . O 1 W M . O W O the following features: WTHS7347 The WW .100Y.C M.TW WW .100Y.C M.TW 0Y.Chas M WW .TW 2 .10 •WIW C interface for system. Y.CO O easy interfacing to the WW 00Y.CO .TW WW C W . W W 0 Y W T . W• Single-supply M .T 00 .10quiescent current of 80 mA at 3.3 V..1 OM Wlow .CO .TW OM to 5-V operation with WW W.1 Y.C2.7-V C . Y W W 0 Y W W W 0 W .T • 2:1 input W 100 W.1 Y.COM W .100mux. OM.T OM W.bias, W W C . W C W . • WInput configuration accepts dc, dc + shift, ac or ac sync-tip clamp selection. Y W W W .T M.T .100 .TW 100 00Y M . O 1 W M . O W C • 500-MHz amplifier to drive ADC/Scalar/Decoder. .CO buffer WW .100Y. WW unity-gain .TW WW .100Y.C M.TW M .TWhas an internal 00Y O 1 • W Monitor Pass-Through path fixed gain of 2 V/V (+6 dB) amplifier that can drive two video lines W M . O W O W W W .C Y.C W W 0 Y W T . W 0 0 Y.C per channel 0with dc coupling, traditional ac coupling, or SAG-corrected ac coupling. W T . 1 0 0 WW T . .1 OM W. OM output impedance W OM Pass-Through path W.1 the .Chigh • WhileW disabled, Monitor (> 500 kΩ ||Y8.CpF) WWhas a00very C W . 0 Y W .TW W 0 Y W T . 1 0 W T M . . 1 0 M . O 1 W M . O • Power-UpWControl (PUC) the THS7347WtoWbe fully disabled or have the Monitor Pass-Through function .C COall allows WW .100Y.C M.TW W W enabled 0Y Y.on Wupon initial TW . 0 0 (withWac-bias mode channels) device power-up. T . 1 0 M . O 1 W . .CMode OM I2C or a general-purpose Won .CO (GPIO) Y WW input/output W 0 Y W TW • Mux W is controlled either pin, based the MUX WW 00by .pin W 0 0 Y.C W T . 1 0 M . .T 1 M . O 1 W M . O logic. W W WW .100Y.C M.TW WW 00Y.CO .TW 0Y.C trigger WW .10Schmitt Tthreshold . • H-SyncW and V-Sync paths have an externally-adjustable M 1 . OM WW 00Y.CO .TW .CO .TW WasW0.1-µA. C . Y W WW W 0 Y W • Disable W mode reduces quiescent current to as low 0 M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 WVOLTAGE M .1 .T 00 OPERATING W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W .T M .1 impact on .T 2.7 V to 5 W 100 to +85°C The THS7347 W is designed V overW a .-40°C The W Mfrom .100to operate OM temperature range. .CO .TW O W W C . Y W C W . 0 Y W performance over the entire temperature range is negligible because of the implementation of thin film resistors W W 0 0 Y W T . 0 W .T capacitors. 00 W.1 Y.COM W and high-quality, low temperature W.1 Y.COM W OM W W.1 Y.Ccoefficient W W W W .T W TW as close .1to00do so OM.T .placed 100 to theOpower-supply 00should be M . 1 W M . A 0.1-µF to 0.01-µF capacitor as possible pins. Failure W O W W C W W such asW100 0Y.C M.TW Y.large 0 0 Y.Cringing.T T . may result in the THS7347 orW oscillating. W Additionally, a capacitor, µF, should 1 0 0 WW .outputs . 1 0 M O W W. OM W 1 line to minimize be placed on the power-supply issues with 50-Hz/60-Hz line frequencies. .CO W WW .100Y.C M.TW WW .100Y T . WW .100Y.C M.TW M O WW 00Y.CO .T W WW 00Y.CO .TW C . W W INPUT VOLTAGE WW Y W .T 00 W.1 Y.COM W.1 Y.COM W OMsignal range from ground W W.1 for Y W C . W W The THS7347 input range allows an input to approximately (V + – 1.6 V). However, W W S 0 W M.T .100 .T M.T factor .100 the O O W M .10of W C because of the internal fixed W gain 2 .V/V (+6 dB), the output is generally limiting for the allowable . O W Y C W V. As a result Y.C W of the WW .T3.4 WW with M .100 linear input range. For example, the linear input range.1is00 from GND to .TW 00aY5-V supply, M 1 W M . O W .CO O linear input range from W W the allowable C . Y W C gain, the linear output range W limits GND to 2.5 V at most. W . 0 Y W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 13 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W WW 00Y.CO .TW WW .100Y.C M.TW PROTECTION W W 0Y.C OVERVOLTAGE WW .10INPUT T . 1 M . O W M O W W internal junction WWhigh-speed THS7347 built using W a very bipolar process..TThe W .CO .TisW 0Y.C Y.C complementary WWand CMOS 0 0 Y T . 1 0 0 WW .1The M . 1 0 M . O W M very small geometry devices. These.C breakdowns are reflected in O W for these O voltages are relativelyWlow W W breakdown Ware .TW ESD protection W Ratings 00Y with internal 0Y.Cand M Y.C Maximum Wtable. All TWdevice pins . Absolute input output protected 1 0 0 WW the T M . . 1 0 . O W .1 O W Figure OM Wdiodes to the power supplies, as shown Y.C 3. .TW WW .100Y.C M.TW 0 WW in 0 WW .100Y.C M.TW 1 O W OM W. O W WW .100Y.C M.TW WW .100Y.CV M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W W.1 Y.COM W M.T .100 W.1 Y.COM W O W W External W C . W .T W 00 W WW .100Y Internal Input/ M.T Circuitry .100 W.1 Y.COM W M.T O W O W Output W C . W W WW .100Y Pin WW .100Y.C M.TW M.T .100 M.T O W O W C . O W W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M.T .100 O W O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W O WW 00Y.CO .TW W .COProtection WInternal C W . Y W Figure 3. ESD W W 0 Y W T . 0 W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W M 100 M.T above and below .overdrive These W diodes provide voltages W.1the supplies. M.T protection to input .100 moderate O W .CO The O W W C . Y W C W . 0 Y W W .TW protection diodes can typically support 30 mA of continuous current when overdriven. W 0 0 Y W T . 1 0 W M . .T 1 00 M . O 1 W M . O W WW .100Y.C M.TW WW 00Y.CO .TW WW .100Y.C M.TW TYPICALW CONFIGURATION 1 OM WW 00Y.CO .TW W. WW 00Y.CO .TW C . W W W Y W W M .1 4. It shows .TTHS7347 as an ac-coupled A typical application circuit Figure 00 usng the M buffer is shown in Ovideo W.1withinput .COwith .TW OM (such as the TVP7000) WanWoutput W.1a video C . Y W C the THS7347 driving ADC 0-dB gain and also driving line W . 0 Y W W W 0 W 00 drivenMto.Tthe ADC and the W W M .1 00Y M.T Sync signalsWare 6-dB gain. The Horizontal Monitor Output O W.1also Y .CO .TW OVertical W W.1 Yand C . Y C W . 0 W W W signals .Tthese channels canWeasily separately. Although the 0computer resolution W M .10 be the .TW R’G’B’HV .100are shown, M .1 0enhanced-definition OM (SD) Y’P’BP’R (sometimes W .CO .TW O W W C high-definition video (HD), (ED), or standard-definition labeled . Y W C W . 0 Y W W W 0 0 Y W T . 0 W labeled M .T Y’U’V’ or incorrectly These channels also W.1 andYthe .100Y’C’BC’OR)Mchannels. OMbe S-Video Y’/C’ channels W.1 could CO . W W C W . W C W . 0 Y W W composite video baseband signal (CVBS). could .be W that theWR’G’B’ channels T professional/broadcast 00 W .10G’B’R’ OM.T .TNote 1sync 00Y based M . 1 W M . O W C signals or other R’G’B’ variations on the placement of the signals that are commonly called R’G’sB’ . O WW .100Y WW 0(sync .TW WW .100Y.C M.TW 0Y.Con allMsignals). (sync on Green) orW R’sG’sB’s M .TW O 1 W . O W O W W .C Y.C Winputs .TW W 00be 0Y Y.C shown WW TW . 1 0 0 The second set of inputs are connected to another set of inputs. Again, these can WW (B-Channels) T M . . 1 0 M . O 1 W M . W W signal00toY.C .CO for.Tvirtually either HD, ED, SD, or R'G'B'/G'B'R' any W input W .CO signals. WW 00Yvideo .T W The THS7347 0Yallows WW flexibility 0 W T 2 . 1 M . be driven into the THS7347 regardless ofMthe other set of inputs. Simple control of the I C configures W.1the Y.COM .1 O W O W W C . W Y be configured W THS7347 for any conceivable example, the Y.C For WTHS7347 .TW to haveWChannel WW combination. M.T .1010 MSee .100can O 100 W M.TChannel 3 are connected .Channel O W C . Input connected to input A while 2 and to input B. the multiple application O W W .C Y W .C W W W documentWfor 0Yconfiguring .TW M .100 notes sections explainingW the I2C interface details these options. 10on 00Y laterMin.Tthis M . 1 W . O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y T the more common.1 W for the Note that the Y' term is used rather .T throughoutWthis document, M.than .10 .100luma channels Oluminance Wdefinition OM WW W C . W C luminance (Y) term. The reason for this usage is to account for the true of as stipulated by W . Y W W W 0 Y W T . 0 0 W T departs from true.1luminanceObecause .Video 0 M the CIE (International CommissionW on.1Illumination). a nonlinear term, M W .C W .CO .TR'G'B' W signals. WW gamma, is added to the true RGB signals These.1R'G'B' 00Y signals WW 00Y to form M.Tare then utilized to 1 M . O W O W mathematically create luma (Y').WTherefore, true luminance (Y) is not maintained, and thus the difference in C W Y.C WW .100Y. 0 W T . 0 terminology arises. 1 M . W .CO .TW WW 00Y WW from the nonlinear R'G'B' terms and This rationale is also utilized forWthe chroma (C') term. Chroma is derived M .1 .COis derived therefore it is also nonlinear. True chominance WW 00Y(C) W from linear RGB, and thus the difference between W M.T signals (P'B/ P'R/U'/V') are also referenced this way .1 color difference chroma (C') and chrominance (C) exists.W The O .C to denote the nonlinear (gamma-corrected) WW signals. 00Y 1 . WW R'G'B' (commonly labeled RGB) is W also called G'B'R' (again commonly labeled as GBR) in professional video S+ systems. The SMPTE component standard stipulates that the luma information is placed on the first channel, the blue color difference is placed on the second channel, and the red color difference signal is placed on the third channel. This approach is consistent with the Y'P'BP'R nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be 14 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 75 W 75 W 75 W 75 W INPUT1 75 W . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O in the system. Since W W color difference Y.C and the WW(P'B).1is00next blue channel W 0Y.CcolorMdifference WW the TW . 0 0Y.C first WW .10placed T M.T red . 1 . O W M O channel (P' ) is last, then it also makes logical sense to place the B' signal on the second channel and the R' W C O R W .C W W compatibility .Con 0Y. achieved YThus, WW is .1better TW . W 0 0 Y W T . 0 0 the third channel, respectively. hardware when using G'B'R' WW .1signal T M . 0 O OM sync is embedded W.1G'B'R'Y.systems, .Cchannels; OM WW W ratherYthan C W R'G'B'.W Note that for many on all three this configuration Y W C W . 0 W T W W .T W M. .10 .T 100 00not always M . O 1 may be the case for all systems. W M . O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M Monitor Output O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW 2.2 mF O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W Red W Y W W M .1 .T 00 W.1 Y.COM W WW 75 0W0Y.CO .TW W.1 Y.COM 75WW W W W W .T 00 W W.1 Y.COM Y’ W M.T .100 W.1 Y.COM W 2.2 mF O W W W C . W .T 00 GreenW W WW .100Y M.T .100 W.1 Y.COM W M.T O W O W W C . W W 75 W.100 WW .100Y WW .100Y.C M75.TWW M.T M.T O W O W C . O P’B W W W W W 2.2 mF WW .100Y.C M.TW 00Y 1 WW .100Y.C Blue T M.T . . O W M O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C 75M TW M O W. W O W O W W75WW .100Y.CP’ M.TW WW .100Y.C M.TW WW .100Y.C M.TW R O806 W WW 00Y.CO .TW W H-Sync WWV 00Y.CO .TW V C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T W 1.4 kW .T .100 W.1 Y.COM W M .100 OM W O W W C . W C W 00 W 48 47 46.1450044Y43 42 41 M TW 40 .39 38 37 WW .100Y. M.T .TW O W.1 +3.3 O W 1 36 806 O W M C V-Sync . V +1.8 V W W C . W .TW 00Y W2 W .100Y .TW35 WW .100Y.C M.TW M 0.1 mFW.1 M O O V O W 3 WW 34 kW WW .100Y.C M.TW W 0Y.C M.TW Y.C W 0 WW .1001.4 T . 4 33 1 . O W ADC OM W WW 00Y.CO .T32W 0.1 mFWW 5 0Y.C M.TW W 0 W Scalar/ 1 WW .100Y.C 0.1 mF T . . M 31 .1 6 O WW Decoder W Y’ Y.COM W W .CO .30 Y.C WWTHS7347 W V Component 0 Y W W 7 0 0 W T 1 0 0 W M.T . .T 1 0 M . O 1 W M . O W 8 29 C 480i W W 75 W O Y. .TW WW .100Y.C M28.TW 0.1 mW F 9 100 WW .100Y.C M.TW 576i M . O W O 27 W O W 10 2.2 mF 480p WW .100Y.C M.TW WW .100Y.C M .TW WW P’B.100Y.C M.TW 11 576p 26 O WW 00Y.CO .TW W WW 00Y.CO25 .TW C 12 720p . W W W Y W W 1 21 22 23 24OM 13 14 15 16 17 18W 19 .20 W.1 Y.COM W 1080i M.T .1750W0 O W W C . W C W . Y W W 1080p W .T W M.T .100 .TW 100 02.20Y mF M . O 1 W M . O W G’B’R’ C . O P’RW WW .100Y .T WW .100Y.C M.TW WW .100Y.C M.TW OM W O W C . 3.3 V 3.3 V O W W C . Y 75 W W .C and .TW W WW .100Y WW .100YH-Sync M.T .100 V-SyncM 0.1 mF M.T O 22 pF W 22 pF O W C . O W W Not Used Y W WW .100Y.C M.TW WW .100Y.C M.TW M .100 W O W .CO O W W .C Y C 100 WW100 W . 0 Y W W W 0 0 Y .T5 V 0 W .1 .T 3.3M V to 00 W.1 YV.C= O WW W.1 Y.COM W W W W W W .T W .100 IC M.T .100 OM W O W C . W C W Y W Y. if desired. W WbeWac- or .dc-coupled (1) Inputs and/or outputs can M.T .100 100 M.T O W O W C W to any .C = 2.2 Y. (2) H-Sync and V-Sync input resistance kΩ, but may beW changed WW as.1shown .TW 100desired resistance. 00Y aboveM . W (3) If the Monitor or Buffer PCB trace it isO recommended to place at least WisW> 25 0mm, WW a 10-Ω resistor in series with each 0Y.C M.TW Wissues signal to reduce PCB parasitic 1 . O W W Y.C WWY'P'B.P' Figure 4. Typical R'G'B'HV and 0R0AC-Coupled 1 M.T Inputs and DC-Coupled Output Configuration O W C . WW .100Y W WW A A A INPUT2 A A 2 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 15 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W 2 W CO WW .100Y.C M.TW W NOTESWW .100Y.C M.TW WW .10I0CY.INTERFACE T . M CO WW 0I02Y W .CO registers WW the I.2C COinterface is used toWaccess C. is a two-wire W of theWTHS7347. Yinternal .TW serial interface W 0 Y T . 1 0 0 WW .1The T M . . 1 2 M 0 . O W M IO C Bus Specification, Version 2.1, January 2000). W(see the .C Oby Philips Semiconductor W W developed W The THS7347 Y.Cspecifications. Wconsists .T(SDA) W 0of0Y 02.1 Y.C WWversion TW The bus . designed in compliance with a data line and a clock 1 0 0 WW was T M . . 1 0 M . Oare pulled high. WSCL lines M pull-up structures. .1 (SCL) Owith O is idle, both SDA and W C . W W C line When the bus All the W . Y W C W . Y W .T .Topen-drain 100 and O WW I2C-compatible M . .TW connectWto theWI.21C00bus 00Y M devices through I/O pins, SDA SCL. A master device, 1 W M . O .C W W W CO a controls The master W or a digital 00isYresponsible 0Y.C M Y.microcontroller WWsignal.1processor, TW the bus.W . 1 0 0 WW usually T M.T for generating . . 0 O 1 W M . O W C the SCL signal and device addresses. The master also generates specific conditions that indicate the START . W W Y W CO W 0under Y.C and/or.Ttransmits Won TW . W A slaveWdevice 0 0 Y.of 1 0 0 WWand STOP T M . data transfer. receives data the bus control of the master . 1 0 . O W OMthe standard mode W Wand .Ckbps) OM works as a slave W.1 TheY.THS7347 C W . Y W C device. supports transfer (100 and fast mode W 0 Y W T W . W W2 .T 00 0 kbps)Mas.Tdefined W transfer M fully functional .10tested toObe 1Specification. 0(400 M . 1 W in the I C Bus The THS7347 has been . O W C . O W Wit is not00specified .C mode Y.C at.this WW .100Y WW TWtime. the high-speed but Wwith M.T .TW(3.4 Mbps)W 1 00Y M . O 1 W M . O W W access00cycles. .CO .TI2W Y.C WW .100Y.C M.TW WW5 shows Figure C start and W stop .TW W 1 00Y the basic M . 1 M . O consists of the following: WW 00Y.CO .TW W access WW 00Y.CO .TW C . W W The basic cycle W Y W W M .1 .T M .1 100 OM WW 00Y.CO .TW W.condition • AW start WW 00Y.CO .TW C . W W Y W W .T W.1 Y.COM W .100 cycle • A slave W.1 Y.COM W OM W Waddress W C . W W W .T W number M.T .100 .TW • Any 100 0of0Ydata cycles M . O 1 W M . O W C W .CO .TW WW .100Y. .TW • A stop WW .100Y.C M.TW WWcondition M 00Y O 1 W M . O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W .T 100 W.1 Y.COM W W.1 Y.COM W OM W W.SDA W C . W W W .T W M.T .100 .TW 100 00Y M . O 1 W M . O W C . O W W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M.T .100 O W O W C O W WW .100Y. .TW WW .100Y.C M.TW WW SCL.100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW P WW .100Y.C S M.TW O W O W O W WW .100Y.C M.TW W WW .100Y.C M.TWStop Start WW .100Y.C T . Condition OM WW 00Y.CO .TW W WW 00Y.CO .Condition W W W W T WW .100Y.C Figure T .1Conditions W.1 Y.COM W M. 5. I2C Start and W Stop OM W O W W C . C W Y W .T W 00 W WW .100Y. M.T .100 W.1 Y.COM W M.T O W O W W C . W WW .100Y .TW WW .100Y.C M.TW M.T .100 GENERAL I2C PROTOCOL M O W O W C . O W .C Y.C WW .100aY .T WWcondition. .TW WWdata .1transfer .TW • The master initiates a start condition exists when 100 TheOstart 00Y byMgenerating M . OM W W C . O 2 W W C . Y W 5. All I C-compatible high-to-low transition on the is W high, as00 shown in Figure Y W W Wwhile SCL W Y.CSDA line Woccurs M.T .100 M.T .1 O W M.T .100condition. devices should recognize aW start O W C . O W Y W Y.C and the W .TW 0Y.Cpulses WW the TWtransmits W M .100 .and • The master then generates the 7-bit .address read/write direction bit 100 0SCL M 1 W M . O W .CO O W Wall transmissions, C . Y W C R/W on the SDA line. During the master ensures that data is valid. A valid data condition W . 0 Y W W W 0 0 Y W .T 0 W .T high period 00 W.1 Mentire requires the SDA line to be stable the of the (see Figure 6). All devices OM W.1clock Ypulse O W W.1 during C . W C W . W W Wrespective recognize the address sent W by the.1master .TW it to the 00Y andMcompare M.T addresses. Only the .100internalOfixed W O W C slave device with a matching address generates an acknowledge (see Figure 7) by pulling . W C Wthe SDA line low . Y W acknowledge, .Tmaster WW .TW 100 00Y SCL cycle. M . during the entire high period of the.1ninth On detecting this W the knows that a M O W W .CO .TW Y.C communication link with a slave established. 0 Y W 0 0 WWhas .been 0 .1 W 1 Y.COM W WW W W W .T 00 W.1 Y.COM W W SDA W M.T .100 O W C . WW .100Y W SCL WW Data Line Stable; Data Valid Change of Data Allowed Figure 6. I2C Bit Transfer 16 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W WW 00Y.CO .TW WW .100Y.C M.TW W W WW .100Y.C Data T . M .1 M Output O WW 00Y.CO .TW W by Transmitter WW 00Y.CO .TW C . W W W Y W 0 W .1 W.1 Y.COM W M.T .10 OM W O W W C . W C W Y W .T W W Not Acknowledge WW .100Y. .100 M.T .100 OM W M.T O W C . O W W C W Y W WW .100Y. .TW WW .100Y.CData M M.T .100 .TW M O W Output O W C . W COReceiver WW .100Y .TW WW .100Y.C M.TW WW .100Y.by M .TW O W M O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW Acknowledge O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W OM WW 00Y.CO .TW W.1 SCL W C . W W From W Y W .T 00 W .1 9 OM .100 MasterOM.T 8 WW 1 W.1 2 M O .C W C W . W C W . Y W W 00Y 0 W T . 1 0 WW .100Y T M.T . . 1 M . O W M O W C O W 0Y. for M.TW WW Clock WW .100Y.C M.TW 10Pulse WW .100Y.C M.TSW . O W O Start Acknowledgement W W W Y.C WW 00Y.CO .TW 0 W W 0 W 1 WW .100Y.C Condition T M.T . . 1 M . O W M O W C O W WW .100Y. .TW 0Y.C M.TW WW 7. I2.C 0Acknowledge WW .100Y.C M.TW M Figure 1 O W O WW 00Y.C W WW .100Y.C M.TW WW 00Y.CO .TW Weither Tthe . 1 M . • TheW master generates further SCL cycles to transmit data to slave (R/W bit 1)Wor receive data O from 1 M Oeither Wthe transmitter. W. bit 0). .CO .Tthe Y.C So,.T WW C W . 0 Y W W the slave (R/W In case, the receiver must acknowledge data sent by anW W 0 0 Y W 1 0 0 W M . .T 1 0 M . O 1 W M . O W masterY.or C is theTW acknowledge can either be generated byW the on whichY.one Wsignal Y C by theTslave, W depending .CO WWcan . W 00 0 data W . 1 0 0 WW T M . . receiver. The 9-bit valid data sequences consisting of 8-bit and 1-bit acknowledge continue as long 1 0 M . O 1 W M . O W C . O W W W Y as necessary .C8). .TW W WW .100Y.C M.TW WW (see.1Figure M.T .100 00Y O W M O W C . W W 1O 2 3 4 5 6 7 8W9 1 20Y3.C 4 5 6 W W .T 7 8 9 W W.100Y OM.TW 0 WW .100Y.C M.TW 1 M . O W O W WW .100Y.C M.TW W Y.C WW .100Y.C M.TW 0 WW SCL T . 0 O W O W OM W.1 WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WWSDA .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TStop C W . W W W Y W W M .1 .T 1 00 OM WW 00Y.CO .TW W.1MSB Y.COM WAcknowledge WW. 0Y.CAcknowledge W W W W Data .T 0 W Address W.1 Y.COM M.T .100 SlaveO W.1 Y.COM W W W W C . W .T 2W 00 W Data .Cycles WW .100YFigure M 8. .IT C Address and 100 M.T W.1 Y.COM O W O W W C . .C Y W WaWstop .condition .TW the SDA W 100 M.T .low .TW generates 100 00Y theMmaster M • To signal the end ofW the data.1transfer, by pulling line from O W O W C . O W W .C Y W bus andWstops the to high while the SCL transaction Y.C (see Figure WW .Tthe 00Yreleases WWline .is100high M .100 .TW 2 5). This 1 M . W M O W communication link with theW addressedCslave. All I C-compatible devices must recognize the stop condition. .CO O W C . Y W W . 0 Y W W W 0 0 Y .T 0 Upon the receipt of a W stop condition, .T know thatWthe bus 00 all devices W.1 OMand they wait for aWstart W.1is released, OM W.1address. C . W C condition followed by a matching W . Y W W W Y W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 17 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W .C O W W WW cycle, drive the SDA signal 1 line during the.T cycle, so W the transmitting 00Y 0Y.CmustMnot WW .1device TW . 0 0Y.C a write WW .10During T M acknowledge . . O W M O that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the W C . O W W C W . Y W W cycle. AWstop condition .C device 0 is initiated Yone SCL.Tclock T by the transmitting . W 0 0 Y W 1 0 0 pulls the SDA line low for WW .1receiving T M . . 0 M .1 O OMthe last byte is transferred. WW W device W Note that the .C9Oand .Figure after 10 show an example cycle. Yof.Ca write.T WW Figure C W . 0 Y W W W 0 0 Y W T 1 0 0 W Mto the THS7347, in . .Tnot allow multiple W 1 transfers 0 M . O 1 THS7347 does write to occur. See the example, Writing W M . O C W W .C W .CO more WW .100Y. WW Section M.T .TWinformation.W W.100Y OM.TW 00Y12 for M O 1 W . O W WW .100Y.C M.TW Receiver .TW 0Y.C WW .10From WW .100Y.C M.TW M O O WNoWAcknowledge W Y.C (SDA High) WW 00Y.CO .TW C A= . 0 W W .TW W 0 Y W 1 W M . .T Address W A W.DATA 1 00 M A = Acknowledge O 1 W M . O S Slave A DATA P A O W Condition W Y.C SW = Start .TW WW .100Y.C M.TW 100 WW .100Y.C M.TW M . P = Stop Condition O W O W .C O W W W WW = Write 00Y WW .100Y.C M.TW WW .100Y.C M.TW M.T R = Read W.1 O O W O W .C From WTransmitter WW .100Y.C M.TW W .TW 00Y2 WW .100Y.C M.TW 1 M . O Cycle W 9. IYC.CWrite O WW 00Y.CO .TW W Figure W C W . W W W 0 Y W T . W M .1 .T 00 M .10 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W 0 W Acknowledge .1 Acknowledge Acknowledge M .1 .T M 10Start W O(Receiver) W .CO .TW (From Receiver) (Transmitter) OM W W.Condition C . Y W C W . 0 Y W W W 0 Y W .T W .100 W.1 Y.COM W M.T .100 OM W O W W C . W C . A5 .TA1W A0 R/W ACKW D7 D6 00D1Y D0 ACK .TWD7 D6 W D0 ACK.100 .T WW .100YA6 D1 M .1 OM W M O W C . O W W C W Y W WW .100Y. .TW WWSDA .100Y.C M.TW M.T .100 M O W O W C . O W .C Other.TW Last Data Byte .C Address WW .1Stop .TW First Data 00Y 00Y WW WW .10I02 CYDevice M .TWand 1 M . O W M Condition Byte Data Bytes O W Read/Write O Bit W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW Figure 10. Multiple Byte Write Transfer O WW 00Y.CO .TW W .CO WW C W . Y W W W 0 Y W T . 0 W .T 00 W.1 Y.COM W W.1 Y.COM W OM Wthe W.1the slave W C . W W W During a read cycle, receiver acknowledges the initial address byte if it decodes Y W W M.T .100 asOits M.Tdevice becomesWaWaddress .100the master M.T .100initial Oacknowledge O W C . address. FollowingWthis by the slave, receiver and C . W W 00Y fromM.TW WW .TW 00Yreceived 0Y.Cby the .1bytes .TW When the acknowledges W data bytes slave. master.1has all of the requested data 0sent M O 1 W M . O W C keeping Y.C COcondition the slave, the not acknowledge the SDA signal W 0before Y.by WWhigh .just WW 00Y.(A) .TW W is initiatedWbyWthe master 0 0 T . 1 0 W T M . 1 M . O W M .1 it asserts the stop (P) W condition. This sequence terminates a read cycle, as shown in Figure 11 and Figure 12. O W .C O WW .from W read transfers 00Ythe M.TW 0Y.C SeeMthe Y.Callow multiple WW to TWexample, Reading . Note that the THS7347 not occur. 1 0 0 WW does T . 1 0 . 1 OM WW 00Y.CO .TW THS7347, in Section W 12 W for. more information. WW 00Y.CO .TW C . W W Y W W M W.1 Y.COM W M.T .100 W.1 YA.C= O O W W No Acknowledge (SDA High) W C W . W W S Slave P .T W Address M.T .100 .TW A DATA WA W 100 A = Acknowledge 00YR A MDATA M . O 1 W . O C . O W Start Condition WW .100Y .T WW .100SPY==.CStop .TW WW .100Y.C M.TW Condition M OM W O W C . O W W W = Write C . Y W W Y.C WW .10R0Y = Read M.T WWTransmitter M.T .100 .TW O W MReceiver .100 O W C . O W W Y W WW .100Y.C M.TW WW .100Y.C M.TW 2 M .100 W O W .CO O W Figure 11. I C Read Cycle W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Start Y W W Y. W .TAcknowledge M.T Not .100 Condition W 100 M .Acknowledge O W O W C (From (From.C Y. WW .100Acknowledge WW .1Receiver) TW .Transmitter) 00Y (Transmitter) M W O W WW WW .100Y.C M.TW O W A6 D0 D7 ACK D1 W D7 D6 Y.C D0 ACK SDA 0 WA0WR/W ACK 0 1 M.T . O W C . WW .100Y W Stop 2 Last Data Byte Data Other I C Device Address WWand First Condition Byte Data Bytes Read/Write Bit Figure 12. Multiple Byte Read Transfer 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W WW .100Y.C M.TW W WW .100Y.C M.TW 0Y.C Address WW .10Slave T . M O W connected .CO resistor. WW via00aYpull-up W Wbe COSDA T and the SCL must voltage W supplyW .the Y.C to a positive .TW These resistors W 0 Y W T . 1 0 0 WW .1Both M . . 1 2 0 M . O W M range comply When is free, both lines O with the I C specification. .C the bus O from 2 kΩ to 19 kΩWinWorder to W should W .C WW condition .Tmaster W byte isW 00Y from the 0Y Y.C The address TW the START . high. the first byte received following device. The 1 0 0 WW are T M . . 1 0 M . O THS7347 address W M .1 five bits O to 01011. The next W C . O W W C first (MSBs) of the address are factory-preset two bits of the are W . Y W C . 0 W T W 0Y I2C, A1 W .TWI2C, A0 pins. 2.10 2M. 0the WW controlled .T 1 00Y by the M . logic levels appearing on and The I C, A1 and I C, A0 address inputs O 1 W M . W .C O W TTL/CMOS W .CO0, or.Tactively W Wby toW VDD for logic 1, GND 0 for driven .TW The device 00Y logicMlevels. 0Ylogic Y.C WW 1 0connected WW can.1be T . . 1 0 M . O W M O W C address is set by the state of these pins and is not latched. Thus, a dynamic address control system be . O W C Wto four THS7347 0Ycan beMconnected Y.system. WW devices TW could . W devices 0 0 Y.C WW T . 1 0 WWused.1to00incorporate T . several on the same Up to the . 1 . W OM 1 lists the possibleW .CO OM requiring additional W I2C bus .CTable Yfor WW same glue logic. addresses the THS7347. W .Cwithout 0 Y W .TW W 0 0 Y W T . 1 0 0 WW T M . . 1 0 M . O 1 W .C OM W W. W .COSlave WW1. THS7347 00Y W Table Addresses W .TW 1 00Y WW .100Y.C M.TW M.T . 1 M . O W O W O W 0Y.C MREAD/WRITE WW .10WITH SELECTABLE .TW WW .100Y.C M.TW WW .100Y.C M.TWFIXED ADDRESS O W ADDRESS PINS BIT O W W W Y.C WW 00Y.CO .TW C . 0 W T W . W 0 Y W 1 1 (A0) OMBit 0 (R/W) W Bit 7 (MSB)100 Bit 6 .T Bit 5 Bit.14 Bit 3 Bit 2 (A1) .Bit M W M . O W C W W Y. .CO 0 1 .TW 0 W .T0W WW 1 .100Y.C M 1000 WW M . 00Y 1 M.TW 0 O 1 W . O W 0 W 1O 0 WW .10 00Y.C M.1TW W 0 WW 1 .100Y.C 1 M.TW W0W .100Y.C T . 1 OM 0 1 1 0 WW 1 00Y.CO 0 .TW W WW 00Y.CO .TW C . W W W Y W W 0 1 1 0 1.1 M1 .T 0 00 1 W.1 Y.COM W WW0 00Y.CO 0 .TW W.1 1Y.COM W W W 0 W 0 1 1 1 W W M .1 .100 1 OM.T W M.T 0 .1001 W .CO1 .TW O 0 1 1 0 W W C . Y W C W . 0 Y W W W 0 0 Y W T . 0 W .1 .T 00 0 1 0 M W.1 Y1.COM W1 W1W 00Y.CO W.1 1 Y.COM 0 W W W TW W 01 W T 1 . 0 W 100 0 1 1 1 M. 1 0 T . . 1 M . O 1 W O W OM W. WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW W PinY.CO O W and Power-Up Channel Selection Condition (PUC) W RegisterODescription (Subaddress) WW .TW WW .100Y.C M.TW 100 WW .100Y.C M.TW M . O W O The THS7347 operates only toW that illustratedWin FigureY9 O a single-byte transfer .Csimilar WWprotocol 0 .Cand W 2. When TW WW 0using W and theWfunctionality 0writing 0Y Y.C registers Tgiven in Table . 1 0 0 T . Figure 11. TheW internal .subaddress of each are toM. . 1 M . O 1 W M O W C O byte of data to the corresponding W of0all W send Y. the device, it is required If W .Cone Wcontrol .TW WW .100Y.Cinternal .Tsubaddress. 1 0seethree WW to M . .TW 00Y M O 1 W M . channels is desired, then the master must cycle through all the subaddresses (channels) one at a time; the O O W WW procedure WW .100Y.C M.TW W12) for theWproper 0Y.C of M Y.C(in Section TWto the THS7347. example, WritingW toW the THS7347 writing . 0 0 T . 1 0 . 1 OM WW 00Y.CO .TW W. .CO (or.T WW subaddress C W . Y W W W 0 Y During a read cycle, the THS7347 sends the data in its selected channel) in a single transfer to W 0 W M M example (in Section .10 the THS7347 W.112) for M.T See the Reading .10the O W .CO .TW O the master device requesting information. from W W C . Y W C W . 0 Y W W 0 Y W .T 00 .TW the proper procedureWon reading THS7347. W.1 Y.COM M .100from the W.1 Y.COM W O W W W C . .T W 00 Y W T If the PUCWpin is tied WW registers On power-up, the THS7347 Control M.pin. .100 (PUC) W.1 to Y.COM M.T by the Power-Up .100 areOdictated O W W W C . W PUC 0pin C disabled GND, the THS7347 powers in aY.fully state. IfW the the Yis tied to.TVW W DD, upon power-up WW up M.T .100 .TWbuffers disabled, M .1 0 pass-through O W MADC .100 state: THS7347 is configured in theW following monitor enabled, and ac-bias O W C . O W Y W write sequence Y.C W WWby the on, for all three input channels. a.Tvalid 0Y.C in WW .1It0remains TWstate dictated M .1is00 .the 100PUC unti M . W M O W .CO O W W C completed. . Y W C W . 0 Y W W W 0 0 Y W .T 0 W W.1 M.T .100 W.1 Y.COM W O W W W C . W W Table Register W YChannel .Selection W Bit.1Assignments .T 00 W2. THS7347 MT .100 OM W O W C . W C BIT ADDRESS W W 0Y) Y. W (b b .b10....b WW NAME M.T REGISTER 7 6 5 0 M.T .100 O W O W C Y. W 1 00Y.C WW0000 .0001 Channel W .TW 100 1 M . W O W Channel 0000 0010 WW WW 2 .100Y.C M.TW Channel 3W 0000 0011 .CO .TW W 00Yand Channel H Sync, W Channel V .Sync, 1 0000 0100 OM W Disable Controls WW .100Y.C W WW Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 19 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O Register Bit Descriptions W WW .100Y.C M.TW WW .100Y.C M.TW 0Y.C M WW .10Channel .TW O .CO WW 0in0Ythe W WW selection) bitOof the subaddress (channel described previous Wregister asW .C Y.C control .TWsection allows the W 0 Y W T . 1 0 0 WW .1Each T M . . 1 0 M . O W M to individually control the THS7347 This process allows functionality of O W functionality. C controlTthe .to W the user W user Y .CO independently Y.Cother channels. Wdescription . 1Wthrough Channel W 00Y 0the WW TW The bit . channel with regard to for Channel 1 0 0 WW each T M . . 1 0 M . O W W W3.1is shownOinM Table 3, while the H/V the described in Table 4. .CO and.T Y.C Wanalog channel 0are WW states .TW 0 WW sync.1channels 1 00Y WW .100Y.C M.TW M . M O W O W .C O W W 0YDecoder WW 3) Table 3..TTHS7347 Channel 1 through Channel Table. W 0Bit 0Y.C(Channel WW Register TW . 1 0 WW .100Y.C M.T . 1 M . O W M O Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011) W C . W .CO .TW WW .100Y .TW WW .100Y.C M.TW WW .1BIT M 00Y O FUNCTION BIT VALUE(S) RESULT W M O W O W W .C 0Y.C M.TW W Y.C WW .100Y TW filter on the W . 0 0 500-kHz STC circuit.10 WW (MSB) T . 0 M O 1 W O OMSync-Tip Clamp Filter WW W W.7 W Y.C C W . 10Y.C 5-MHz filter on the STC circuit 0 W W W 0 Y W T . W M.T .1 .T 10 00 M . O 1 W M . O W O 0000 MUX Input A W WW .100Y.C M.TW WW 0.100001Y.C MUX .TWA WW .100Y.C M.TW M Input O O WW 00Y.CO .TW W WW0 0 1000Y.CMUX C W . W W W Y W T . Input A W M .1 .T 00 .1 OM WW 00Y.CO .TW W.1 Y.COM W WW 0 0 1 1 0Y.C MUX InputT AW W W W W M .1 .T 00 M. A .10 MUXOInput 0W 100 WW 00Y.CO .TW W.1 Y.COM W C . W W Y W W W 0 1 0 1.100 MUX Input .T W W.1 Y.COM W M.T .100 OMB W O W W C . W C Y Input B .TW W .T W W 0 1 1 0 .100MUX WW .100Y. .100 M OM W M.T O W C . O W W C W Y 111 MUX .C W W 0Y. Input BM.TW W0 W M.T .100 6, 5,W 4, 3 .TW 10MUX 00YMUX Selection . O 1 W M . O W C 1 0 0 0 Input B . O W W .C WW .100Y WW 00YInput B M.TW WW .100Y.C M.TW M.T 1 0 0 1 W.1MUX O W O O W .C W Reserved; WW .100Y.C M.TW 1W 010 .TW 00Y do notMcare WW .100Y.C M.TW 1 . O W O WW 00Y.CO .TW W .C C 10W 1 1W Reserved; do not careTW . Y W W W 0 Y . W M .1 .T 00 .10 OM W 1100 Reserved; do not care WW 00Y.CO .TW W.1 Y.COM W C . W W Y W W W Reserved; .T 00 not care W M .1 .T 00 1101 OM W.1 do WW 00Y.CO .TW W.1 Y.COM W C . W W Y W W 1 1 1 0 W Reserved; .T W .100do not care W.1 Y.COM W M.T .100 OM W O W W C . 1 1 1 1 Reserved; do not care W C W W .T W W 00Y WW .100Y. .100 M.T .1both OM W M.T O 000 Disables monitor and buffer paths of the respective W C . O W W C W Y W Y. W Wchannel/register .TW WW .100Y.C M.TW M.T .100 100 M . O W O W C . O W 001 Channel W Mute00Y.C WW .100Y .TW W .TW WW .100Y.C M.TW M 1 M . O W O 010 Input Mode W = dc Y.C W Mode Y.CO Input WW .100Y.C M.TW W 0+ Shift M.TW WW 2, 1, 0 0 0 WW T . 1 0 1 1 Input Mode = dc . + .10 OM (LSB) WW 00Y.CO .T W .CO .TW WW= ac-bias C . Operation Y W W W 1 0 0 Input Mode 0 Y W W M .1 .T 00 .10 OM W WW 00Y.CO .T W.1 Y.COM 1 0W1 C . Input Mode = ac-STC Y with low bias W W W W W W M.T .100 with midObias W.1 Y.COM M.1T1 0 .100 Input Mode =W ac-STC O W W C . W C W . Y W W Input Mode 0 high bias W = ac-STC .T WW .100Y M .100 1.T 11 10with M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 .T 00 Bit 7 (MSB): ControlsW the sync-tip filter. AC-STC mode W.1 OM is selected. W.1 input OM Useful only when W W W.1 clamp C . C W . Y W W W Y W .T Bits 6, 5, 4, 3: Selects the W Input .MUX .100 100 channel. M.T OM W O W C . W C W Y 4, Bits Bits 2, 1, and 0 (LSB): W Configures the mode See Table 6 and 5, for more W W and operation. Y. channel.T W M.T .100 M .100 O information with respect to the enable/disable state. W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW 20 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . W .C W W .COSync Channel + Analog W .CO 4. .THS7347 WW Channels W 00Y State) 0Y(H/V WW Register TChannel . 1 0 WW .100YTable T M.TBit Decoder Table. . 1 M . O W Use in Conjunction With Register Bit Code (0000 0100) M O W C O W WW .100Y. .TW WW .100Y.C BIT .TW WW .100Y.C M.TW M M O W O W O W W Y.C WW .100RESULT W FUNCTION Y.C WW .100Y.CVALUE(S) TW . WW .100BIT T M.T . M O W M O W (MSB) C O W W Y. Reserved; Do not W do not W Wcare .TW Wcare .100Y.C X M.TReserved; 100 WW .1007 Y.C M.TW M . O W O W .C O W W all monitor regardless 2:0W of Register 1 Wchannels W 00Y of bits WWDisable.100Y.C0 M.Disables TW Register 1 WW .100Y.C Monitor T Pass-Through Path M.T . . through 3 O W M O W C . O W 6 Y W Y.C WW functions .TW W Mode withW Enables programmed .TW monitor channels 100dictatedObyMeach WW .100Y.C (Use in Table 3) .100 1 . .TConjunction M W M O W register code C . O W W C W . Y W .T WW .100Y0 .TWall buffer channels 100 of bitsO WW .100Y.C M.TW M . Disables regardless 2:0 of Register 1 M W OBuffer Path Disable Mode WW W W W .CO through Y.C Register 3 C W . 0 Y W T W . W 0 0 Y W T . 0 W 5 .100 (Use inMConjunction M .1 by each .T M buffer channel functions with Table 3) W.1 1 OEnables .CO programmed O WWdictated W C . Y W C W . 0 Y W W .TW W W register.T code 10 00 W M . .T 1 00Y M . O 1 W M . O Input A W O W WW .100Y.C M.TW WW .0100 0Y.CMUX M .TW WW .100Y.C M.TW O W B O Channel MUX Selection WW 0 1 Y.MUX W Vertical CO Input T W .CSync WW .100Y.C M.TW 3 W 0 Y W . 0 0 W4,W T . 0 Reserved; M do not care O W W1.10 OM W.1 .CO do.Tnot Wcare WW .100Y.C M.TW WW 1 1.100YReserved; WW .100Y.C M.TW OMA O WW 00Y.CO .TW W .CInput 00 MUX WW C W . Y W W W 0 Y W T . W 10 MUX Input 00 W.1 Y.COM W M.T OM 0W 1 . B O W W.1 Sync C . W C W . 2, 1 WHorizontal Channel MUX Selection Y W 0 W 1 0 .10Reserved; .Tcare W M.T .100 .TW doM not 00Y O 1 W M . O W C . O W .C WW .100Y .TW W1W1 .1Reserved; TW .care 00Y do not WW .100Y.C M.TW M M O W O W .C and.TV-Sync 0 W ChannelsWW .100Y.C M.TW .CO .TMode WW W 0YH-Sync Y W0W Disable H/V Sync Paths Disable 0 0 1 0 M . (LSB) W 1 1 H-Sync Channels OM WW 00Y.CO .TW W. .COand V-Sync WWEnable C W . Y W W W 0 Y W T . 0 W M .1 .T 00 Mcare. W.1 Y.COM W O Bit (MSB) 7: Reserved; not WW 00Y.CO .TW W.1 Y.do W C W W W W .T 00 W Monitor OM Bit 6: Master Disable. regardless of what isWprogrammed W.1 Y.Cinto M.T Disables all monitor .100 Path O OM W.1 channels W C W . W C W . 0 Y W W each register W .T 0Yto 3). M.TW W channel M.T .10 100 0(1 M . O 1 W . O W C . W PathYDisable. .C Bit 5: Master Buffer all buffer regardless .CO Disables WW .1into 00Yeach M.TW WWchannels .TofWwhat is programmed 00Y WW(1 to.13). .TW 1 00 M . O register channel W M W W W Y.C WW 00Y.CO .TW .COchannel 0 W W 0 Y W 1 0 Bits 4, 3: Selects MUX for the Vertical Sync. WWthe Input T M.T . . 1 0 M . O 1 W M . O W C . WInput MUX .C .CO Bits 2, 1: Selects the channel for the Horizontal WW .100Y .TW WW Sync. .TW 00Y WW M .TW 1 00Y M . O 1 W M . O W O H-Sync and V-Sync W Bit 0 (LSB): Enables or disables the Channels. W .C WW .100Y.C M.TW W .TW 00Y WW .100Y.C M.TW 1 M . O WW 00Y.CO .T W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 21 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW READ EXAMPLES W WW .100Y.C M.TW 0Y.C AND WW .10WRITE T . O W OM W CO to and WW way illustrate theWproper to theW THS7347. Wread from W .Cexamples 0Y.C M.TW Y.write W 0 0 Y T . 1 0 0 WW .1These T . . 0 M .1 OM WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W WRITING TO THE THS7347 0 W M .1 W.1 Y.COM W M.T .10 O W O W W C . W C W . Y W .T followed by the initiates WW An.10I20CYmaster .100condition .TW a writeWoperation M.T by generatingWaWstart .10to0 the THS7347 OM(S) 2OM O W C . W THS7347 I C address, in MSB-first order, followed by a '0' to indicate a write cycle. After an C Y W Y. W .TWreceiving W THS7347,Wthe 0it 0wants 0presents Y.C from.Tthe TW . 1 0 0 WW acknowledge M . 1 0 master the subaddress (channel) to write, consisting of M . O 1 C OM MSB first. The THS7347 WW 00ofY.the W. byte Y W Finally, the .CO .Tthe WW acknowledges C W . Y W T W one of data, byte after completion transfer. . W 0 W 0 W M 00 W.1 acknowledges M.Tdata it wants to write OM master to.1the register (channel) and the THS7347 W .CO .Tthe Othe W W.1 presents C W byte. The . Y W C W . 0 Y W W 2 W the writeWoperation 0 that theMTHS7347 0 generating Ythen terminates T a stop condition (P). .Note . 1 0 0 W I C master T by does . 1 0 M . O 1 W M transfers. To writeWtoWall three .channels . O C . O W W C W Y not support multi-byte (or registers), this procedure must be repeated for C W . Y W W .T 8 for eachWchannel). Weach M.T .100 .TW 100steps 1Othrough 00Y one series M . O 1 register, at a time (that is, repeat W M . W WW .100Y.C M.TW WW 00Y.CO .TW WW .100Y.C M.TW W Step 1 0 1 M . O WW 00Y.CO .TW WW 00Y.CO .TW C . W WW(Master) W I2W C Start S Y W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W 0 W T Step 7 60 5 M. 4 3 0 W2 .T W.21 Y.C1OM W .100 W.11 Y.CO OM W W W C I2C General Address (Master) 0 0 1 1 X X W . 0 W T W W .T W M. 0 .10 .TW 100 00Y M . O 1 W M . O W C W .C being.T Y. 2 W I2C-A0 Wto either VW .CO defined WWX logic .TW WhereWeach pins tied Wand DD or GND. 100 00Y M . .TW by I C-A1 1 00Ystate isM M . O 1 W . O W Step 3 WW .100Y.C M.TW WW 00Y.CO .TW 9 WW .100Y.C M.TW W 1 . I2C AcknowledgeW (Slave) A OM WW 00Y.CO .TW WW 00Y.CO .TW C . W W W Y W W .T 00 M .1 W.1 1 Y.COM W W.1 Y.COM W Step 4 7 6 5CO 4 W 3 2W 0 . W Y W W .TW 00 0 W T . 1 0 0 W T M . . 1 0 2 M . O 1 W I C Write Channel Address 0 0W 0 O 0 0 AddrW Addr .CAddr .TW W. (Master)OM W 00Y WW .100Y.C M.TW 1 WW .100Y.C M.TW M . O W Where Addr is determined by.Cthe 2. O values shown in Table WW 00Y.CO .TW W C . W W Y W W W W .T 00 W M .1 .T 00Y Step 5 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM 9 W W W W W .T I2C AcknowledgeW (Slave) .100 W.1 Y.COM W MA.T .100 OM W O W W C . W C Y W .T W 00 0 W TW WW .100Y. Step 6 6 4OM. 3 2 1 W.1 .1500 OM M.T 7 W C . O W W C W 0Y Y. W WW Data TW Data WData .10Data I2C Write Data (Master) Data WW .100Y.C M.TData M.T 100 DataOM.Data . O W W C . W W .C W .CO shown WW .100Y 0Yvalues WW by.10the M.T .TW in Table 3.W W.100Y OM.TW Where Data is determined O W M O W WW .100Y.C M.TW WW .100Y.C M.TW Step 7 WW .100Y.C 9 M.TW WW 00Y.CO .T W WW 00Y.CO .TW C I2C Acknowledge (Slave) AO . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.0COM W W W W Step 8 W .T 00 W W.1 Y.COM .100 P OM.T W.1 Y.COM W W I2C Stop (Master) W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW 22 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 THS7347 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW 0 W T . 1 0 M . M .1 WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W W W M .1 .T 00 W.1 Y.COM W .CO OM .................................................................................................................................................. WW SLOS531A W.1 www.ti.com – MAY 2007W Y W C . 0 W W .T – REVISED SEPTEMBER 2008 W W .T 10 00 W M . .T 1 00Y M . O 1 W M . O W O W THE THS7347 WW .100Y.C M.TW WW .100Y.C M.TW 0Y.C MFROM WW .10READING .TW O O W phases. WW phase. W read consistsW ofW two address W is theW .CO operation 0Y.CIn this Y.CThe first.Tphase TW an I2C master .phase, W 0 0 Y 1 0 0 WW .1The T M . . 1 0 M . O W initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C M O W .C O W W C . Y W C W . 0 Y W W .TW W address, by receiving an M acknowledge from the .T a write cycle. After W .10 .TW order, followed 10a0'0' to indicate 00Y in MSB-first M . O 1 W M . O W C . O W W THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is C W . Y W C . W .T 00 condition W .TW by generating 1stop 00Ycycle immediately WW acknowledged M . .TW 1 00Y (A), the master terminates the a (P). M . O 1 W M . O W W .CO .TW 0Y.C M Y.C an I.2TCW WWa read TW 0operation 0phase, WW In this 1 0 WW The.1second . is the data phase. master initiates to. the THS7347 by 1 00Y phase M . O W M O W C . O W .C I2C address, Y followed by the THS7347 followed by.T aW '1' to indicate WW order, Y.aCstart condition WW .TW 2 in MSB-first 100one 00YTHS7347, WWgenerating M . .TanWacknowledge 1 M . O W M .100cycle. After a W read from the the I C master receives byte of data O W C . O W C W from the . Ythe master W transferred W .C the data 0 Y W T . W 0 0 Y W T . THS7347. After byte has been from the THS7347 to the master, generates a 1 0 0 WW T M . .1 O1 through W M.followed by a stop.W .10 OMfunction, to read all W Wwith C . O W C not-acknowledge (A) As the Write channels, steps W 11 must . Y C W . W W Wbe M.T .100 .TW desired.W W.100Y OM.T 00Yfor eachMchannel repeated O 1 W . WW .100Y.C M.TW WW 00Y.CO .TW WW .100Y.C M.TW W THS7347.1Read Phase 1: M O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W 1 Step 0 M .1 .T .100 W.1 Y.COM W OM WW 00Y.CO .TW W W W I2C Start (Master) 0Y.C S WW W 0 T . 0 W .T W.1 Y.COM W .10 W.1 Y.COM W OM W W W C . W W StepW 2 5 .T 4 3 2 .100 1 W7 M.T0 .TW 1060 00Y M . O 1 W M . O W C 2 W (Master)O I C General Address 0 W 1 Y.C 0 1 WW X YX. .0TW W .TW1 100 00 WW .100Y.C M.TW M . 1 M . O W O O WGND. 00Y.C 2 W WIW Wor Where W each X logic0state and C-A00pins to either VDD WW Wby I2C-A1W 0Y.CbeingMtied Y.C is defined TW . T M.T .1 . 1 0 . O 1 W M . O W C . O W Step 3 9 WW .100Y .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O I2C Acknowledge (Slave) A W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O Step 4 7 2 WW 1 O W W Y.C 0 W6W 00Y5.CO 4.TW 3 C . 0 W W W 0 Y W 0 W Address M.T .1 .T 0(Master) M I2C Read Channel 0 0 W.1 0 0 0 Addr Addr Addr O 1 W M . O C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O Where Addr is determined by the values shown in TableW 2.W WW .100Y.C M.TW WW 00Y.CO .TW 0Y.C M.TW W 0 W 1 . O Step 5 W O W OM 9 W.1 WW .100Y.C M.TW WW .100Y.C M.TW I2C Acknowledge (Slave) WW .100Y.C MA.TW WW 00Y.CO .TW W WW 00Y.CO .TW CO . W W W Y W 0 W T Step 6 0 . .1 W.1 Y.COM W M .10 OM W O W W C . 2 W C W Y W I C Start (Master) P .T W 00 W WW .100Y. M.T .100 W.1 Y.COM W M.T O W O W W C . .C W WW .100Y .TW THS7347 Read Phase 2: WW M.T .100 .TW 00Y M O 1 W M . O W C . O W WW .100Y .T Step 7 WW .100Y.C M.TW WW .100Y.C0 M.TW OM W O W C . O W W C I2C Start (Master) S . Y W W WW .100Y WW .100Y.C M.TW M.T .100 M.T O W O W C . O W W Step 8 1 W 0 .100Y W5 W .1400Y.C3 M.T2W WW .100Y.C 7 M.TW 6 M O W I2C General Address (Master) 0 1 0 1 1 X X O W1W 00Y.CO W C . W C W . Y W W W 0 Y W W 10 00 M.T W.1 M.TI2C-A0 pins beingW O W.to Oand W W.1by I2Y C Where each X Logic state is defined C-A1 tied either V or GND. . C DD W . Y W W W W .T W .100 M.T .1090 OM W Step 9 O W C . W C W Y W W WW .1A00Y. M.T .100 I2C Acknowledge (Slave) M.T O W O W C WW .100Y. WW .1007Y.C M.6TW Step 10 5 4 3 2 1 0 W WW .CO Data W Data WData WW .1Data T I2C Read Data (Slave) Data Data Data Data . 00Y M WW 00Y.CO .TW W Where Data is determined by the logic values OMin the Channel Register. W.1 contained C . W Y W 9 .100 Step 11 W I2C Not-Acknowledge (Master) A WW Step 12 0 I2C Stop (Master) P Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 23 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 THS7347 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T 00 0 W WW .100Y .TW M.T .102008 W.1 Y.COM W M– MAY O W O W W SLOS531A 2007 – REVISED SEPTEMBER .................................................................................................................................................. www.ti.com C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W .C O W W WW .100Y.C Revision .TW HistoryW W.100Y OM.TW WW .100Y.C M.TW M W WW 00Y.CO .TW .CO .TW WW .100Y.C M.TW Y W 0 WW .1Changes 0 M .1 from toW Revision A ........................................................................................................... Page OM Original (May 2007)W WW 00Y.CO .TW W .CO .TW C . Y W W W 0 Y W 1 0 0 W M . .T 1 Electrical 0 M Digital to .3.3-V table ..................................................................... 3 OM Characteristics section WW 00Y.CO .TW W•.1 Added .CO Characteristics WW C W . Y W W W 0 Y W T . 1 0 0 W T • 1Added Digital Characteristics section to 5-V Electrical Characteristics table ........................................................................ 6 M . . 1 0 W OM W. .CO .TW OM W W. C . Y W C W . 0 Y W W W 0 Y W .T W .100 W.1 Y.COM W M.T .100 OM W O W W C . W C W Y W .T W 00 W WW .100Y. M.T .100 W.1 Y.COM W M.T O W O W W C . W WW .100Y .TW WW .100Y.C M.TW M.T .100 M O W O W C . O W W WW .100Y WW .100Y.C M.TW WW .100Y.C M.TW M.T O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . 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W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW 24 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): THS7347 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 .1 OMOPTION ADDENDUM PACKAGE W M .1 W.1 Y.COM W C . O W W W Y W C . W W .T WW .100Y M.T .100 .TW 100 M . O W M O W O W 25-Sep-2007 WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C www.ti.com .TW O W M O W C . O W W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M.T .100 O W O W C O W WW .100Y. .TW WW .100Y.C M.TW 0Y.C M.TWINFORMATION WW .10PACKAGING M O W O W .C W .CO Device WW .TW MSL Peak Temp (3) (1) W 0(2)0YLead/BallMFinish 0Y.CPackage WW TWPins Package . 1 0 WW .100YOrderable T . Status Package Eco W Plan . 1 M . O M O W C W W Qty .CDrawing Y. .CO .TW .TW WW Type 10&0 CU NIPDAU 00Y PHPM.TW48 250 W WW .100YTHS7347IPHP M . 1 . O W ACTIVE HTQFP Green (RoHS Level-3-260C-168 HR M O W .C O W W WnoW T Sb/Br) 100Y . WW .100Y.C M.TW WW .100Y.C M.TW M . O W O W C . O W THS7347IPHPG4 ACTIVE WHTQFP 48 250 Green (RoHS & CU HR C .PHP 0YNIPDAUM.Level-3-260C-168 WW TW W .TW 00Y WW .100Y.C M.TW no Sb/Br)W.10 1 M . O O W .C W W .C .CO .TW ACTIVE WW HTQFP 00Y PHP 48 NIPDAU Level-3-260C-168 HR .TW 00Y TW1000 GreenW(RoHS & .1CU . WW .1THS7347IPHPR M 1 00Y M . O W M no Sb/Br) O W C . O W Y W .C Y.C 48.TW WW .TW 100NIPDAU OM WW THS7347IPHPRG4 1000 Green (RoHS & .CU Level-3-260C-168 HR .TW ACTIVE WHTQFPW.100PHP 00Y M 1 W M . O O W no Sb/Br) WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW (1) Ovalues are defined as follows: WW 00Y.CO .TW TheW marketing status WW 00Y.CO .TW C . W W W Y W W M .1 .T ACTIVE: Product for new designs. .1 00 device recommended OM OM that the device will be discontinued, WW 00Y.CO .TW W.TI1 has announced LIFEBUY: a lifetime-buyW period is in effect. .C WW 00and C . Y W W W Y W T . W Not recommended Musing this part in .T designs. Device is in production NRND: for new 00 W.1not recommend OMexisting customers, but TIWdoes W.1 toYsupport .CO .TW W.1 Y.COM W C . a new W design. Y W W 0 W .T 10 00 W T but is not inWproduction..1Samples M PREVIEW: Device mayM 00has been announced M.the .1has O or may not be available. WW. W .CO .TW O W C . OBSOLETE: TI discontinued production of the device. Y W C W . 0 Y W W W 0 0 Y W T . 0 W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W (2) W W 0Pb-Free (RoHS W (RoHS), EcoW Plan - The planned eco-friendly Pb-Free .T Exempt), or Green (RoHS 1& no Sb/Br)O- please M check .T classification: .10and Mthe .100 OMproduct content details. WW. http://www.ti.com/productcontent for latest availability information additional W C . O W C . Y W C . W W .TW W TBD: The conversion plan has not been defined. .TW 100 00Y 0Y WPb-Free/Green TW M . . 1 0 M . O 1 W M . O Pb-Free (RoHS):W TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible withW current RoHS .C requirements O .C in homogeneous WW0.1%0by W the .TW W that lead notWexceed 00Y to beM 0Yweight Y.C TW for all 6 substances, the requirement materials. Where.1 designed soldered . 0 WW including T . 1 0 M . O 1 W O W lead-free at high temperatures, products specified processes. .C OM are suitable for use inW W W.TI Pb-Free W W a RoHS exemption 00Y the M 0Y1).Clead-based Y.C W TW Pb-Free (RoHS This component has for either flip-chip solder W bumps used between die.T and . 1 0 0 WWExempt): T . . 1 0 M . O 1 W M . O W C package, or 2) lead-based die adhesive is otherwiseW Pb-Free (RoHS W O used between the dieWand leadframe. .CThe component Y. W considered WWabove. W compatible) asW defined .TW 100 00Y 0Y.C M.TW M.T . 1 0 M . O 1 W . O W C Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame W . O W W C C by weight W Win homogeneous 00Y 0Y. Y.0.1% WW TW . retardants (Br orW SbW do not exceed material) 1 0 0 T M.T . . 1 0 M . O 1 W M . O W C W W .C .CO .TW WW .100Y. WW to.1the .TWstandard classifications, 00Y (3) WW-- The.1Moisture M.T 00Y Sensitivity M MSL, Peak Temp. Level rating accordingW JEDECOindustry and peakC solder O W M O W W temperature. WW .100Y. WW .100Y.C M.TW WW .100Y.C M.TW M.T O W O W C . W W W .C Y W .COinformation .TW and beliefWas of the 100 that it isOM.T 00Y TI'sM Important Information and Disclaimer:The represents knowledge date WW . .TW provided onWthis page 1 00Y . 1 W M . O Wparties,Yand provided. TI bases its knowledge belief provided byW third makes noW representation orW warranty as Y to.C the W and Y .COon information 00to take M.TW 0 .Cthird parties. Winformation T TI has takenW . 1 0 0 WW Efforts accuracy of such information. are underway.T toW better integrate from and continues . 1 0 M . 1 W M information but may W have conducted CO Oaccurate W analysis reasonable steps to provide representative and testing or chemical W. .CO destructive Y.on Wnot C W . 0 Y W W W 0 0 Y W T . 0 proprietary,Mand thus CAS numbers andW W T incoming materials and chemicals. TI1and certain information to other .1 limited OM.T 00 TI suppliers .1be M.consider .release. O W O W W information may not be available for C . Y.C W WW .100Y .TW 100 WW .100Y.C M.TW M.T . M O W O W C . O W W Y C Y.C W W out of 0such In no event shall TI's liability W arising exceed atW issue in this document sold1by W the total purchase WW price .T 0Y.information M . 00TI .T 10of0 the TI part(s) M . 1 W M . to Customer on an annual basis. O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Addendum-Page 1 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 OM PACKAGE W.1 MATERIALS M .1 W.1 Y.COM W C . O W W W INFORMATION Y W C . 0 W T W . W 0 0 Y W T . 0 W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W www.ti.com 11-Mar-2008 W W W W W M .1 M.T .100 O W M.T .100 O W C . O W W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M.T .100 O W O W C O W WW .100Y. .TW W INFORMATION WW .100Y.C M.TW 0Y.C AND WW .10TAPE M .TREEL O W M O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W W W W W .T 00 W W.1 Y.COM W M.T .100 W.1 Y.COM W O W W W C . W .T W 00 W WW .100Y M.T .100 W.1 Y.COM W M.T O W O W W C . W W WW .100Y WW .100Y.C M.TW M.T .100 M.T O W O W C . O W W W Y W WW .100Y.C M.TW WW .100Y.C M.TW M.T .100 O W O W C O W WW .100Y. .TW WW .100Y.C M.TW WW .100Y.C M.TW M O W O W O W WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW O WW 00Y.CO .TW W WW 00Y.CO .TW C . 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W W W Y W W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .T W.1 Y.COM W W W W W .T 00 W W.1 Y.COM M.T .100 W.1 Y.COM W O W W W C . W W .T WW .100Y M .100 .TW 100 M . W M O W .CO O W W C . Y W C W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 W.1 Y.COM W WW W.1 Y.COM W W W W W .T W .100 M.T .100 OM W O W C . W C W Y W W WW .100Y. M.T .100 M.T O W O W C WW .100Y. WW .100Y.C M.TW W O W WW WW .100Y.C M.TW O W WW .100Y.C M.TW O W WW .100Y.C W WW Pack Materials-Page 1 . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 OM PACKAGE W.1 MATERIALS M .1 W.1 Y.COM W C . O W W W INFORMATION Y W C . 0 W T W . W 0 0 Y W T . 0 W M .1 .T 00 W.1 Y.COM W WW 00Y.CO .TW W.1 Y.COM W www.ti.com 11-Mar-2008 W W W W W M .1 M.T .100 O W M.T .100 O W C . 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WW .10TI0will M.T solutions: W.1 Y.COM W M.Ton other Texas Instruments O W Following are URLs where you W can obtain information products and application O W C . W 0Y WW .TW WW .100Y.C M.TW M.T .100 Products Applications .10 M O W O W C . O W Amplifiers Audio WW .C WW .100Y .T 0Y.C www.ti.com/audio .TW WWamplifier.ti.com .TW 00Y M Data Converters dataconverter.ti.com Automotive W.10 www.ti.com/automotive OM 1 W M . O C . O W W C . Y DSP dsp.ti.com W W W Broadband 0Y www.ti.com/broadband Y.C WW WW M.T .100 M.T Clocks and Timers www.ti.com/clocks Digital Control W.10 www.ti.com/digitalcontrol O W M.T .100 O C . O W W .C Y W Interface Medical www.ti.com/medical .C W W .TW Winterface.ti.com M .100 .TW Military W W.100Ywww.ti.com/military 00Y M Logic logic.ti.com 1 W M . O .CO O W W C . Y W C Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork W . 0 Y W W W 0 0 Y W .T 0 W .1 .T 00 Microcontrollers microcontroller.ti.com OM W.1 www.ti.com/security WW W.1 Y.COM WSecurity C . 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