EENG341 ELECTRONICS I 1
INTRODUCTION
SIGNAL SOURCE
A. THEVENIN FORM
B. NORTON FORM
SINUSOIDAL SIGNAL
V(t)
Va
t
-Va
V(t)=Vasinwt
v
Peak value=Va
v
Root-Mean-Square(RMS) value=
Va
2
v
EENG341 ELECTRONICS I 2
PEAK-TO-PEAK VALUE = 2Va
V
EXPONENTIAL SIGNAL
V1(t) = 5ejwt
RMS of V (t) = 5
1
ELEMENTS
i.
RESISTOR
SYMBOL
(RESISTANCE)
ii.
UNIT
Ohm(Ω)
CAPACITOR
Farad(F)
(CAPACITANCE)
L
iii.
Henry(H)
INDUCTOR
(INDUCTANCE)
DERIVATIVES
i.
CONDUCTANCE
1/R
Siemens (S)
mho
EENG341 ELECTRONICS I 3
MULTIPLE ELEMENTS
i.
IMPEDANCE
ii.
ADMITTANCE
DEVICES
EENG341 ELECTRONICS I 4
CIRCUITS
A circuit is defined as one which contains a source and at least one element (or a combination
of elements) or a device (or a multiplicity of devices) which perform a specific function.
Examples:
SUBSYSTEMS
EENG341 ELECTRONICS I 5
A subsytem is one which contains more than one circuit to perform a specific function.
Examples: Transmitter, Receiver
SYSTEMS
A system is one which contains more than one subsystem to perform a specific function.
Examples: Satellite T.V., Radio
Exercise: A list of items which contains electronic is given below. Identify whether they are
circuits, subsystems or systems.
Item
Classification
Amplifier
Circuit
Oscillator
Circuit
Vending Machine
Door bell
Calculator
Alarm Clock
Camcorder
PC
EENET (EMU)
EENG341 ELECTRONICS I 6
WHAT YOU CAN DO IS TO CHANGE:
A. AMPLITUDE (MAGNITUDE)
Modulation, Gain (Amplification), Attenuation,
Limiting, Clipping, Filtering
B. PHASE (ANGLE)
Modulation, Delaying, Leading, Lagging, Adding,
Subtracting
C. DIRECTION (PATH)
Feedback, Selecting, Dividing, Combining
OF A SIGNAL.
CAN YOU THINK OF ANYTHING ELSE?
EENG341 ELECTRONICS I 7
DEPENDENT SOURCES (CONTROLLED SOURCES)
A dependent source is a secondary circuit whose value depends on the source (i or v) and a
parameter which is intrinsic to the circuit.
There are four types of dependent controlled sources:
(i)
Voltage-Controlled Current Source (VCCS)
Intrinsic parameter
Note: The standard
diamond shape is used to
represent controlled sources.
+
V1
gmV1
-
(ii)
Current-Controlled Current Source
Intrinsic parameter
i1
βi1
(CCCS)
EENG341 ELECTRONICS I 8
1.
DIODES
The ideal diode may be considered as the most fundamental nonlinear devices.
Examples:
+10v
-10v
1 kΩ
1 kΩ
+
+
V1
-
V2
-
i1
i2
I1=?
V1=?
ON
I1=10 Ma, V1=0
+10v
I2=?
1 kΩ
V3
+
i3
V2=?
I3=?
V3=?
OFF
OFF
I2=0
I3=0
EENG341 ELECTRONICS I 9
The i-v characteristic of the ideal diode is highly nonlinear; it consists of two straight-line
segments at 90o to one another. A nonlinear curve that consists of straight-line segments is
said to be piecewise-linear.
Terminal Characteristics of Junction Diodes
i
Compressed
scale
1
i
Forward
-VZK
0
0
V
V
2
3
Breakdown
0.5
Reverse
knee=k
Silicon junction diode
The i-V curve consists of
1) The forward-biased region, determined by V>0.
2) The reverse-biased region, determined by V>0.
3) The breakdown region, determined by V>-VZK
Expanded
scale
EENG341 ELECTRONICS I 10
Forward Bias
In the forward bias V is positive and i is given by
i = I s (e
V
nVT
− 1)
Where Is is the saturation current also known as the scale current as Is is direcly
proportional to the cross-sectional area of the diode. For “small-signal” diodes (low power
applications) Is is of the order of 10-15 A and its value doubles for every 5 oC rise in
temperature. VT is called the thermal voltage given by
VT =
kT
q
Where k=Boltzmann’s constant = 1.38x10-23 Joules/Kelvin.
T=the absolute temperature in Kelvin = 273+temperature in oC.
q= the magnitude of electronic charge = 1.602x10-19 Coulomb.
VT=25 mV at room temperature (20 oC)
1 for IC diode
n=
2 for discrete diode
For
i>>Is, we have
i = Ise
V
nVT
− Is
EENG341 ELECTRONICS I 11
i ≅ Ise
V
nVT
 Exercise : Show That


i 

V=nVT ln( )
I s 

For a diode voltage V1 we can evaluate the current I1:
I1 = I s e
V1
nVT
Similarly, for V2 :
I2 = I se
V2
nVT
Combining the last two equations we obtain
(V2 −V1 )
I2
nVT
=e
I1
or
V2 − V1 = nVT ln
I2
I1
or
V2 -V1=2.3nVT log
I2
I1
EENG341 ELECTRONICS I 12
The last equation states that for a decade (factor of 10) change in current the diode voltage
drop changes by 2.3nVT, approximately 60 mV. For n=1 and 120 mV. For n=2.
A conducting diode has 0.7 V voltage drop across it; for Vd less than 0.5 V the current is
negligibly small.
Reverse Bias
The reverse-biased region of operation is entered when the diode voltage Vd is made negative.
From
i = Ise
Vr
nVT
−1
e
-
10 3
1x25
= e −40
Exponential term becomes negligible for Vd negative Therefore,
i ≅ −Is
A good part of the reverse current is due to leakage effects. The reverse current doubles for
every 5 oC rise in temperature.
Breakdown
EENG341 ELECTRONICS I 13
The breakdown region is entered when the magnitude of the reverse voltage exceeds a
threshold value called the breakdown voltage.
Diode breakdown is normally not destructive provided that the power dissipated in the diode
is limited by external circuitry to a safe level. This safe value is normally specific on the
device data sheets.
Example:
A silicon diode said to be a 1 mA. Device displays a forward voltage of 0.7 V at a current of 1
mA. Evaluate the junction scaling constants would apply for a 1-A diode of the same
manufacture that conducts 1A at 0.7 V?
Solution:
i = Ise
V
nVT
-
==>
I s =ie
V
nVT
For the 1-mA. Diode :
n =1
n=2
I s = 10−3 e
−700
25
−700
−3 50
I s = 10 e
≅ 10 −15 A
≅ 10−9 A
For the 1-A. Diode :
n =1
I s ≅ 10−15 x103 = 10−12 A
n=2
I s ≅ 10 −9 x103 = 10−6 A
EENG341 ELECTRONICS I 14
Example: A diode has Is=10-17 and n=1. Calculate the diode voltage if the diode current is (a)
100 µA
(b) 10 µA. Calculate the diode current if the diode voltage is (c) 0 V
and
(d) -0.06 V
and
(e) -4 V.
Solution:
V = nVT ln(1 +
i
)
Is
VT = 25mV
(a )
(b)
i = 100 x10−6 A
100 x10 −6
V = 1x0.025ln(1 +
) = 0.748 V
−17
10
i = 10 x10−6 A
10 x10−6
V = 1x0.025ln(1 +
) = 0.691 V
−17
10
Now,
(c )
i = I s (e
V
nVT
− 1)
V =0 V
i = 10−17 (e0 − 1) = 0 A
(d )
V = −0.06 V
i = 10
(e)
−17
(e
−
0.06
0.025
− 1) = −0.909 x10 −17 A
V = −4 V
i = 10−17 (e
−
4
0.025
− 1) = −1.00 x10 −17 A
EENG341 ELECTRONICS I 15
Analysis of Diode Circuits
Assuming VDD>0.5 V, we have
I D = I s (e
VD
nV T
==> I D = I s e
− 1) = I s e
VD
nVT
VD
nVT

→ (1)
Apply KVL to the circuit,
VDD − VD
V V
= − D + DD
R
R
R
V
V
==> I D = − D + DD 
→ (2)
R
R
ID =
We have 2 equations and 2 unknowns which can be obtained by:
A. Assumption + Circuit analysis
B. Graphical analysis
C. Iterative analysis
D. Computer circuit analysis
A. Assumption + Circuit analysis
Will be studied with same examples
since I D >>I s
EENG341 ELECTRONICS I 16
B.
Graphical analysis
Use i-V plane.
y = mx + c
1
V
I D = − VD + DD
R
R
EENG341 ELECTRONICS I 17
C.
Iterative analysis
Start with an assumption: assume a value for VD. Using this VD solve for ID. Use this
value of ID to find the new diode voltage using
V2 − V1 = 2.3nVT log
I2
I1
Using this new VD solve for ID and repeat the calculations until the last calculated values
differ negligibly (or by a specific amount) from the previous values.
D.
Computer Circuit-Analysis
EENG341 ELECTRONICS I 18
Simplified Diode Models
1. Piecewise-linear model
2. Constant –voltage-drop (CVD) model
3. Ideal diode model
4. Small-signal model
EENG341 ELECTRONICS I 19
1.
Piecewise-linear model
A piecewise-linear model is substituted for the exponential i-V model.
Slope=
ID
1
ς
(mA)
Typically, rD=20Ω
VD0=0.65 V
VD (V)
We have ,
VD ≤ VDD
1) iD =0,
2) iD =
(VD -VDD )
rD
,
VD ≥ VDD
≡
≡
EENG341 ELECTRONICS I 20
2.
The Constant-Voltage-Drop Model
EENG341 ELECTRONICS I 21
3.
The Ideal Diode Model
VD=0 V.
4.
The Small-Signal Model
iD(t)
+
Vd(t)
VD(t)
VD(T)
+
VD
-
Tangent at Q
ID
(mA)
Slope=
Bias Point
Q
Id(t)
ID
0
t
0.6
0.65
VD
0.70 0.75
VD0
Vd(t)
t
VD(V)
1
rd
EENG341 ELECTRONICS I 22
The diode is biased to operate at a point on the forward i-V characteristic and a small
ac signal is superimposed on the dc quantities. The dc voltage is VD and the ac signal is the
triangular waveform Vd(t). The diode is modeled by a resistance rd equal to the inverse of the
slope of the tangent to the i-V curve at the bias point.
In the absence of Vd(t) the diode voltage is equal to VD and the diode current is ID
given by
VD
I D = Ise
nVT
When the signal Vd(t) is applied, the total instantaneous diode voltage VD(t) will be
given by
VD (t ) = VD + Vd (t )
and iD (t ) will be
VD ( t )
iD (t ) = I s e
nVT
or
iD (t ) = I s e
(VD +Vd )
VD
==>
iD (t ) = I s e
nVT
Vd
nVT
e
Vd
iD (t ) = I D e
nVT
nVT
EENG341 ELECTRONICS I 23
Vd
<< 1
nVT
If
iD (t ) ≅ I D (1 +
Vd
)
nVT
This is the small-signal approximation. It is valid for signals whose amplitudes are
smaller than about 10 mV (VT=25 mV).
Hence
iD (t ) = I D +
ID
Vd
nVT
iD (t ) = I D + id
where
id =
ID
Vd
nVT
The diode small-signal resistance, rd , is given by
rd =
nVT
ID
rd =
1
Γ∂id1
Q. Show that
EENG341 ELECTRONICS I 24
The equation of the tangent at Q is
iD =
1
(VD − VD 0 )
rD
This equation is a model for the diode operation for small variations around the bias. The
equivalent circuit is:
iD
Ideal
VD0
rd
Apply KVL:
VD = VD 0 + iD rd
=VD0 +(I D +id )rd
=(VD0 +I D rd )+id rd
=VD +id rd
The signal voltage across the diode is given by
EENG341 ELECTRONICS I 25
Vs=Signal voltage
VDD=dc source
ID=dc current
VD=diyote dc voltage
id=?
signal current across the diode
Vd=?
signal voltage across the diode
Apply KVL to the equivalent circuit:
VDD +Vs =iD R+VD0 +iD rd
=(I D +id )R+VD0 +(I D +id )rd
=I D R+(VD0 +I D rd )+id (R+rd )
=I D R+VD +id (R+rd )
EENG341 ELECTRONICS I 26
VDD + Vs = I D R + VD + id ( R + rd )
Seperating dc & signal quantities on both sides for dc:
VDD = I D R + VD
The diode signal voltage is given by
EENG341 ELECTRONICS I 27
Small- signal model application:
Power supply ripple
Soln:
Assume
VD ≅ 0.7 V
10-0.7
= 0.93 mA
10 4
Since ID is close to 1 mA, the assumption is valid.
nV
2 x 25
rd = T =
= 53.8 Ω
0.93
ID
Then
ID=
Hence
Vd ( p - p ) = 2
rd
0.0538
=2
R + rd
10 + 0.0538
= 10.7 mV
The signal amplitude is 5.35 mV.
Example:
Find the Q-point fort he diode given in the following circuit using
(a) the ideal diode model and
EENG341 ELECTRONICS I 28
(b) the constant voltage drop model with Von=0.6 V
(c) Discuss the results. Which answer do you feel is most correct?
+4V
2kΩ
3kΩ
I
-
V
+
2kΩ
2kΩ
Solution: Using Thevenin equivalent circuits:
RTH = 2 // 2 =
+
2kΩ
VTH =
4V
VTH
4
= 1 kΩ
2+2
2
4=2V
2+2
2kΩ
and
+
4V
2kΩ
VTH
Therefore,
3x2 6
= = 1.2 k Ω
3+ 2 5
2
8
4 = =1.6 V
=
2+3
5
RTH =
3kΩ
VTH
EENG341 ELECTRONICS I 29
Combining the sources:
(a) Ideal diode model: The 0.4 V source appears to be forward biasing the diode so we will
assume it is “ON”. Substituting the ideal diode model for the forward region yields.
I=
0.4
= 0.182 mA
3
2.2.x10
This current is greater than zero, which is consistent with the diode being “ON”.Thus the Qpoint is
(0 V, +0.182 mA)
EENG341 ELECTRONICS I 30
(b)
CVD model:
The 0.4 V source appears to be forward biasing the diode so we will assume it is “ON”.
Substituting the CVD model with Von=0.6 V yields
I=
0.4 − 0.6
= −90.9 µ A
2.2.x103
This current is negative which is not consistent with the assumption that the diode is “ON”.
Thus the diode must be “OFF”. The resulting Q-point is
(0.4 V ,0 mA)
(c)
The second estimate is more realistic. 0.4 V is not sufficient to forward bias the diode
into significant conduction. For example, let us assume that Is=10-15 A and assume that the full
0.4 V appears across the diode. Then
i0 = 10
−15
(e
0.4
0.025
− 1) = 8.89 nA
EENG341 ELECTRONICS I 31
Example: Find I and V in the following circuit using
(a) ideal diode model and (b)CVD model with Von= 0.7 V.
+5V
20kΩ
20 kΩ
+
V
v
I
5V
5V
-5V
Solution: (a) Diode is forward biased:
V=-5+0=-5 V
I=
5 − (−5)
= 0.5 mA
3
20 x10
Example: Find the Q-point for the diodes in the following circuit using (a) the ideal diode
model and (b) CVD model with Von=0.75 V.
EENG341 ELECTRONICS I 32
Solution:
(a)
D1 OFF,
I D1 = 0,
D2 ON:
ID2 =
10 - (-15)
= +1.67 mA.
15 x103
VD1 = 10 − 104 I D 2 = −6.67 V
VD 2 = 0
D1 : (0 A, -6.67 V ),
(b)
D1 OFF ,
I D1 = 0,
ID2 =
D2
D2 : (1.67 mA, 0 V )
ON :
10 - 0.75 - (-15)
= +1.62 mA.
15 x103
VD1 = 10 -10 4 I D 2 = -6.17 V
, VD 2 = 0.75 V
D1 : (0 A, - 6.17 V ) , D2 : (1.62 mA, 0.75 V )
Example: Find the Q-points fort he diodes in the following circuit using (a) the ideal diode
model and (b) CVD model with Von=0.6 V.
Solution: (a) D1 ON, D2 OFF, D3
ID2=0
ON :
EENG341 ELECTRONICS I 33
I D1 =
10 = 0
= 1 mA.
(3 + 7) x103
I D 3 + 1 mA =
0 − (−5)
2.5 x103
==>I D 3 = 1.00 mA
VD 2 = 5 - (10 - 3000 I D1 ) = -2 V
VD1 = VD 3 = 0
D1 : (1 mA, 0 V ), D2 : (0 mA, −2 V ), D3 : (1 mA,0 V )
(b) D1 ON , D2 OFF , D3 ON :
I D2 = 0
I D1 =
10 - 0.6 - (-0.6)
= 1 mA.
(3 + 7) x103
I D 3 + 1 mA =
-0.6 - (-5)
2.5 x103
==> I D 3 = 0.760 mA.
VD 2 = 5 - (10 - 0.6 - 3000 I D1 ) = -1.4 V
D1 : (1 mA, O.6 V ), D2 : (0 mA, -1.4 V ), D3 : (0.76 mA, 0.6 V )
EENG341 ELECTRONICS I 34
2.
DIODE APPLICATIONS
Voltage Regulation
A voltage regulator is a circuit which provides a constant dc voltage between its output
terminals. The output voltage is required to remain as constant as possible in spite of
(a) Changes in the load current drawn by the regulator output terminal and
(b) Changes in the dc power-supply voltage that feeds the regulator circuit.
Since the forward voltage drop of the diode remains almost constant at
≈ 0.7 V while the
current through it varies by relatively large amounts, a forward-biased diode can make a
single voltage regulator.
Regulated voltages greater than 0.7 V can be obtained by connecting a number of diodes
in series.
EENG341 ELECTRONICS I 35
Operation in the Breakdown Region – Zener Diodes
At a specific test current , IZT, the voltage across the Zener diode is VZ, (-IZT,-VZ) is
denoted as Q.
For a change of ∆I in current, the Zener voltage changes by ∆V:
∆V=rz ∆I
rz is the incremental resistance(also known as the dynamic resistance) at point Q.
EENG341 ELECTRONICS I 36
Typically, rz is in the range of 5
≈ 50Ω.A low value of rz is preferred because it provides a
more stable outPut voltage. Its value is high at the vicinity of the “knee”. The Zener voltage is
given by:
VZ=VZ0+rz IZ
Which is valid for IZ>IZK & VZ>VZ0.
Zener Shunt Regulator
Regulation quality is measured by: the line regulation and the load regulation.
EENG341 ELECTRONICS I 37
The line regulation is defined as the change in V0 corresponding to a 1-V change in Vs,
Line regulation
≡
∆Vo
∆Vs
mV/V
The load regulation is defined as the change in V0 corresponding to a 1-V change in IL
Load Regulation
≡
∆V0
∆I L
The output voltage is
Vs − IR − Vzo − I z rz = 0
IR = Vs − Vzo − I z rz
R=
Vo =Vzo +
Vs − Vzo − I z rz
Iz + IL
rz
R
+ Vs
− I L ( rz // R )
R+rz
R + rz
EENG341 ELECTRONICS I 38
Using the output voltage and the definitions we obtain
Line regulation =
rz
R + rz
&
Load regulation = -( rz // R )
We must ensure that the current through the Zener diode never becomes too low.
Minimim Zener current occurs when Vs is at its minimum and IL is at its maximum load
current. This can be achieved by the proper selection of the value of R. Set Vs=Vsmin Iz=Izmin
and IL=ILmax to get
R=
Vs min − Vzo − r z I z min
I z min + I L max
Temperature effects
The dependence of the Zener voltage Vz on temperature is specified in terms of its
temperature coefficient TC (mV/oC).
EENG341 ELECTRONICS I 39
A forward conducting diode’s voltage drops by 2 mV for every 1oC.
Rectifier Circuits
Vs = 120
WHAT IS RECTIFIER?
AC TO DC CONVERTER
N2
N1
EENG341 ELECTRONICS I 40
The Half-Wave Rectifier
EENG341 ELECTRONICS I 41
Using the piecewise-linear diode model we have
V0=0 ,
V0 =
Vs<VD0
R
R
Vs − VD 0
,
R + rD
R + rD
Vs ≥ VD0
Using these equations we can plot the transfer characteristic; also, for many
applications rD<<R which gives
V0 ≅ Vs - VD 0
Rectifier diodes are chosen based on:
1- Current handling capability (Burn out), and
2- The peak inverse voltage(PIV)
When Vs is negative the diode will be cut off and V0 will be zero. Hence
PIV=Vs
When choosing a rectifier diode it is customary to choose one with 50% greater
breakdown voltage than the expected PIV.
EENG341 ELECTRONICS I 42
Full Wave Rectifier
≅
≅
Positive half cycles: D1 conducts, D2 cuts off
Negative half cycles: D2 conducts, D1 cuts off
To find the PIV: positive half cycles
The voltage at the cathode of D2 is V0 with peak value of Vs-VD0 and at the anode we
have –Vs with peak=Vs. Thus PIV -2Vs-VD0
EENG341 ELECTRONICS I 43
PEAK INVERSE VOLTAGE (PIV)
LARGEST REVERSE VOLTAGE
HALF-WAVE
FULL-WAVE
EENG341 ELECTRONICS I 44
The Bridge Rectifier (FULL-WAVE)
Positive half cycles: D1 conducts , through R, D2 conducts. D3 & D4 off. Two diodes in
series , V0 is lower than Vs by 2 diode drops.
Negative half cycles: D3
D1&D2 OFF
R
D4
EENG341 ELECTRONICS I 45
To determine the peak inverse voltage (PIV) of each diode, consider the circuit during
the positive half cycles. The reverse voltage across D3 can be determined from the loop
formed by D3, R and D2 as
VD3 (reverse) =V0+VD2 (forward)
The max VD3 is the PIV: We have from the output waveform, V0=Vs-2VD0
PIV=Vs-2VD0+VD0=Vs+VD0
PIV is about half the value for the full-wave rectifier with a centre-tapped transformer.
Another advantage of the bridge rectifier circuit over that utilizing a centre-tapped
transformer is that only about half as many turns are required for the secondary winding of the
transformer.
The bridge rectifier is the most popular rectifier circuit configuration.
EENG341 ELECTRONICS I 46
The Peak Rectifier
EENG341 ELECTRONICS I 47
Choose C such that CR>> T, where T is the period of the input sinusoid. A large CR
ensures a more constant V0.
iL =
V0
R
iD = iC + iL
=C
dVI
+ iL
dt
Observations
1. The diode conducts for a brief interval, ∆t near the peak of the input sinusoid and supplies
the capacitor with charge equal to that lost during the much longer discharge time which
is approximately equal to the period T.
2. Conduction begins at t1 and stops at t2; the exact value of the t2 can be determined by
setting iD=0.
EENG341 ELECTRONICS I 48
σ0
3. During the diode-off interval the capacitor C discharges through R and thus V0 decays
exponentially with a time constant Cr. At the end of the discharge interval V0=Vp-Vr,
when Vr is the peak-to-peak ripple voltage.
4. When Vr is small, V0 is approximately equal to Vp. The dc component of iL is given by
IL =
V0 V p − Vr
{iL = =
R
R
Vp
R
A more accurate expression for the output dc voltage can be obtained by taking the
average of the extreme values of V0,
1
V0 = V p − Vr
2
With these observations we can now find Vr, iDav and iDmax.
At the end of discharge interval we have
Vp - Vr = V 0
During the diode-off interval
V0 = V p e
With t=T
V p -Vr ≅ V p e
-T
CR
−t
CR
EENG341 ELECTRONICS I 49
Since CR>>T
e
−T
CR
≅ 1−
T
CR
Vr ≅ V p
T
CR
For CR>>T Vr is very small Using
Vr =
Vp
fCR
To find diode conduction interval ∆t:
V p cos( ω∆t )=V p -Vr
where
ω=2Πf=
For small ω∆t,
2Π
T
1
cos( ω∆t)=1- (ω∆t ) 2
2
1
V p [1- (ω∆t ) 2 ]=V p -Vr
2
V
==> ω∆t = 2 r
Vp
EENG341 ELECTRONICS I 50
To determine the average diode current during conduction, iDav, we equate the charge
that the diode supplies the capacitor,
Qsup plied = iCav ∆t
To the charge that the capacitor loses during the discharge interval,
Qlost =CVr
To obtain
iDav =I L (1+Π 2
We have assumed that
iLav =
Vp
R
Vp
)
Vr
= IL
iD max can be determined by evaluating
iD =C
at t=t1=-∆t
dVI
+ iL
dt
(t=0 is at the peak)
Then,
iDmax = I L (1 + 2Π 2
Vp
Vr
)
For Vr <<V p , iDmax ≅ 2iDav .This means that the
waveform iD is almost a right-angle triangle.
EENG341 ELECTRONICS I 51
To obtain a full-wave peak rectifier a capacitor is connected across the load of the fullwave rectifier circuit. In this case the period is replaced by
Vr =
V
T
.Hence
2
p
2 fCR
Q. For the full-wave peak rectifier, show that
iDav = I L (1 + Π
Vp
iDmax =I L (1+2Π
Vp
2Vr
)
&
2Vr
)
In the analysis of the peak rectifier circuit more accurate results can be obtained by
replacing the ideal diode by the real diode,i.e., by taking the diode voltage drop into
account.Hence, replacing Vp by Vp-VD0 & Vp-2VD0 where appropriate.
Peak rectifier in also known as a peak detector (because it detects the peak of an input
signal). They are widely used in the design of demodulators for amplitude-modulated (Am)
signals.
EENG341 ELECTRONICS I 52
Limiters(Clippers)
For now, K ≤ 1
The input signal range is
LL+
≤ VI ≤
K
K
EENG341 ELECTRONICS I 53
EENG341 ELECTRONICS I 54
Clamped Capacitor –dc restoration
Because of the diode’s polarity, the capacitor will charge to a voltage Vc equal to the
magnitude of the most negative peak of the input signal.
The output voltage will be
V0 = VI + Vc
That is, shifted upwards by Vc with lower peak clamped to 0V.
EENG341 ELECTRONICS I 55
Voltage Doubler
Because the output voltage is double the input peak, the circuit is known as a voltage
doubler. The technique can be extended to provide output dc voltages that are higher
multiples of Vp.
EENG341 ELECTRONICS I 56
Example: What is the maximum load current IL that can be drawn from the Zener regulator in
the following figure if it is to maintain a regulated output? What is the minimum value of RL
that can be used and still have a regulated output voltage? What is power dissipation in the
Zener diode for RL=∞?
R=15kΩ
Solution:
R=15kΩ
KVL gives : I s =
30-9
= 1.40mA
15k Ω
KCL gives : I s =I z +I L
I L =I s -I z
For voltage regulation I z >0
I L <1.40 mA
EENG341 ELECTRONICS I 57
For voltage regulation I z > 0
Iz = Is - IL
Is =
Vs - Vz
R
Iz =
& IL =
Vz
RL
Vs − Vz Vz Vs
1 1
−
= − Vz ( + )
R
RL R
R RL
Vs
1 1
− Vz ( + ) > 0
R
R RL
Solving for RL gives
RL >
R
Vs
−1
Vz
=
15
30
−1
9
=6.43 k Ω
For RL =∞ ,
Is=1.40 mA
P=9x1.40=12.6 mW
EENG341 ELECTRONICS I 58
3.
Bipolar Junction Transistor - BJT
The bipolar transistor structure has n-and p-type semiconductor material. These layers
are called emitter (E), base (B) and collector (C). We have two types of BJJ:
(a) npn transistor &
(b) pnp transistor
The physical structure is given in the following figure.
EENG341 ELECTRONICS I 59
Forward Characteristics
We apply a voltage to the base-emitter (VBE) junction and set VBC=0.
iC has the form of an ideal diode current:
iC = I s (e
VBE
VT
− 1)
Where Is is the transistor saturation current and is proportional to the cross-sectional area of
the active base region of the transistor. Its value is between:
EENG341 ELECTRONICS I 60
10 −18 A ≤ I s ≤ 10−9 A
VT = 25 mV.
iB is given by
iB =
iC
βF
=
Is
βF
(e
VBE
VT
− 1)
Where βF is called the forward common-emitter current gain. Its value is in the range given
below:
20 ≤ β F ≤ 500
By considering the transistor as a super node we can find iE:
iE = iC + iB
iE = ( I s +
Is
βF
)(e
VBE
VT
− 1)
or
I
β +1
iE = I s ( F )(e V − 1) = s (e V − 1)
βF
αF
VBE
T
Where
αF
VBE
T
is called the forward common-base current gain which has a value of
EENG341 ELECTRONICS I 61
0.95 ≤ α F ≤ 1.0
and it is given by
αF =
βF
βF +1
For the forward active region we can obtain the following useful relationships:
iC
= βF
iB
&
or
i C =β F iB
iE =( β F + 1)iB
Also we have
iC
= αF
iE
or
iC =α F iE
The transistor “amplifies” its base current by the factor βF . Because the current gain
βF>>1, injection of a small current into the base of the transistor produces a much larger
current in both the collector and the emitter terminals. The collector and the emitter currents
are almost identical, because
α F ≈ 1.
EENG341 ELECTRONICS I 62
Reverse Characteristics
We now apply a voltage VBC to the base-collector junction and set VBE=0.
The reverse current is given by
EENG341 ELECTRONICS I 63
iR = I s (e
VBC
VT
− 1)
and
iE = −iR
Also
iB =
iR
βR
=
Is
βR
(e
VBC
VT
− 1)
Where βR is called the reverse common-emitter current gain.
βr is in the range:
0 < β R ≤ 20
iC can be found by combining iB & iE:
iC = − I s (1 +
Where
1
βR
)(e
VBC
VT
− 1) =
−Is
αR
(e
VBC
VT
α R is called the reverse common-base current gain:
αR =
βR
βR +1
α R has values in the range
0 < α R ≤ 0.95
− 1)
EENG341 ELECTRONICS I 64
General Bias Equations
VBC
 VVBE
 I
VT
T
iC = I s e − e  − s

 β R
 VVBC 
 e T − 1


VBC
VBE
 VVBE



I
VT
VT
s
T
iE = I s  e − e  +
 e − 1
β
F 




V
 I  VVBC 
I s  VBET
iB =
 e − 1 + s  e T − 1
β F 
 β R 

Example: In the following figure and npn transistor is biased by two dc voltage sources.
Find the terminal voltages and currents.
β F = 50
Solution:
,
βR = 1
EENG341 ELECTRONICS I 65
VBE = VBB = 0.75 V
VBC = VBB - VCC = 0.75 - 5 = -4.25V
0.75
-4.75
-4.75
 0.025


−16  0.025
0.025
iC = 10 e
−e
− 1
 − 10 e




= 1.07 mA
-16
10-16
iE =
50
0.75
-4.75
0.75
 0.025



−
16
0.025
0.025
e
−
e
+
10
e
−
1



 = 1.09 mA




0.75
-4.75
 0.025


−16  0.025
e
−
1
+
10
e
−
1



 = 21.4 µ A




I
I
1.07
1.07
Also, β F = C =
= 50 & α F = C =
I B 0.0214
I E 1.09
10-16
iB =
50
= 0.982
The pnp transistor
Circuit symbol for the pnp transistor is
E
IE
iB
B
IC
C
Consider the following circuit with VEB applied and VCB=0.
EENG341 ELECTRONICS I 66
 VVEB 
iC = I s  e T − 1


V

I s  VEBT
iB =
e
1
=
−


β F β F 

iC

1
iE = iC + iB = I s  1 +
 βF
V

  VEBT
  e − 1
 

Now, consider the following circuit with VCB applied and VEB=0
EENG341 ELECTRONICS I 67
The collector-base voltage establishes the following currents:
 VVCB 
− iE = I s  e T − 1


V

I s  VCBT
iB =
 e − 1
β R 


1
iC = − I s  1 +
 βR
where iC =iE -iB
For the general bias voltage:
V

  VCBT
 e − 1
 

EENG341 ELECTRONICS I 68
VCB
VCB
 VVEB



Is
VT
VT
T
IC = I s e − e  −
 e − 1

 β R 

VCB
VEB
 VVEB



I
VT
VT
s
T
iE = I s e − e  −
e − 1


 β F 
V
 Is
I s  VEBT
iB =
 e − 1 +
β F 
 β R
 VVCB 
 e T − 1


Note that these equations are identical to those for the npn transistor except that VEB and VCB
replace VBE and VBC, respectively.
THE OPERATING REGIONS OF THE BJT
We can have four possible regions of operation as defined below:
EENG341 ELECTRONICS I 69
The i-V Characteristics of the BJT
These are for the
(a) Output characteristics
IC vs VCE
or IC vs VCB
and
(b) transfer characteristics
IC vs VBE
(a) Output characteristics
Circuits for common-emitter output characteristics are given below:
The base of the transistor is driven by a constant currents source, and the output
characteristics represent a graph of iC vs VCE (npn) or iC vs VEC (pnp) with base current iB as a
parameter.
EENG341 ELECTRONICS I 70
Saturation region
Forward- active
region
2.5 mA
iB = 100µ A
2 mA
iB = 80µ A
1.5 mA
iB = 60 µ A
iB = 40 µ A
1 mA
iB = 20 µ A
0.5 mA
iB = 0µ A
0 mA
Cutoff
Saturation
β F = 25, β R =5
-1 mA
-5 V
0V
5V
10 V
Reverse - active
region
iC
i
C
vs
VCE
:
vs
VEC
:
npn 
pnp 
For IB=0, the transistor is non-conducting or cut off.
i = β F iB ).
For
VCE ≥ VBE ,
For
VCE ≤ VBE , saturation region of operation.
For
VBE ≤ VCE ≤ 0 , saturation region of operation.
For
VCE ≤ −VBE , reverse active region ( iC = −( β R + 1)iB ) Ic is independent of
VCE
forward active region iC is independent of VCE ( C
EENG341 ELECTRONICS I 71
For the pnp transistor, the output characteristics will appear exactly the same as the
npn except VCE is replaced by VEC.
Circuits for measuring the common-base output characteristics of the npn and pnp
transistors are shown below.
In these circuits, the emitter of the transistor is driven by a constant current source, and
the output characteristics plot ic vs VCB for the npn (or ic vs VBC fo the pnp), with the emitter
current iE as a parameter.
EENG341 ELECTRONICS I 72
iE = 1 mA
iE = 0.8 mA
iE = 0.6 mA
iE = 0.4 mA
iE = 0.2 mA
iE = 0
βF =25, βR =5
For
ic
VCB ≥ 0 V , operation is in the forward active region with ic independent of VCB, and
≅ iE.
For
VCB ≤ 0 V ,
the base-collector junction becomes forward biased, and the collector
current grows exponentially (diode current)in the negative direction as the base-collector
junction begins to conduct.
For the pnp BJT, we have exactly the same characteristics except VCB becomes VBC.
EENG341 ELECTRONICS I 73
(b) Transfer characteristics
For the BJT this is defined as
Ic
Vs VBE
The transfer characteristic is virtually identical to that of a pn junction diode:
iC = I s (e
VBE
VT
− 1)
Only a 60 mV change in VBE is required to change ic by a factor of 10.
EENG341 ELECTRONICS I 74
Simplified Models
(1) Cutoff region
Both junctions are reverse-biased. We need
VBE ≤ 0
Assume that VBE<-0.1 V
&
VBC<-0.1 V
In cutoff npn terminal currents are:
&
VBC ≤ 0.
EENG341 ELECTRONICS I 75
VBC
 VVBE
T
iC = I s  e − e VT

 I  VVBC

s
T
−
e
−
1



 β R 

VBC
 VVBE
T
iE = I s  e − e VT

V
I s  VBET
iB =
e
β F 
 I  VVBE

s
T
+
 e − 1

 β F 

 I s  VVBC
− 1 +
 e T − 1
 β R 

or
iC =
Is
βR
,
iE =-
Is
βF
,
iB =-
Is
βF
−
iC
Is
iB
βR
Is
βR
iC
iB
Is
βF
iE
iE
(2) Forward-Active region
Emitter-base junction is forward-biased and the collector-base junction is reversebiased. Because of the BJT in this region can exhibit a high voltage and current gain, it is
useful for analog amplification.
For and npn:
VBE ≥ 0 & VBC ≤ 0
Further
EENG341 ELECTRONICS I 76
VBE > 0.1 V
VBC < −0.1 V
&
in Forward – Active npn terminal currents are:
VBC
 VVBE
iC = I s  e T − e VT

 I  VVBC

s
T
− 1
−
e
β
R 



VBC
 VVBE
iE = I s  e T − e VT

 I  VVBE

s
T
− 1
+
e
β
F 



V

 I s  VVBC
I s  VBET
T
iB =
− 1 +
− 1
e
e
β F 
 β R 

iC =I s e
Is
iE =
αF
i0 =
Is
βF
VBE
VT
e
e
+
VBE
VT
VBE
VT
Neglecting the small terms, we have
Is
βR
+
−
Is
βF
Is
βF
−
Is
βR
EENG341 ELECTRONICS I 77
iC = I s e
iE =
iB =
Is
αF
Is
βF
VBE
VT
e
e
VBE
VT
VBE
VT
The terminal currents all have the form of diode currents and the controlling voltage is
VBE and the currents are independent of VBC.
iC
= αF
iE
==>
iC =α F iE
iC
= βF
iB
==>
iC =β F iB
iE =iC +iB
==> iE =(1+β F )iB
iC = β F i B
iE = (1 + β F )iB
(3) Reverse-Active region
iC = β F i B
EENG341 ELECTRONICS I 78
The base-collector junction is forward-biased and the base-emitter junction is reverse-biased.
In reverse-active region the terminal currents are:
VBC
 VVBE
iC = I s  e T − e VT

 I  VVBC

s
T
−
−
1
e



β
R 



VBC
 VVBE
iE = I s  e T − e VT

 I  VVBE

s
T
+
−
1
e



β
F 



V

 I  VVBC
I s  VBET
s
T
iB =
e
−
1
+
e
−
1




β F 
β
R 



Neglecting the small terms, we have
iC =-
Is
αR
iE =-I s e
iB =
Is
βR
e
VBC
VT
VBC
VT
e
VBC
VT


 ==> iE = − β
R

iB



iE
= αR
 ==>
i
C


==>
iE = − β R iB
==>
iE =α R iC
−iE = β R iB
Ise
VBC
VT
−iC = (1 + β R )iB
(4) Saturation region
−iC = (1 + β R )iB
EENG341 ELECTRONICS I 79
Both junctions are forward-biased, and the transistor operates with a small voltage between
collector and emitter terminals. In the saturation region, the dc value of VCE is called the
saturation voltage: VCESAT (npn) or VECSAT (pnp).
To find VCESAT, we obtain the terminal currents with both junctions forward-biased:
iC = I s e
iB =
Is
VBE
VT
e
−
VBE
VT
Is
αR
+
e
Is
VBC
VT
e
VBC
VT
βF
βR
αR
U sin g β R =
, we obtain VBE & VBC :
1−αR
iB + (1- α R )iC
VBE = VT ln
VBC = VT ln
VCESAT
 1

+ (1- α R ) 
Is 
 βF

i
iB - C
βF
 1  1

Is   
+ (1- α R ) 
α R   β F


 1
= -VT ln 
 α R


 (1 + β R )iB 


i
C

1−

(1 + β R )iB 
1+
The simplified model for the transistor in saturation is:
iC
,
iB >
iC
βF
EENG341 ELECTRONICS I 80
The junctions are replaced with their ON voltages.
VCESAT=0.75-0.7=50 mV.
In saturation, the terminal currents are determined by the external circuit elements ; no
i + iB = iE .
simplifying relationships exist between iC, iB and iE other than C
The Early Effect and Early Voltage
i
In a real transistor C is not entirely independent of VCE; this observed experimentally
by James Early. When the output characteristic curves are extrapolated back to the point of
zero collector current, the curves all intersect at a common point, VCE=--VA. This is called the
Early Effect and the voltage VA is called the Early voltage.
EENG341 ELECTRONICS I 81
iB = 100 µ A
80 µ A
60 µ A
40 µ A
20 µ A
The Early voltage is in the range
25 V ≤ VA ≤ 150 V
Modelling the Early Effect
The dependence of iC on VCE can be included using the forward-active region:
iC = I s e
VBE
VT

 VCE 
1 + V 
A 

β F = β F 0 1 +

iB =
Where
VCE 
VA 
I s VBE 
β F 0  VT 
β F 0 represents the value of β F
extrapolated to VC=0.
EENG341 ELECTRONICS I 82
Biasing the BJT
The goal of biasing is to establish a known quiescent operating point, or Q-point.
For the npn BJT the Q-point is (IC, VCE), that is, the dc values of the collector current
and collector-emitter voltages.
For the pnp BJT the Q-point is (IC, VCE).The Q-point establishes the initial operating
region of the transistor.
We shall now illustrate the dc biasing with an example. Early voltage is assumed to be
infinite, that is, we will neglect the Early effect.
The four-resistor bias network is shown below:
16kΩ
36kΩ
22kΩ
β F = 75
18kΩ
16kΩ
EENG341 ELECTRONICS I 83
R1 & R2 form a resistive voltage divider across the power supply and common (12V & 0V)
and attempt to establish a fixed voltage at the base of transistor Q1.
RE & RC are used to define the emitter current and collector-emitter voltage of the transistor.
Our goal is to find the Q-point: (IC, VCE).
Step 1: Split the power supply into two equal voltages as shown below:
36kΩ
18kΩ
22kΩ
16kΩ
Step 2: Replace the base-bias network by it’s Thevenin equivalent circuit as shown below.
EENG341 ELECTRONICS I 84
I1 ≅ I 2
22kΩ
12kΩ
16kΩ
VEQ & REQ are given by
VEQ = VCC
R1
R1 + R2
VEQ = 4V
&
REQ =
&
R1 R2
R1 + R2
REQ = 12k Ω
Step 3: Assume a region of operation. We will assume that the transistor is operating in the
forward-active region.
KVL in loop1:
VEQ = REQ I B + VBE + RE I E
4 = 12,000 I B + VBE + 16,000 I E
For forward - active region VBE = 0.7V & I E = (1 + β F ) I B
4 = 12,000 I B + 0.7 + 16,000 (1 + β F ) I B
β F = 75
IB =
4 - 0.7
= 2.73µ A
1.21x106
EENG341 ELECTRONICS I 85
I C = β F I B = 205µ A
I E = (1 + β F ) I B = 208µ A
y=mx+c
To find VCE , we use loop2:
VCE =VCC -RC I C -RE I E =VCC -(RC +
We use I E =
RE
αF
)I C
IC
VCE =VCC (RC +
αF
RE
αF
)I C
VCE =12-38,200 I C =12-7,83=4,17V
All the calculated currents are positive, and
VBC = VBE − VCE = 0.7 − 4.17 = −3.47 V
Thus, the base-collector junction is reverse-biased. This means that our assumption of
forward-active region of operation was correct.
The Q - po int is (205µ A, 4.17 V )
Q. Estimate the Q-point using the load line.
− IC =
VCE − VCC
R
RC + E
αF
==> I C =
VCC
VCE
−
R
R
RC + E RC + E
αF
I C = −mVCE +
αF
VCC
R
RC + E
αF
EENG341 ELECTRONICS I 86
Design Objectives for the four-resistor bias network
To explore the design objectives, we first solve for the emitter current using the
The’venin equivalent circuit:
VEQ = REQ I B + VBE + RE I E
IE =
VEQ − VBE − REQ I B
≅
RE
VEQ − VBE
RE
for REQ I B << (VEQ - VBE )
REQ is normally designed to be small enough to neglect the voltage drop caused by the
base current flowing through REQ. Therefore, IE is set by the combination of VEQ, VBE and RE.
Normally VEQ is designed to be large enough that small variations in the assumed values of
VBE will not affect the values of IE.
Looking at the bias network, we can see that the assumption IBREQ<<(VEQ-VBE) is equivalent
to assuming
I B << I 2
so that
I1 << I 2
The base current of Q1 does not disturb the voltage divider action of R1 & R2.
36kΩ
18kΩ
22kΩ
16kΩ
EENG341 ELECTRONICS I 87
Using the approximate expression for IE, we have
IE =
4 − 0.7
= 206 µ A
16,000
Which is essentially the same as before.
A very large number of possible combinations of R1 & R2 will yield the desired value
of VEQ. We need to impose an additional constraint to finalize the design choice. A good
choice is to limit the power dissipated in bias resistors R1 & R2 by choosing
Example: Design the following circuit to give a Q-point of
I2 ≤
IC .
5
(750 µ A, 5V ) using a 15V
supply with a transistor having a minimum current gain of 100.
EENG341 ELECTRONICS I 88
Solution:
The Thevenin equivalent circuit is
where
R1
R1+R2
VEQ =VCC
&
REQ =
R1 R2
R1+R2
We assume that the voltage drop in REQ can be neglected. To find VEQ, we must
know the voltage across the emitter resistor RE. It is common to divide the remaining power
supply voltage VCC-VCE=10V equally between RE and RC.
VE=5V
and
VEQ=VBE+VE=5.7 V(neglecting IBREQ)
VEQ
VCC
=
R1
R1 + R2
==>
5,7
R1
=
------------(1)
15 R1 + R2
To find R1 & R2 , we need a second equation. Because the minimum current is 100,
I C = 750µ A
I B ≤ 7.5µ A
IC = β F I B
IB =
IC
βF
EENG341 ELECTRONICS I 89
We have shown that
4=12,000I B +VBESAT +16,000I E
12=56,000I C +VCESAT +16,000I E
Assume: VBESAT =0.75V +VCESAT =0.05V
Also, I E =I B +I C
3,25=28,000I B +16,000I C
11,95=16,000I B +72,000I C
We have, I B =24 µ A, I C =160 µ A & I E =184 µ A
IC
< βF
IB
( β For < β F )
Q1 is in saturation
I B << I 2
I 2 ≥ 75µ A
Choose
I 2 = 100 µ A
Because
I 2 >> I B ,
I1 ≅ I 2
VCC = I 2 R2 + I1 R1 ≅ I 2 ( R1 + R2 )
==> R1+R2 =
VCC
15V
=
= 150k Ω
I 2 100 µ A
R1+R2 =150k Ω
− − − − − − − − − (2)
We now have two equations with two unknowns which give
EENG341 ELECTRONICS I 90
R1 = 57 k Ω
&
R 2 = 93k Ω
Finally, the values of RC & RE are given by
RC =
5V
5
=
= 6.67 k Ω
I C 750 µ A
&
RE =
5V
5V
=
= 6.60k Ω
I E 758µ A
Example: Find the terminal currents and the region of operation for the following circuit.
56kΩ
12kΩ
16kΩ
Assume forward-active region:
KVL to loop1:
β F = 75
EENG341 ELECTRONICS I 91
Since VCE is negative, the assumption of forward-active region is not valid.
Assume that Q1 is saturated:
KVL for loop1 & 2 gives
4=12,000I B +VBESAT +16,000I E
12=56,000IC +VCESAT +16,000I E
Assume: VBESAT =0.75V +VCESAT =0.05V
Also, I E =I B +IC
3,25=28,000I B +16,000IC
11,95=16,000I B +72,000IC
We have, I B=24 µ A, IC =160 µ A & I E =184 µ A
IC
< βF
IB
( βFor < βF )
Q1 is in saturation
EENG341 ELECTRONICS I 92
BJT Modeling and Small-Signal Analysis
The hybrid-pi small-signal model for the intrinsic bipolar transistor is given below:
rπ
rπ
Where gm is the transconductance
IC
= 40 I C
VT
gm =
rπ is the input resistance
rπ =
β 0VT
IC
=
β0
gm
ro is the output resistance
ro =
ro =
VA
IC
VA + VCE
IC
where VA=Early Voltage
EENG341 ELECTRONICS I 93
β 0 represents the small-signal common-emitter current gain.
β 0 = g m rπ
The small-signal model has a voltage-controlled current source gmVbe. We can transform this
into a current-controlled current source by
Vbe = ib rπ
g mVbe = g m rπ ib
=β0 ib
This result is modeled below:
rπ
ic = β 0ib +
β0 ib
Vce
≅ β 0ib
r0
for
Vce
<< β 0ib
r0
Amplification factor
Defined by
µ f = g m ro =
µf ≅
IC
VT
VA
≅ 40VA ,
VT
VA + VCE VA + VCE VA VCE
=
=
+
IC
VT
VT VT
for VCE << VA
EENG341 ELECTRONICS I 94
T-Model
The BJT small-signal T-model is shown below:
β 0ib
re =
VT
IE
g mVbe
EENG341 ELECTRONICS I 95
α ie
Fort he small-signal modeling to be valid we need
Vbe ≤ 0.005V
Small-signal models fort he pnp transistor are identical to that of the npn.
EENG341 ELECTRONICS I 96
THE BJT COMMON-EMITTER (C-E) AMPLIFIER SMALL-SIGNAL
ANALYSIS
The C-E amplifier is given below:
30kΩ
4.3kΩ
∞
∞
1kΩ
100kΩ
∞
10kΩ
1.3kΩ
To use the transistor as an amplifier, ac signals need to be introduced into the circuit,
but application of these ac signals must not disturb the dc Q-point that has been established by
the bias network. To do this we use ac coupling through capacitors. Their values at ac are
negligible but they provide dc blocking by behaving like open circuits at dc. C1 & C2 are,
therefore, called coupling capacitors or dc-blocking capacitors. As indicated their
values are chosen to be very large.
In many circuits, we want to force signal currents to go around elements of the bias
network. This is done by using bypass capacitors, C3 in this figure is a bypass capacitor.
EENG341 ELECTRONICS I 97
Capacitor C3 provides a low impedance path for ac current from the emitter to ground,
bypassing emitter resistor RE. Thus RE, which is required for good Q-point stability, can be
effectively removed from the circuit when ac signals are considered.
dc equivalent circuit
This is used to find the Q-point of the circuit. For this analysis, we assume that
capacitors are open circuits and inductors are short circuits.
Once we have found the Q-point, we determine the response of the circuit to the ac
signals using an ac equivalent circuit. For this purpose we must use the small-signal models
that we have developed.
dc and ac equivalent circuit analysis steps
dc analysis
1. Find the dc equivalent circuit by replacing all capacitors with open circuits
and inductors by short circuits.
2. Find the Q-point using the dc equivalent circuit.
ac analysis
3. Find the ac equivalent circuit by replacing all capacitors by short circuits and
all inductors by open circuits. dc voltage sources.
EENG341 ELECTRONICS I 98
Bias voltages are replaced by ground connections, and dc current sources are replaced by
open circuits in the ac equivalent circuits.
4. Replace the transistor by its small-signal model.
5. Analyses the ac characteristics of the amplifier using the small-signal ac equivalent circuit
from step 4.
6. Combine the results from step 2 and 5 to yield the total voltages and currents in the
network. This is called superposition.
Now we are in a position to analysis the C-E amplifier.
A.
dc analysis of the C-E amplifier. This is done by open-circuiting all the capacitors:
4.3kΩ
30kΩ
β F = 100
VBE = 0.7V
10kΩ
VA = ∞
1.3kΩ
dc circuit for C-E Amplifier
The Q-point is (Ic=1.66 mA, VCE=2.68 V)
EENG341 ELECTRONICS I 99
B. ac small-signal analysis of the C-E amplifier We first obtain the ac equivalent circuit by
short circuiting C1,C2 & C3 and VCC:
1kΩ
7.5kΩ
4.3kΩ
100kΩ
We apply Thevenin to the left the dotted line to obtain the simplified circuit:
880Ω
4.3kΩ
Vth =
RB
Vs
RB + Rs
&
Rth =
RB Rs
RB + Rs
100kΩ
with RB = R1 // R2
We then replace the transistor by its small-signal model .Since the emitter terminal is
grounded we use the hybrid-pi model:
EENG341 ELECTRONICS I 100
rπ
A final simplification gives:
rπ
EENG341 ELECTRONICS I 101
R L = r0 // Rc // R3
The voltage gain is given by
V
AVth = 0
Vth
V0 = - g mVbe R L
Vbe =
AV =
rπ
Vth
rπ + Rth
V0
g r R
RB
=− m π L
Vs
rπ + Rth R B + R s
==-
β 0 RL
rπ + Rth
RB
RB + Rs
g m RL
1
R
R
rπ + th 1 + s
rπ
RB
Example: Calculate the voltage gain of this C-E amplifier with
point is(1.45, 3.86 V).
Solution:
β0 = 100 , VA=75V & the Q-
EENG341 ELECTRONICS I 102
AV = -
β 0 RL
rπ + Rth
RB
, RB = R1 // R2
RB + Rs
First, we calculate the the small-signal model parameters:
rπ =
β0VT
IC
=
100 (0,025)
= 1,72k Ω
1,45
VA + VCE 75 + 3,86
r0 =
=
= 54,4k Ω
IC
1,45
RB = R1 // R2 = 7,50k Ω
Rth = Rs // RB = 882Ω
RL = RC // R3 // r0 = 3,83k Ω
100 x 3,83 7,50
= -130
1,72 + 0,882 7,50 + 1
in decibel ,
AV (db) = 20 log130
AV = -
= 42,3dB
C-E Input Resistance
The input resistance RIN to the C-E amplifier is defined in the following figure
EENG341 ELECTRONICS I 103
30kΩ
C1 → ∞
4,3kΩ
C2 → ∞
1kΩ
10kΩ
1,3kΩ
C3 → ∞
RIN represents the total resistance presented to the signal source.
ac equivalent circuit is
4,3kΩ
30kΩ
10kΩ
Replacing the BJT by its small-signal model gives
rπ
100kΩ
EENG341 ELECTRONICS I 104
Vx = ix ( RB // rπ )
RIN =
Vx
= RB // rπ = R1 // R2 // rπ
ix
C-E OUTPUT RESISTANCE
The output resistance is defined below
30kΩ
4,3kΩ
C1 → ∞
C2 → ∞
1kΩ
10kΩ
1,3kΩ
The ac equivalent circuit is obtained below (Vs is set to zero).
Replacing the BJT by its small-signal model:
rπ
C3 → ∞
EENG341 ELECTRONICS I 105
ix =
Vx Vx
+ + g mVbe
Rc r0
The base node gives
Vbe Vbe Vbe
+
+
=0 ,
Rs RB rπ
g mVbe = 0
ROUT =
Vx
= r0 // Rc
ix
For r0 >> RC :
ROUT ≅ RC
Vbe = 0
EENG341 ELECTRONICS I 106
Field-Effect Transistors-FETs
We shall study the Field-effect-transistors (FETs) with their respect to their:
Structure
Linear operation
Biasing and
Small-signal modelling
Namely, we shall cover,
Metal-oxide-semiconductor FET (MOSFET)
p-channel MOS (PMOS)transistor
n-channel MOS (NMOS)transistor
And
Junction FET (JFET)
The MOS Capacitor
The behaviour of the MOS capacitor forms the basis of operation fort he MOSFET.
EENG341 ELECTRONICS I 107
The metal electrode is called the
gate.
The insulating layer is formed by
silicon dioxide with thickness Tox.
The semiconductors, which can
n-type or p-type acts as the second
electrode. This is called substrate or
body.
When a large negative bias is
applied
a
shallow
charge
sheet(holes) is formed below the
gate. This is called accumulation.
When the voltage is increased the
hole density near the surface is
reduced below the majority-carrier
level set by the substrate doping
level. The region beneath the metal
electrode is deleted of free carriers
and this is called depletion.
At some voltage level, the electron
density at the surface will exceed the
hole
density;
the
surface
has
inverted polarity from the p-type to
an n-type inversion layer. This
voltage is called the thresholdvoltage VTN.
EENG341 ELECTRONICS I 108
Structure of the NMOS Transistor
The NMOS transistor is illustrated below
EENG341 ELECTRONICS I 109
The n-channel MOSFET is usually called and NMOS transistor, or NMOSFET
The channel is the MOS capacitor; two heavily doped n-typed regions (n+) are called the
source (S) and drain (D).The substrate forms a fourth terminal known as the substrate
terminal or the body terminal (B). The terminal voltages are given by
VGS = VG − VS
VDS = VD − VS
VSB = VS − VB
These voltages are all ≥ 0 during normal operation of the NMOSFET.
The pn junctions formed by the source-substrate and drain substrate are kept reverse-biased
times in order to provide isolation between the junctions and the substrate as well as between
adjacent MOS transistors. Thus,
VB ≤ VS
and
VB ≤ VD
The gate length L and gate width W are measured in the direction of current and
perpendicular to the direction of current, respectively. These are important design parameters
for the NMOSFET.
EENG341 ELECTRONICS I 110
Qualitative i-V behavior of the NMOSFET
We use the following illustration in which the source, drain, and body of the NMOSFET are
all grained.
For
a
dc
gate-source
voltage
VGS=VGS well below VTN, back –
to-back pn junctions exist between
the source and drain, and only a
small leakage current can flow
between these two terminals.
For VGS<VTN, a depletion region
forms in the channel and merges
with the depletion regions of the
source and drain. The depletion
region is devoid of free carriers, so
a current cannot appear between
the source and drain
When VGS>VTN, electrons flow in
from the source and drain to form
an inversion layer that connects the
n+ source region to the n+ drain
The current in the NMOSFET
always enters the drain terminal,
travels down the channel, and exits
the source terminal.
EENG341 ELECTRONICS I 111
Since the gate voltage “enhances” the conductivity of the channel, this type of MOSFET is
named an enhancement-mode device.
Linear Characteristics of the NMOSFET
We have established that iG=0 & iB=0.
is=iD=iDS
We can find iDS by using the following figure
To find iDS we consider the flow of charge in the channel. The electron charge per unit length
(a line charge) at any point in the channel is given by
Q ' = −WCox" (Vox − VTN )
C / cm, Vox ≥ VTN
EENG341 ELECTRONICS I 112
Where C”ox= Єox/Tox , oxide capacitance per unit area (F/cm2)
Єox= oxide permittivity (F/cm) [Єox=3.9 Єo]
Єo= 8.854 x 10-14 F/cm
Tox=oxide thickness (cm)
The voltage Vox represents the voltage across the oxide and will be a function of position in
the channel
Vox=VGS-V(x)
Where V(x)=voltage at any point x in the channel referred to the source.
Vox must exceed VTN for an inversion layer to exist, so Q’=0 for Vox<VTN.
At the source end of the channel,
Vox=VGS
At the drain end of the channel,
Vox=VGS-VDS
The electron drift current at any point in the channel is given by the product of the charge per
unit length times the velocity Vx:
i(x)=Q’(x)Vx(x)
EENG341 ELECTRONICS I 113
i(x)=[-WC”ox(Vox-VTN)][-µn Ex]
where µn is the electron mobility and
Ex is the transverse electric field in the channel
The transverse electric filed is given by
Ex = −
dV ( x)
dx
The current at any point in the channel is given by
dV ( x)
dx
i ( x)dx = − µ n C "oxW (VGS − V ( x) − VTN ) dV ( x)
i ( x) = − µ n C "oxW (VGS − V ( x) − VTN )
or
The voltages applied to the device terminals are V(0)=0 and V(L)VDS, we can now integrate
between O & L:
L
VDS
0
0
"
i
(
x
)
dx
=
−
µ
C
∫
∫ n oxW (VGS − V ( x) − VTN )dV ( x)
At any point x in the channel i(x)=-iDS
iDS L = µ C "oxW (VGS − VTN −
or
iDS =µ C "ox
VDS
)VDS
2
V
W
(VGS − VTN − DS )VDS
L
2
EENG341 ELECTRONICS I 114
The value of µnC”ox is fixed for a given technology.
iDS = K n '
V
W
(VGS − VTN − DS )VDS
L
2
where K n' =µ nC" ox
or
iDS =K n (VGS -VTN -
where
K n =K n'
VDS
)VDS
2
W
L
The parameters Kn and Kn’ are called the transconductance parameters and both have the units
of A/V2.
This iDS is for the ear region of operation and is valid for
VGS − V ( x) ≥ VTN
for
0≤x≤L
V ( x) is maximum when x=L
V(L)=VDS
iDS is valid for
VGS -VTN ≥ VDS
iDS is sometimes written as
V

iDS = WC" ox (VGS -VTN - DS
2

 V 
)  µ n DS 
L 

EENG341 ELECTRONICS I 115
Linear Region i-V Characteristic
iDS = K n '
V
W
(VGS − VTN − DS )VDS
L
2
for VGS -VTN ≥ VDS ≥ 0
& K n' =µ nC" ox
Sketch for
VTN=1 V & Kn=250 µA/V2
A portion of the output characteristic (VSB=0)
The characteristics appear to be a family of straight lines (except for VGS=2V).
For small VDS,i.e., VDS<<VGS-VTN, we have
iDS ≅ µ nC "ox
W
(VGS − VTN )VDS
L
iDS becomes proportional to VDS and MOSFET behaves like a resistor.
 ∂i

Ron =  DS |VDS →0 
 ∂VDS

−1
1
=
Q − po int
Kn'
W
(VGS − VTN )
L
EENG341 ELECTRONICS I 116
Saturation of the i-V Characteristics
We have obtained iDS for an MOSFET with VGS>>VTN and VDS=0. Now we shall study this
MOSFET with non-zero VDS as shown below:
The MOSFET is operating in the
linear region with VDS<VGS-VTN
As discussed before.
The value of VDS has increased to
VDS=VGS-VTN,
For
which
the
channel
just
disappears at the drain.
Now, we apply
VDS>VGS-VTN
The channel region has disappeared
or “pinched off” before reaching the
drain end of the channel.
EENG341 ELECTRONICS I 117
We may think that iDS=0 in the MOSFET. However, this is not the case as well shall show by
the use of the following figure.
The voltage the “pinch-off point” in the channel is always equal to
VGS − V ( x po ) = VTN
or
V ( x po ) = VGS - VTN
There is still a voltage equal to VGS-VTN across the inverted portion of the channel, and the
electrons move in the direction of x. When the electrons reach the pinch-off point, they are
injected into the depleted region between the end of the channel and the drain. The electric
field in the depleted region then sweeps the electrons on to the drain. Once the channel has
reached pinch-off, the voltage drop across the inverted channel region is constant, and the
MOSFET enters the saturation region of operation. This region is also known as the pinch-off
region.
EENG341 ELECTRONICS I 118
To find iDS in this region we use
iDS = K n '
V
W
(VGS − VTN − DS )VDS
L
2
with VDS =VGS -VTN
iDS =K n '
W
(VGS − VTN ) 2 ,VDS ≥ (VGS -VTN ) ≥ 0
L
The current depends on the square of VGS-VTN but is independent of VDS.
At saturation VDS-VDSAT and is defined by
VDSAT = VGS − VTN
VDSAT is known as the saturation voltage or pinch-off voltage.
iDS can be modified as
(V − VTN )   (VGS − VTN ) 

µn
iDS = WC "ox GS



L
2


E − field of
VGS -VTN
L
EENG341 ELECTRONICS I 119
The complete output charactersistics for an NMOSFET with
VTN=1 V & Kn=25µA/V2
is given below:
The locus of pinch-off points is determined by
VDS=VDSAT
To the left the pinch-off locus the MOSFET is operating in the linear region.
To the right of the pinch-off locus the MOSFET is operating in the saturation region.
For VGS≤VTN=1,the transistor is cut off.
EENG341 ELECTRONICS I 120
Channel-Length Modulation
When VDS increases, iDS also slightly increases when the device is in saturation. This
phenomenon is called the channel-length modulation which is explained below.
VDS>VDSAT
The channel pinches off before it makes contact with the drain.
The actual length of the resistor channel is
EENG341 ELECTRONICS I 121
L=Lm-∆L
VDS increases
∆L increases and L decreases
L depends on VDS
We modify iDS to include this drain-voltage dependence as
'
iDS
K W
= n
(VGS − VTN ) 2 (1 + λVDS )
L L
Where λ is called the channel-length modulation parameter. λ is dependent on the channel
length and typically is given by
0,001V −1 ≤ λ ≤ 0,1V −1
NMOSFET Summary for the complete i-V model
For all regions:
Cutoff region:
W
iG=0 , iB=0
L
iDS =0 for VGS ≤ VTN
Kn=µnC" ox
Linear region:
iDS =Kn(VGS -VTN -
VDS
)VDS
2
For VGS -VTN ≥ VDS ≥ 0
Saturation region:
iDS =
Kn
(VGS −VTN )2 (1+ λVDS ) for VDS ≥ (VGS -VTN ) ≥ 0
2
EENG341 ELECTRONICS I 122
Transfer Characteristics & the Depletion-mode MOSFET
For the transfer characteristic we plot iDS vs VGS for a fixed VDS.
For the enhancement type NMOSFET the threshold voltage VTN is positive. However, it is
also possible to fabricate NMOSFETs with values of VTN≤0. These transistors are called
depletion-mode devices and has an structure as illustrated below:
An n-type channel is built-in using ion-implementation the source and drain are connected
through this resistive channel region. A negative VGS must be applied in order to deplete the
n-type channel region and quench the current path between the source and drain (hence the
name depletion-mode device).
Note that for VGS=0 IDS is
nonzero and a negative VGS is
needed to turn off this device.
EENG341 ELECTRONICS I 123
PMOS Transistors
This type of MOS transistor uses p-type channel (PMOS) The qualitative behaviour of MOS
is essentially the same as that of NMOS except that the normal voltage and current polarities
reserved. The normal directions of current in the PMOS transistor are depicted in the
following figure.
A negative voltage gate relative to the source (VGS<0) or VSG>0 is required to attract holes
and create a p-type inversion layer in the channel region. In order to initiate conduction in the
enhancement-mode PMOS transistor, the gate-source voltage must be more negative than the
threshold voltage of the p-channel device, denoted by VTP. To keep the source-substrate and
drain-substrate junctions reverse-biased, VSB and VDB must also be less than zero. This
requirement is satisfied by VSD≥0 (VDS≤0).
EENG341 ELECTRONICS I 124
Output Characteristics
The output characteristic for an enhancement-mode PMOS transistor is given below.
For VGS≥VTP=-1 (VSG ≤-VTP=+1) PMOS is off
PMOSFET Summary
For all regions :
Cutoff region:
W
iG=0 & iB=0
L
iSD=0, for VSG ≤ -VTP(VGS ≥VTP )
Kp=µpC"ox
Linear region:
iSD=Kp(VSG+VTP -
VSD
)VSD for VSG+VTP ≥VSD=0
2
Saturation region:
Kp
iSD= (VSG +VTP )2 (1+ λVSD ) for VSD ≥ (VSG +VTP ) ≥ 0
2
EENG341 ELECTRONICS I 125
For the enhancement-mode PMOSFET, VTP<0
For the depletion-mode PMOSFET, VTP ≥0.
In the PMOS device, the charge carries in the channel are holes, and so current is proportional
to hole mobility µp.Hole mobility is typically only 40% of the electron mobility, so far a given
set of voltage conditions, the PMOS device will conduct on 40% of the current of the NMOS
device.
MOSFET Circuit Symbols
NMOS enhancement-mode
NMOS depletion-mode
Three-terminal NMOS
PMOS enhancement-mode
PMOS depletion-mode
Three-terminal PMOS
EENG341 ELECTRONICS I 126
Biasing the MOSFET
We have found that the MOSFET operator is:
Cutoff,
Linear and
Saturation mode.
For circuit applications, we want to establish a well-defined quiescent operating points, or Qpoint, for the MOSFET in a particular mode of operations.
The Q-point for the MOSFET is represented by the dc values (IDS,VDS) that locate the
operating point on the MOSFET output characteristics.
For hand analysis and design of Q-points, we usually set λ=0.
Consider the following biasing circuit for the NMOSFET.
70kΩ
30kΩ
100kΩ
VTN = 1 V
K n = 25µ A / V 2
EENG341 ELECTRONICS I 127
A dc voltage source VGG is used to establish a fixed gate-source bias fort he MOSFET, and
source VDD supplies drain current to the NMOSFET through resistor RL.
We simplify the gate bias network by applying The’venin equivalent circuit:
100kΩ
VEQ =
R1
VGG
R1 + R2
& REQ =
R1 R2
= 21k Ω
R1+R2
=3V
KVL gives
VEQ =I G REQ +VGS
VDD =I D S RL +VDS
I G =0
VGS =VEQ =3V
To find the Q-point, we must assume a mode of operation. Assume that the MOSFET is
saturated.
EENG341 ELECTRONICS I 128
I DS
Kn
25 x10−6
2
=
(VGS − VTN ) =
(3 − 1) 2 = 50 µ A
2
2
And
VDS = VDD − I DS RL
=10-50x10 -6 x10 5 =5V
Check:
VGS -VTN =2
VDS exceeds (VGS-VTN) so that the MOSFET is saturated.
Q-point is (50µA,5V) with VGS=3 V.
Example: Electronic current source-current sink
Let VGS=3 V
EENG341 ELECTRONICS I 129
If VDD≥VGS-VTN=3-1=2 V, then the output current will be constant at 50µA.
Q.
A current source with IDC=25µA is indeed, and an NMOSFET is available with
Kn=25 µA/V2 and VTN=1V. What is the required value of VGS? What is the minimum value of
VDS needed for current source behavior?
[Ans: 2.41V, 1.41 V]
The fixed gate-source bias theoretically works fine but in practice VTN & Kn values are not
exactly known. Also, ambient conditions may affect component values. Therefore, in order to
have a stable Q-point we use four-resistor bias circuit as shown below:
R2 = 150k Ω
RD = 75k Ω
VTN = 1V
R1 = 100k Ω
Rs = 39k Ω
K n = 25µ A / V 2
The simplified equivalent circuit is obtained by applying The’venin to the gate:
EENG341 ELECTRONICS I 130
RD = 75k Ω
REQ = 60k Ω
VEQ = 4V
KVL gives the loop equations
EENG341 ELECTRONICS I 131
V EQ = I G R EQ + VGS + ( I G + I DS ) R s
V DD = I DS R D + V DS + ( I G + I DS ) Rs
But
IG = 0
V EQ = VG S + I D S R
s
V D D = I D S (R D + R s )V D S
A ssu m e sa tu ra tio n :
Kn
(V G S − V T N ) 2
2
P u t in V E Q :
I DS =
V EQ = VG S +
K n Rs
(V G S − V T N ) 2
2
V T N = 1 & K n = 2 5 x1 0 -6 A /V
2
2 5 x1 0 -6 x3 .9 x1 0 4
4 = VG S +
(V G S − 1) 2
2
S im p lifyin g w e h a ve
V G S 2 + 0 .0 5 V G S -7 .2 1 = 0
V G S = ± 2 .6 6 V
For VGS=-2,66 V MOSFET is cutoff (VGS<VTN)
EENG341 ELECTRONICS I 132
VGS=2,66 V
I DS
25 x10 −6
=
(2,66 − 1) 2 = 34, 4 µ A
2
10 = 34, 4 x10 −6 (75 x103 + 39 x103 ) + VDS
→ VDS = 6,08V
We have
VDS =6,08 V, VGS -VTN =1,66 V
VDS ≥ (VGS -VTN )
Q-point: (34.4, 6.08 V) with VGS =2.66 V
Example: Design a four-resistor bias network with VDD=10 V, VTN=1 V, Kn=25 µA/V2 for a
Q-point of (100 µA,6V)
Solution:
EENG341 ELECTRONICS I 133
VDD − VDS = I DS ( RD + Rs )
RD +Rs =
VDD -VDS
10 − 6
=
= 40 k Ω
100 x10 −6
I DS
But Rs can be obtained using
VEQ =VGS +I DS Rs
==>Rs =
VEQ -VGS
I DS
We need to find VGS first.
Using I DS =
Kn
(VGS -VTN )2
2
==> VGS =VTN +
2I DS
=1+
Kn
2x100
25
=3,83 V
Rs =
4-3,83
=1,7k Ω
100x10 -6
With this value of Rs , Vs is only 0.17 V which is small. Therefore, we increase VEQ 4 to 6 V.
Rs =
6 − 3,83
= 21,7 k Ω
−6
100 x10
&
RD =40-21,7=18,3k Ω
For VEQ=6V &
REQ=60kΩ
EENG341 ELECTRONICS I 134
We have R1=150 kΩ & R2=100 kΩ
Example: For the depletion mode MOSFET shown below, find the value of Rs required to
achieve IDS=100µA.
Solution: We must determine the value of VGS needed to establish the design value of IDS.
Assume saturation mode:
VGS
2 I DS
2 x100 x10−6
= VTN +
= −3 +
= −2V
−6
Kn
200 x10
Since I G = 0, the loop equation gives
VGS = - I DS Rs
==> Rs = -
Check:
VGS
−2
=−
= 20k Ω
−6
100 x10
I DS
EENG341 ELECTRONICS I 135
VDS = VDO − Vs = 10 − 2 = 8V
VGS − VTN = −2 − ( −3) = +1
Because VDS>(VGS-VTN) , saturation-mode assumption was correct, and Rs=20kΩ will set the
Q-point to
(100µA,8 V) with VGS=-2 V.
Example: Electronic voltage source.
This is illustrated using an n-channel depletion-mode MOSFET. The goal for the MOSFET is
to supply a constant output voltage even through the load current iL may change. We need to
calculate the output voltage VL and then the output resistance for the circuit.
EENG341 ELECTRONICS I 136
Solution: We first simplify the circuit using a Thevenin transformation of the gate-bias
network.
KVL to the input loop gives (iG=0):
5 = 73,000iG + VGS + VL
==> VL =5-VGS
iDS =iL =20mA
Assume saturation mode:
VGS =VTN +
2I DS
Kn
2(2x10 -2 )
=-5+
= 0V
−3
1,6 x10
VL =5V
EENG341 ELECTRONICS I 137
Check:
VGS − VTN = +5V
VDS = 12 − 5 = 7V
VDS > VGS − VTN
==> saturation - mod e
Thus, for a load current of 20 mA, this circuit produces and output voltage of 5 V.
Now let us investigate the behavior of the circuit for small changes in iL. The output
resistance of this circuit can be defined as
Ro =
VL = 5 − VGS = 5 − VTN −
∂VL
|Q − po int
∂iL
2iDS
Kn
(iL = iDS )
Ro =
=
1
2
1 (VGS -VTN )
|Q − po in t =
2 K niDS
2
I DS
1 5
= 125Ω
2 0,02
The final circuit is given below:
EENG341 ELECTRONICS I 138
The value of Ro is valid only for small changes in circuit near the Q-point. Ro is called
the small-signal output resistance of this circuit.
Note that VEQ=7,5 V, not 5 V, in order to account fort he voltage drop across Ro so
that VL=5 V when iL=20mA.
Example: Find the Q-point fort he PMOS device which is biased using two resistors and a
voltage source.
EENG341 ELECTRONICS I 139
The loop equations VSD & VSG give:
VSD =12 −105 ISD
VSG =VSD −106 IG
IG = 0, VSD = VSG.
Assume saturation mode :
100x10-6

VSG =12-10 
(VSG -2)2 
 2

5
==> VSG = 3.32 V, 0.58 V
Since VTP = -2 V , VSG = 0.58 V is not sufficient to turn on
the PMOSFET
VSG = 3.32V
ISD = 87.1µA & VSD = 3.29V
We see that VSD≈VSG. Also, VSG+VTP=1.29 V and VSD>VSG+VTP, so PMOSFET is saturated.
Q-point: (87.1µA, 3.29 V)
For VGS=VDS (or VSG=VSD), an enhancement-type device will always be in saturation.
EENG341 ELECTRONICS I 140
Example: Find the Q-point for the PMOSFET in the following circuit.
Solution:
VSG =4 V
Output loop equation gives
4 − VSD = 1600 I SD
Assume saturation-mode:
250x10 -6
2
I SD =
4
+
(
−
1)
[
] = 1.13mA
2
& VSD =2.19 V
Check:
VSG +VTP =4+(-1)=3V
VSG +VTP >VSD
[3 V>2.19 ]
assumption of saturation-mode is incorrect.
EENG341 ELECTRONICS I 141
Assume linear-mode:
VSD
)VSD
2
V 

==> 4 − VSD = 1600 x 250 x10−6  4 − 1 − SD  VSD
2 

==> VSD 2 -11VSD + 20 = 0
4 − VSD = 1600 K p (VSG + VTP −
VSD1 = 8.7 V
VSD 2 = 2.3 V
VSD1 = 8.7 V is not possible
VSD = 2.3 V
2.3 

I SD = 250 x10-6  4 -12.3

2 

= 1.06mA
Check :
VSG + VTP = 4 -1 = 3 V & VSG + VTP > VSD
and
Thus, the PMOSFET is operating in the linear-mode at the Q-point (1.06 mA, 2.3 V ).
EENG341 ELECTRONICS I 142
The Junction FET(JFET)
JFET can be found without the need for an insulating oxide by using pn junction as
shown below. It consists of a block of semiconductor material (n-type, or p-type) and two pn
junctions that from the gate.
In the n-channel JFET current enters the channel at the drain and exits from the source.
An applied voltage to the gate changes the width of the channel and thus, the resistance
becomes dependent on this voltage. This voltage-controlled resistance is given by
RCH =
ρ L
t W
Where p=resistivity channel region; L=channel length
W=channel width and t=depth of the channel diodes
Application of a reverse bias to the gate-channel diodes will cause the depletion layers to
widen, reducing W and decreasing current. Thus, the JFET is inherently a depletion-mode
devide, a voltage must be applied to the gate to turn off the device.
EENG341 ELECTRONICS I 143
The JFET Bias Applied
VGS is now negative and the
depletion layers have increased
in width, increasing the channel
resistance. W’<W. Because G-S
junction is reverse –biased ,iG=IS
and we can assume iG≈0.
When we apply more negative VGS
the conducting channel disappears.
The channel becomes pinched-off
and pn junctions merge at the centre
of the channel. VGS=Vp
RCH → ∞
VGS must not exceed the zener
breakdown voltage.
EENG341 ELECTRONICS I 144
JFET with Drain-Source Bias (VDS)
VGS is fixed for all cases.
For small values of VDS, the
resistive
channel
connects
drain and source, and JFET is
linear mode.
For larger values of VDS, the
depletion layer widens at the
drain and until the channel
pinches-off near the drain. At
pinch-off, we have
VGS-VDSP=Vp
VDSP=VGS-Vp
Once the JFET channel pinches
off, the drain current saturates.
Electrons are injected into the
depletion region and swept on
to the drain by the field. For an
even larger value of VDS the
pinch-off point moves to the
source and JFET suffers from
channel-length modulation.
EENG341 ELECTRONICS I 145
n-Channel JFET i-V Characteristics
The JFET is structurally different from MOSFET but the i-V characteristics are virtually
identical. For the JFET VTN is replaced by Vp.
For the saturation mode we have
Kn
(VGS − V p ) 2
2
Kn
VGS 2
2
=
( −V p ) (1 −
)
Vp
2
iDS =
or
iDS =I DSS (1 −
VGS 2
)
Vp
where
Kn 2
2I
Vp or K n = DSS
Vp 2
2
Typically , we have
-25 ≤ V p ≤ 0 V
I DSS =
and 10 -5 ≤ I DSS ≤ 100 A
With channel-length modulation Ids in pinch-off (saturation) becomes
iDS =I DSS (1-
VGS 2
) (1+λVDS )
Vp
for VDS ≥ VGS -V p ≥ 0
EENG341 ELECTRONICS I 146
For the linear mode of the JFET we have
iDS =
2 I DSS
VDS
(
V
−
V
−
)VDS
GS
p
2
Vp
2
for VGS ≥ V p & VDS ≤ VGS -V p
Transfer Characteristic
The transfer characteristic for a JFET operating in pinch-off is shown below:
IDSS is the current in the JFET for VGS=0 and represents the maximum current in the device
under normal operating conditions because the gate diode should be kept reverse-biased, with
VGS.
EENG341 ELECTRONICS I 147
Output Characteristics
The overall output characteristics for an n-channel JFET with λ=0 are given below:
The drain current decreases from a maximum of IDSS toward zero as VGS ranges from zero to
Vp.
EENG341 ELECTRONICS I 148
Circuit Symbols
The arrow identifies the polarity of the gate-channel diode. Source and drain are
determined by the voltages in the circuit in which the JFET is used. However, the arrow that
indicates the gate-channel junction is often to indicate the preferred source terminal of the
device.
JFET Summary
n-channel JFET
iG=0
Cutoff mode:
for VGS≤0 (Vp<0)
iDS=0
for
VGS≤Vp
Linear mode:
iDS =
2 I DSS
VDS
(
V
−
V
−
)VDS
GS
p
Vp 2
2
for VGS - V p ≥ VDS ≥ 0
EENG341 ELECTRONICS I 149
Saturation mode:
saturation mod e
iDS = I DSS (1 −
VGS 2
) (1 + λVDS )
Vp
for VDS ≥ VGS - V p ≥ 0
p − channel JFET
iG ≈ 0
for
VSG ≤ 0 (V p > 0)
Cutoff mod e :
iSD = 0
for VSG > V p
Linear mod e :
2 IDSS
VSD
iSD =
(VSG + Vp −
)VSD
Vp 2
2
for VSG + Vp ≥ VSD ≥ 0
saturation mod e :
V
iSD = I DSS (1 + SG ) 2 (1 + λVSD )
Vp
for VSD ≥ VSG + V p ≥ 0
EENG341 ELECTRONICS I 150
Small-Signal MODELS for FETs
The hybrid-pi small-signal model for the MOSFET is given below:
G
id
D
+
Vgs
ro
gmVgs
Vds
S
Where gm is the transconductance
gm =
∂ iD S
|Q
∂ VG S
po int
= K n (V G S − VT N )(1 + λ V D S )
I DS
2 ID
=
V G S − VT N
V G S − VT N
2
ro is the output resis tan ce
∂ iD S
K
1
=
|Q po int = λ n (V G S − VT N ) 2
ro
∂V DS
2
=
=
1
ro = λ
λ ID
ID
=
1
1 + λV D S
+ VDS
λ
+ V DS
I DS
A lso
µ f = g m ro
EENG341 ELECTRONICS I 151
T-Model
The MOSFET small-signal T-model is shown below:
Definition of Small-Signal Operation for the MOSFET
The limits of linear operation of the MOSFET can be explored using the simplified iDS with
λ=0:
iDS =
Kn
(VGS − VTN ) 2 for VDS ≥ VGS - VTN
2
U sin g
VGS = VGS + Vgs
&
iDS = I DS + ids
we have
iDS =
2
Kn
VGS + Vgs - VTN 
2
or
I DS + ids =
Kn
 (VGS − VTN ) 2 + 2Vgs (VGS − VTN ) + Vgs 2 
2
But
I DS =
Kn
(VGS − VTN ) 2
2
EENG341 ELECTRONICS I 152
ids =
Kn
 2Vgs (VGS − VTN ) + Vgs 2 
2
For this equation to be considered linear ids must be directly proportional to Vgs, which is
achieved for
Vgs 2 << 2Vgs (VGS − VTN )
Simplifying, we find that for small-signal operation of the MOSFET requires
Vgs << 2(VGS − VTN )
or
Vgs = 0.2(VGS − VTN )
A factor of 10 satisfies the inequality.
Because the MOSFET can easily be biased with (VGS-VTN) equal to several volts,
we see that it can handle much larger values of Vgs then the values of Vbe corresponding to
the BJT. This is another fundamental difference between the MOSFET and BJT and can be
very important in circuit design, particularly in RF amplifier design for example.
Small-signal models for the PMOS & JFET are identical to that of the NMOS.
EENG341 ELECTRONICS I 153
The Common-Source Amplifier
Now we can analyse the small-signal characteristics of the common-source (C-S) amplifier
shown below, which uses an enhancement-mode n-channel MOSFET in a four-resistor bias
network.