SOFTWARE DEFINED RADIO
BASED SPECTRUM ANALYZER WITH
HARDWARE ACCELERATION
TEAM DAEDALUS
GEORGE MASON UNIVERSITY
VOLGENAU SCHOOL OF ENGINEERING
SENIOR DESIGN PROJECT FALL 2015
Faculty Supervisors
Dr. Kris Gaj
Dr. Brian Mark
Additional Advisors
Malik Umar Sharif
Team Members
Richard Haeussler - PM
Daniel Barcklow – TM
Christopher Fortman
Joshua Herr
Commercial Spectrum Analyzer
•
•
•
•
Keysight N9343C
Fixed set of features
Total $16,901
Limits undergraduate
exposure
Antenna
User
Interface
2
Display: Amplitude vs. Frequency
Our Daedalus Spectrum Analyzer






70 MHz – 6 GHz
Large bandwidth
Near real-time performance
Touch screen interface
Potentially portable
Reprogrammable for
different applications
Target Price: under $1000
3
Functional Decomposition
4
Hardware Decomposition
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RF FRONT-END
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Sampling
Phase
No Phase
Benefits:
• Increases Bandwidth
• Demodulation
Source: National Instruments, http://www.ni.com/tutorial/4805/en/
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Analog Device’s RF-transceiver: AD9364
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Source: Analog Devices, AD9361 and AD9364
Source: Analog Devices, https://wiki.analog.com
PROCESSING SYSTEM
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Zynq-7000 All Programmable SoC
Processing System
• Dual-core ARM Cortex –A9
• Up to 1 GHz
Programmable Logic
• Allows for parallel processing
• 85K Logic Cells
• 4.9 Mb Block RAM
Our current utilization = 31%
Source: http://www.zynqbook.com/
10
10
Linux OS
Bare Metal
• Open source platform
• Simpler initial development
• More difficult future
development
• Less tested
• Does not fit well with our
goals
• User friendly
• Extensively tested
• Supports multiple
development
environments and
applications
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PROGRAMMABLE LOGIC
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Discrete Fourier Transform(DFT)
• Computationally Intensive O(𝑁 2 )
– FFT O(𝑁 log 𝑁 )
• Frequency Resolution
– Large N is desirable
• Xilinx DFT IP Core
Source: Oppenheim, Willsky, Nawab, “Signals and Systems”
Source: Xilinx DFT v4.0 LogiCORE IP Product Guide
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DFT Implementation Using Xilinx Vivado
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14
DFT Bit Packing
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15
Controller and Datapath
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Datapath
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17
Controller
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GNU RADIO
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Software Defined Radio (SDR)
• Hardware components implemented with software
• GNU Radio is an SDR development tool
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Source: National Instruments, http://www.ni.com/cms/images/devzone/tut/appframeworkusrprio.png
Source: GNU Radio http://gnuradio.org/redmine/projects/gnuradio/wiki
GNU Radio Companion
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GRAPHICAL
USER
INTERFACE
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GUI Development
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GQRX
PICTURE
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Compiling Software for OsmoSDR
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CHASSIS
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Chassis
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DEMONSTRATION
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https://youtu.be/Dzr6LCWmviM
TESTING
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Local Oscillator Testing
Frequency tone Successful
70MHz
✓
300MHz
✓
800MHz
✓
1.0GHz
✓
1.5GHz
✓
2.0GHz
✓
3.0GHz
✓
4.0GHz
✓
4.4GHz
✓
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Testing of the Daedalus DFT core
Input signal
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GNU Radio DFTconverter Output
Original
GNU Radio
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ADMINISTRATIVE
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Cost of Device
Component
Price
Status
AD-FMCOMMS4
$416.56 Purchased
ZedBoard*
$495.00 Donation from Xilinx
Antenna
$45.00 Purchased
Display
$134.95 Purchased
SD card
$15.00 Purchased
Chassis
$35.00 Printed
Total funds spent
$646.51 With Xilinx donation
With academic discount
$965.51
Total Cost
*Academic discount available
$1,141.51
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Man Hours Spent
Team member
Time in hours
Focus
Richard Haeussler
525
RF, GNU Radio
Daniel Barcklow
700
FPGA, GNU Radio
Christopher Fortman
550
GUI, GNU Radio
Joshua Herr
600
Linux, Chassis
Total Hours
2375
36
Breakdown of Man Hours
Focus Area
Percent of man hours
Research
40%
Zynq – Programmable Logic
15%
GQRX Development
13%
Linux
10%
GNU Radio
7%
Documentation & Reporting
5%
Chassis
5%
Testing
5%
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Technical Skills (Learned)
• Python, C, Matlab, C++, Octave, XML
• VHDL, Verilog
• Qt, CMake, Git, PyBombs, GNU Radio
• Linux Kernel Development
• Cross Compiling/embedded device development
• Xilinx Vivado, Xilinx SDK
• Networking
• DSP
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Special Thanks To
• Dr. Kris Gaj and Dr. Brian Mark
• Malik Umar Sharif
• Dr. Pachowicz
• ECE Department
• Xilinx for the donation
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COMMENTS/QUESTIONS?
We will be giving a live demo at the break!
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APPENDIX
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Vivado Testbench Result
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FFT: Software vs. Hardware
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Time (ms)
1
0.1
Software
0.01
Hardware
0.001
0.0001
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72
108
216
480
600
720
Transform Size (N)
960
1080
1200
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Programmable Logic
•
Allows for parallel processing
–
•
•
•
FFT
Offload operations from processor
Allows for higher sampling rates
More samples
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