1
Thyristor Based HVDC with Forced
Commutation
D. Jovcic, Member IEEE
Abstract—This paper presents a novel converter
configuration, based solely on conventional thyristors and aimed
for the use with High Voltage DC (HVDC) Transmission. The
converter utilizes resonant turn off and forced commutation with
auxiliary thyristors to aid commutation in the converter switches.
The PSCAD/EMTDC simulation confirms that the HVDC
inverter is capable of operating with a wide range of firing
angles, including operation with reactive power export. Further
simulation proves that the system is immune to commutation
failure even in the case of most severe close single-phase faults.
The harmonic generation is comparable to the conventional
converter and also the thyristor voltage stress is not significantly
increased. The auxiliary thyristors do increase costs, but this is
offset by the elimination of reactive power support and the
improvements in performance.
Index Terms— HVDC transmission, HVDC converters,
commutated circuits, reactive power.
I. INTRODUCTION
HVDC has found many applications in countries worldwide
since the first installation in 1954. There are however well
known limitations that have hampered further proliferation of
conventional HVDC transmission [1]:
• The need for reactive power support and in particular
variable reactive support which increases costs.
• Even modest (around 10%) voltage decrease at the
inverter AC terminals will cause commutation failure.
Commutation failure causes a short-circuit on DC
voltage and thus power transfer is interrupted.
• The inability to operate with weak inverter AC systems,
which is indirectly caused by poor control capabilities
at the inverter side and the above two issues.
Recently, HVDC transmission based on Voltage Source
Converters has been introduced and some medium-power
systems have been installed [2]. VSC Transmission has none
of the above issues with conventional HVDC, however other
notable limitations are present:
• The rating of the converters is limited, presently to
around 360MW.
• The losses are noticeably higher than with conventional
HVDC, caused primarily by the increased switching
losses.
• The cost of this technology is high.
In parallel with the developments in VSC transmission,
there has been a stream of research on improving
D. Jovcic is with Department of Engineering, University of Aberdeen,
Aberdeen, AB24 3UE, UK d.jovcic@abdn.ac.uk
conventional, thyristor based, HVDC. In particular the concept
of Capacitor Commutated Converters (CCC) has shown
promising results [3-7]. The researchers in [3] have concluded
that only series capacitor configuration might be of practical
importance for improving commutation in HVDC converters.
The CCC technology was further investigated and improved in
a series of projects [4-7] and recently it has been installed in a
practical back-to-back HVDC at Garabi station Brasil. [8].
The CCC concept offers HVDC converters that could operate
at an improved power factor and with reduced commutation
failure probability. However the following issues with CCC
HVDC have been identified:
• The occurrence of ferromagnetic resonance [7].
Research shows that this can be resolved using thyristor
controlled capacitors or advanced feedback control
[5,7], but at the increased costs.
• Typically CCC achieves around 10-15% reactive power
consumption. In order to operate with a leading power
factor, and to completely eliminate commutation
failure, very large series capacitors would be needed.
This increases voltage stress, harmonics and costs.
• The increased voltage stress on thyristors, which can be
2 p.u. or even 3p.u with very large capacitors,
• The insulation of series commutating capacitors,
• The harmonic generation is somewhat increased, and in
particular DC harmonics are significantly larger.
It is clear that there is incentive and the scope for further
development of HVDC transmission and that the potential
benefits are significant. Ideally, the research on HVDC
converters would improve HVDC technology:
• To operate at higher firing angles enabling reactive
power export,
• To eliminate commutation failure issues, if possible
including most severe single-phase faults,
• Not to significantly increase harmonic pollution, or
thyristor voltage stress or costs.
In this paper, a new HVDC converter that potentially meets
the above goals is studied. The concept is based on combining
forced commutation and the resonant turn off methods. The
basic principles of these techniques are known since they have
been used with some low power DC-DC choppers [9-11],
although such techniques have not been employed in high
power, three-phase circuits. The paper will further give
detailed analysis of operation and the method of calculating
optimum parameters. A wide range of PSCAD/EMTDC
simulation results will be presented to evaluate performance of
the new scheme in terms of: reactive power exchange,
commutation failure resilience, harmonic generation and
stability aspects.
2
II. CIRCUIT DESCRIPTION
Figure 1 shows the proposed converter and the AC system
at the inverter side of an HVDC. There are two six-pulse
bridges in Y and ∆ transformer connections. Thyristors TY1TY6 and T∆1-T∆6 are the main thyristors in the conventional
Graetz connection. Each main thyristor has one auxiliary
thyristor to aid commutation (TY1a-TY6a and T∆1a-T∆6a).
There are also three commutating capacitors Cc and a single
resonant capacitor Cs (per 6-pulse bridge).
The complete HVDC test system is based on the CIGRE
HVDC Benchmark model and all parameters can be found in
[12]. This is a monopolar 12-pulse HVDC system with
1000MW, 500kV, 2000A rating, and with weak AC systems at
both ends. It is desired to keep the test systems as close as
possible to the original CIGRE model, to enable comparisons.
Some minor modifications are made, however. Since the new
converters enable zero reactive power exchange, implying
higher AC voltage, the reactive power support capacitors are
removed, and also the transformer ratio is changed. In this
way the same DC voltage level is achieved, the same power
transfer and with a similar AC voltage level. The remaining
circuit including the filters is identical to that in CIGRE
Benchmark model. The switchable load zload is added in some
tests to simulate large disturbances.
All the standard labeling for HVDC variables is used [1].
lower implying less heating and losses [9,10]. This method has
not been used in high power applications primarily because
large oscillations (resonant conditions) would not be
acceptable to the components. However, with 12-pulse HVDC
the 6-pulse bridge oscillation may be induced in such way to
enable cancellation between Y and ∆ groups.
With HVDC converters each thyristor conducts for 120deg
intervals, once per cycle. In order to have the minimum
current at the end of each thyristor conduction interval, the
frequency of the oscillations fc should be triple multiple of the
fundamental frequency. Considering further an oscillatory
circuit on any phase, where two thyristors are involved, the
condition for frequency of oscillations is:
(1)
fc = n × 6 × f , f = 50 Hz , n = 1,2,...
The second condition is that the oscillations mutually
cancel in a 12-pulse configuration. Since the Y and ∆ thyristor
groups are displaced by 30deg, their oscillations could be
cancelled if half the period is a multiple of (1/f)2π/12. This
condition is same as that that in (1) and therefore the final
formula for frequency in the resonant circuit is (1).
The resonant condition is created on each 6-pulse bridge
between the transformer impedance Ltr and the resonant
capacitors Cs. The value for the capacitance is calculated from
the resonant frequency for a LC circuit:
III. RESONANT TURN-OFF FOR HVDC
Some converters in low power applications use resonant
turn-of principle to enable low currents and voltages at
switching instants. As a result, thyristor switching stresses are
Idc Ls
VTY
Vdc
TY2
2
TY2a
Cs
Vd1
ITY2a
Icc Cc
VCc
ITY2
TY6
TY3
TY5
TY3a
a
b
c
TY1
T∆6
T∆5a
Vc
T∆4
T∆4a
Cc
T∆3
T∆3a
Y ∆
fault
a
b
c
Cc
T∆5
Ltr
TY1a
T∆6a
Cc
T∆2a
(2)
TY4
TY4a
Cc
TY6a
Cc
T∆2
Cs
1
2
Ltr (2πf c )
Ic
TY5a
Vd2
Cs =
T∆1
a bc
Ltr
∆ ∆
Vacinv
Pinv,
Qinv
CBl
zf
zload
T∆1a
zinv
Figure 1. The proposed inverter converters and the AC system configuration.
Pload, Qload
Current [kA]
4.00
3.00
2.00
1.00
0.00
-1.00
-2.00
-3.00
-4.00
0.004
IT4
ICc
IDC
IT1
IC
0.009
0.014
0.019
0.029
0.034
0.039
0.044
Vdc
600
Voltage [kV]
0.024
Time [s]
a) Currents
400
200
0
-200
-400
0.004
VCc
0.009
0.014
0.019
Vd2
Vd1
0.024
time [s]
0.029
0.034
0.039
0.044
b) Voltages
Figure 2. The resonant turn off principle. A) DC and valve side AC Currents,
b) DC voltages and commutating capacitor voltages.
3.0
190
THD
2.5
Alpha inv
2.0
1.5
1.0
180
170
THD
Conventional Inv.
Commutation
failure
160
Commutation
failure
0.5
150
Alpha [deg]
Assuming that n=1, and using the transformer impedance
value Xtr=18%, (Ltr=0.0512H) as given in the PSCAD
tutorial model, the capacitance is calculated as Cs=5.5µF.
This is a theoretical value assuming ideal LC resonant circuit.
By observing the harmonic level during PSCAD simulations,
it was found that the best value is lower, around Cs=4.5µF.
Note that the resonant circuit is also affected by impedance of
the inverter AC system and other parameters, but this
influence is not significant, as it will be shown in the
simulation section. A remark is also made that there is no
benefit in selecting larger n in (1), since at larger frequencies
the oscillations are more attenuated and the current minima are
higher. Higher switching current implies higher harmonics.
Figure 2 shows traces of the variables (PSCAD simulation)
in the resonant circuit. In Figure 2a) we see that the AC
current has two full cycles in each 120deg interval and it is at
its minimum (almost zero) at the instant of commutation. The
DC current has no oscillations because of the Y-∆
cancellation. In Figure 2b) it is observed that each 6-pulse
group has large oscillations on the DC voltage but the main
DC voltage is unaffected by these oscillations and the profile
is similar to the conventional inverter circuit. This is important
conclusion since DC cable insulation is normally vulnerable to
AC currents. It should be noted that the simulation in Figure 2
uses the final circuit, i.e. it also includes the forced
commutation circuit presented in Section IV (hence distortion
at the end of conduction).
Figure 3 shows the benefits of the resonant turn-off circuit
by comparing with the conventional inverter. In this figure, the
inverter firing angle (α) is gradually increased from 145deg to
180deg. With the conventional inverter the commutation
failure occurs below 150deg because of the large commutation
overlap and the lack of sufficient commutation margin. With
the resonant circuit, better responses are observed. As a
consequence of smaller thyristor switching currents, the
commutation overlap is smaller, and smaller commutation
margin can be allowed. The commutation failure occurs at
larger angles, close to 180deg.
Harmonics [% of fund]
3
140
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Figure 3. Variation in THD, Gamma and Inverter power as Alpha at inverter
increases. Case with only resonant capacitors.
Note that these results are applicable only at steady state,
and because of the presence of disturbances in the actual
circuit much larger practical margins should be allowed. As
seen in Figure 3, the Total Harmonic Distortion (THD) on the
AC voltage is somewhat increased with the resonant circuit.
Since the resonant circuit gives only limited improvement
in performance, an additional forced commutation circuit is
included.
IV. FORCED COMMUTATION
A. Principles of operation
There are a number of forced commutation circuits for
conventional thyristors [9,11]. In practice they have been
primarily used at very low-power, low-cost circuits and with
DC-DC converters. The main issue with forced commutation
is the cost of additional thyristors and the increase in harmonic
pollution. Nevertheless, with HVDC applications, the
additional cost might be offset by the savings in the reactive
power supply and significant improvement in the performance
like stability and the resilience to commutation failures.
The forced commutation circuit shown in Figure 1 is found
to be most suitable for HVDC applications. The principle of
operation is explained with reference to Figure 4, and
considering the commutation from valve TY2 to TY4. Figure
4a) shows the circuit configuration at the instant of ending
TY2 conduction and closing TY2a. Prior to this commutation
it is assumed that the commutating capacitor Cc is charged to
the polarity as shown. At the same instant of firing T4, the
auxiliary thyristor TY2a is also fired and this brings the Vcc
across the thyristor TY2, implying that cathode of TY2
becomes positive. Since the capacitor Cc brings the highest
positive voltage at phase c, the capacitor will take over the
load current. Consequently, current through TY2 reduces to
zero and assuming that it stays zero for at least the interval
equal to the extinction period, thyristor TY2 regains blocking
state. In a short time capacitor Cc changes polarity, reducing
the capacitor current. At this stage, Thyristor TY4 takes over
the load current and commutation is complete. At the end of
commutation, capacitor Cc is charged to the reverse polarity
as shown in Figure 4b). It is now ready to assist commutation
of thyristor TY5. The instant of turning off TY5 (i.e starting of
conduction in TY1) is shown in Figure 4b).
Figure 5 shows the firing sequence for the main thyristors
4
Idc
Ls
+
Ls
TY2
TY2
TY2a
TY2a
Cs
Vd1
-
Ic
Cc
+
Cs
+
Vd1
c
Cc
Ic
-
c
TY5a TY5
TY5a TY5
-
a) Circuit at the instant of
closing TY2a
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
-0.50
0.0200
a) currents
Current [kA]
+
b) Circuit at the instant of
closing TY5a
Figure 4. The forced commutation. a) Switching TY2a to turn off TY2, b)
Switching TY5a to turn off TY5.
Voltage [kV]
Idc
500
400
300
200
100
0
-100
-200
-300
0.0200
IT2
Ic=ICc
TY5a
Phase C
TY1
Phase A
0
60
TY3
TY6a
TY6
Phase B
TY2a
TY2
120
TY1a
ICc
180
240
TY3a
300
TY4 firing
TY2 turn off
0.0205
IT4
TY2a turn off
0.0210
0.0215
0.0220
0.0225
0.0230
Vd2
Vd1
VT2
Vc
VCc
0.0205
0.0210
0.0215
0.0220
0.0225
0.0230
time [s]
Figure 6. Forced commutation between TY2 and TY4, a) corresponding
currents, b) corresponding voltages.
TY5
TY4
IDC
TY2a firing
b) Voltages
Gate
pulses
Ic=IT2
TY4a
360
ωt [deg]
Figure 5 Firing sequence for the main and the auxiliary thyristors.
and the auxiliary thyristors. The conduction intervals for the
main thyristors are shown shaded. The pulses for the auxiliary
thyristors are supplied at the firing instant of the next thyristor
on the same half bridge. The auxiliary thyristors conduct for
short periods, usually 10-15deg.
Figure 6 shows the actual currents and voltages during the
commutation from TY2 to TY4. In Figure 6a) it is seen that
the current in the outgoing thyristor TY2 is rapidly brought to
zero when the auxiliary thyristor TY2a fires. This implies that
there is no commutation overlap in the proposed converter.
Note that commutation overlap in conventional converters is
usually 15-25deg [1], which deteriorates power factor.
It is also seen in Figure 6a) and 2a) that the current in the
auxiliary thyristors is small, and the RMS value is calculated
to around 12% of the RMS current of the main thyristors.
Considering that the voltage across the commutating thyristors
is similar to the main thyristors, the commutating thyristors
will have below 1/8 of the power rating of main thyristors.
In Figure 6b) we observe that the voltage across the main
thyristors (Vt2) reverses during the commutation, as the result
of the connection of commutating capacitors, and this enables
thyristor turn-off. The additional benefit is that this reverse
voltage will also accelerate regrouping of charges on p-n
junction and it will shorten the thyristor extinction time [9,10].
To appreciate the benefit of the proposed converter, it is
emphasized that the commutating capacitors are charged from
the DC voltage. If the DC voltage is at a required level, the
capacitors Cc will be charged enabling commutation of the
main thyristors, regardless of the actual AC voltage levels.
The commutating voltage is therefore provided from the DC
side, rather than from the AC side as in conventional inverters.
This is very important for HVDC applications since DC faults
are rare, whereas AC faults more frequent.
B. Sizing of commutating capacitors
The size of the commutating capacitors Cc is determined
considering the required performance. Theoretically,
commutating capacitors should be large enough to store
energy required to sustain the load current for the interval
larger than the extinction time of thyristors Te. As seen in
Figure 2b), the voltage on commutating capacitors changes
polarity at each commutation, but only the first half of the
voltage change interval enables reverse voltage across main
thyristors. A simplified calculation for the capacitor is [11]:
Cc
dVcc
= icc dt
dt
Cc =
t2
1
i dt
∫
t
(Vcc 2 − Vcc1 ) 1 cc
(3)
(4)
where the capacitor voltage changes from Vcc1 to Vcc2, in the
interval t2-t1 assuming the capacitor current is icc. The time
interval for capacitor voltage reversal is:
t 2 − t1 = 2(Te + Tm )
(5)
where Te is the extinction time, and Tm is the commutating
margin in seconds. The extinction time for high-power
thyristors varies widely with the power rating, the circuit
conditions, the manufacturer and type, and in general it is
between few tens of microseconds and several hundreds of
microseconds [10]. Since the forced commutation introduces
fast voltage reversal across thyristors, the extinction time will
be smaller than with conventional inverters and it is initially
taken as Te=200µs. The additional margin for safe
commutation Tm, is required to enable thyristors achieving
blocking state even under disturbances when current might
increases or DC voltages reduces, and simulation tests indicate
5
that around 1-1.5deg is adequate. This is significant
improvement since in conventional inverters the commutation
margin is usually over 10deg. The total interval for the voltage
Vcc reversal is therefore taken as (t2-t1)=500µs. The change in
capacitor voltage is close to twice the 6-pulse bridge DC
voltage, and it can be taken as approximately (Vcc2Vcc1)=400kV.
The capacitor current ICc is assumed as:
I Cc = I m + I o sin(6ω o t ),
(6)
where: Io=1.7kA - the peak current, Im=2kA – the DC current,
ωo=314.15rad/s, - the fundamental frequency. Replacing (6)
in (4) we obtain the formula for capacitor Cc:
2π


I o cos(π − (t2 − t1 )
) − cos(π )
1
/
300
 + I m (t2 − t1 ) (7)
Cc = − 
∆V 6ω0
∆V
but the following design aspects reduce harmonics:
• The proposed converter operates at firing angles closer
to 180deg where the harmonic generation is lowest
because of small difference between phase voltages.
Conventional inverters operate around 140deg.
• There is no commutation overlap because of the fast
turn-off of the thyristors. Conventional inverters have
commutation overlap of 15-25deg, which deteriorate
voltage profile.
Analysing the results in Figure 7, the system with
Cc=4.0µF is selected as the base model for all further tests,
since it has good overall performance. With this system the
maximum extinction time should be below 200µs to enable
operation without commutation failure under most sever
faults. The system is capable of operating at high firing angles
corresponding to around 500MVar reactive power export.
THD
Extinction time
The required capacitor value is initially calculated as
Cc=3.4µF. The final value for the capacitance Cc is
determined using simulation testing.
By reducing the value of commutating capacitors the
harmonics are reduced, but too low value would jeopardize
safe commutation during faults. A series of test is performed
by varying the capacitor Cc size and considering a range of
values for the extinction time (50<Te<300µs). The following
observations are made:
• The harmonic level on AC and DC voltage (individual
harmonics and total harmonic distortion (THD))
• The incidence of commutation failure during single and
three-phase faults, and current step changes.
In the commutation failure tests, the value of the inverter
firing angle is limited to 190deg and the most severe zeroimpedance single-phase faults at the inverter terminal are
applied. The capacitor value that enables operation without
commutation failure is recorded. The summary of these results
is shown in Figure 7. The test results show that, as an
example, selecting Cc=4.0µF, the converter can operate with
no commutation failure if the thyristor extinction time is
200µs. Note that this system would be able to operate with
larger extinction angles at steady-state but the commutation
failure would occur if the voltage on a single phase drops to
some low values. The Figure also shows the THD level
assuming operation at zero reactive power exchange. It is seen
that total harmonic level is higher but it is of the same order of
magnitude as with equivalent conventional inverter.
Table 1 specifies further the values of individual harmonics.
We can conclude that the filtering costs would not be
significantly increased. Furthermore, the DC side harmonics
are lower because of the additional capacitors. The overall
harmonic generation would be similar or better than with CCC
HVDC.
The low THD level might be surprising considering the
additional “spikes” introduced by the commutating thyristors,
THD conventional inverter
Figure 7. The AC voltage total harmonic distortion [THD] and the maximum
extinction time as the function of the commutating capacitance.
TABLE 1. INDIVIDUAL HARMONICS AS THE FUNCTION OF COMMUTATING
CAPACITOR SIZE.
Harm. [%]
0.22µ
µF 1.2µ
µF
4µ
µF
10µ
µF
5th AC side
7th AC side
11th AC side
13th AC side
THD AC volt
6th DC side
12th DC side
0.13
0.07
0.55
0.69
1.0
0.1
1.13
0.07
0.03
0.8
1.32
1.47
0.04
2.44
0.07
0.03
1.33
0.94
1.29
0.04
1.46
0.07
0.03
1.32
1.2
1.51
0.04
1.61
Conv.
Invert.
0.027
0.014
0.89
0.61
0.97
0.05
3.00
C. The operating parameters
The results for the harmonic level in Figure 7 are obtained
by assuming steady-state operation at around neutral reactive
power exchange. As with conventional converters, the
harmonic level will change as the operating point changes. In
Figure 8, the inverter firing angle is increased in the interval
155-190deg, while keeping the inverter AC voltage constant
(an AVR is used at the AC source). The operating point at
approximately 2.65s (with around 165deg angle) corresponds
to the results in Figure 7. Note that the neutral reactive power
exchange is achieved at around 165deg since the series
connected commutating capacitors contribute to the additional
reactive power generation. Also, over 500Mvar is exported at
190deg as seen in Figure 8b.
We observe in Figure 8a) that the harmonics are minimal
around 165deg and they increase with the increase or decrease
of the firing angle. As an example if 300MVar is exported the
harmonic level would be 3 times that with conventional
inverter. It is presumed that such system would be normally
6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
12thDC
Alpha inv
13th
THD
11th
5th
1.2
1.7
2.2
2.7
7th
3.2
3.7
190
185
180
175
170
165
160
155
150
Alpha [deg]
Harmonics [% of fund]
operated around neutral reactive power exchange and only
transient variations in a certain firing angle range would be
allowed.
If a permanent operation at a wide range of firing angles is
adopted, filtering would be more demanding and
adaptive/active filtering might be needed. The system already
has a set of filters and therefore the results serve for relative
comparison with conventional inverters.
Note also that the DC voltage level follows the cos(α)
relationship and therefore the active power reduces on either
side of the 180deg operating point, as seen in Figure 8b).
4.2
Power [MW], [MVar]
a) Harmonic level and inverter firing angle
400
200
0
-200
-400
-600
-800
-1000
Q-inv
reactive power regulation, although this is not common in
HVDC.
The proposed inverter controller structure is shown in
Figure 9, where the gains are obtained using model in [13] and
they are given in the Appendix. The controller consists of two
independent units: the low-gain AC voltage PI controller and
the fast stabilizing feedback loop. The stabilizing feedback
loop is based on the AC current angle feedback, since this
signal was found to be most beneficial in improving stability
of HVDC systems [14]. Assuming that the AC voltage is close
to the nominal value such system will operate with the inverter
firing angle around 165deg. During fast disturbance the
stabilizing controller (which has high gain) will have
dominant influence. If the AC voltage changes, the slowacting AC voltage PI controller will modify the firing angle
thus changing the reactive power injection in order to return
the voltage to nominal level.
TABLE 2 LOCATION OF DOMINANT EIGENVALUES
Conventional inverter
-38.6±433.7j
-190.6±633.4j
-109.3±217.5j
-19.6±9.5j
-12.9
-8.1
With forced commutation
-32±435.2j
-184.4±632j
-69.7±215.1j
-3.96±5.18j
-4.86±4.67j
Vacinvref
Vacinv
P-inv
1.2
b) Inverter power
1.7
2.2
2.7
3.2
3.7
4.2
Time [s]
Figure 8. Variation in harmonics level and power with the increase in inverter
alpha 160-190deg.
V. DYNAMIC STUDY
The proposed inverter includes the resonant capacitors Cs,
and also the commutating capacitors Cc, that influence
dynamics at the system level. Also, there is no commutation
overlap, implying very low commutating resistance Rc=6fLtr
[1], which is assumed zero. A reduction in the commutating
resistance has negative influence on the stability [1,14]. The
inverter controller gain also changes because of the different
operating point. On the positive side, the proposed converter
has no commutation failure issues, therefore the inverter firing
angle can be varied in a wide range, and this implies
possibility for versatile large-gain inverter feedback control.
The HVDC-HVAC, MATLAB-based, small-signal
analytical model [13] is used to study stability of the proposed
converter. A simplified model is developed assuming that only
the DC side capacitance and the commutating reactance is
changing. Table 1 shows the location of most dominant
eigenvalues, assuming constant firing angle operation (no
active control) at the inverter converter. It is seen that with
forced commutation the eigenvalue real parts are smaller, and
stability is slightly degraded as expected.
The system stability can be improved if a feedback
controller at the inverter side is used, like AC voltage or
+
1/(Tis+1)
Θaci
-
kv
Kvi/s
+
+
+
1/(Tis+1)
Θaci - AC current angle
ka
194
αinv
145
Stabilising feedback
loop
Figure 9. Inverter controller.
VI. SIMULATION RESULTS
This section presents the PSCAD/EMTDC simulation of
HVDC with the proposed converter circuit. The extinction
time for all thyristors is set to 200µs, and a low simulation step
(10µs) is used to improve accuracy.
Figure 10 shows the electrical and control variables
following a 0.05s zero-impedance single phase fault at the
inverter terminal. Phase A voltage reduces to zero during the
fault, but as it is seen in Figure 10c) DC voltage remains
positive and there is no commutation failure. For comparison,
the conventional converter response is also shown, and it is
evident that commutation failure is present because of the
short circuit on the DC voltage. The extinction angle shows
transient dip but it returns to the nominal value of around 5deg
as seen in Figure 10b). Figure 10d) shows the power, where it
is evident that the new converter shows much better power
delivery during the fault.
Figure 11 shows simulation of a 0.1s three-phase lowimpedance fault at the inverter terminal. It is evident that there
is no commutation failure and that the responses are much
better than with the conventional converter.
The simulation with a weak AC system, in Figure 12, is
also given since HVDC normally have difficulties when
inverter AC system has low Short Circuit Ratio (SCR) (say
7
200
100
0
0.25
200
Inverter firing angle
5
190
Gamma Y
4
180
3
170
2
160
1
Alpha [deg]
Gamma [deg]
6
0.30
-150
0
140
0.1
0.2
0.3
b) Inverter Gamma and Alpha
600
0.4
0.5
3.0
Vdc
500
2.5
400
2.0
Idc
300
1.5
200
1.0
100
0.5
Vdc - Conventional Inv.
0
0.0
0.0
0.100
0.1
0.2
0.3
c) DC voltage and DC current
300
100
-100
-300
-500
-700
-900
-1100
0.4
0.5
Q inv
P - Inv Conventional Inv.
0.200
0.2
0.3
0.4
0.5
time [s]
Figure 10. System response after a 0.05s zero impedance single-phase fault at
inverter AC terminal.
0.300
Vdc
400
300
200
100
Vdc - Conventional Inv.
b) DC voltage
300
100
-100
-300
Q inv
P inv Conventional Inv.
-500
-700
P inv
-900
-1100
0.050 0.150 0.250 0.350 0.450 0.550 0.650
c) Power
300
280
260
240
220
200
180
160
140
120
0.05
Vacinv
Vacinv Conventional Inv
Alpha inv
0.15
d) Inverter AC voltage
0.1
0.250
500
P inv
0.0
0.150
0
0.050 0.150 0.250 0.350 0.450 0.550 0.650
150
Gamma D
0.0
DC Voltage [kV]
0.20
Power [MW, MVAr]
0.15
AC Voltage [kV]
0.10
a) AC voltages
DC Voltage [kV]
-50
600
-300
0.05
Power [MW, MVAr]
50
a) AC voltages
-200
d) Power
150
-250
0.050
-100
DC current [kA]
Voltage [kV]
300
Vinva
Vinvb
Vinvc
250
0.25
0.35
0.45
0.55
200
190
180
170
160
150
140
130
120
aplpha [deg]
Vinva
Vinvb
Vinvc
In this Figure the capability of fast regulation of AC voltage
using HVDC converters is also demonstrated. In this aspect,
the proposed concept can be compared with VSC based
HVDC transmission.
To enable full comparison with the conventional converters,
the voltage across main thyristors during steady-state
operation is analysed as shown in Figure 13. It is evident that
there is only 30-40% increase in the peak forward blocking
level. Contrasting further this converter against conventional
inverters it is mentioned that reliability is degraded because of
the increased number of components.
Voltage [kV]
SCR<2) [1]. The inverter AC impedance (zac in Figure 1) is
modified to represent a circuit with SCR=1.2, at 75deg. The
considered system is therefore extremely weak, at the margin
of AC transfer capability, and an HVDC with conventional
converters would not be able to maintain stable operation. At
0.1s an additional large load (400MW, 200MVAR) is
connected to the inverter AC bus (as shown in Figure 1).
Finally at 0.9s a low-impedance single phase fault is applied.
The purpose of this test is to demonstrate that the AC circuit
parameter changes can not affect the proposed converter to a
degree that jeopardize stable operation. Note that minimal
change in the resonant circuit frequency does occur but the
normal operation is maintained. It is concluded that the
proposed converter is suitable for very weak AC systems and
that complete resilience to commutation failure is maintained.
0.65
time [s]
Figure 11. System response after a 0.1s low impedance three-phase fault at
inverter AC terminal.
Power [MW, MVAr]
8
500
300
100
-100
-300
-500
-700
-900
-1100
significant cost savings are also introduced because of the
elimination of reactive power support, downsizing of
converter transformers and the much-improved performance.
P load
Q load
Q inv
VIII. REFERENCES
[1]
[2]
P inv
[3]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
280
260
240
220
200
180
160
140
200
190
180
170
160
150
140
130
Vacinv
Alpha inv
0.0
0.2
0.4
b) AC voltage and Inverter alpha
0.6
0.8
1.0
1.2
[4]
aplpha [deg]
AC Voltage [kV]
a) Inverter power and load power
1.4
[6]
Time [s]
Figure 12. Simulation results with very weak inverter AC system (SCR=1.2).
At 0.1s, a 400MW, 200MVAr load, is connected, and at 0.9s there is a zero
impedance single phase fault.
Voltage [kV]
[5]
500
Vt2
400
300 Vt2c - conventional
200
100
0
-100
-200
0.000
0.010
0.020
Switch on Vt2c
[7]
[8]
[9]
[10]
[11]
Switch on Vt2
0.030
0.040
[12]
[13]
Time [s]
[14]
Figure 13. Comparison of voltage stress across main thyristors.
VII. CONCLUSIONS
This paper proposes a converter for HVDC systems, which
is based solely on conventional thyristors, and is capable of
operating with firing angles that provide leading power factor.
It enables HVDC to have wide range of reactive power
exchange in exporting and importing region. For the minimal
harmonic generation the operating point should be linked with
the neutral reactive power exchange, which is close to 165deg
in the proposed circuit. The HVDC system with such
converters will have approximately 50% increased harmonic
content and slightly increased thyristor voltage stress
compared with conventional converters.
The PSCAD/EMTDC simulation with 200µs thyristor
extinction time is used to test the proposed converter. The
results demonstrate that even for zero impedance single-phase
faults at the inverter AC bus, commutation failure will not
occur. The tests with very weak AC systems confirm good
operation and unchanged resilience to communication failure.
Considering the auxiliary thyristors and capacitors, the
proposed converter will have higher costs and reduced
reliability compared with conventional converters. However
P. Kundur: “Power System Stability and Control” McGraw Hill. 1994.
Kjell Ericsson "Operational Experience of HVDC Light" Seventh
International Conference on AC-DC Power Transmission IEE. 2001,
pp.119-24. London, UK
J. Reeve, J.A. Baron, G.A. Hanley, “Technical assessment of Artificial
Commutation of HVDC Converters With Series Capacitors” IEEE
Transactions on Power Apparatus and Systems Vol 8 no 10 October
1968, pp 1830-1840
M.Meisingset, A.M. Gole, “A Comparison of Conventional and
Capacitor Commutated Converters Based on Steady State and
Dynamic Considerations” Proceedings, IEE 7th conference on AC-DC
transmission, London November 2001, pp49-54
Sadek, K.; Pereira, M.; Brandt, D.P.; Gole, A.M.; Daneshpooy, A.
“Capacitor commutated converter circuit configurations for DC
transmission”
IEEE
Transactions
on
Power
Delivery,
Vol. 13 (4) Oct 1998 Pp: 1257-1264
Gomes, S., Jr.; Martins, N.; Jonsson, T.; Menzies, D.; Ljungqvist, R
“Modeling capacitor commutated converters in power system stability
studies” IEEE Transactions on Power Systems, Volume 17 (2) May
2002, Pp 371-377
D.A. Woodfford, “Solving the Feroresonnace problem When
Compensating a DC converter Station with a Series capacitor” IEEE
transactions on Power systems, Vol 11, no 3, pp 1325-1331.
N Ottosson, L Kjellin, Modular back-to-back HVDC with capacitor
Commutated converters (CCC) IEE 7th conference on AC-DC
transmission, London November 2001, pp55-59
C. Lander “Power Electronics” McGraw Hill, 1987
N. Mohan, T. M. Undeland, W. P. Robbins “Power Electronics
Converters, Applications and Design,” John Wiley & Sons, 1995
R.M.Davies, J.R.Melling, “Quantitative Comparison of Commutation
circuits for bridge inverters” Proceedings of IEE, Vol 124 (3) 1977, pp
237-246.
M. Szechman, T. Wess and C.V. Thio, April 1991, "First Benchmark
model for HVDC control studies", CIGRE WG 14.02 Electra No. 135,
pages: 54-73.
D. Jovcic N. Pahalawaththa, M. Zavahir “Analytical Modelling of
HVDC-HVAC Systems.” IEEE Trans. on PD, Vol. 14, No 2, pp. 506511, April 1999
D.Jovcic N.Pahalawaththa, M.Zavahir, “Inverter Controller for Very
Weak Receiving AC Systems” IEE Proceeding – Gen., Transmission
and Distribution, Vol. 146, no 3, May 1999, pp. 235-240.
IX. APPENDIX INVERTER CONTROLLER GAINS
Comment
AC voltage control
Stabilising control
Filter
Gain
Kv
Kvi
Ka
Ti
value
0.3 [deg/kV]
5 [deg/kVs]
-0.14
0.008 [s]
X. BIOGRAPHY
Dragan Jovcic (S’97, M’00) obtained a B.Sc. in Control Engineering from
the University of Belgrade, Yugoslavia in 1993 and a Ph.D. degree in
Electrical Engineering from the University of Auckland, New Zealand in
1999.
He is currently a lecturer with the University of Aberdeen, Scotland where
he has been since 2004. He also worked as a lecturer with University of
Ulster, in period 2000-2004 and as a design Engineer in the New Zealand
power industry in period 1999-2000. His research interests lie in the areas of
FACTS, HVDC and control systems.