CMOS Logic Circuit Design
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Special-Purpose Digital Circuits
• Buffer Circuits
• Path-Selector Circuits
• Information-Storing Circuits
• Trigger Circuits
• Multi-Vibrator Circuits
• Voltage-Generator Circuits
Mattausch, CMOS Design, H20/5/2
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Necessary Functions other than Logic Operations
1) Transmission of signals over long interconnection lines
or to many receivers
- Buffer (inverting, non-inverting, tri-state)
2) Selection of an interconnection for a Signal according to a condition
- Selector (multiplexer, demultiplexer)
3) Storing an information for some time
- Flip-flop, latch
4) Removing Noise from a Signal
- Trigger circuits
5) Generation of Synchronous or Asynchronous Control Signal
- Multi-vibrator circuits (a-stable, bi-stable, mono-stable)
6) Generation of other Voltages than VDD or VSS
- Voltage generator circuits
CMOS logic circuits do contain more than only logic gates.
Mattausch, CMOS Design, H20/5/2
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Buffer Circuits
-
Increasing the driving capability of a logic
signal for large load capacities
Conventional non-inverting buffers
Inverting buffers
Tri-state buffers
Mattausch, CMOS Design, H20/5/2
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Reduction of Logic-Gate Fan-Out with a Buffer
NAND-gate with
fan-out = k, fan-in = m
2
1
3
m-1
m
NAND-gate with
fan-out = 1, fan-in = m
1
2
2
3
k
Delay without buffer
tdf , NAND = m⋅ (m⋅ t fin + k⋅ t fex )
tdr , NAND = m⋅ trin + k⋅ trex
1
1
3
2
m-1
m
3
Non-inverting
Buffer
k
Delay with buffer
tdf , NAND = m⋅ (m⋅ t fin + t fex ) + tbuffer
tdr , NAND = m⋅ trin + trex + tbuffer
The delay of a circuit with large fan-out (i. e. large output
load) can be reduced with a buffer, if (k-1)·trex > tbuffer is valid.
Mattausch, CMOS Design, H20/5/2
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Construction of Non-Inverting CMOS Buffers
Vin
Vout
Optimum choice of A and N
Cload
VSS
C 
A ni − buffer =  load 
 Cin1 
Vin
W
A0 p
Wn
W
A1 p
Wn
I1
I2
W
W
A 2N − 2 p A 2N −1 p
Wn
Wn
I2N-1
Vout
Cload
I2N
VSS
1
2N

C 
N ni − buffer = int  12 ln load 
Cin1 

(Cin1 is the input capacity of the 1st inverter)
Non-inverting buffers have even number of inverters. Each
stage has a factor Ani-buffer (Cload,Cin) larger driving capability.
Mattausch, CMOS Design, H20/5/2
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Construction of Inverting CMOS Buffers
Vin
Vout
Optimum Choice of A and N
Cload
VSS
C 
A i − buffer =  load 
 Cin1 
Wp
A
Wn
0
Vin
I1
W
W
A p A2 p
Wn
Wn
1
I2
I3
A
2N −1
Wp
W
A 2N p
Wn
Wn
I2N
I2N+1
VSS
N i −buffer
Vout
Cload
1
2 N +1
 1  Cload  1 
 − 2 
= int  2 ln 
C
  in1  
(Cin1 is the input capacity of the 1st inverter)
Inverting buffers use an odd number of cascaded inverters.
Each stage has again Ai-buffer(Cload,Cin) larger driving capability.
Mattausch, CMOS Design, H20/5/2
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Tri-State Inverter
Symbol
CMOS-Circuit Implementation
En
VDD
In
Out
In
Out
Truth Table
En In
Out
0
0
floating
0
1
floating
1
0
1
1
1
0
VSS
En
A tri-state inverter has an additional high-impedance or
floating output state selected with an enable signal. It can be
built with a conventional inverter and a transmission gate.
Mattausch, CMOS Design, H20/5/2
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Tri-State Buffers
non-inverting
tri-state buffer
CMOS-Circuit Implementation
VDD
En
In
Out
inverting
tri-state buffer
Out
In
I1
I2
IN-1
IN
En
VSS
In
Out
En
A tri-state buffer combines high driving capability for a large
load capacity Cload and the possibility of a floating output.
Mattausch, CMOS Design, H20/5/2
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Path-Selector Circuits
-
Multiplexer- and Demultiplexer Principles
Implementation with Transmission Gates
Series Connection of Transmission Gates
Implementation with Tri-State Inverters or
Tri-State Buffers
Mattausch, CMOS Design, H20/5/2
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Multiplexer and Demultiplexer Principles
between ln(N) and N
Control/Selector Lines
N
Data
Input
Lines
1
2
3
Multiplexer
(MUX)
One
Selected
Data
Output
between ln(N) and N
Control/Selector Lines
One
Data
Input
1
2
3
N
Possible
0utput
Lines
Demultiplexer
(DEMUX)
N
N
Conditional signal-path selection is performed with
multiplexer- or demultiplexer circuits.
Mattausch, CMOS Design, H20/5/2
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Multiplexer Realization with Transmission Gates
4-Input Multiplexer
Transmission Gates
Minimum Transmission Gates
Symbols
En
In
En1 En2 En3 En4
En
Out
In
In1
In2
In3
In4
Out
Circuits
En
Out
Minimum Select Signals
En
En1
In
Out
In
Out
En2
In1
In2
Out
In3
In4
Path-selector realization is easiest by transmission gates.
Mattausch, CMOS Design, H20/5/2
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Series Connection of Transmission Gates
Series of N
transmission gates
driving a load
Delay model for a
series of N
transmission gates
Delay equation as a
function of N
transmission gates
t PS,hl ≈ t PS,lh ≈ (Rn || Rp )(Cload )⋅ N+ 0.35⋅ (Rn || Rp )(Cinn + Cinp )⋅ N
A series connection of N transmission gates represents an
RC-chain. Therefore, its delay time increases with N2.
Mattausch, CMOS Design, H20/5/2
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2
MUX/DEMUX Realization with Tri-State Buffers
Multiplexer
En1 En2 En3
Demultiplexer
EnN
EnN
En3 En2 En1
In1
Out1
In2
Out2
In3
Out
Out3
In
OutN
InN
With tri-state buffers the delay problem of signal-path
selectors is solved at the cost of larger integration-area.
Mattausch, CMOS Design, H20/5/2
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Information-Storing Circuits
-
Stabilizing-Feedback Principle
Set-Reset Flip-Flop
Clocked Flip-Flops
• Level Sensitive Flip-Flops
• Edge-Triggered Flip-Flops
• Flip-Flop Timing
Mattausch, CMOS Design, H20/5/2
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Stabilizing-Feedback Principle of Data Storage
Stabilizing inverterfeedback coupling
Resulting stable circuit states
Q
Q
“one”
1
0
“zero”
0
1
Stable States
Q
Q
By feeding back the identical signal to a circuit node, stable
circuit states result, which are usable for data storage.
Mattausch, CMOS Design, H20/5/2
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Set-Reset (SR) Flip-Flop
Circuit diagram
Logic Symbol
Truth table
(constructed with NAND gates)
S
R
Q
Q
Q
0
0
1
1
SR
Flip-Flop
R
Q
1
0
1
0
0
1
0
1
1
1
Q
Q
S
Q
S
Q
R
Set-reset flip-flops extend the stabilizing feedback principle
by a method for external modification of the stored data.
Mattausch, CMOS Design, H20/5/2
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Level-Sensitive Data (D) Flip-Flop
Circuit diagram
Logic Symbol
(constructed with NAND gates)
D
S
CLK
Q
D
Q
SR
Flip-Flop
D
Flip-Flop
R
CLK
Q
Q
The level-sensitive data (D) flip-flop extends the SR flip-flop
with additional circuitry for clock-controlled writing of data.
Mattausch, CMOS Design, H20/5/2
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Latch: Transmission-Gate Version of D Flip-Flop
Circuit diagram of a latch
(data flip-flop constructed with inverters and transmission gates)
CLK
Q
D
Q
The simplest construction of level-sensitive data (D) flip-flops
has 2 inverters and 2 transmission gates and is called “latch”.
Mattausch, CMOS Design, H20/5/2
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Edge-Triggered data (D) Flip-Flop
Circuit diagram of a D flip-flop into which data is written at
the positive edge (low-high) change of the clock
(constructed with 2 latches)
CLK
Q
Q
D
Master Latch
Slave Latch
The edge-triggered D flip-flop has 2 latches. Data transfer to
the slave latch occurs only at transition edges of the clock.
Mattausch, CMOS Design, H20/5/2
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Timing of Flip-Flops for Safe Data Writing
D
Volt
positive edge of the clock signal
CLK
VDD
Set-up time ts
hold time th
VSS
Minimum stable data time ts+th
Time
The safe operation of a flip-flop requires stable data signals
for a minimum time around the clock edge, which determines
data transfer into the storage part of the flip-flop.
Mattausch, CMOS Design, H20/5/2
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Trigger Circuits
-
Removal Possibilities of Signal Noise
Schmitt-Trigger Circuit
Mattausch, CMOS Design, H20/5/2
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Signal Noise and Removal Possibilities
Desired Switching-Point
Characteristic of Circuit
High-Switching Point
VSPH
Low-Switching Point
VSPL
VSS
Time
VDD
VDD
Output Voltage
Noise-Removal
Circuit Output
Noise-Removal
Circuit Input
VDD
VSS
VSS
Inverting Removal
Circuit Assumed
Time
VSS
VSPL
VSPH
VDD
Input Voltage
Noise can be removed from a signal with a circuit who has
different switching points for low-high and high-low transition.
Mattausch, CMOS Design, H20/5/2
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Schmitt-Trigger Circuit
Design of n-MOS Transistors M1 and M2
determines the High-Switching Point
Schmitt-Trigger
Symbol
β1  VDD − VSPH 
≈

β 2  VSS+ VSPH − VTH,n 
VDD
2
M5
M6
M4
CMOS
Circuit
VSS
In
Out
M3
VDD
M2
M1
Design of p-MOS Transistors M5 and M6
determines the Low-Switching Point

β5 
VSS+ VSPL
≈
β 6  VDD− VSPL − VTH, p 
2
VSS
The CMOS inverter circuit can be easily modified to obtain an
inverting Schmitt-trigger circuit to reduce input-signal noise.
Mattausch, CMOS Design, H20/5/2
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Multi-Vibrator Circuits
-
Destabilizing-Feedback Principle
A-Stable Multi-Vibrator or Oscillator
Bi-Stable Multi-Vibrator or Flip-Flop
(see Part on Information-Storing Circuits)
Mono-Stable Multi-Vibrator
Mattausch, CMOS Design, H20/5/2
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Destabilizing Feedback: Oscillator Circuits
Destabilizing inverterfeedback coupling
Resulting unstable (oscillating)
signals at circuit nodes
Qi
VDD
Q2
Q1
VSS
Q3
Time
By feeding back the inverted signal to a circuit node, an
unstable state is occurs, which is used for oscillator circuits.
Mattausch, CMOS Design, H20/5/2
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Ring-Oscillator Circuit with N Stages
Ring-Oscillator constructed with
an odd number N of inverters
Obtained oscillator
frequency
fosc
Vosc
1
≈
N⋅ (t IHL + t ILH )
CMOS oscillators can be constructed with an odd number of
inverters. The oscillator frequency fosc is determined by
inverter low-high/high-low transitions and inverter number.
Mattausch, CMOS Design, H20/5/2
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Mono-Stable Multi-Vibrator
Mono-stable multi-vibrator example Generation of long pulse with fixed
constructed with NOR and inverter length by short trigger pulse at input
VDD
Vout
R
Vin
C
V1
tpulse
Vout
V2
V2
V1
t pulse
VDD
≈ RC⋅ ln
VDD− VSP,I
Vin
Time
A mono-stable multi-vibrator is a circuit with delayed stable
feedback. Thus pulses with fixed length can be generated.
Mattausch, CMOS Design, H20/5/2
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Voltage-Generator Circuits
Mattausch, CMOS Design, H20/5/2
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Simple Generator for Voltages >VDD and <VSS
High-voltage generator
Transient output of the high
voltage generator
Vout ≈ 2VDD− 2VTH, n
Low-voltage generator
Vout ≈ − VDD+ 2VTH, n
Voltage-generator circuits are applied, if the circuits in the
CMOS chip need other supply voltages than VDD and VSS.
Mattausch, CMOS Design, H20/5/2
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