Research Report
2004-37T
A Control Scheme in Hybrid Synchronous-Stationary
Frame for PWM AC/DC Converter under Generalized
Unbalanced Operating Conditions
Y. Suh*, T. A. Lipo
*ABB Switzerland Ltd.
Austrasse
CH-5300 Turgi, Switzerland
email: yongsug.suh@ch.abb.com
University of Wisconsin - Madison
1415 Engineering Drive
Madison, WI 53706, USA
email: lipo@engr.wisc.edu
Work performed at WEMPEC sponsored by CPES.
Wisconsin
Electric
Machines &
Power
Electronics
Consortium
University of Wisconsin-Madison
College of Engineering
Wisconsin Power Electronics Research
Center
2559D Engineering Hall
1415 Engineering Drive
Madison WI 53706-1691
© 2004 Confidential
A Control Scheme in Hybrid Synchronous-Stationary
Frame for PWM AC/DC Converter under
Generalized Unbalanced Operating Conditions
Yongsug Suh
Thomas A. Lipo
ABB Switzerland Ltd
Austrasse
CH-5300 Turgi, Switzerland
email: yongsug.suh@ch.abb.com
University of Wisconsin − Madison
1415 Engineering Drive
Madison, WI 53706, USA
email: lipo@engr.wisc.edu
Abstract—This paper proposes a new control scheme of improved
transient response for the pwm ac/dc converter under
generalized unbalanced operating conditions. The overall
bandwidth diminishing filter/functional block for extracting
positive and negative sequence components have been avoided by
employing dual current regulators in positive and negative
rotating synchronous frames. The steady-state error due to 120
Hz ac signals has been reduced by employing a resonant gain
path in the current regulator. This paper also proposes simplified
current reference calculation scheme in the regulation of
instantaneous active/reactive power. Compared to the previous
works, the proposed control method has better transient response
in compensation for generalized unbalanced operating conditions
(unbalanced input supply and unbalanced input impedances) of
wide range while still satisfying unity input power factor
correction and ripple-free dc output voltage regulation without
adding any external hardware. The proposed control system has
been analyzed and tuned based on the ac small signal perturbed
model under unbalance. Simulation and experimental results
confirm the proposed control method under severe unbalance
operating conditions.
unbalanced input supply. Among several control methods, a
control strategy to directly regulate the instantaneous active
power to a constant value without any ripple components has
been considered to be the most effective approach of high
performance.
Rioual et al. [4] and Song and Nam [5] derived control
schemes regulating the instantaneous active power at the input
of the converter in dq synchronous frame for eliminating
harmonics of the boost type rectifier under unbalanced input
supply. These approaches cannot be applied under the extreme
and generalized unbalanced input supply. Stankovic and Lipo
[6] addressed the cases of the generalized unbalanced
operating conditions. However, the proposed control
algorithm needs a great deal of computation steps for dsp
control. Suh, Tijeras, and Lipo [7, 8] have proposed a method
to directly control the instantaneous active power at the poles
of the rectifier, so that the more effective elimination of the
harmonics under the wide range of unbalanced operating
conditions can be achieved. Dual current regulators of positive
and negative rotating synchronous frame employed in the
works of Song and Nam [5] and Suh et al. [7, 8] suffered from
low bandwidth current feedback loop leading to unsatisfactory
transient responses. This insufficient transient characteristic is
mainly due to the notch filter and the functional block of
extracting positive and negative sequence components of the
three-phase ac current quantities. It has been widely
recognized that the filter/functional block for extracting
positive and negative sequence components in the rotating
Keywords-component; ac/dc converter, unbalance, hybrid
synchronous frame controller
I. INTRODUCTION
The pwm ac/dc converter has been increasingly employed
in recent years owing to its advanced features including
sinusoidal input current at unity power factor and high quality
dc output voltage with a filter capacitor of small size. These
features are not necessarily achieved under the operating
conditions of unbalanced input supply and unbalanced input
impedances. Such a generalized unbalanced operating
condition is quite common in power systems, particularly in a
weak ac system. It has been shown that unbalanced input
voltages or impedances result in the appearance of even
harmonics at the dc output and odd harmonics in the ac input
currents [1-3]. Therefore, pwm ac/dc converters under
generalized unbalanced operating conditions necessitate the
use of input/output filters of large size and thereby completely
offset several advantages of the pwm ac/dc converter [2].
Over the past few years, there have been extensive studies
on the control method to eliminate the harmonics under
IAS 2004
2244
idc
SW 1
ea
eb
n
ec
La
Ra
ia
Lb
Rb
ib
Lc
Rc
ic
SW 3
iL
SW 5
va
icap
vb
Cdc
Rdc
vdc
vc
SW 4
SW 6
SW 2
Fig. 1. PWM ac/dc converter under generalized unbalanced operating
conditions.
0-7803-8486-5/04/$20.00 © 2004 IEEE
synchronous frame from three-phase ac quantities put a limit
on the overall bandwidth of the control loop. Therefore, in
order to quickly compensate for transient unbalanced input
supply including transient line faults, the filter/functional
block for extracting positive and negative sequence
components should be implemented without diminishing the
overall bandwidth of the controller.
This paper proposes a new control scheme of improved
transient response for the pwm ac/dc converter under
generalized unbalanced operating conditions. A new control
scheme adopts the control strategy of regulating the
instantaneous active/reactive power at the poles of the rectifier
as introduced in Suh, et al. [7, 8]. The overall bandwidth
diminishing filter/functional block for extracting positive and
negative sequence components used in Suh, et al. [7, 8] have
been avoided by employing dual current regulators in positive
and negative rotating synchronous frames. This paper also
proposes simplified current reference calculation scheme in
the regulation of instantaneous active/reactive power.
The proposed control scheme combined with the
simplified current reference calculation method has relatively
high current loop bandwidth with sufficiently low steady-state
error for ac input current references. Compared to the previous
works [4-8], the proposed control method has better transient
response in compensation for generalized unbalanced
operating conditions (unbalanced input supply and unbalanced
input impedances) of wide range. The proposed control
scheme with relatively simple program implementation allows
the pwm rectifier to generate a dc output without substantial
even-order harmonics and maintain nearly unity power factor
under generalized unbalanced operating conditions, which, in
turn, makes it possible to substantially reduce the size of the
dc-link capacitor and ac inductor. The proposed control
system is analyzed and tuned based on the ac small signal
perturbed model and quasi-static approximation. Simulation
and experiments were conducted under two different
unbalanced operating conditions; 15 % one phase unbalance,
single line-ground fault with unbalanced input filters.
 p
 p
∼ *p
p
p
E dq = Rdq I dq + j ω Ldq I dq + V dq + e-j2ω t Rdq I dq − e-j2ω t
∼
(2)
 n
 n
∼ *n
n
n
E dq = Rdq I dq − jω Ldq I dq + V dq + e j2ω t Rdq I dq + e j2ω t
∼
*n
jω Ldq I dq

(3)
∼
∼*
where Rdq = ( Rd + Rq )/2, Rdq = ( Rd − Rq )/2 + j Rdq, Rdq =
( Rd − Rq )/2 − j Rdq.
B. DC side
The dc link current is represented by two space vectors;
Idqs, Sdqs. Sdqs is the space vector of switching functions (sa, sb,
and sc) in stationary reference frame.
3
3
*
( I S + Iqs Sqs ) = Re { Idqs Sdqs
}
(4)
idc =
2 ds ds
2
Under unbalanced operating conditions the product term of
two space vectors is simplified as the following. The
oscillating terms of twice input frequency have been ignored
under the assumption of constant steady-state dc link current.
dvdc 3
vdc
p
p
p
p
n
n
n
n
Cdc
=
( Id Sd + Iq Sq + Id Sd + Iq Sq ) −
(5)
dt
Rdc
2
The equation of (5) is a nonlinear model with four product
terms. The small signal perturbed model of (5) is derived
using the ac side model of (2) and (3).
d
∆v =Ha ∆vdc+Hb ∆I pd +Hc ∆I qp +Hd ∆I dn +He ∆I qn (6)
dt dc
where
3
p 2
p 2
n 2
n 2
2 { R( I d ) + R( I q ) + R( I d ) + R( I q )
2 Cdc Vdc
1
− E dp I dp − E qp I qp − E nd I nd − E nq I nq } − C R
(7)
dc dc
Ha =
p
R Iq ωL Id
3
p
{ Sq −
+
}
2Cdc
Vdc
Vdc
Hd =
R Id ωL Iq
3
n
{Sd −
+
}
2Cdc
Vdc
Vdc
He =
R Iq ωL Id
3
n
{ Sq −
− V
}
2Cdc
Vdc
dc
 
 
 
where Rd = ( 4 Ra + Rb + Rc )/6, Rq = ( Rb + Rc )/2, Rdq =
( Rc − Rb )/2 3. The inductance parameters are defined
similarly [9]. The equation of (1) is now transformed and
decomposed into two equations in positive and negative
synchronous rotating frame respectively as shown in (2) and
(3) [7, 8].
2245
n
∆ Id p
Hb
∆ Iq p
Hc
(8)
p
Hc =
n
A. AC side
The boost type PWM rectifier under generalized
unbalanced operating conditions in Fig. 1 can be described by
the differential equation of (1) in stationary frame.
dIds
 Eds   Rd Rdq   Ids   Ld Ldq  dt
 Vds 
 =
  +
 dI +  (1)
 Eqs   Rdq Rq   Iqs   Ldq Lq 
 Vqs 
qs
dt
p
R Id ω L Iq
3
p
Hb =
{ Sd −
− V
}
2Cdc
Vdc
dc
p
II. MODEL OF PWM RECTIFIER UNDER UNBALANCED
OPERATING CONDITIONS
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*p
jω Ldq I dq
(9)
n
(10)
n
(11)
1
s
n
Hd
∆ Iq n
He
∆ Id
∆ vdc
− Ha
Fig. 2. AC small signal perturbed model of the dc side of PWM boost type
rectifier under unbalanced operating conditions.
0-7803-8486-5/04/$20.00 © 2004 IEEE
The bold faced letters in (7) ~ (11) are referred to as values
at the quiescent operating point of ac small signal
perturbation. The final dc side model can now be represented
by the block diagram in Fig. 2.
III. INSTANTANEOUS ACTIVE AND REACTIVE POWER UNDER
UNBALANCED OPERATING CONDITIONS
The complex power at the pole of the converter is defined
and given in (12).
p
n
*
Sout = (3/2) Vdqs Idqs
= (3/2) ( e jω t V dq + e-jω t V dq ) ( e jω t
p
n
(12)
I dq + e-jω t I dq )*
The instantaneous active power is obtained by taking the
real part of the complex power. Plugging (2) and (3) into (12)
out
out
out
yields the equations of P o , P c2 , and P s2 [7, 8].
out
out
pout(t) = va ia + vb ib + vc ic = Real{ Sout } = P o + P c2
out
cos(2 ω t) + P s2 sin(2 ω t)
(13)
out
p
n
'
*
Idqs
= (3/2) ( − j e jω t V dq + j e-jω t V dq ) (
Tout = (3/2) Vdqs
p
n
(14)
e j ω t I + e- j ω t I ) *
It is inferred from the relationship between the complex
power Sout and the instantaneous active power pout(t) in (13)
that the real part of quadrature complex power Tout is now
equivalent to the instantaneous reactive power qout(t).
out
out
qout(t) = va' ia + vb' ib + vc' ic = Real{ Tout } = Q o + Q c2
cos(2 ω t) +
sin(2 ω t)
(15)
By following the similar steps as done for the
out
out
out
instantaneous active power, the terms of Q o , Q c2 , and Q s2 in
(15) can be described by the positive and negative
synchronous frame variables of the input voltage and current.
It is also observed that, as in the case of the average
instantaneous active power, the average instantaneous reactive
power is also conserved. Therefore, the average input reactive
in
power Q o is found to be as the following.
in
p
p
p
p
n
n
n
n
(2/3) Q o = ( E q I d − E d I q − E q I d + E d I q )
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out
IV. FOUR CONTROL LAWS TO CALCULATE CURRENT
REFERENCES
There are four control laws that the controller should
comply with for PWM rectifiers under unbalanced operating
conditions. The current references are calculated from these
four control laws and used as references in the current
regulator.
The first control law is about the input average active
power described in (17).
p
⇒
P o = Pload + Ploss
p
n
n
f1( I d , I q , I d , I q ) = 0
(17)
The second control law determines the average input
instantaneous reactive power described in (18). The average
in
input reactive power Q o exchanged between the utility source
and the rectifier determines the input power factor. Unity input
power factor condition is equivalent to zero value of kpf.
in
in
in
kpf =
Qo
in
Po
=
p
⇒
Q o = kpf P o
1 − pf
pf
p
n
n
f2( I d , I q , I d , I q ) = 0
(18)
2
(19)
The third and forth controls laws are achieved by setting
out
out
both of P c2 and P s2 in (13) to zero thereby nullifying the
oscillating components of the output instantaneous active
power as shown in the followings.
dq
out
Q s2
out
those of P s2 , and so do the terms of Q s2 for P c2 . In other
words the ripple components of instantaneous active and
reactive power have the same magnitudes. As a result, by
nullifying the oscillatory components of instantaneous active
power the instantaneous reactive power also becomes flattened
[7 ,8].
in
In the previous works, the instantaneous reactive power
has been calculated by taking the imaginary part of the same
complex power whose real part represents the instantaneous
active power [4, 5]. This way of defining the instantaneous
reactive power is no longer valid under unbalanced operating
conditions [7, 8, and 10].
The more general expression of the instantaneous reactive
power can be developed on the basis of a set of voltages that
lag the pole voltages by 90°. In this paper a new kind of
complex power based on the quadrature voltage is introduced.
A new complex quantity, Tout referred as a quadrature
complex power is defined to be the product of a quadrature
voltage space vector and the conjugate of current space vector
with a scaling factor of 3/2 as shown in (14).
dq
It is noted from the ripple components of the instantaneous
out
reactive power that the terms of Q c2 have same magnitudes as
out
⇒
f3( I d , I q , I d , I q ) = 0
out
⇒
f4( I d , I q , I d , I q ) = 0
P c2 =0
P s2 =0
p
p
n
n
(20)
p
p
n
n
(21)
It is now possible to set four conditions to solve for the
four unknown components of input currents. The equations of
(17) and (18) are linear while the equations of (20) and (21)
are nonlinear with respect to the four unknown input current
components; I dp, I qp, I dn, and I qn [7, 8]. However, with the
knowledge of pole voltages from the reference signals of pole
voltages in the space vector pwm control block, (20) and (21)
can be simplified to linear equations. As a result, the four
unknown input currents are readily obtained as the followings.
(16)
2246
I d = − ( k1 + k2 kpf ) P o
p
in
(22)
p
Iq
in
Po
(23)
I d = ( k3 − k4 kpf ) P o
n
in
(24)
n
Iq
in
Po
(25)
= − ( k2 − k1 kpf )
= ( k4 + k3 kpf )
0-7803-8486-5/04/$20.00 © 2004 IEEE
where
k1 =
p
Vd
n
Vq
k2 =
p
n
Vd Vd
k3 =
n
Ed
(V
k4 =
n
Eq ( V
p
p2
Ed ( V d +
p
n
+ Vq Vd )
p
p2
Eq ( V d +
− V qp V qn )
p
p
n
Ed ( Vd Vd
n2
n2
d +V q )
p
p
n
Ed ( Vd Vq
n2
n2
d +V q )
V
p2
q
)+
n
Ed
(
p
Vq
n
Vq
−
p
Vd
n
Vd
)−
n
Eq
(
V
n
p
n
p
n
Sequential
Component
Extraction
Control Block D
Id +*
Iq +*
Vdcref
n
) − Ed ( Vd Vq + Vq Vd ) + Eq (
DC-link
Voltage
Regulator
Poin
Iq p* Reference Frame
Transformation
Id n* Control Block C
Current
References
Calculating
Block
Vd +*
Positive
Sequence
Current
Regulator
Vq +*
e jwt
Vdqs*
Ed − Eq −
Id − ∗
Iq n*
vdc
Iq − ∗
Vq − ∗
−
n
Vq
)+
p
Eq
(
p
Vd
n
Vq
+
p
Vq
n
Vd
Id −
Iq −
)−
Ed +
Eq +
Ed −
Eq −
(28)
+
p
Vq
n
Vd
)+
p
Eq
(
p
Vq
n
Vq
−
p
Vd
n
Vd
)−
Ed n
Id +
Iq
+
SW 1
~ SW 6
Park Transformation
& Inverse Park
Transformation
Control Block B
ia
ib
Park Transformation
& Inverse Park
Transformation
Control Block B
eab
ebc
Ed p
Eq p
Eq n
(29)
Gate
Drive
Block
e -jwt
(27)
p
Vq
Space
Vector
PWM
Vd − ∗
Negative
Sequence
Current
Regulator
Sequential
Component
Extraction
Control Block A
vdc
Fig. 3. System block diagram.
V. A NEWLY PROPOSED CURRENT REGULATORS FOR
SEQUENTIAL COMPONENTS
Ed +
Gr(s)
I d +*
A newly proposed control scheme in this paper transforms
two nonlinear equations of (20) and (21) into linear equations
by employing additional feedback path for pole voltages (va,
vb, vc). Therefore, the calculation algorithm of current
reference becomes relatively simple. The system block
diagram of the proposed control scheme is shown in Fig. 3. In
this figure the four sequential components of the pole voltages
(V dp, V qp, V dn, and V qn) are extracted from the space vector pwm
block and fed back to the current reference calculating block.
With these four sequential components the computational time
spent on the current reference calculating block in a dsp
controller can be greatly reduced compared to the work done
in [7, 8].
It is important in the unbalance compensation that the
current regulator should regulate the negative sequence
component accurately and rapidly as well as the positive
sequence. In the previous works [3, 5, 7, and 8] of directly
regulating the negative sequence, it was inevitable to employ
sequential component extracting filters which undermine the
overall regulator bandwidth and stability margin.
A control scheme presented in this paper also proposes a
new current regulator which can directly regulate the negative
sequence without sacrificing the overall bandwidth. A newly
proposed current regulator that doesn’t require a bandwidth
undermining sequential component extracting filter stage is
shown in Fig. 4. The measured three-phase ac input current
quantities are directly transformed to either positive or
negative rotating synchronous frame resulting in 120 Hz ac
signal imposed on dc signal without being decomposed into
separated positive and negative sequential components as
shown in Control Block B of Fig. 5.
However, the four current references obtained in Current
Reference Calculating Block are dc signals separated in
positive/negative sequence rotating synchronous frames.
Therefore, in order to match the calculated current reference
values (I dp, I qp, I dn, and I qn) to the measured current quantities
−
−
+
+
(I d , I q , I d and I q ) in the same transformation frames, the
reference values should be transformed in the same manner as
the measured values. This matching transformation is
described in Reference Frame Transformation Block (Control
Block C) of Fig. 6.
IAS 2004
Power
Stage of
AC/DC
Converter
Ed + Eq +
Id p*
(26)
p2
q
Vd p
Vq p
Vd n
Vq n
Controller Stage of
AC/DC Converter
K
+d
pc
Id +
ωL
+
ωL
+d
K ic
s
Vd +*
e jwt
Vd p Vq p Vd n Vq n
Iq
Id p*
Vdcref
K pv
K iv Idcref
s
Po
in
+q
K pc
Iq +*
Iq p*
Current
References
Calculating
Block
Id n*
vdc
Iq
Reference Frame
Transformation
Control Block C
Id − ∗
n*
Vq +*
K
+q
ic
s
Gr(s)
Eq +
d
K pc
Id −
ωL
Iq −
ωL
Vdqs*
Ed −
Gr(s)
Space
Vector
PWM
d
K ic
s
Vd − ∗
Ed p Eq p Ed n Eq n
e -jwt
q
K pc
Iq − ∗
Vq − ∗
K
q
ic
s
Gr(s)
Eq −
Fig. 4. Detailed control block diagram of the current regulator.
Xd +
e -jwt
2φ
Xb
Xq +
Xα
3φ
Xa
Xβ
Xd −
e jwt
Xq −
Fig. 5. Transformation block from abc quantities to the variables in
positive and negative rotating frames (Control Block B in Fig. 3).
Id p*
Iq p*
Id n*
Iq n*
e jwt
e -jwt
Ids*
Iqs*
e -jwt
e jwt
Id +*
Iq +*
Id − ∗
Iq − ∗
Fig. 6. Current references transformed from dc sequential components to
ac-superimposed sequential components (Control Block C in Fig. 4).
Compared to the dual current regulators having a dc
reference signal separated in positive/negative sequence
rotating synchronous frames proposed in [5, 7, and 8], the
proposed current regulators shown in Fig. 4 now have ac
reference signals. This ac reference signal consists of dc value
of positive(negative) sequence component and ac value of
negative(positive)
sequence
component
in
the
positive(negative) rotating synchronous frame controller.
Since two current regulators are structured in symmetry, the
positive and negative sequence components of the current are
equally regulated in same effective control dynamic behavior.
The steady-state error due to 120 Hz ac reference signal is
sufficiently reduced by employing a resonant gain path in the
current regulator. This additional resonant gain transfer
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0-7803-8486-5/04/$20.00 © 2004 IEEE
function, Gr(s) of (30) is multiplied to the error signal of the
current values and added to the output of PI gain stage as
shown in Fig. 4. The resonant transfer function makes it
possible to have a high bandwidth without deteriorating the
stability of the control loop [11].
Root Locus of the Current Regulator
6000
4000
Imag Axis
2000
0
−2000
2
Gr(s) = Kr s / ( s2/ω r + s/Qf ωr + 1 )
(30)
−4000
where ωr = 754 rad/s.
Control Block A of sequential component extraction
calculates separated positive/negative sequential dc
p
p
p
n
n
components (E d , E d , E q , E d , E q ) from the measure threephase ac input voltages (ea(t), eb(t), ec(t)). The calculation
algorithm employed in this block has been proposed and
explained in [7, 8]. The intrinsic delay time of 5.556 ms and
zero steady-state error properties make this calculation
algorithm better function as calculating block of input voltage
sequential components in a feedforward path rather than
calculating block of current sequential components in a
feedback path of the current regulator.
VI. DYNAMIC ANALYSIS OF THE CONTROL SYSTEM
In this section, the dynamic characteristics of proposed
control system are analyzed. The proposed control system
shown in Fig. 3 consists of two regulating loops; outer dc
voltage regulating loop and inner ac input current regulating
loop. The inner ac input current regulating loop is made up of
four partially overlapped parallel loops. The open loop gain of
current regulator is obtained to be as the following.
Kic
Kr s
1
GOL-c(s)=(Kpc+ + 2 2
)
s s /ωr + s/(Qf ωr) + 1 sL + R
(31)
The secondary effects of digital controller such as
sampling delay, propagation delay, and quantization error
have been neglected for the sake of simplified analysis.
However these effects can be integrated into the above
equation without any significant drawback [13].
The Bode plot of the open loop gain of (31) and root locus
of the closed loop transfer function for the current regulator
are shown in Fig. 7 and 8, respectively. These plots
correspond to the system parameters summarized in Table II
(Kpc = 30, Kic = 300, Kr = 0.3, and Qf = 20).
−6000
−12000
−10000
−8000
−6000
Real Axis
−4000
−2000
0
Fig. 8. Root locus of the closed loop transfer function for current regulator
(in rad/s).
On the contrary of the inner current regulating loop the
dynamic equation of the outer voltage regulating loop is fairly
non-linear. A small signal perturbed model in Fig. 2 has been
employed to analyze and design the dynamics of the outer
voltage loop as shown in Fig. 9. The control gains of the
proposed system are tuned on the basis of quasi-static
approximation for the cascaded multi-loop control system
[13]. Assuming the bandwidth of the inner current regulating
loop is relatively higher than that of the outer voltage
regulating loop in general, the total transfer function of the
inner current loop can be approximated as unity when tuning
for the outer voltage loop. Therefore,
Kiv
1
GOL-v(s) = ( Kpv +
) Htot
(32)
s
s − Ha
k3 − k4 kpf
− ( k1 + k2 kpf )
Htot =
Hb − Hc +
Hd
k2 − k1 kpf
k2 − k1 kpf
k4 + k3 kpf
He
(33)
+
k2 − k1 kpf
The Bode plot of the loop gain of the outer voltage
regulating loop is obtained and shown in Fig. 10. It is
calculated for three different cases; Balanced case, Case of
Table II, and Case of Table III all with Kpv=0.09 and Kiv=15.
Current reference
calculating block
Current
regulator
− (k1 + k2 kpf)
∆ Id p*
∆ Id
∆ Id p*
p*
∆ Iq p
∆ Iq p*
∆ Iq
p
(k3 − k4 kpf)
(k2 − k1 kpf)
∆ Id n*
∆ Id n
∆ Id n*
∆ Id n
(k4 + k3 kpf)
(k2 − k1 kpf)
∆ Iq n*
∆ Iq n
∆ Iq n*
∆ Iq n
(k2 − k1 kpf)
∆ vdc*
K pv
K iv
s
Po
in
∆ Iq
−1
∆ vdc
Small signal purturbed model
∆ Id p
p
Hb
Hc
1
s
∆ vdc
Hd
− Ha
He
Fig. 9. Voltage regulator with small signal perturbed model of current
regulator and dc side of the converter (Fig. 2).
Bode Plot of the Current Regulator Loop Gain
80
Magnitude [dB]
60
40
Bode Plot of the Voltage Loop Gain
60
20
Balanced Case
Case 1
Case 3
40
−20
−1
10
0
10
1
2
10
10
3
10
Magnitude [dB]
0
4
10
20
0
−20
−40
50
−60
−1
10
0
10
1
2
10
10
3
4
10
10
−84
−50
Balanced Case
Case 1
Case 3
−85
−100
Phase [deg]
Phase [deg]
0
−150
−200
−1
10
0
10
1
2
10
10
3
10
4
−86
−87
−88
−89
10
Frequency [Hz]
−90
−1
10
0
10
1
2
10
10
3
10
4
10
Frequency [Hz]
Fig. 7. Bode plot of the loop gain of inner loop current regulator.
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Fig. 10. Bode plot of the open loop transfer function for voltage regulator.
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TABLE I
BANDWIDTH AND PHASE MARGIN OF VOLTAGE AND CURRENT REGULATOR
Voltage loop
Bandwidth
Phase margin
Current loop
70 Hz
Bandwidth
Phase margin
90°
2.0 kHz
74°
VII. SIMULATION & EXPERIMENTAL RESULTS
The proposed control scheme was simulated using
SABER. The steady state and transient performance of the
pwm rectifier in Fig. 1 with the proposed control circuits in
Fig. 3 ~ 6 were evaluated using a laboratory prototype pwm
rectifier. The complete control algorithm was implemented in
a DSP processor TI TMS320F240 with both a sampling rate
and a switching frequency of 8.3 kHz. To verify the feasibility
of the proposed control scheme under the various generalized
unbalanced operating conditions, computer simulations and
experiments were conducted under two different unbalanced
operating conditions.
harmonic contents in the input current under the unbalanced
input supply. In other words, the output instantaneous active
power, pout(t) in Fig. 12 is almost flat compared to pout(t) in
out
Fig. 11. This also explains the fact that Pout
s2 and P c2 have to be
regulated to zero in order to achieve a constant output
instantaneous active power. As noted from Fig. 12, ea and ia
are nearly in-phase. This result of almost unity power factor is
consistent with the condition of setting the average input
reactive power (Qino ) to zero in (18). The one of advantages of
the proposed control scheme is its capability of controlling the
power factor. The line voltage between phase-a and phase-b,
phase-a input current, and output dc link voltage under the
same unbalanced operating condition as Table II except now
with leading power factor of 0.707 are shown in Fig. 13. This
condition is achieved by setting kpf to −1 in (18). It is observed
from Fig. 13 that ia leads eab by approximately 1 ms. It
confirms the performance of the proposed control scheme
achieving both elimination of the output voltage ripple and
leading power factor control.
Waveforms for the single controller under Case 1
400
vdc
300
Voltage (V) & Current (A)
The bandwidth and phase margin for these two loop gains
are summarized in Table I. It is noted from Table I that the
bandwidth of the current regulating loop is designed to be 20
times as high as the bandwidth of the voltage regulating loop
validating quasi-static approximation.
A. Case 1: 15% unbalance in one phase input voltage
This kind of unbalanced input condition of one-phase sag
is quite common in a weak ac system. This input configuration
has been chosen to verify the performance of the proposed
control algorithm under the most popular type of unbalance
input supply. The system parameters of this condition are
summarized in Table II.
200
ea
100
0
10ia
−100
−200
0
0.005
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05
Fig. 11. Experimental waveforms of the single frame controller without a
compensation for the 15% one phase unbalance.
TABLE II
Waveforms for the dual controller under Case 1
400
Value
Parameter
La, Lb, Lc
1.6 mH
Ra, Rb, Rc
vdc
Value
Vdcref
0.2 Ω
400 V
eb
140 sin(ω t−120°) V
Cdc
100 uF
ec
119 sin(ω t+120°) V
Rdc
100 Ω
ea
vdc
10ia
300
Voltage (V) & Current (A)
Parameter
140 sin(ω t) V
0.01
Time (sec)
PARAMETERS USED IN THE SIMULATION & EXPERIMENT FOR THE CASE OF
15% UNBALANCE IN ONE PHASE INPUT VOLTAGE
ea
ea
vdc
10ia
200
ea
100
0
10ia
−100
Fig. 11 illustrates the converter output dc voltage(vdc), the
phase-a input current(ia), and the phase-a input voltage(ea) of
the conventional PI-regulator in a positive sequence only
synchronous frame without having any unbalance
compensation control scheme. Fig. 12 shows the waveforms
for the proposed controller with the control scheme explained
in Fig. 3. Notice the reduction of the output dc voltage ripple
in Fig. 12 compared to that of Fig. 11. THD(Total Harmonic
distortion) of the output dc link voltage was measured to be
decreased from 1.39 % to 0.87 % after employing the
proposed controller. THD of the ac input current is also
improved to 7.49 % from 7.74 %. It is noted that the proposed
dual frame controller with a proposed control scheme could
smooth out the dc output ripple and reduce the odd-order
IAS 2004
−200
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05
Time (sec)
Fig. 12. Experimental waveforms of the proposed controller with a
compensation for the 15% one phase unbalance.
The simulated waveforms obtained under the transient
operating condition of Case 1 are shown in Fig. 14. At the
time of t = 0.3 s, the amplitude of phase-c voltage is decreased
from 140 V to 119 V. The settling time for dc link voltage to
stay within ± 5 % of steady-state value is measured to be
approximately 30 ms. This settling time of 30 ms is mainly
determined by the bandwidth of outer voltage regulating loop
(70 Hz) and the intrinsic delay time (5.6 ms) of the input
voltage sequential component calculating algorithm.
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B. Case 2: Single line-ground fault transient
Although this kind of unbalanced operating condition is
not as common as that of Case 1, a complete collapse of one
phase voltage is considered to be one of most extreme
unbalanced operating conditions. As mentioned earlier in this
paper, the proposed control scheme can also compensate for
the unbalance input filters in addition to the unbalance input
supply. In Case 2, the filter inductance of phase-c(Lc) is set to
twice of phase-a(La) and phase-b(Lb). A single line-ground
fault and unbalanced input filters constitute a generalized
unbalanced operating condition. The fault ride-through
capability as well as the proposed controller’s performance
can be effectively tested under this extreme unbalanced
operating condition. The system parameters of this condition
are summarized in Table III.
vdc
ia
eab
Fig. 13. Experimental waveforms of the dual frame controller under the
operating condition of Case 1 with power factor of 0.707 leading (Channel
1: input line voltage eab [100 V/div], Channel 3: phase-a input current ia
[5 A/div], Channel 4: dc link voltage vdc [100 V/div], Time: [5 ms/div]).
The proposed control scheme using dual frame current
regulator has been tested under the same transient operating
condition as in the simulation. From the waveforms shown in
Fig. 15, it is observed that the peak-to-peak ripple size of dc
link voltage has been increased to 15 V from 12 V. The
settling time of the dc link voltage is approximately 200 ms.
This settling time of 200 ms is relatively close to 170 ms
measured from the case of single frame controller. This
confirms the fact that the dynamic of dc link voltage heavily
depends on the PI gains of the voltage regulating loop.
ea
200.0
eb ec
Ec
(V)
50.0
Ea
0.0
−50.0
−100.0
−150.0
−200.0
ia(Uncompensated)
ea
200.0
150.0
10.0
100.0
(V)
(A)
Ea
(A) : t(s)
Ia(Uncompensated)
50.0
0.0
(V) : t(s)
0.0
−50.0
−10.0
Ia(Compensated)
−100.0
ia(Compensated)
−150.0
−20.0
−200.0
(V) : t(s)
Vdc(Compensated)
Vdc(Uncompensated)
(V)
404.0
400.0
396.0
392.0
0.29
vdc(Uncompensated)
vdc(Compensated)
0.3
0.31
0.32
0.33
0.34
0.35
t(s)
Fig. 14. Simulation results under 15 % one phase unbalance transient for
two different controllers; the proposed controller(Compensated), the
conventional single frame controller(Uncompensated).
vdc
400 V
ebc
Fig. 15. Experimental results under 15 % one phase unbalance transient
for the proposed controller (Top: dc link voltage [5V/div], Bottom: line
voltage between phase b and c [100V/div]).
IAS 2004
Value
Parameter
La, Lb
1.6 mH
Ra, Rb, Rc
3.2 mH
pf
Vdcref
eb
ec
140 sin(ω t) V
140 sin(ω t−120°) V
0V
Source inductance (Lua, Lub, Luc)
Eb
100.0
Parameter
Lc
ea
(V) : t(s)
150.0
20.0
TABLE III
PARAMETERS USED IN THE SIMULATION FOR THE CASE OF SINGLE LINEGROUND FAULT
Value
0.2 Ω
0.707 leading
400 V
Cdc
100 uF
Rdc
100 Ω
0.2 mH
The simulated waveforms obtained during the fault
transient are shown in Fig. 16. The phase-c input voltage has
completely collapsed at the time of t = 0.3 s. Like in Case 1, it
takes approximately 40 ms for the dc link voltage to settle
within ± 5 % of the steady-state value. It is understood that
once same controller gains are used in both cases the operating
point(level of unbalance) doesn’t have a critical effect on the
dynamic performance of the output dc link voltage. It is noted
from Fig. 16 that the ripple of dc link voltage is kept within 15
V peak-to-peak while the ripple of dc link voltage of the single
frame controller without compensation scheme is 100 V peakto-peak. It is also clearly seen that the phase-a input current of
the single frame controller has been dramatically contaminated
by the odd-order harmonics in opposition to relatively clean
input current of the proposed controller. As a result, the
waveforms shown in Fig. 16 confirm the performance of the
proposed control scheme in transient conditions as well as in
steady-state conditions.
The proposed control method has been simulated under the
complete single line to ground voltage sag of 5 cycles. The
results are shown in Fig. 17. The waveforms of the single
frame controller under the same operating condition have been
also obtained and overlaid together for comparison purpose.
This shows the better fault-ride through capability of the
proposed controller against the single frame current regulator.
It is also noted that the same settling time of 40 ms is obtained
during both fault occurrence and clearance transient. The
utility source inductance of 0.2 mH has been considered
during the simulation.
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ec
200.0
ea
150.0
eb
Eb
Ec
50.0
(V)
employing an additional resonant gain path in the current
regulator.
An extreme unbalanced operating condition of single lineground fault with unbalanced input filters was chosen as one
of two example conditions for the simulation and the
experiment in this paper. The performance of the proposed
controller has been confirmed in transient operating conditions
as well as in steady-state operations. The dc output without
substantial even-order harmonics and nearly unity power
factor in ac side of the rectifier make it possible to reduce the
size of the output dc-link capacitor and ac side inductors
leading to the possibility of reduced total system cost.
(V) : t(s)
100.0
Ea
0.0
−50.0
−100.0
−150.0
200.0
ia(Compensated)
ea
(V) : t(s)
Ea
150.0
100.0
(A) : t(s)
Ia(Compensated)
50.0
(V)
(A)
−200.0
40.0
30.0
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
0.0
−50.0
−100.0
ia(Uncompensated)
vdc(Compensated)
−150.0
−200.0
440.0
(V) : t(s)
Vdc(Uncompensated)
Vdc(Compensated)
420.0
400.0
(V)
Ia(Uncompensated)
380.0
360.0
340.0
vdc(Uncompensated)
320.0
300.0
0.29
0.3
0.31
0.32
0.33
0.34
ACKNOWLEDGMENT
This work was supported primarily by the ERC Program of
the National Science Foundation under Award Number EEC9731677.
REFERENCES
0.35
t(s)
Fig. 16. Simulation results under single line-ground fault transient for two
different controllers; the proposed controller(Compensated), the
conventional single frame controller(Uncompensated).
ec
200.0
150.0
ea
Ea
100.0
Eb
50.0
(V)
[1]
(V) : t(s)
eb
Ec
0.0
−50.0
[2]
−100.0
−150.0
40.0
30.0
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
200.0
ia(Compensated)
ea
(V) : t(s)
Ea
150.0
100.0
(A) : t(s)
Ia(Uncompensated)
50.0
(V)
(A)
−200.0
0.0
[3]
−50.0
−100.0
ia(Uncompensated)
vdc(Compensated)
−150.0
−200.0
440.0
(V) : t(s)
Vdc(Uncompensated)
[4]
Vdc(Compensated)
420.0
400.0
(V)
Ia(Compensated)
380.0
360.0
340.0
vdc(Uncompensated)
320.0
300.0
0.28
0.3
0.32
0.34
0.36
0.38
0.4
0.42
[5]
0.44
t(s)
Fig. 17. Simulation results during the voltage sag transient of 5 cycles for
two different controllers (Top: unbalanced input supply, Center: phase-a
input voltage and input current, Bottom: dc link voltage).
[6]
VIII. CONCLUSION
This paper proposes a new control method for a line side
connected pwm ac/dc converter operating under generalized
unbalanced operating conditions. By nullifying the oscillating
components of the instantaneous active power at the poles of
the converter instead of the front-end, the harmonics in an
output dc voltage can be more effectively eliminated even
under generalized unbalanced operating conditions in ac input
sides. A newly proposed control scheme employs an
additional feedback path from the output of space vector pwm
block to the current reference calculating block in the current
regulator. Owing to this additional software feedback path in
dsp code, a set of nonlinear equations in current reference
calculating block can be simplified to linear equations which
are relatively easy to implement in dsp control without
requiring many computational steps. A proposed scheme of
directly transforming the measured abc input current variables
into the positive and negative rotating synchronous frames
without separating the sequential components doesn’t require
bandwidth undermining sequential filters. The possible
drawback of steady-state error at 120 Hz has been solved by
IAS 2004
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