ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 6, December 2012
Performance Evaluation of Various Unipolar
SPWM Strategies of Trinary DC Source
Multilevel Inverter
V.Arun, B.Shanthi, A.Bharathi
Abstract— Multilevel inverters have become more popular over
the years in high power electric applications without use of a
transformer and with promise of less disturbance and reduced
harmonic distortion. This paper proposes a trinary DC source
9-level inverter [11]. Unipolar Sine Pulse Width Modulating
(USPWM) strategies using Phase Disposition (PD) strategy,
Alternate Phase Opposition Disposition (APOD) strategy, Carrier
Overlapping (CO) strategy and Variable Frequency (VF) strategy.
The performance measures like Total Harmonic Distortion
(THD), VRMS (fundamental), crest factor and form factor are
evaluated for various modulation indices. Simulation is
performed using MATLAB-SIMULINK. It is observed that
UPDPWM strategy provides output with relatively low distortion
and UCOPWM provides relatively higher fundamental RMS
output voltage.
Index Terms— APOD, CO, PD, PWM.
I. INTRODUCTION
Multilevel inverters have gained much attention in recent
years due to their various advantages. The general concept of
multilevel inverters involves the utilizing a higher number of
power electronics switches to perform the power conversion
in small voltage steps. The small voltage steps lead to obtain
the low harmonic distortion and switching losses, devices
possessing low voltage ratings and higher efficiency.
schauder and Mehta[1] proposed trinary multilevel inverter
used for statcom application and space vector modulation
techniques is used to control the inverter. It is hard to connect
a single power semiconductor switch directly to medium
voltage grids. For these reasons, a new family of multilevel
inverters has emerged as the solution for working with higher
voltage levels. Lai and Peng [2] developed modulation
control techniques for three phase trinary multilevel inverter.
Dixon and Moran [3] introduced sinusoidal space vector
modulation control techniques for three phase trinary
multilevel inverter. Seyezhai and Mathur [4] introduced the
inverted sine PWM techniques for asymmetric cascaded
multilevel inverter. Lin and Luo [5] introduced trinary
81-level multilevel inverter for motor drive. Geethalakshmi
and DelhiBabu [6] introduced common properties of PWM
modulation technique due to reduction of losses with between
harmonics. Krishna in [7] proposed harmonic elimination
based on selection of switching angle. Rajesh Gupta et al [8]
proposed
switching
characterization
of cascaded
multilevel-inverter-controlled systems [8]. Rabiya in [9]
introduced reduced switch multilevel inverter topology for
drive application. Rokan et al [10] developed new multilevel
inverter with reduced number of switches. This paper presents
a single phase trinary DC source nine level inverter topology
for investigation with various SPWM switching techniques.
Simulations were performed using MATLAB-SIMULINK.
Harmonic analysis and evaluation of different performance
measures for various modulation indices have been carried
out and presented.
II. BASIC OPERATION OF MULTILEVEL INVERTER
Fig. 1 shows a circuit configuration of a cascaded H-bridge
multilevel inverter employing trinary dc input source. It looks
like a traditional cascaded H-bridge multilevel inverter except
input dc sources. By using Vdc and 3Vdc, it can synthesize
nine output levels; -4Vdc, -3Vdc, -2Vdc, -Vdc, 0, Vdc, 2Vdc,
3Vdc, 4Vdc.The lower inverter generates a fundamental
output voltage with three levels, and then the upper inverter
adds or subtracts one level from the fundamental wave to
synthesize stepped waves. Here, the final output voltage
levels becomes the sum of each terminal voltage of H-bridge,
and it is given as
Vout  VHB1  VHB 2
(1)
In the proposed circuit topology, if n number of H-bridge
module has independent DC sources in sequence of the power
of 3, an expected output voltage level is given as
Vn  3n , n  1, 2,3..
(2)
Fig. 1 Trinary DC source MLI
III. CARRIER BASED PWM METHODS
In this proposed work a unipolar sine wave with a
triangular carrier is used to generate firing pulses for a nine
level inverter. For an m-level inverter using unipolar
multi-carrier technique, (m-1)/2 carriers with the same
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ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 6, December 2012
frequency fc and same peak-to-peak amplitude Ac are used.
C. Unipolar Carrier overlapping PWM strategy
In carrier overlapping technique, (m-1)/2 carriers are
The reference waveform has amplitude Am and frequency fm
and it is placed at the zero reference. The reference wave is disposed such that the bands they occupy overlap each other;
continuously compared with each of the carrier signals. If the the overlapping vertical distance between each carrier is Ac/2.
reference wave is more than a carrier signal, then the active The carrier arrangement is shown in fig.4.
devices corresponding to that carrier are switched on.
Otherwise, the device switches off [6]. There are many
alternative strategies are possible, some of them are tried in
this paper and they are:
a. Phase disposition PWM strategy.
b. Alternate phase opposition disposition PWM strategy.
c. Carrier overlapping PWM strategy.
d. Variable frequency PWM strategy.
The formulae to find the Amplitude of modulation indices are
as follows:
For PDPWM, APODPWM and VFPWM:
(3)
ma  2 A m /(m  1) Ac )
For COPWM:
ma  Am / (2.5* A c )
(4)
A. Unipolar Phase disposition PWM strategy.
In case of UPDPWM strategy, all the carrier waveforms
are in phase. The carrier arrangement is shown in fig.2.
Fig. 4 Carrier arrangements for UCOPWM strategy ( ma =
0.9 and mf=40)
D. Unipolar Variable frequency PWM strategy.
The number of switching for upper and lower devices of
chosen MLI is much more than that of intermediate switches
in PDPWM using constant frequency carriers. In order to
equalize the number of switching for all the switches, variable
frequency PWM strategy is used. The carrier arrangement is
shown in fig.5.
Fig. 2 Carrier arrangements for UPDPWM strategy
(ma = 0.9 and mf = 40)
B. Unipolar Alternate phase opposition disposition
PWM strategy
In case of UAPOD PWM, every carrier waveform is in out
of phase with its neighboring carrier by 180°. The fig.3 shows
the carrier arrangement for UAPOD strategy [4].
Fig. 5 Carrier arrangements for UVFPWM strategy
( ma = 0.9 and mf1=20,mf2=40)
IV. SIMULATION RESULT
Fig. 3 Carrier arrangements for UAPODPWM strategy
( ma = 0.9 and m f = 40)
The single phase trinary DC source nine level inverter is
modeled in SIMULINK using power system block set.
Switching signals for trinary multilevel inverter using
USPWM strategies are simulated. Simulations were
performed for different values of ma ranging from 0.8 to 1 and
the corresponding %THD are measured using the FFT block
and their values are shown in Table I. Figure 6 to13 show the
simulated output voltage of
Trinary MLI and their
corresponding harmonic spectrum. Figure 6 displays the nine
level output voltage generated by UPDPWM strategy and its
FFT plot is shown in Figure 7. Figure 8 shows the nine level
output voltage generated by UAPODPWM strategy and its
FFT plot is shown in Figure 9. Figure 10 shows the nine level
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ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 6, December 2012
output voltage generated by UCOPWM strategy and its FFT
plot is shown in Figure 11. Figure 12 shows the nine level
output voltage generated by UVFPWM strategy and its FFT
plot is shown in Figure 13. For ma= 0.9, it is observed from
the figs. (9, 11, 13, 15) the harmonic energy is dominant in: a)
39th order in UPDPWM strategy. b) 29th, 31st, 35th, 37th and
39th order in UAPODPWM strategy. c) 5th, 35th and 39th order
in UCOPWM strategy. d) 19th, 21st, 29th, 31st and 33rd order in
UVFPWM strategy.
The following parameter values are used for simulation:
VDC =75V, R (load) = 100 ohms, fc=2000 Hz and fm=50Hz.
Fig. 9. FFT plot for output voltage of UAPODPWM strategy
Fig. 6 Output voltage generated by UPDPWM strategy
Fig. 10. Output voltage generated by UCOPWM strategy
Fig. 7 FFT plot for output voltage of UPDPWM strategy
Fig. 11 FFT plot for output voltage of UCOPWM strategy
Fig. 8 Output voltage generated by UAPODPWM strategy
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ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 6, December 2012
TABLE III. % CF FOR DIFFERENT MODULATION INDICES
ma
UPD
UAPOD
UCO
UVF
1
1.413923
1.414542
1.414443
1.41431
0.95
1.414187
1.413981
1.413958
1.41437
0.9
1.414481
1.414353
1.413707
1.41372
0.85
1.414254
1.414309
1.413775
1.41452
0.8
1.413915
1.414649
1.414102
1.41414
TABLE IV. FORM FACTOR FOR DIFFERENT MODULATION
INDICES
ma
UPD
UAPOD
UCO
UVF
1
8.84E+04
8.58E+04
1.48E+05
8.76E+04
0.95
1.37E+05
7.59E+04
1.29E+05
1.30E+05
0.9
4.87E+04
6.04E+04
4.48E+04
0.85
4.75E+04
5.48E+04
4.55E+04
0.8
7.30E+04
8.18E+04
4.18E+04
4.35E+0
4
3.95E+0
4
7.11E+0
4
Fig. 12 Output voltage generated by UVFPWM strategy
V. CONCLUSION
Fig. 13 FFT plot for output voltage of UVFPWM strategy
TABLE I .% THD For Different Modulation Indices
ma
UPD
UAPOD
UCO
UVF
1
13.44
13.33
18.18
15.16
0.95
15.66
15.64
19.97
16.81
0.9
16.76
16.75
22.03
17.35
0.85
16.94
16.93
23.76
17.20
0.8
16.97
17.28
26.16
16.22
TABLE II. VRMS FOR DIFFERENT MODULATION INDICES
ma
UPD
UAPOD
UCO
UVF
1
212.6
211.8
217.4
212.4
0.95
201.6
201.7
209.2
200.3
0.9
190.6
190.9
199.9
189.5
0.85
179.6
180.3
190.2
179
0.8
169.6
169.3
178.7
168.3
In this paper, USPWM techniques for Trinary DC source
nine level inverter have been presented. Trinary DC source
multilevel inverter gives higher output voltage with low
harmonics. Performance factors like %THD, Vrms, CF and
FF have been evaluated presented and analyzed. It is found
that the UAPDPWM and UAPODPWM strategy provides
lower %THD, UCOPWM is found to perform better since it
provides relatively higher fundamental RMS output voltage.
Depending on the performance measure required in a
particular application of chosen MLI based on the output
quality appropriate PWM have to be employed.
REFERENCES
[1] C. Schauder and H. Mehta, "Vector analysis and control of
static VAR compensator," IEEE. Conf Proc. Generation,
Transmission, Distribution, 1993 pp.299-306.
[2] J.S Lai and F.Z.Peng, "Multilevel converters-a new breed of
power converters," IEEE Trans. Ind. Applicant., vol 32,pp.
509-517,1996
[3] J.Dixon and L.Moran, "Multilevel inverter, based on
multi-stage connection of three converters, scaled in power of
three," in proc.IEEE IECON, Seville, Spain, 2002,
pp.886-891.
[4] R.Seyezhai, B.L.Mathur, “Performance Evaluation of Inverted
Sine PWM Technique for an Asymmetric Cascaded Multilevel
Inverter,” Jou. of Theoretical and Applied Information
Technology (JATIT), pp-91-99, 2005-2009.
[5] Yu Lin and Fang Lin Luo,"Trinary hybrid 81 –level multilevel
inverter for motor drive with zero common –mode voltage", in
proc. IEEE Conf., 2007, pp 1-7.
[6] Geethalakshmi and DelhiBabu ,"Performance evaluation of
three phase cascaded H-bridge multilevel inverter based on
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ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 6, December 2012
multi carrier PWM techniques," in proc. International Conf. on
Advances in energy Research, 2007, pp-257-261.
[7] S. Krishna, “Harmonic Elimination by Selection of Switching
Angle and DC Voltages in Cascaded Multilevel Inverters”, in
proc. 15th National power system conference (NPSC), 2008, pp
119-124.
[8] Rajesh Gupta, Arindam Ghosh and Avinash Joshi, “Switching
Characterization of cascaded multilevel-Inverter-Controlled
Systems”, IEEE Trans. on Ind. Electrons, Vol.55, No.3, pp
1047-1058, 2008
[9] Rabiya Rasheed, “A Reduced Switch Multilevel Topology for
Drives Application”, in proc. 10th National Conf. on Techno.
Trends (NCTT09), 2009, pp 53-57.
[10] Rokan Ali Ahmed, S.Mekhilef, Hew Wooi Ping, “New
Multilevel Inverter Topology with Reduced Number of
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[11] C. R. Balamurugan,S. P. Natarajan, R. Bensraj” Investigations
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AUTHOR BIOGRAPHY
V.Arun was born in 1986 in Salem. He obtained
his B.Tech. degree in Electrical and Electronic
Engineering with distinction from SRM
University ,Chennai , India, and M.E. degree in
Power Systems Engineering with distinction from
Sona College of Technology, Salem, India in 2007
and 2009 respectively .In 2009, he joined the
Faculty of Electrical and Electronics Engineering,
Arunai Engineering College, Tirvannamali, India,
where he has been an Assistant Professor since
2009. He has presented 15 technical papers in various national /
international conferences. His research interests include power electronics,
multilevel inverters and digital power electronics.
B.Shanthi was born in 1970 in Chidambaram. She
has obtained B.E (Electronics and Instrumentation)
and M.Tech (Instrument Technology) from
Annamalai University and Indian Institute of
science, Bangalore in 1991 and 1998 respectively.
She obtained her Ph.D in Power Electronics from
Annamalai University in 2009.She is presently a
professor in Central Instrumentation Service
Laboratory of Annamalai University where she has
put in a total service of 20 years since 1992.Her
research papers (7) have been presented in various / IEEE international
/national conferences. She has 3 publication in national journal and 12 in
international journals. Her areas of interest are: modeling, simulation and
intelligent control for inverters.
A.Bharathi was born in 1988 in Vellore. She obtained
her B.E. degree in Electrical and Electronic Engineering
from Ganadipathy Tulsi Engineering College, Vellore
India in 2011, and pursuing her M.E. degree in Power
Electronics and Drives from Arunai Engineering
College, Tirvannamali, India. Her areas of interest are:
power electronics, multilevel inverters and converters.
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