FABRICATING SILICON THIN-FILM
TRANSISTORS ON PLASTIC AT 300oC
Kunigunde H. Cherenack
A DISSERTATION
PRESENTED TO THE FACULTY
OF PRINCETON UNIVERSITY
IN CANDIDACY FOR THE DEGREE
OF DOCTOR OF PHILOSOPHY
RECOMMENDED FOR ACCEPTANCE
BY THE DEPARTMENT OF
ELECTRICAL ENGINEERING
Adviser: Professor Sigurd Wagner
JANUARY 2009
© Copyright by Kunigunde H Cherenack, 2009
All rights reserved.
iii
ABSTRACT
It is not a trivial task to fabricate displays on plastic and significant challenges
arise when clear plastic is used to replace glass as the display substrate. The trend has
been to reduce the deposition temperature of amorphous silicon thin-film transistors (aSi:H TFTs) in the display backplanes on plastic but that results in a-Si:H TFTs with poor
stability under gate-bias stress. The goal of this thesis work has been to develop a hightemperature TFT process at 300oC on plastic to enable stable backplanes that are
competitive with backplanes fabricated on glass. After deposition at high temperatures
the strain in the device layers becomes very large, affecting the substrate dimension and
resulting in misalignment between consecutive mask layers. This problem needs to be
addressed when the goal is to develop a process suitable for large-area fabrication. We
have investigated back channel passivated and back-channel cut a-Si:H TFTs fabricated
on plastic at 300oC and have obtained TFTs with a stability under gate-bias stressing
equivalent to that of TFTs in commercial backplanes on glass. We looked at ways to
improve the effective device mobility by replacing the n+ doped a-Si:H material in the
source-drain contacts with nc-Si material. Next, we looked at ways to mitigate the impact
of misalignment at high temperatures that was caused by large strains built into the
substrate by device fabrication. We did this by implementing stress control and by
developing self-alignment methods between the gate, the channel passivation and the
source-drain terminals. Finally, we tested our fabrication in a circuit by fabrication ring
oscillators.
iv
ACKNOWLEDGEMENTS
First and foremost, I would like to thank my advisor Prof Sigurd Wagner, for his
unwavering support and encouragement. Under his guidance, I have grown both as a
researcher and a person – surely a student cannot ask for a better advisor!
I would also like to express my gratitude to Professor James C. Sturm and
Professor Claire Gmachl for constant collaborations and their enthusiasm, and Professor.
I-Cun Cheng and Professor Helena Gleskova for reviewing this thesis as well as their
kind and patient advice. Special thanks goes to the members of my research group who
have made working at Princeton enjoyable and eventful: Joyelle Jones, Prashant Mandlik,
Lin Han, Bahman Hekmatshoar, Yifei Huang, Noah Jafferis, Oliver Graudejus, and
Wenzhe Cao. I also thank my friends Asa Rennermalm, Medini Padmanabhan and all the
members of the Princeton Shotokan Karate club for providing a means to escape the
stress of lab-work. I am also especially grateful to the members of the cleanroom staff,
Joe Palmer and Mikhael Gaevski, as well as Conrad Silvestre, who assisted me with
many processing related questions.
Finally, I want to thank my family: my mother, Marianne Cherenack. who
instilled a love of learning in me and believed in me even when I didn’t, and my father,
Professor Paul Cherenack, for setting a shining example of how to be a great researcher
and a great human being. I also thank my sister Genoveva, who reminded me of what is
important in life when I disappeared into the cleanroom for too long.
v
Contents
Motivation ...................................................................................................................... 1
1.1 Introduction ............................................................................................................. 1
1.2 AMOLED displays .................................................................................................. 2
1.3 Required a-Si:H TFT properties ........................................................................... 4
1.4 Required substrate properties ............................................................................... 5
1.5 Thesis overview ....................................................................................................... 9
References .................................................................................................................... 10
INTRODUCTION TO a-SI:H TFTs ......................................................................... 12
2.1 Introduction ........................................................................................................... 12
2.2 a-Si:H TFTs ........................................................................................................... 12
2.3 TFT operation ....................................................................................................... 15
2.4 Improving a-Si:H TFTs device performance ..................................................... 17
2.4.1 a-Si:H TFT stability ......................................................................................... 17
2.4.2 TFT mobility .................................................................................................... 21
2.5 Conclusion ............................................................................................................ 23
References .................................................................................................................... 24
FABRICATING a-SI:H TFT CIRCUITS ON PLASTIC ....................................... 27
3.1 Introduction ........................................................................................................... 27
3.2 Misalignment between device layers ................................................................... 27
3.3 Reducing misalignment ........................................................................................ 29
3.4 Ring oscillators fabricated using a-Si:H TFTs ................................................... 32
3.5 Conclusion ............................................................................................................. 38
References .................................................................................................................... 39
DEPOSITION OF a-SI:H DEVICE LAYERS ON PLASTIC ............................... 41
4.1 TFT device layers .................................................................................................. 41
4.1.1 Deposition system ............................................................................................ 41
4.1.2 Hydrogenated amorphous silicon .................................................................... 44
vi
4.1.3 Doped amorphous silicon ................................................................................ 48
4.1.4 Doped nanocrystalline silicon .......................................................................... 48
4.1.5 Silicon nitride ................................................................................................... 49
4.1.6 Metal layers ...................................................................................................... 52
4.2 Developing a high temperature process on plastic............................................. 53
4.2.1 Origin of strain in inorganic device layers ....................................................... 53
4.2.2 Strain classification .......................................................................................... 55
4.2.3 Substrate curvature after film deposition ......................................................... 56
4.3 Determining built-in strain experimentally ........................................................ 58
4.4 Implication of strain for a high temperature a-Si:H TFT process ................... 61
4.5 Summary ................................................................................................................ 63
References .................................................................................................................... 64
CLEAR PLASTIC SUBSTRATES ........................................................................... 67
5.1 Introduction ........................................................................................................... 67
5.2 Substrate properties.............................................................................................. 68
5.2.1 Optical transmission......................................................................................... 68
5.2.2 Substrate surface properties ............................................................................. 71
5.2.3 Substrate cofficient of thermal expansion (CTE) ............................................ 74
5.2.4 Substrate glass transition temperature ............................................................. 77
5.3 Depositing SiNx barrier layers on clear plastic CP-2 and CP-3 at 300oC ........ 78
5.3.1 Adjusting SiNx built-in strain with RF deposition power at 300oC ................. 79
5.3.2 Adhesion between CP and SiNx films deposited at 300oC .............................. 82
5.3.3 Substrate loading and handling ........................................................................ 85
5.3.4 Substrate chemical resistance .......................................................................... 92
5.4 Optimized barrier layer deposition at 300oC on CP-2 and CP-3 ..................... 93
5.5 Summary ................................................................................................................ 95
References .................................................................................................................... 96
STANDARD a-SI:H TFTs FABRICATED AT 300oC ON CLEAR PLASTIC .... 97
6.1 Introduction ........................................................................................................... 97
6.2 Back-channel cut a-Si:H TFTs ............................................................................ 98
6.3 Back-channel passivated a-Si:H TFTs .............................................................. 103
6.4 Performance of a-Si:H TFTs fabricated on CP-2 at 300oC............................. 107
6.4.1 Electrical performance ................................................................................... 110
6.4.2 Threshold voltage stability............................................................................. 113
vii
6.5 Performance of a-Si:H TFTs fabricated on CP-2 at 350oC............................. 118
6.6 Decreasing the S/D parasitic contact resistance ............................................... 120
6.6.1 TFT performance with n+ a-Si:H and n+ nc-Si contacts ................................ 118
6.6.2 TFT performance with thick and thin a-Si:H layers ...................................... 123
6.6.2 Discussion of the measured increase of the electron field-effect mobility .... 125
6.7 Conclusion ........................................................................................................... 126
References .................................................................................................................. 126
DEVICE LAYER ALIGNMENT ............................................................................ 127
7.1 Introduction ......................................................................................................... 127
7.2 Strain control ....................................................................................................... 128
7.3 Implementing self-alignment ............................................................................. 132
7.3.1 Aligning the channel passivation layer to the gate (SA-1) ............................ 134
7.3.2 Aligning the source-drain layer to the gate (SA-2) ........................................ 145
7.3.3 Simplified process to align the source-drain layer to the gate (SA-3) ........... 158
7.4 Combining SA-1 and SA-3 self-alignment ........................................................ 166
7.5 Outlook................................................................................................................. 173
References .................................................................................................................. 175
A-SI:H RING OSCILLATORS ............................................................................... 176
8.1 Introduction ......................................................................................................... 176
8.2 Ring oscillator designs ........................................................................................ 177
8.3 Ring oscillator fabrication .................................................................................. 178
8.3.1 Fabricating ring oscillators using non-self-aligned back-channel cut TFTs .. 181
8.3.2 Fabricating ring oscillators using SA-1 self-aligned back-channel passivated
TFTs ........................................................................................................................ 182
8.3.3 Fabricating ring oscillators using SA-3 self-aligned back-channel cut TFTs 184
8.4 Oscillator performance ....................................................................................... 187
8.5 Outlook................................................................................................................. 194
CONCLUSION AND FUTURE WORK ................................................................ 195
References .................................................................................................................. 197
viii
APPENDICES A: PE-CVD DEPOSITION CONDITIONS ................................. 198
A.1 Back-channel cut TFT geometry, 300oC .......................................................... 199
A.2 Back-channel passivated TFT geometry, 300oC ............................................. 200
A.3 Back-channel cut TFT geometry, 250oC .......................................................... 201
A.4 Back-channel passivated TFT geometry, 250oC ............................................. 202
A.5 SiNx deposition rate at 300oC in the N-chamber ............................................. 203
A.6 n+ nc-Si deposition (layer-by-layer) .................................................................. 204
APPENDICES B: MEASUREMENT TECHNIQUES ......................................... 205
B.1 TFT parameter extraction ................................................................................. 206
B.2 Measuring TFT stability .................................................................................... 210
B.3 Measuring misalignment on our mask-set ....................................................... 212
B.4 Characterizing the n+ nc-Si layer ...................................................................... 212
B.5 Measuring ring oscillator performance............................................................ 216
References .................................................................................................................. 219
APPENDICES C: TFT FABRICATION PROCESSES ....................................... 220
C.1 Back-channel cut TFT geometry, non-self-aligned ......................................... 221
C.2 Back-channel passivated TFT geometry, non-self aligned ............................. 223
C.3 Back-channel passivated TFT geometry, back channel self-aligned , SA-1 226
C.4 Back-channel cut TFT geometry, S/D terminals self-aligned, SA-2 .............. 229
C.5 Back-channel cut TFT geometry, S/D terminals selfaligned, SA-3 ............... 232
C.6 SA-1 and SA-3 combined................................................................................... 235
APPENDICES D: RING OSCILLATOR PROCESSES ...................................... 238
D.1 Ring oscillator, back channel cut, non self-aligned ......................................... 239
D.2 Ring oscillator, back channel passivated, back-channel selfaligned ............. 241
D.3 Ring oscillator, back channel cut, source-drain terminals self-aligned ....... 244
D.4 Ring oscillator mask layout ............................................................................... 243
ix
PUBLICATIONS AND PRESENTATIONS AS A RESULT OF THIS WORK
..................................................................................................................................... 247
1
Chapter 1
MOTIVATION
1.1 Introduction
Flat-panel displays (FPDs) are becoming increasingly commonplace in
commercial handheld electronic devices such as flat-panel TV, desktop and laptop
computers, cellular phones, personal digital assistants (PDAs), and camcorders. The
leading commercial flat-panel displays are active-matrix liquid-crystal displays
(AMLCDs) [1]. However, displays based on active matrix organic light emitting diodes
(AMOLEDs) [2-5] have a large market potential [6]. Amorphous silicon (a-Si:H) thin
film transistors (TFTs) are the technology of choice for use in display backplanes (due to
their industrial accessibility and low fabrication cost over large area).
Handheld electronics require FPDs that are lightweight, portable, rugged, lowpower and high-resolution [7]. Currently, displays are fabricated on glass substrates but
displays fabricated on plastic substrates have the potential to be more rugged, lightweight
and cheaper if fabricated using a roll-to-roll process [8]. As a first step towards making
flexible displays we fabricated a-Si:H TFTs on plastic substrates. Commercial a-Si:H
TFT processes on glass substrates are optimized at deposition temperatures around 300350oC to reduce TFT instability [9] and our goal in this thesis was to transfer this 300oC
TFT fabrication process to plastic.
High processing temperatures result in large misalignment between various
device layers. To obtain functional device over large surface areas it becomes necessary
to either design photolithography masks with large tolerances, or implement self-
2
alignment methods [10,11]. This chapter will discuss the operational requirements of
AMOLED displays, and their implications for TFT performance. In section 1.2 we
discuss the operation of an AMOLED pixel, then in Section 1.3 we go on to discuss the
a-Si:H TFT requirements for integration into AMOLED backplanes. Section 1.4
describes the substrate properties that are necessary for implementing a 300oC process
and for developing a self-alignment method to eliminate misalignment between device
layers.
1.2 AMOLED displays
An AMOLED display consists of OLEDs that have been deposited onto a thin
film transistor (TFT) array to form a matrix of pixels that emit light upon electrical
activation. The threshold voltage of a-Si:H TFTs is unstable and shifts with an applied
gate voltage [12]. If the threshold voltage shift is not compensated by on-pixel and/or
external circuitry [13, 14] it has a direct impact on the brightness of the OLED.
The circuit schematic of a conventional AMOLED pixel [15] is shown in Figure
1.1 and the schematic cross-section is shown in Figure 1.2. To create this structure, nchannel a-Si:H TFTs are fabricated on the substrate at temperatures up to 300oC, then we
deposit an insulating, planarizing layer and etch vias down to the TFT contact pads.
Finally the OLED anode (consisting of patterned ITO) is deposited so that it is connected
to the TFT source terminal. Next a blanket layer of organic and a blanket cathode layer
are deposited on top of the anode. To select an individual display pixel a voltage,
VSELECT, is applied to the control TFT. The OLED will emit light when the data voltage,
VDATA, is pulsed high to charge the storage capacitor and the gate of the driving TFT. The
3
resultant high voltage at the gate of the driving TFT is converted into an OLED driving
current, IPIXEL. This current causes electrons to be injected into the OLED emissive layer,
which recombine with holes to emit light (phosphorescence).
VDD>0
VSELECT
CS
VDATA
IPIXEL
G
D
D
S
n-channel
control TFT
n-channel driving
TFT
G
S
OLED
GND
Figure 1.1 An illustration of a basic active-matrix AMOLED pixel [15]
Figure 1.2 Schematic cross-section of the conventional AMOLED structure of Fig. 1.1
4
1.3 Required a-Si:H TFT properties
Two important performance criteria that are used to evaluate a-Si:H TFTs in the
display backplane are their threshold voltage shift in response to a stress, ∆VTH, and the
electron field-effect mobility in the saturation regime, µSAT, and in the linear regime, µLIN.
Applying a voltage to a TFT gate causes the threshold voltage, VTH, to shift and is
known as gate-bias stressing [16, 17] (refer to Appendix B.2 for a description of our
specific gate bias stress test). This type of stress causes problems for TFTs used in
AMOLED display backplanes where voltages are routinely applied to the driving TFT
gate (shown in Figure 1.1) for long periods of time over the display lifetime. An increase
in the driving TFT VTH decreases the amount of current driving the OLED for a specific
applied driving voltage, and therefore decreases the OLED brightness. Even worse, since
individual TFTs may experience different amounts of ∆VTH, IPIXEL may vary from pixel
to pixel, leading to pixel brightness non-uniformly. In the structure shown in Figure 1.1
VDATA is applied across the gate-source of the driving TFT. This turns on the driving TFT
supplying current to the OLED. Therefore the OLED driving current depends on both the
characteristics of the driving TFT and OLED.
At present the stability of OLEDs is higher than that of a-Si:H TFTs. The time
over which the OLED luminance decays to 50% under constant current is defined as the
OLED half-life. Similarly we define the time over which the TFT current drops to 50% of
its initial value under constant voltage bias in saturation as the TFT half-life [18]. The
half-life of commonly used TFT's is less than a month (for a gate field of 2.5x105 V/cm)
while the luminance half-life of green (typically referred as standard color)
5
phosphorescent OLEDs is 100,000 hours (~12 years) for an initial luminance of
1000Cd/m2 [19]. Therefore the a-Si:H TFT stability limits the pixel life-time. For this
reason it becomes imperative to reduce ∆VTH for a-Si:H TFTs integrated into display
backplanes. High TFT mobilities are also important since TFTs with higher mobilities
will source larger currents to drive the OLED for a specific applied gate voltage
compared to TFTs with lower mobilities. Such TFTs can also allow bigger pixel
apertures since they can be designed to be smaller. Therefore displays that have highermobility TFTs need smaller applied voltages at the driving TFT gate to achieve a specific
OLED brightness, which has the effect of reducing the driving TFT ∆VTH caused by
normal circuit operation. In summary, to achieve longer OLED pixel lifetimes we require
a-Si:H TFTs that have high mobilities and low threshold voltage shifts.
1.4 Required substrate properties
The choice of flexible substrate is very important for developing a successful high
temperature a-Si:H TFT fabrication process. Table 1.1 summarizes some of the properties
of flexible substrates that are available for display fabrication. The most important substrate
property required to develop a high temperature process is the ability to withstand our
maximum processing temperatures of 300oC (i.e. a plastic glass transition temperature,
Tg>300oC ).
Next, it is important to have a substrate with a low coefficient of thermal
expansion (CTE) for minimizing the strain that develops in inorganic device layers
deposited on plastic substrates. When a series of inorganic layers is deposited on a plastic
6
substrate (as is the case when we deposit the TFT stack), the combined film-on-substrate
structure experiences a strain [20]. If the strain in the device layers exceeds a critical
value the layers will crack, delaminate and possibly deform the substrate. At high
deposition temperatures around 300oC the dominant strain component is the thermal
mismatch strain, εTH, caused by the mismatch in the coefficient of thermal expansion
(CTE) of the inorganic device layers and the organic plastic substrate. The thermal
mismatch strain that develops in inorganic device films deposited on plastic substrates is
described by the following equation [20]
TH = (CTEs – CTEf)  (Troom – Tdeposition).
- 1.1
where CTEs is the coefficient of thermal expansion [ppm/oC] for the substrate, CTEf is
the coefficient of thermal expansion of the film, Troom is the room temperature [oC] and
Tdeposition is the deposition temperature. Equation 1.1 can be used to calculate TH that
develops when a SiNx layer with CTE ~ 2ppm/oC is deposited on a plastic substrate as
follows: let us assume a deposition temperature Tdeposition of 300o C, a room temperature,
Troom, of 25oC, and deposit the film on Kapton®E and CP-2 plastic substrates. From
Table 1-1, the CTE of Kapton®E is 16ppm/oC and the CTE for CP-2 is 6 ppm/oC. This
results in a compressive thermal mismatch strain of 0.39% for SiNx deposition on
Kapton®E and 0.06% on CP-2. Therefore SiNx films deposited on Kapton will be more
likely to crack at 300oC than SiNx films deposited on CP-2. This discussion highlights the
fact that we require a substrate with a very low CTE to keep the strain in the combined
structure below a certain critical value at which the deposited films will start cracking.
7
Table 1.1. Summary of the material properties for various flexible substrates..
Substrate
Surface
Tg
CTE
Chemical
Dimensional
(°C)
(ppm/K)
Stability
Stability
Roughness Ra
[nm]
304 Stainless Steel
1400
18
Fair
High
>1000 (as rolled)
Thin Glass (Corning Eagle
2000)
600
2
High
High
4
Kapton® E Polyimide
300
16
High
Fair
2-5 (roll)
PEN (polyethylene naphthalate)
150
20-60
High
Low
1.5>
PET (polyethylene
terephthalate)
120
20-60
High
Low
2>
CP –1
312
4
Poor
Fair
14
CP – 2
339
6
Poor
Fair
14
CP – 3
379
4.5
Poor
Fair
14
Another consequence of high temperature deposition is strain-induced
misalignment between various mask layers when they are patterned using standard
photolithography. The origin and implications of misalignment will be discussed in detail
in Chapter 4. The key issue to understand is that large misalignment between device
layers forces designers to implement masks with very large tolerances to achieve
functional devices over a large surface area. The impact on displays is that the minimum
pixel size is increased, which decreases the achievable display aperture. A self-aligned
process can be used to pattern device layers as an alternative to standard
photolithography [10]. This can eliminate misalignment between critical mask layers,
8
enabling the design of displays with higher fill factors. The self-alignment techniques
used in this thesis all involve spinning a photoresist layer onto the front of the substrate
and exposing the resist through the back. Therefore, a critical requirement for
implementing these self-alignment techniques is to have a clear substrate.
To summarize substrate requirements: we need a substrate that can withstand a
process temperature of 300oC, has a low CTE and is optically clear. Flexible substrates
considered for display applications include thin glass substrates, metal and plastic foils.
Thin flexible glass substrates (with thicknesses less than ~100µm) and steel foils both
have low coefficients of thermal expansion and good chemical resistance. Unfortunately
both have disadvantages: glass substrates are fragile and hard to handle during processing
while steel foils are opaque and cannot be used together with through-substrate selfalignment methods. The surface of steel foil is also very rough and requires planarization
and electrical insulation. The advantage of using plastic foils is that they can be optically
clear, but they are generally dimensionally and chemically more unstable and this needs
to be considered when developing a fabrication process. The clear plastic (CP) used in
our process was designed to have a very low CTE, good optical clarity and a melting
point higher than 300oC. The CP underwent two major recipe changes during the
development of the 300oC process. Different recipes are labeled CP-1, CP-2 and CP-3.
The details on CP substrate characterization, handling and preparation for high
temperature processing are discussed in Chapter 5.
9
1.5 Thesis overview
Chapter 2 and 3 provide the theoretical background required for this work. Chapter 2
introduces a-Si:H TFT theory and performance. Chapter 3 focuses on the implication of
misalignment for the fabrication of a-Si:H circuits over large surface areas, and presents the
theory of the ring-oscillator circuits that we fabricated for this thesis. Chapter 4 discusses
deposition of the required TFT device layers, and the theory on how strain originates when the
inorganic device layers are deposited on plastic. Chapter 5 contains details on CP properties,
handling and barrier layer coating. Then in Chapter 6 we discuss the non-self-aligned (standard)
the back-channel cut and back-channel passivated TFT fabrication processes and measured
device performance. In Chapter 7 we present the self-alignment processes that we developed to
eliminate the large misalignment in the TFT channel regions for standard fabrication processes.
Then Chapter 8 provides details on the a-Si:H ring oscillator circuits that we fabricated. Finally,
Chapter 9 provides an outlook on ongoing and future work that arises from this thesis work.
10
REFERENCES
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[5] A. Nathan, D. Striakhilev, P. Servati, K. Sakariya, A. Kumar, K.S. Karim, and A.
Sazonov, “Low Temperature a-Si:H Pixel Circuits for Mechanically Flexible AMOLED
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[6] M. Hack, M. H. Lu, R. Kwong, M. S. Weaver, Y-J. Tung, A. Chwang, and J. J.
Brown, “High efficiency phosphorescent OLED technology”, 16th Annnual Meeting of
the IEEE LEOS, vol. 2, pp. 531-532, 2003
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Topical Meetings, pp.36-37, 1995
[8] R. F. Service, “Patterning Electronics on the Cheap”, Science, vol. 278, pp. 383‐384,
1997
[9] C. Blaauw, “Preparation and characterization of plasma-deposited silicon nitride”, J.
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no. 3, pp. 166-168, 2006
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51, pp. 1242–1244, 1987
11
[13] J. C. Goh, J. Jang, K. S. Cho and C. K. Kim, "A new a-Si:H thin-film transistor pixel
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no. 9, pp. 583-585, 2003.
[14] S. Jafarabadiashtiani, G. Chaji, S. Sambandan, D. Striakhilev, P. Servati, and A.
Nathan, “A New Driving Method for a-Si AMOLED Displays Based on Voltage
Feedback”, Dig. of Tech. Papers, SID Int. Symp., pp. 316-317, 2005
[15] B. Hekmatshoar, A. Z. Kattamis, K. H. Cherenack, S. Wagner and J. C. Sturm, “A
Novel TFT-OLED
Integration for OLED-Independent Pixel Programming in
Amorphous-Si AMOLED Pixels”, Journal of the SID, vol. 16, no. 1, pp. 183-188, 2008
[16] K. H. Cherenack, A. Z. Kattamis, J. C. Sturm and S. Wagner, “Amorphous-Silicon
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Plastic”, IEEE Electron Dev. Lett., vol. 28, no. 11, pp. 1004-1006, 2007
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[19] http://www.universaldisplay.com/default.asp?contentID=604
(download : Sept 2008)
[20] S. Wagner, H. Gleskova, I-C. Cheng, J. C. Sturm, and Z. Suo, “Mechanics of
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Crawford, Ed. Wiley, pp. 263 – 282, 2005
12
Chapter 2
INTRODUCTION TO a-SI:H TFTs
2.1 Introduction
This chapter introduces basic concepts required for understanding a-Si:H TFT
performance and design considerations. Section 2.2 introduces TFT structures, which is
followed by a discussion of TFT device operation in section 2.3. Then we look at TFT
stability (section 2.4.1) and TFT mobility considerations (section 2.4.2) which are the
main parameters used later in this thesis to compare the performance of various TFTs.
2.2 a-Si:H TFTs
The first a-Si:H TFTs were fabricated in 1981 by Snell, Mackenzie, Spear,
LeComber, and Hughes [1] and independently by H. Hayama and M. Matsumura [2].
Thin film transistors (TFTs) are a special kind of field effect transistor made by
depositing thin films of a semiconductor active layer as well as a dielectric layer (for our
a-Si:H TFTs this is usually silicon nitride, SiNx) and metallic contacts on a substrate.
These layers are selectively etched away to create the desired structure. a-Si:H TFTs
operate as n-channel, accumulation mode devices where the channel is formed at the
interface between the SiNx and the a-Si:H semiconductor.
TFTs can be made using a variety of semiconductor materials, but the most
common material is silicon. The characteristics of silicon based TFTs depend on the
crystalline state of the semiconductor layer which can be either hydrogenated amorphous
13
Single-crystalline
silicon
Poly-crystalline
silicon
Amorphous
silicon
Figure 2.1 An illustration of the microstructure of the three silicon materials (not to scale)
[3]
silicon (a-Si:H), nanocrystalline silicon (nc-Si), polycrystalline silicon (p-Si) or
crystalline silicon (c-Si) [3, 4]. The maximum achievable mobility of silicon based TFTs
increases with increasing grain size of the semiconductor layer. The lowest mobilities are
obtained for TFTs made from a-Si:H since it has no long range atomic order, and many
trapping states, limiting electron field-effect mobilities to around 1 cm2/Vs [4]. At the
other end of the spectrum transistors fabricated on single-crystal c-Si have electron and
hole mobilities up to 600 cm2/Vs [5].
Schematic microstructures of the three material types are shown in Fig. 2.1. The
high defect density in amorphous silicon largely prevents the formation of an inversion
layer. Therefore the fabrication of depletion mode a-Si:H TFTs results in devices with
very low mobilities, although depletion mode a-Si:H TFTs with mobilities of up to 0.4
cm2/Vs have been reported [6]. Since the mobility of holes in amorphous silicon is lower
than that of electrons by about a factor of 100 no p-channel a-Si:H TFTs are made for
commercial applications [7]. In this thesis work, all a-Si:H TFTs function as n-type
14
Cr/Al/Cr drain electrode
n+ a-Si
SiNx channel
passivation
Cr/Al/Cr source
electrode
n+ a-Si
a-Si channel layer
SiNx gate dielectric
Cr/Al/Cr gate
electrode
SiNx barrier layer
(front)
SiNx barrier layer
(back)
Figure 2.2 a-Si:H TFT structures: (a) back-channel cut, bottom-gate staggered sourcedrain, (b) back-channel passivated
accumulation mode transistors. Hydrogen is usually added to the source gasses during
amorphous silicon deposition to passivate dangling bonds in the bulk a-Si:H thin film and
at the interface between the a-Si:H layer and the SiNx gate dielectric. This increases the
measured TFT effective electron mobility, and decreases the subthreshold slope and the
threshold voltage [8].
a-Si:H TFTs can be fabricated using various geometries but the bottom-gate
geometry shown in Figure 2.2 is preferable due to enhanced electrical performance and
device stability. Two commonly used variations are the back-channel etched (Figure
2.1a) and the back-channel passivated configuration (Figure 2.2b). More complicated
geometries include vertical a-Si:H TFTs with extremely short channels to compensate for
15
the low mobility of a-Si [9], or a double gate structures which can create dual channels
and double the on-current [10, 11]. These geometries are not commonly used because of
fabrication complexity and large OFF currents in the case of vertical a-Si:H TFTs.
The back-channel cut, bottom-gate structure in Figure 2.2 (a) needs the least
amount of photolithographic mask steps, and is the simplest structure to fabricate. The
disadvantage with this structure is that the amorphous silicon layer is exposed to the
environment and can be damaged during subsequent plasma processing steps, leading to
back-channel formation and an increased TFT off-current [12]. This can be avoided by
using the slightly more complicated structure shown in Figure 2.2 (b) in which a top SiNx
layer is deposited on top of the a-Si:H layer to passivate the TFT channel. This is known
as a back-channel passivated TFT. Another benefit of using a back-channel passivated
structure is that it allows us to decrease the thickness of the a-Si:H active layer which
helps to decrease the S/D contact resistance (as discussed in section 2.4.2). The
disadvantage with a back-channel passivated geometry is that it is harder to get a good
contact between the a-Si:H layer and the n+ doped layer. If care is not taken during
fabrication, a high-resistance between these two layers will degrade device performance
[13].
2.3 TFT operation
a-Si:H TFTs function similar to accumulation mode metal-oxide-semiconductor
field-effect-transistors (MOSFETs) and can be modeled and evaluated using the same
theory [14]. In the ON state, a positive voltage is applied to the gate, attracting electrons
that form a conducting channel at the interface between the dielectric and semiconductor
16
layers. During the OFF state the density of electrons in the channel is at it’s lowest
possible value and the OFF current is set by the intrinsic conductivity of the undoped
active layer. The TFT performance is divided into two regimes: linear and saturation.
When the drain-source voltage, VDS, is much less than the gate-source voltage, VGS,
minus the threshold voltage VTH (VDS << VGS – VTH), the TFT is operating in the linear
regime. When VDS > VGS – VTH, the transistor is in saturation, independent of VDS. The
drain-source current IDS can be modeled as follows [14]:
Linear: I DS 

V2 
W
μ LIN Ci (VGS  VTH )VDS  DS  for 0  VDS  VGS  VTH
L
2 

Saturation: I DS 
W
μ SAT Ci (VGS  VTH ) 2 for VDS  VGS  VTH ,
2L
where
Ci 
ε SiNX
t SiN X
- 2.1
.
where W is the TFT channel width, L is the channel length, μLIN is the electron mobility
measured in the linear regime, Ci is the capacitance per unit area for the SiN x layer, VGS
is the voltage applied between the gate and the source terminal, VTH is the threshold
voltage, VDS is the voltage applied between the drain and source terminals, μSAT is the
electron mobility measured in the saturation regime, εSiN X is the dielectric constant of the
SiNx layer and t SiN X is the thickness of the SiNx layer. The important TFT parameters to
characterize device performance are: threshold voltage (VTH), linear and saturation
electron field-effect mobility (µLIN and µSAT), the ON to OFF current ratio (ION/IOFF) and
the sub-threshold slope (S). All of the TFT parameters mentioned above can be calculated
using a “transfer characteristic” which is a semi-log plot of IDS and IGS versus VGS for a
17
constant applied VDS of 0.1V and 10V. The method we use to measure transfer
characteristics and extract the TFT performance parameters is described in Appendix B.1
2.4 Improving a-Si:H TFT device performance
As discussed in Chapter 1, the two TFT performance parameters that we use to
evaluate our TFTs are their stability (evaluated by measuring ∆VTH) and their electron
field-effect mobility in the linear and saturation regime, μ LIN and μSAT . In section 2.4.1
we discuss the origin of ∆VTH. Section 2.4.2 discusses various components of the device
structure that can impact the measured electron field-effect mobilities, and how we can
design our process to increase the measured mobility in our devices. In our thesis we
carry out a series of gate-bias stress tests to determine ∆VTH as discussed in Appendix
B.2. The electron mobility is extracted from TFT transfer characteristic measurements as
described in Appendix B.1.
2.4.1 a-Si:H TFT stability
The two widely accepted mechanisms for threshold voltage instability in a-Si:H
TFTs are creation of metastable defects in the a-Si:H channel layer and charge trapping in
the SiNx gate insulator [15-17], as well as at the interface between the a-Si:H channel and
the insulator [18-20]. Defect creation dominates at low positive gate bias voltages. In this
situation charge is trapped in electron states that are produced when excess electrons
react with weak Si-Si bonds to create dangling bonds [21]. Charges trapped in newly
created dangling bonds in the a-Si:H channel and charge trapped in the SiNx insulator
both shift VTH. We now discuss these two mechanisms in more detail.
18
When a positive bias is applied to the gate of an a-Si:H TFT, electrons accumulate and
form a channel at the a-Si:N /a-Si:H interface where they predominantly reside in
conduction band-tail states [22]. These tail states have been identified as weak silicon–
silicon bonds which, when occupied by electrons, can break to form silicon dangling
bonds (deep-state defects) [23, 24] as shown in Fig. 2.3. The negatively charged dangling
bonds act as fixed charges in the middle of the band-gap, as illustrated in the banddiagram in Figure 2.4. In the figure at the left, the solid lines indicate the position of the
energy bands before the bias stress. After applying a bias stress the new negatively
charged defect states caused by bond breaking decrease the bending of the bands, as
shown by the solid lines in the figure at the right. The rate of deep-state defect creation is
a function of the barrier to defect formation, the number of electrons in the tail states, and
density of the weak bond sites.
It has been proposed that deep-state defect creation is characterized by a power
law time dependence and is strongly affected by temperature [25]. For the defect state
creation mechanism in a uniform a-Si:H TFT channel, the threshold voltage shift ∆VTH
can be expressed as [4, 23]
∆VTH(t) = A(VGS-VHTi )tβ
- 2.2
where A and β are temperature-dependent parameters, VGS is the gate bias stress voltage,
VTHi is the threshold voltage of the TFT before the bias stress is applied and t is the bias
stress time duration.
19
Figure 2.3 An illustration of the creation of dangling bond defects. The bidirectional
arrows signify that this process can either create or annihilate dangling bonds (Courtesy
of Bahman Hekmatshoar)
Figure 2.4 A band diagram of the SiNx/a-Si:H interface before and after defect state
creation. D- designates negatively charged dangling-bond defects in the middle of the aSi:H band gap [26]
Figure 2.5 A band diagram of the SiNx/a-Si:H interface before and after charge injection
into the SiNx [27]
20
In contrast, at high gate voltages, charge is injected from the a-Si:H channel into
the gate insulator near the interface. This situation is shown graphically in Figure 2.5.
The solid lines in the figure on the right indicate the position of the energy bands after the
bias stress and the dashed lines indicate the position of the bands before charge injection.
The TFT threshold voltage shift due to charge trapping in the insulator is described by the
stretched-exponential equation [17]:

| V TH (t ) || Vo | (1  e (t /  ) )
- 2.3
where Vo approximates the effective voltage drop across the insulator,    o e E / kT
represents the characteristic trapping time of carriers where the thermal activation energy
is given by Ea=Eτβ. Here β is the stretched-exponential exponent and τo is the thermal
prefactor for emission over the barrier. In this model, Eτ =Ea/β in equation 3 is the
average effective energy barrier that carriers in the a-Si:H channel need to overcome
before they can enter the insulator. As a result of increased band-bending due to both
defect state creation at the mid-gap of a-Si:H and charge injection into the gate insulator,
a larger gate voltage is needed to create the inversion layer at the interface and turn the
TFT on. Therefore the TFT threshold voltage increases (i.e. if the TFT transfer
characteristic before and after a gate stress is plotted on the same set of axes, the transfer
characteristic after bias stress is shifted to the right).
The work presented in this thesis is focused on improving the TFT stability by
depositing high quality SiNx at elevated temperatures on plastic – i.e., we are improving
the device stability at high applied gate voltages.
21
2.4.2 TFT mobility
The transport properties of amorphous semiconductors such as a-Si:H differ from
those of crystalline semiconductors by having lower charge carrier densities and shorter
mean free paths due to disorder. The time-of-flight technique can be used to study charge
transport a-Si:H. In this experiment electrons and holes are generated at the surface of the
sample by a short flash of light and charge carriers are pulled across the thickness of the
sample by an applied field, generating a displacement current. The mobility of electrons
in the undoped a-Si:H was measured using time-of-flight measurements at 1 to 2 cm2/Vs
[28, 29].
However, the measured electron field-effect mobility in TFTs can be much lower.
The reason for this is that the resistance between the source/drain (S/D) terminals is not
only made up of the resistance in the channel, RCH, but also includes a parasitic
resistance, RP/2, at each of the terminals. Figure 2.6 shows a schematic of the resistance
path between the S/D terminals. The
Gate
Source
Source
Drain
Drain
Figure 2.6 Schematic of the resistance path between the S/D terminals of an a-Si:H TFT
22
measured mobility is reduced from the true field-effect mobility by the parasitic
resistance at terminals since part of the voltage applied across the terminals is applied
across the parasitic resistance and not the channel region. This is particularly true for
short channel devices where the parasitic resistance makes up a larger percentage of the
total resistance between the source-drain contacts, and a larger portion of the applied
voltage between the S/D terminals drops across these parasitic resistances. This leads to a
decrease in the measured effective field effect mobility, which is especially noticeable for
TFTs with short channels.
RP is influenced by many geometrical or extrinsic factors such as the a-Si:H
thickness [30,31], source/drain to gate overlap [32], and source/drain (S/D) contact
quality [33]. The parasitic resistance can be broken down into (1) the contact resistances
(between the source/drain metal and the n+ a-Si:H layer) and n+ a-Si:H film resistance;
(2) the bulk resistance (due to the intrinsic a-Si:H layer between the n+ a-Si:H and the
conducting channel; (3) the resistances associated with the overlap between the
source/drain and gate electrodes. We aimed at increasing the measured mobility by
reducing the parasitic resistance. This was done (i) by decreasing the thickness of the aSi:H layer channel layer, and (ii) by replacing the n+ doped a-Si:H layer in the contacts
with a n+ doped nanocrystalline silicon (n+ nc-Si:H) layer.
23
2.5 Conclusion
This chapter discussed the fundamental concepts required to understand a-Si:H
TFT performance and evaluation criteria. Chapter 3 will introduce the concepts that
become important when we consider fabricating circuits from individual devices to cover
a large surface area. We will also discuss the theory of a-Si:H ring oscillator circuits and
design implications for these types of oscillator circuits.
24
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Electrochem. Soc. Proc. Thin Film Transistor Technologies IV, vol. 98-22, pp. 191197, 1999
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Mobility in Laser Crystallized LT poly-Si TFTs”, Proc. ASID’99, pp 293-299, 1999
[14] A. Neamen, “Semiconductor physics and devices”, Boston: IRWIN, 1992
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[15] M. J. Powell, “Charge trapping instabilities in amorphous silicon–silicon nitride
thin-film transistors”, Appl. Phys. Lett., vol. 43, no. 6, pp. 15–17, 1983
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vol. 51, pp. 1242–1244, 1987
[17] F. R. Libsch and J. Kanicki, “Bias-stress-induced stretched-exponential time
dependence of charge injection and trapping in amorphous silicon thin-film
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[18] S. C. Kim, S. Bae, E. Oh, and J. H. Kim, “Effects of N2 Plasma Treatment on SiO2
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775-780, 1994
[19] B. S. Sahu, A. Kapoor, P. Srivastava, O. P. Agnihotri and S. M. Shivaprasad,
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[21] R. A. Street and C. C. Tsai, “Fast and slow trapping states at the interface of
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[22] T. Leroux, “Static and dynamic analysis of amorphous silicon thin film transistors”,
Solid State Electron., vol. 29, pp. 47–58, 1986
[23] W. B. Jackson and M. D. Moyer, “Creation of near interface defects in hydrogenated
amorphous silicon–silicon nitride heterojunctions: the role of hydrogen”, Phys. Rev.
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removal of dangling-bond states in amorphous silicon thin-film transistors,” Appl.
Phys. Lett., vol. 60, no. 2, pp. 207–209, 1991
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pool model in amorphous silicon thin-film transistors,” Phys. Rev. B, Condens.
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26
[26] C. van Berkel, “Amorphous and Microcrystalline Semiconductor Devices” in
Amorphous and Microcrystalline Semiconductor Devices, Vol. II, Artech House,
Boston, pp. 397 – 447, 1992
[27] W. Kruhler, H. Pfleiderer, R. Plattner, and W. Stetter, “Optical effects in amorphous
semiconductors”, AIP Conference Proceedings, vol. 120, pp. 311-317, 1984
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drift mobility in hydrogenated a-Si”, Appl. Phys. Letters, vol. 36, no. 8, pp. 695-697,
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[29] R. A. Street, “Measurements of depletion layers in hydrogenated amorphous
silicon”, Phys. Rev. B, vol. 27, pp. 4924 – 4932, 1983
[30] P. G. LeComber, “Present and future applications of amorphous silicon and its
alloys”, J. Non-Cryst. Solids, vol. 115, no. 1, pp. 168-170, 1989
[31] H. H. Busta, J. E. Pogemiller, R. W. Standley, and K. D. Mackenzie, “Self-aligned
bottom-gate sub-micrometer-channel-length a-Si:H thin-film transistors”, IEEE
Trans. Electron Dev., vol. 36, pp. 2883-2888, 1989
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[33] H. F. Bare and G. W. Neudeck, “Formation of source and drain regions for a-Si:H
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27
Chapter 3
FABRICATING a-Si:H TFT CIRCUITS ON PLASTIC
3.1 Introduction
This chapter introduces concepts that impact the design of large-area a-Si:H TFT
circuits on plastic for processes that use high deposition temperatures. The biggest
concern for such circuits is how to deal with the misalignment between various mask
layers. In this chapter we discuss the origin of such misalignment and how self-alignment
methods can be used to eliminate misalignment. We also discuss the theory of a-Si:H ring
oscillator circuits which were used in this thesis to demonstrate a-Si:H TFT circuits.
3.2 Misalignment between device layers
Since our long-term goal is to enable roll-to-roll fabrication we are working with
free-standing substrates. To obtain functional devices on free-standing plastic substrates,
the mechanical stress in the workpiece needs to be designed carefully [1, 2]. The origin of
stress in inorganic device layers deposited on plastic and how it can be adjusted by
changing deposition conditions, is discussed in detail in Chapter 4. Even if the deposited
device layers are crack-free, the stress in the TFT stack causes the substrate to expand or
contract (depending on the nature of the combined strain of the total structure), resulting
in misalignment between consecutive mask layers. Misalignment is defined by Δ  106 x
d/λ [ppm]. In this equation d is the local misalignment between the alignment mark in the
bottom layer (patterned before device layer deposition) and the alignment mark in the top
layer (patterned after device layer deposition) and λ is the distance from the center of the
substrate to the center of the alignment mark. Figure 3.1
28
Center of substrate
(Top and bottom
alignment marks
overlap)
λ
Bottom alignment
mark
d
Top alignment
mark
Figure 3.1 Schematic indicating where d and λ are measured to calculate the degree of
misalignment between mask layers (not to scale)
shows a schematic of a substrate before and after misalignment, indicating where d and λ
are measured. The detailed process that was used to measure misalignment on our masksets is discussed in Appendix B.3.
For TFTs this misalignment has the following implication: if the device layers
delineating the TFT channel do not overlap the TFT will not turn on. The critical overlap
for back-channel cut TFTs (Figure 2.2a) is between the gate electrode and the S/D
electrodes. For back-channel passivated TFTs (Figure 2.2b) there are two critical
overlaps: 1) between the channel passivation and the gate electrode, and 2) between the
S/D electrode terminals and the gate electrode. The critical overlaps which are necessary
for the TFT to function are indicated in Figure 3.2 which shows a top view of a backchannel passivated TFT.
29
Gate via
Gate electrode
a-Si:H layer
Overlap 1: Overlap between the
channel passivation and gate electrode
S/D electrode
Channel
passivation
Overlap 2: Overlap between S/D electrode and gate
Figure 3.2 Schematic of a back-channel passivated TFT (top view) indicating the two
critical overlaps: 1) between the gate and the channel passivation and (2) between the
gate and the S/D electrode
3.3 Reducing misalignment
Our technique for reducing the misalignment between device layers is minimizing
the total strain in the substrate. This is done by adjusting deposition conditions to reduce
the total stress in the workpiece [3], as will be discussed in Chapter 4. At high
temperatures it is often not possible to reduce the total strain sufficiently using this
method, since the thermal mismatch strain εTH becomes very large. Therefore it becomes
necessary to investigate alternative methods to reduce the misalignment. These methods
include laminating or electrostatically bonding the substrate to a stiff carrier plate [4],
clamping the substrate into a rigid frame [5], or digitally compensating the masks for
substrate distortion [6].
30
Alternatively, it is possible to develop self-alignment methods which would
eliminate overlay misalignment completely. Self-alignment is a broad term, covering
various methods used to pattern the top device layer in lieu of standard photolithography.
Different processes that have been attracting attention include ion implantation followed
by laser annealing [7], chromium silicide formation [8] and back-side exposure of the
photoresist [9]. The distinguishing feature of self-alignment methods is that they involve
the use of a previously patterned device layer as a mask to pattern a subsequent device
layer. This is in contrast to a standard photolithographic process where patterns are
transferred from a rigid glass mask to the top device layer on the substrate. Usually the
device layers that act as „masks‟ in self-alignment processes are metal layers, such as the
patterned gate electrodes in bottom-gate TFT structures. However, in self-alignment
methods requiring back-side exposure of the photoresist any layer that blocks the
transmission of UV light (for example thick layers of a-Si:H) can serve as a mask for
self-alignment.
In the past, our group has demonstrated using self-alignment to align the channel
passivation to the gate-electrode for back-channel passivated TFTs fabricated on clear
plastic at 200oC [9]. The schematic of the self-alignment step is shown in figure 3.3. The
first step in this process is to deposit and pattern a layer of metal on top of the substrate to
form the gate electrode. Next we deposit a TFT stack – in the case of the back-channel
passivated TFT this stack consists of a SiNx gate dielectric, a thin a-Si:H active layer and
a second SiNx layer for the channel passivation. Then a layer of photoresist is spun onto
the front of the substrate and exposed from the back. Since the metal blocks UV light,
31
Area of photoresist that
is not exposed
Photoresist
Gate
TFT stack
Front of
substrate
Back of
substrate
UV radiation
radiationradiation
Fig. 3.3. Schematic illustrating how the top SiNx channel passivation layer for backchannel passivated TFTs is self-aligned using back-exposure
parts of the photoresist directly over the metal will not be exposed while all other parts
are exposed and can be removed by subsequent development. Therefore the pattern in the
photoresist (which is used to pattern the SiNx channel passivation layer) is entirely
determined by the position of the metal gates. Even if the gates shift from their original
position, due to changes in substrate/device layer strain, the channel passivation layer will
still be perfectly aligned to the gate.
The details of the self-alignment processes that we developed between various
device layers for our 300oC process are presented in Chapter 7. The next subsection
covers the theory of a-Si:H TFT ring oscillators.
32
3.4 Ring oscillators fabricated using a-Si:H TFTs
In this thesis, we used ring-oscillators fabricated using the various 300oC
processes which we developed. An oscillator is a basic unit for circuits requiring an exact
operating frequency. Since the electron mobility in a-Si:H TFTs is relatively low
(compared, for example, to c-Si TFTs) oscillators made from a-Si:H TFTs will only
operate in the low kHz range [10]. However there is an increasing interest in such lowfrequency applications since a-Si:H TFTs can be used to fabricate low-cost circuits. One
potential application for low-frequency oscillators are their integration into radio
frequency identification (RFID) tags. At low frequencies (below several hundred kHz)
RFID can be used for an inexpensive system as access control [11].
VDD
Load TFT
VOUT
VIN
Driver TFT
GROUND
Figure 3.4: A single inverter stage
33
Ring oscillators are composed of an odd number of inverters whose output
oscillates between two voltage levels. A single inverter stage consists of a two n-type aSi:H TFTs connected as shown in Figure 3.4. The gate and drain of the top TFT in the
inverter are connected to the power supply voltage to form an active load. This TFT is
known as the load TFT. The bottom TFT is called the driver TFT.
To form the ring oscillators the inverter stages are attached in a chain where the
output of the last inverter is fed back into the input of the first inverter (as shown in
Figure 3.5) [12]. For an odd number of inverters connected into a row, the signal at the
input of the first stage is inverted at the output of the last stage. For example, if we
assume a „high‟ input at the input to the first inverter stage, it will be changed to a „low‟
value at the output of the last inverter stage (which is again connected to the input of the
first stage). The reason that the output of ring oscillator starts to oscillate is due to the fact
that no gate can switch instantaneously. The TFTs gate capacitance needs to be charged
before current can flow between the source and the drain, turning on the TFT switch.
Therefore, the output of every inverter of a ring oscillator changes a finite amount of time
after the input has changed.
34
VDD
VOUT
GROUND
GROUND
Figure 3.5: Circuit schematic of a 5 stage ring oscillator, including an output buffer.
Ring oscillators can be modeled as an inverting amplifier with a time delay
element between the amplifier output and its input. Consider the initial case where the
amplifier input and output voltages are momentarily balanced at a stable point. A small
amount of noise can cause the amplifier output to rise slightly, and after passing through
the time delay element this small output voltage change will appear at the amplifier input.
With an amplifier that has a negative gain of greater than 1 the output will change in the
direction opposite to this input voltage with a gain larger than 1. This amplified, reversed
signal again propagates from the output through the time delay and back to the input,
where it is amplified and inverted yet again. The oscillation will grow until the amplifier
output voltage reaches its limits, where it will stabilize.
35
VDD = 15V
9 Stages
Period
Delay per Stage
(a)
VDD = 15V
9 Stages
Vhigh
Amplitude
Vlow
(b)
Figure 3.6 (a) The propagation delay time and (b) the output amplitude of a 9 stage ring
oscillator with different β values, measured for an applied power supply voltage of 15V
[10]. VDD is the power supply voltage. Vlow is the lowest output voltage swing and Vhigh
is the highest output voltage swing.
36
An important oscillator geometry design parameter for the inverters in oscillator circuits
is β, which is the ratio of the W/L of the load TFT to the W/L of the driver TFT as
follows:
β = (WDRIVER/LDRIVER) / (WLOAD/LLOAD)
- 3.1
It has been proved that the amplitude and propagation delay time through each inverter
stage decrease as the β ratio decreases. Figure 3.6 (a) shows the effect of changing the
oscillator β value [10]. From this 3.6(a) it would seem that we require low β values in our
design to have high-frequency ring oscillators. However, from Figure 3.6(b) we can see
that the output amplitude of our oscillators decreases for low β values. Therefore
oscillator designs must strike a compromise when choosing the β value to achieve a high
oscillation frequency while maintaining acceptable output amplitude swings.
The oscillation frequency f OSC of an N-stage ring oscillator is given by by [13]
f OSC 
1
2 N
-3.2
where  is a propagation delay of one inverter stage. The propagation delay, or the time
one inverter stage needs to switch from high to low or low to high, is proportional to the
output capacitance COUT driven by the inverter. In the ring oscillator, the TFT gate
capacitances of the following inverter stage constitute the major contribution to COUT.
Therefore,
  COUT
- 3.3
and
f OSC 
1
COUT
- 3.4
37
Consequently, to achieve high oscillation frequency, COUT must be minimized.
For TFTs fabricated using standard lithography, it is necessary to design a large
overlap between the channel and the S/D to tolerate the misalignment between
lithography steps. This results in a large parasitic capacitance (Coverlap) between the S/D
electrodes and the gate and reduces the speed at which TFTs can switch from the off-state
to the on-state (and vice versa). The reason for this is that Coverlap caused by the S/D
overlap needs to be charged or discharged before the TFT can turn on/off. To put
numbers to this discussion, let us compare COUT for a TFT that has a 1µm S/D overlap
with the gate, with COUT for a TFT that has a 10µm S/D overlap with the gate. For the
sake of this argument let us assume that Coverlap is the major contributor to COUT (i.e. COUT
≈ Coverlap). Using the equation COVERLAP   SiNx A / d where  SiNx is the SiNx dielectric
constant, A  W  X is the area of the S/D overlap with the gate, W is the channel width,
X is the length of the S/D overlap, and d is the thickness of the gate dielectric we can
calculate the ratio of C(X=20µm)/C(X=1µm) = 20/1. Therefore Coverlap for a TFT with
X=20 µm is 20 times larger than that of a TFT with X=1µm. Therefore if we compare
the oscillation frequencies of a ring oscillator made from a-Si:H TFTs with a S/D overlap
of 20µm to the oscillation frequency of a ring oscillator with TFTs that have a S/D
overlap of 1µm, we will find that the frequency for the oscillator made from TFTs with a
1µm overlap should be 20x faster than that for a ring oscillator using TFTs with a 20µm
S/D overlap!
From a high-speed circuit performance perspective it is therefore desirable to selfalign the a-Si:H TFT S/D terminals to the gate, as demonstrated by [14]. In this work the
authors demonstrate that, by reducing the large parasitic capacitances at the overlap
38
between the S/D terminals and the gate, they were able to raise the operating frequency of
their a-Si:H TFT oscillators by as much as 35%.
3.5 Conclusion
This chapter discussed the implication of fabricating a-Si:H TFT circuits at
elevated temperatures over large areas on plastic substrates. We now turn to the material
properties of the clear plastic substrates and device layers used in our process to fabricate
a-Si:H TFTs at 300oC. Chapter 4 will discuss the deposition of TFT device layers, and
how the deposition conditions affect the crack-free deposition of inorganic device layers
on plastic at high temperatures.
39
REFERENCES
[1] S. Wagner, H. Gleskova, I-C. Cheng, J. C. Sturm, Z. Suo, “Mechanics of TFT
Technology on Flexible Substrates”, in Flexible Flat Panel Displays, G. P. Crawford,
Ed. Wiley, pp. 263 – 282, 2005
[2] H. Gleskova, I-C. Cheng, S. Wagner, J. C. Sturm and Z. Suo, “Mechanics of thin-film
transistors and solar cells on flexible substrates”, Solar Energy, vol. 8, no. 6, pp. 687693, 2006
[3] I-C. Cheng, A. Z. Kattamis, K. Long, J. C. Sturm, and S. Wagner, “Stress control for
overlay registration in a-Si:H TFTs on flexible organic-polymer-foil substrates”, J.
Soc. Inf. Disp., vol. 13/7, pp. 563-568, 2005
[4] F. Lemmi, W. Chung, S. Lin, P. M. Smith, T. Sasagawa, B. C. Drews, A. Hua, J. R.
Stern, and J. Y. Chen, “High-performance TFTs fabricated on plastic substrates”,
IEEE Electron Device Lett., vol. 25, no. 5, pp. 486–488, 2004
[5] A. Z. Kattamis, I-C. Cheng, K. Long, J. C. Sturm, and S. Wagner, “Dimensionally
stable processing of a-Si TFTs on polymer foils”, in Proc. 47th Ann. TMS Electron.
Mater. Conf., pp. 73, 2005
[6] W. S. Wong, K. E. Paul, and R. A. Street, “Digital-lithographic processing for thinfilm transistor array fabrication”, J. Non-Cryst. Sol., vol. 338–340, pp. 710–714,
2004.
[7] J. P. Lu, P. Mei, J. Rahn, J. Ho, Y. Wang, J. B. Boyce and R. A. Street, “The impact
of self-aligned amorphous Si thin film transistors on imager array applications”,
J.Non-Cryst. Solids, vol. 266-267, part 2, pp. 1294-1298, 2000
[8] Y. Huang, B. Hekmatshoar, S. Wagner, and J. C. Sturm “Top-Gate Amorphous
Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility”, IEEE
Elect. Dev. Lett, vol. 29, no. 7, 2008
[9] I-C. Cheng, A. Z. Kattamis, K. Long, J. C. Sturm and S. Wagner, ”Self-aligned
amorphous-silicon TFTs on clear plastic substrates”, IEEE Electr. Dev. Lett, vol. 27,
no. 3, pp. 166-168, 2006
40
[10] I-C. Chu, B-S. Wu, H-K. Tsai, and T–S. Weng, “Circuit Applications of
Amorphous-Silicon Thin Film Transistor-Ring Oscillator : LCD Technologies”, ITEJ
Technical Report, vol.17, no.64, pp. 25-29, 1993
[11] A. Qaiser and S. A Khan, “Automation of Time and Attendance using RFID
Systems”, Proceedings of the 2nd IEEE-ICET, pp 60-66, 2006
[12] M. Predko, “Digital Electronics Demystified: A Self-teaching Guide”, McGraw-Hill
Professional, 2005
[13]R. M. Kodkani, and L. E. Larson, ”A 25 GHz Quadrature Voltage Controlled Ring
Oscillator in 0.12μm SiGe HBT (Student paper)”, IEEE SiRF 2006, pp. 383-386,
2006
[14] J. P. Lu, P. Mei, R. Lujan, J. B. Boyce, “Performance study of self-aligned
amorphous silicon thin-film transistor circuits”, Thin Film Transistor Technologies
IV, Electrochemical Soc. Proc V, pp. 98-22, 1998
41
Chapter 4
INTRODUCTION OF a-Si:H TFT DEVICE LAYERS ON PLASTIC
4.1 TFT device layers
The first half of this chapter discusses the deposition conditions for the inorganic
and metallic device layers in an a-Si:H TFT. The inorganic device layers used in this
thesis for fabricating a-Si:H TFTs are SiNx, a-Si:H, n+ a-Si:H and n+ nc-Si. The metal
layers that were used in the TFT gate and S/D terminals are chromium (Cr) and
aluminum (Al).
In the second half of this chapter we discuss how inorganic device layer
deposition conditions need to be adjusted to deposit crack-free layers on plastic substrates
at high temperatures [1].
4.1.1 Deposition system
The inorganic layers used in our TFT stack are (i) hydrogenated intrinsic and n +
doped amorphous silicon (a-Si:H) and (ii) silicon nitride (SiNx). These layers are
deposited using plasma enhanced chemical vapor deposition (PE-CVD). This deposition
method is used for low to mid temperature processing (room temperature to ~500°C). It
enables the deposition of both dielectric and semiconductor materials at temperatures
well below the thermal decomposition temperature of the source gases. During PE-CVD
a plasma is produced by an AC or DC electric field that decomposes the gas mixture in
the reactor chamber by electron impact into reactive radicals, ions, and secondary
electrons. These radicals then interact with the substrate to form a deposition product [2].
42
The secondary electrons in the plasma collide with the gas molecules causing their breakup and ionization; consequently more electrons are released to sustain the plasma.
We used an in-line Innovative S900 four-chamber PECVD system. Our PECVD
deposition system has a load lock and three deposition chambers, each of which is
dedicated for the deposition of a specific type of film to prevent cross-contamination. The
three chambers consist of an i-chamber for the deposition of intrinsic films, a p-chamber
for doped films, and an n-chamber for dielectrics. A schematic of a deposition chamber is
shown in Figure 4.1. The electrodes in each reactor chamber are built in a triode
configuration consisting of a grounded bottom electrode, a powered grid with an area of
225 cm2, and a grounded substrate holder. Both the bottom electrode and the powered
electrode have a showerhead profile for uniform introduction and distribution of the
source gases. The spacing between the bottom electrode and powered electrode is 0.875”
(~2.22 cm) and the substrate holder sits 0.625” (~1.59 cm) above the powered electrode.
The reactor is designed so that the plasma is generated mainly between the bottom
electrode and powered electrode, and the reactive species then diffuse through the holes
of the powered electrode to reach the substrate. This arrangement reduces the exposure of
the substrate to energetic ion bombardment. Each chamber has three independent
resistance heaters with a maximum set-point temperature of 400C. Two heaters are
placed at the top of the chamber, to the left and the right of the substrate holder, and one
bottom heater is placed at the bottom of the chamber beneath the powered electrode.
43
Substrate
Heater
V
13.56 MHz
Source gases
Pump
stack
SiH4
H2
PH3
NH3
Figure 4.1 Schematic cross section of the deposition chamber of Solarex/Innovative
Density of states N(E)
S900 PECVD system
Defect
states
Conduction
band
Valence
band
Band tails
Energy
Mobility edge
Figure 4.2 Electronic density of states N(E) of a-Si:H displaying the band tails [3]
44
The base pressure of the chambers is ~ 10-6 Torr (10-4 Pa). Twelve process gases are
currently available in our system: Ar, He, HCl, NF3, H2, SiH4, NH3, GeH4 (5% in H2),
B2H6 (1% in H2), N2O, PH3 (1% in H2), SiH2Cl2. The dopant gases, B2H6 and PH3, are
highly diluted with H2 to obtain better control of the doping level. The gas flows are
individually controlled by an MKS 1159B-series or 1179A-series mass flow controller.
The power source used in this system is a radio frequency (RF, 13.56MHz) power supply
system consisting of an ENI RF generator model ACG-3B and an Advanced Energy
AM5 matching network.
4.1.2 Hydrogenated amorphous silicon
Amorphous silicon (a-Si) is the non-crystalline allotropic form of silicon.
Crystalline silicon consists of four-fold coordinated Si atoms that are tetrahedrally
bonded to four neighboring silicon atoms, forming a well-ordered lattice with long-range
order. In contrast, amorphous silicon has no long-range order and the atoms form a
continuous random network.
Amorphous silicon is characterized by a mobility gap of around 1.8eV [3]. The
lack of long range atomic order in a-Si:H leads to band tails in the energy band gap as
well as charge localization and scattering, which limit the carrier mobility in a-Si. The
presence of the coordination (dangling bond) defects results in electronic states at the
middle of the band gap. The electronic density of states versus energy is shown in Figure
4.2 [3]. Conduction in this material occurs by carrier hopping between localized states in
the band-tail and by thermal activation of carriers from the defect states near the Fermi
energy (EF) to above the mobility edge.
45
Figure 4.3 An illustration of some of the possible surface reactions which occur during aSi:H growth [6]
The number of defect states in the middle of the energy gap can be reduced by
passivating the material with hydrogen. The bonding between unpaired silicon atoms and
hydrogen removes defect states in the bandgap, resulting in less recombination of
minority carriers. Chittick, Alexander, and Sterling pioneered this approach in 1969 when
they grew hydrogenated amorphous silicon (a-Si:H) using plasma-enhanced chemical
vapor deposition (PE-CVD) from SiH4 source gas, which resulted in a hydrogen retention
of up to 30 at. % and enabled the use of a-Si:H in electronic devices [4].
During a-Si:H growth, SiH4 decomposes into radicals under electron impact. SiH3
radicals account for ~80% of the species involved in growth when a pure SiH4 source is
used [5]. In order for the SiH3 radicals to bond at the surface they require an unterminated
Si bond. Therefore hydrogen needs to be removed from the growing surface to create
dangling bonds. Hydrogen can be stripped from the growing surface by gas radicals or
can be released spontaneously by thermal excitation. Next the SiHn radicals (primarily
SiH3) bind to the surface at dangling bonds. Figure 4.3 shows some of the possible
46
surface reactions that can occur during a-Si:H growth [6]. As the film grows, it becomes
important to balance the removal of hydrogen from the growing surface into the gas, the
attachment of radicals from the gas onto the growing surface, and the reconstruction of
the growing silicon network via H2 release and a subsequent dangling bond
recombination.
The decomposition of SiH4 produces a-Si films containing significant amounts of
hydrogen ranging from about 4 to 40 at.%[7]. Atomic H forms a strong bond to silicon
and the optimum structure is one which minimizes the hydrogen that is not strongly
bonded to silicon. Therefore ideal a-Si:H consist of primarily Si-Si and Si-H bonds and a
minimum of silicon dangling bonds or interstitial hydrogen. Therefore we add hydrogen
to the deposition gases during PE-CVD to bond with excess interstitial hydrogen that
which allows us to remove it from the material. At high substrate temperatures the
amount of hydrogen incorporated in the a-Si:H layer decreases due to increased rejection
of the H from the growth surface. Therefore there is an intermediate temperature at which
hydrogen is incorporated most effectively in the film, leading to the best quality film.
Figure 4.4(a) shows a plot of H concentration and defect density versus temperature. The
defect density reaches a minimum at the substrate temperature of 250°C, which is
therefore the optimal temperature for deposition of electrically stable a-Si:H material [7].
The plasma power density is another important parameter for deposition of a-Si:H films
with low defect density. Figure 4.4 (b) shows the H content and defect density of PECVD deposited a-Si:H versus RF deposition power. Therefore the highest quality a-Si:H
films are obtained by using a low plasma deposition power and a deposition temperature
optimized at 250oC
1018
40
30
1017
20
1016
Defect density (cm-1)
Hydrogen concentration (vol %)
47
10
1015
0
0
100
200
300
400
15
1017
10
1016
Defect density (cm )
1018
20
-1
Hydrogen concentration (vol %)
Substrate temperature (oC)
(a)
5
1015
0
0
10
20
30
RF power (W)
(b)
Figure 4.4 Hydrogen concentration and defect density in a-Si:H film as functions
of (a) substrate temperature and (b) rf power during PECVD process [7].
48
4.1.3 Doped amorphous silicon
Substitutional doping of a-Si:H was first reported in 1975 by Spear and
LeComber [6]. To grow n+ doped a-Si:H phosphine (PH3) is added to the SiH4 gas during
a-Si:H deposition. This raises the electrical conductivity of a-Si:H by a factor of up to 108
from the intrinsic value of ~1x10-10 Ω-1cm-1. The conductivity increases with increasing
doping concentration up to about 1%. Higher doping concentrations lead to a decrease in
conductivity.
4.1.4 Doped nanocrystalline silicon
Nano-crystalline silicon possesses much higher carrier mobility than a-Si. With
conventional PE-CVD, nc-Si films can be deposited using continuous growth or layer by
layer growth (LBL) methods. The major difference between these two growth methods is
the way hydrogen is introduced. During LBL deposition a-Si:H film growth is alternated
with H2 plasma exposure, at a substrate temperature of 300C or less. It has been
postulated that during the H2 plasma exposure step (also called hydrogen annealing) the
atomic hydrogen diffuses into the a-Si:H surface layer and selectively breaks strained SiSi bonds, allowing the silicon network to relax [8-11]. Depending on the number of
cycles and the ratio of H2 plasma treatment duration to a-Si:H deposition duration, the
film composition can be altered from the non-equilibrium amorphous structure to the
more stable crystalline structure. Layer-by-layer deposition has the potential to provide
better control of the film/substrate interface and promote nucleation in the early stage of
nc-Si:H growth [12]. Therefore this method potentially allows us to reduce the nucleation
region that usually occurs between the a-Si:H channel region and the n+ nc-Si doped layer
to a few nm or even eliminate it completely [13,14].
49
LBL growth with hydrogen annealing produces films with a high crystalline
volume fraction [15]. However, the disadvantage of this technique is that it requires a
large number of layers and requires a long time to deposit [15,16]. It has been reported
that the addition of an argon (Ar) plasma can effectively produce silicon dangling bonds
to promote the density of nucleation sites, thus resulting in a fast coalescence of the
nucleation centers and a dense film [17]. In our thesis we deposit n+ doped nc-Si by
incorporating Ar into the H2 plasma step of the LBL technique following the method
proposed in [18, 19]. The deposition conditions for n+ nc-Si deposition using LBL growth
in our PE-CVD system are summarized in Appendix A.6. The method used to
characterize our n+ doped nc-Si films is given in Appendix B.4.
4.1.5 Silicon nitride
Silicon nitride is a hard, chemically inert, dielectric material which forms an
excellent diffusion barrier against H2O, Na, and many other ionic species. In our TFT
fabrication process it is used as a barrier layer to encapsulate the plastic substrate, as well
as the gate dielectric in the TFT stack. It is the device layer that requires the highest
deposition temperature for optimal device performance. Therefore, for the rest of this
thesis, we refer to the temperature of a TFT process as the deposition temperature for the
SiNx layer (i.e., a 300oC process means that the SiNx layer is deposited at 300oC), while
the other device layers are deposited at their own optimized temperatures.
300
Index of refraction
Pinhole density [cm-2]
50
100
30
2.1
Chamber pressure
= 0.9 Torr
= 0.7 Torr
1.8
1.5
0
200
400
100
600
Substrate temperature ( oC )
300
500
Substrate temperature ( oC )
Figure 4.5 (a) SiNx pinhole density and (b) index of refraction versus deposition
temperature [22]
Two factors are important for growing high quality SiNx film for device
applications: a film composition close to the stochiometric composition and a low pinhole
density.
Silicon nitride films deposited by PECVD are non-stochiometric and a high
ammonia (NH ) dilution of silane (SiH ) is required to deposit SiN films close to the
3
stoichiometric
4
composition
[21].
Non-stoichiometric
x
compounds
are
chemical
compounds with an elemental composition that cannot be represented by a ratio of welldefined natural numbers. These solids contain point defects that result in the excess or
deficiency of an element.
The pinhole density impacts the leakage current of a TFT made with that material
– the larger the pinhole density, the more the TFT gate is likely to be shorted to the
51
channel. The pinhole density of SiNx decreases with increasing temperature as is
demonstrated in Figure 4.5(a). To understand the importance of using a high SiN x
deposition temperature let us consider a TFT with a W/L of 80µm/40µm and a 5µm S/D
overlap with the gate. Using Figure 4.5(a) to determine the expected pinhole density per
cm2, we can expect approximately 80 pinholes per cm2 in a TFT with a gate dielectric
deposited at 200oC and 28 pinholes per cm2 in a TFT with a gate dielectric deposited at
300oC. This TFT has a channel plus overlap area of 80µm times (40+10)µm=0.4x10-4
cm2. Therefore a TFT deposited at 200oC will have roughly 0.003 pinholes and a TFT
deposited at 300oC will have roughly 0.001 pinholes. This means that the chance of
having a pinhole in a TFT deposited at higher temperature is three times smaller than in a
TFT deposited at lower temperature.
It is desirable to have more stoichiometric films because the threshold voltage of
TFTs is lowest when the refractive index of the SiNx layer lies between 1.85 and 1.9 [20]
- which is the case for more stoichiometric films. The composition of SiNx films
deposited at low temperatures is far from stoichiometric, although the film structure can
be improved by using H2 dilution during deposition [22]. The process used in our group
for making a-Si:H TFTs at 150°C substrate temperature includes H2 dilution for both the
SiNx and a-Si:H deposition [24]. Studies of the SiN film composition versus substrate
x
temperature show that higher deposition temperature results in more stochiometric films
with lower H contents. From Figure 4.5 (b) we can see that SiNx films have optimal
refractive indices (between 1.85-1.9) at temperatures around 300-350oC. Therefore
commercial a-Si:H TFT processes using SiNx layers are run in this temperature range.
52
A final point that is important for our TFT processes is that the a-Si:H TFT
electrical stability improves with increasing SiNx deposition power (i.e., ∆VTH becomes
small) [23]. Therefore we ideally want to use a SiNx RF deposition power that is as high
as possible.
4.1.6 Metal layers
The metal gate and source-drain layers used in our TFT process were deposited
using a BOC Edwards Auto 306 thermal evaporator. Two metals were commonly used:
chrome (Cr) and aluminum (Al). The deposition rate for chrome was between 0.4 - 0.7
nm/s while the deposition rate for aluminum was between 0.8 and 1.7 nm/s. The PECVD
layer deposition temperature can affect the roughness of the gate metal, which is
deposited before the inorganic device layers in the bottom-gate TFT structure. Metals
such as Al need to be encapsulated if they are to be subjected to a high-temperature
process since they tend to roughen or diffuse into the SiNx gate dielectric. We usually use
100 nm of Cr as the gate metal for process runs on glass substrates. Fabricating a gate
from a thick Cr layer causes problems for processes on plastic substrates since Cr has a
high tensile built-in stress, and a post-processing of Cr gates at high temperature always
leads to cracking of the Cr gate metal. Therefore our fabrication process on plastic
substrates always uses a gate consisting of a tri-layer of Cr/Al/Cr of 15/70/15nm
thickness.
The following section discusses how we need to adjust the device layer deposition
conditions in our PE-CVD system to achieve crack-free layer deposition on plastic
53
substrates at elevated temperatures. Chapter 5 presents the actual 300oC process that was
developed for plastic foils.
4.2 Developing a high temperature process on plastic
As discussed in Chapter 1 the first step towards developing a process at 300oC on
plastic is to choose a substrate that can withstand such high temperatures – i.e. a substrate
with a Tg > 300oC. Secondly, we need to choose a plastic substrate that allows us to
minimize the total strain in the substrate and the device layers. To do this, we need to
understand how strain develops in device layers deposited on plastic. Sections 4.2.1 4.2.3 and 4.3 discuss the origin of strain in inorganic device layers deposited on plastic,
following the theory developed by Suo, Gleskova and Cheng [1, 24, 25]. In section 4.4
we discuss the implications of device layer strain on developing a high temperature
process.
4.2.1 Origin of strain in inorganic device layers
Flexible plastic substrates change their dimension noticeably when a film is
deposited on the substrate and exerts a force on the surface. The combined film-onsubstrate structure experiences a strain (M) that can be broken down into three separate
components: the built-in strain (B), the thermal mismatch strain (TH) and the moisture
mismatch strain (CH) [1, 24]. The combination of all these strains gives the total
mismatch strain:
M = B + TH + CH
- 4.1
54
The B component develops when atoms are deposited in non-equilibrium positions. It
can be controlled to a certain degree by changing the deposition conditions (deposition
power, deposition temperature, etc.). In the device layers that we deposit B tends to be
tensile in chromium, compressive in amorphous silicon (a-Si:H) and can be varied in
silicon nitride (SiNx).
The thermal strain, TH, is caused by the mismatch between the coefficient of
thermal expansion (CTE) of the device film and the substrate. Or, to put it differently,
different materials expand at different rates. Therefore as you increase/decrease the
temperature of the combined substrate-film structure, the different layers will expand or
contract by different amounts, resulting in TH . The TH that develops in an inorganic
layer deposited on plastic can be modeled mathematically by:
TH = (CTEs – CTEf)  (Troom – Tdeposition)
- 4.2
where CTEs is the coefficient of thermal expansion [ppm/oC] for the plastic substrate,
CTEf is the coefficient of thermal expansion of the film, Troom is the room temperature
[oC] and Tdeposition is the deposition temperature. The inorganic layers for our process are
always deposited at elevated temperatures. The TH between a substrate and the deposited
film is zero while the sample is still in the deposition chamber at Tdeposition. However, once
the sample is moved to the load-lock and cooled to Troom the substrate and the film shrink
by different amounts and therefore strain develops in the structure.
The CH component is similar to TH, except that it depends on the change in
humidity, i.e. the humidity during the vacuum growth and the humidity at which the
devices are operated (or exposed to). Our plastic substrates are encapsulated with a SiNx
55
layer on both sides before device fabrication, which limits the amount of moisture that it
can absorb from the atmosphere or during wet photolithography steps. This strain
component tends to be small compared to TH and is usually not included in our analysis.
4.2.2 Strain classifications
Strained films can be classified as tensile or compressive. First, consider an
inorganic film (with a typical CTE between 1-5 ppm/oC) deposited at high temperature
on a plastic substrate (with CTE > 10 ppm/oC). At the time of deposition both the film
and substrate have the same dimensions and are stress free (neglecting the built-in stres in
the growing film). When the combined structure is cooled down to Troom while held flat
the substrate will shrink much more than the deposited device film due to its larger CTE,
which results in a large TH. Therefore the substrate exerts a force on the film forcing it to
become smaller than it „wants‟ to become – i.e., the film is under compression. The
substrate on the other hand experiences a force exerted on it by the film forcing it to
become larger than it „wants‟ to be – i.e., the substrate is under tension. Assuming that
the device layer doesn‟t crack, a compromise is reached in which the device film is
bigger than the substrate would „like‟ it to be but smaller than it would be if it was freestanding. The reverse is true for a film under tension – in this case the device film is
smaller than the substrate would „like‟ it to be but larger than it would be if it was freestanding. By convention a negative sign is used for a compressive strains and a positive
sign for tensile strains.
56
4.2.3 Substrate curvature after film deposition
The behavior of the combined film-on-substrate structure under stress depends
strongly on the strength of the respective materials. The mechanical strength of a thin
film or substrate is defined as the product of the biaxial elastic modulus (Y*) and the
thickness of the material (d) [1]. The biaxial elastic modulus is:
Y* 
Y
,
1 v
- 4.3
where Y is the Young‟s modulus and v is the Poisson ratio of the respective material. The
different situations that can be encountered during processing are listed in Table 4.1.
Usually the combined structure will roll into a cylinder along one of the axes to
reduce the total elastic deformation energy. When the strength of the film is much less
than the strength of the substrate ( Y f* · df << Ys* · ds) the substrate dominates the behavior
of the composite structure and the film complies with it. In this situation the stress in the
substrate is small, and the film/substrate couple curves little or only slightly, even when
the film is highly stressed. However, in the situation where an a-Si:H TFT is fabricated
on a plastic, Y*f · df ≈ Y*s · ds, and the strain that develops in the film has a large impact
on the plastic substrate. In this situation the thin film has a visible effect on the total
structure, causing it to curve.
57
Figure 4.6 A film-on-foil structure bent to a cylindrical roll. A TFT structure is in
compression when the deposited device film is on the outside of the cylinder. [1]
Table 4.1 Device film / substrate combinations grouped by elastic moduli [1]
Thin film (small df)
Stiff (large Y f* )
Thick
Stiff (large Ys* ) Si TFT / glass
substrate
Compliant
(large ds)
ITO / plastic
*
s
(small Y )
Compliant (small Y f* )
OLED / steel
OTFT / plastic
58
For compressive films, the device film will be on the outside of the cylinder. This
situation is illustrated in Figure 4.6. The opposite situation is achieved if a tensile film is
deposited, in which case the film is on the inside of the cylindrical roll. In mathematical
equations throughout the rest of the text the radius of curvature, R, indicated in Figure 4.6
is positive for tensile films and negative for compressive films. (Is not it reversed?) The
curvature of a substrate can be used to calculate the total strain in a substrate and from it
the built-in strain using the following equation [25]:
M 
(YS* d S2  YF* d F2 ) 2  4YF*YS d F d S (d F  d S ) 2 1
1
(

)
*
RF RO
6YF YS d F d S (d F  d S )
- 4.4
where RO and RF are the initial and final radii of curvature of the substrate. Our 50µm
thick Kapton® E foil, when cut from its roll, has a starting radius of R0 ~ 14cm. The
radius of the clear plastic (CP) foil used in our high-temperature experiments is
effectively infinite (flat substrate).
4.3 Determining the built-in strain experimentally
The procedure to calculate the various strain components of  M following a film
deposition step is as follows: after the film deposition, the sample is removed from the Nchamber to the PE-CVD load lock and unloaded right away without cooling down. The
substrate‟s RF is measured just after it has been removed from the deposition system, and
after it has cooled down to room temperature (RF should be measured at room
59
temperature; otherwise it reflects the built-in strain only.) This radius is now used in
conjunction with equation 4.3 to calculate  M . Then we calculate  TH from equation 4.2.
Finally  B is calculated from equation 4.1 by subtracting  TH from  M .
Our group has studied the dependence of  B on RF deposition power for SiNx films
deposited using a range of deposition powers and a deposition temperature of 150oC [25].
In this experiment a series of 300nm thick SiNx films were deposited on Kapton using
various deposition powers and  B was extracted using the procedure outlined above. The
result is shown in Figure 4.7, where the various strain components are plotted versus RF
deposition power. The film is under tension at positive strains and compression at
negative strains. This experiment shows that for SiNx depositions at 150oC,  B changes
from 0.26% tensile strain at a deposition power of 5W to ~0.1% compressive at a
2
deposition power of 25W. The crossover point lies at about 17 W (75 mW/cm ). What we
learn from this experiment is that we can adjust  M in a SiNx layer simply by adjusting
the RF deposition power. This is used as a tool in this thesis to develop a 300oC
deposition process.
60
Strain components [% ]
0.2
B
0.1
0.0
-0.1
-0.2
5
10
15
20
25
SiNx deposition power [W]
Figure 4.7 Strain components calculated for 300nm thick SiNx films deposited onto
Kapton at 1500C at varying deposition powers [27] The electrode area is 225cm2.
61
4.4 Implication of strain for high-temperature a-Si:H TFT process
We need to minimize  M in the deposited inorganic device layer on plastic as
much as possible. Since the largest strain component making up  M is  TH this implies a
choice of a substrate that has a CTE close to the CTE of the inorganic device layers. The
CTE of SiNx (the layer that we commonly use to adjust strain in the total work-piece) is
taken between 1-2 ppm/oC [1]. Therefore the CTE of the plastic substrate needs to be as
low as possible.
Inorganic device layers can withstand higher compressive strains than tensile
strains. Past experiments in our group have determined that SiNx films can withstand
roughly 2% compressive strain and 0.2% tensile strain [1] when the coated substrate is
subjected to mechanical bending at room temperature. The reason for this is that tensile
strains cause SiNx layers to fail by crack propagation from pre-existing defects. In
compression, however, the layers fail by delamination followed by buckling and fracture.
The critical compressive strain can also be increased by improving the adhesion between
the substrate and the film [26].
We tend to use the tensile and compressive strain limits derived from roomtemperature mechanical bending to estimate the maximum  M that the film will be able
to withstand when the strain in the film is caused by high temperature. However, when
we experimented with depositing SiNx films on plastic substrates, we experienced film
fracture at compressive strain values much lower than 2%. We speculate that there is
another factor that impacts film cracking when the film strain develops as a result of
high-temperature deposition (compared to the case in which strain is caused by an
external force that is applied to an initially crack-free film at room temperature). The
62
main candidate that we consider as a factor influencing film cracking is the adhesion
between the plastic substrate and the SiNx film. We know that the adhesion between the
SiNx film and the substrate for our room-temperature bending experiments is good –
however, we have no detailed knowledge of the adhesion between the film and substrate
at elevated temperatures. The adhesion between the film and the substrate at elevated
temperatures could be much lower than at room temperature and the lower adhesion
could promote film cracking as the film cools down from Tdeposition to lower temperature
(before reaching Troom). This area still requires more research to confirm this theory.
As a general rule of thumb, we calculate the maximum plastic CTE that will still
allow us to deposit device layers at 300oC as follows: we combine equations 4.1 and 4.2
to give us
M = B + (CTEs – CTEf)  (Troom – Tdeposition) + CH
-4.5
Now we calculate  TH using equation 4.5, CH =0,  M =0.5% = 5000 ppm,  B =0 (since
 TH >>  B for a 300oC process), Troom = 0oC , Tdeposition = 300oC, and CTEf = 1ppm/oC.
This gives us CTEs ≈ 15ppm/oC. Therefore, according to this discussion, we require a
substrate with a CTE<15ppm/oC for successful deposition of SiNx layers at 300oC.
In our TFT process we adjust the strain in three main layers: the SiNx gate
dielectric deposited at 300oC, and the two SiNx barrier layers deposited onto the bare CP
substrate prior to device fabrication. The recipes of the other device layers (metals, aSi:H, etc) are not changed. Since  TH becomes very large for SiNx films deposited at
300oC we need to keep  M in the combined structure below the critical fracture point.
This is done by adjusting the RF deposition power as was demonstrated in Figures 4.7.
63
We used this approach to develop a 300oC a-Si:H TFT process on CP, as will be
discussed in Chapter 5.
4.5 Summary
This chapter discussed the theory of a-Si:H TFT device layer deposition, and how
we can adjust deposition conditions to obtain a high temperature process on plastic
substrates. In the next chapter, the actual process developed at 300oC is presented.
64
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Technology on Flexible Substrates”, in Flexible Flat Panel Displays, G. P. Crawford,
Ed. Wiley, pp. 263 – 282, 2005
[2] S. K. Ghandhi, “VLSI Fabrication Principles: Silicon and Gallium Arsenide”, 2nd
Edition., John Wiley and Sons, 1994
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M. van de Sanden, “On the growth mechanism of a-Si:H”, Thin Solid Films, vol. 383,
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[5] R. C. Chittick, J. H. Alexander, and H. F. Sterling, “The Preparation and Properties of
Amorphous Silicon”, J. Electrochem. Soc., vol. 116, no. 1, pp. 77 – 81, 1969
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[7] R. A. Street, “Hydrogenated amorphous silicon”, Cambridge: Cambridge University
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[8] A. Asano, "Effects of hydrogen atoms on the network structure of hydrogenated
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[10] M. J. Powell, S. C. Deane, and W. I. Milne, “Bias-stress–induced creation and
removal of dangling-bond states in amorphous silicon thin-film transistors”, Appl.
Phys. Lett., vol. 60, no. 2, pp. 207–209, 1991
[11] M. J. Powell, C. van Berkel, A. R. Franklin, S. C. Deane, and W. I. Milne, “Defect
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65
[12] C. Godet, N. Layadi, and P. Roca i Cabarrocas, “Role of mobile hydrogen in the
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[13] K. Saitoh, M. Kondo, M. Fukawa, T. Nishimiya, A. Matsuda, W. Futako, and I.
Shimizu, “Role of the hydrogen plasma treatment in layer-by-layer deposition of
microcrystalline silicon”, Appl. Phys. Lett., vol. 71, no. 23, pp. 3403-3405, 1997
[14] H. Shirai, “Surface Morphology and Crystallite Size during Growth of Hydrogenated
Microcrystalline Silicon by Plasma-Enhanced Chemical Vapor Deposition”, Jpn. J.
Appl. Phys, part 1, vol. 34, pp. 450-458, 1995
[15] S. Koynov, S. Grebner, P. Radojkovic, E. Hartmann, R. Schwarz, L. Vasilev, R.
Krankenhagen, I. Sieber, W. Henrion, and M. Schmidt, “Initial stages of
microcrystalline silicon film growth”, J. Non-Cryst. Solids, vol. 198-200, no. 2, pp.
1012-1016, 1996
[16] S. Hamma and P. Roca i Cabarrocas, “In-situ correlation between optical and
electrical properties of intrinsic and n-type microcrystalline silicon films”, J. Appl.
Phys., vol. 81, no. 11, pp 7282-7288, 1997
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I. Lin, “Growth of nanocrystalline silicon thin film with layer-by-layer technique for
fast photo-detecting applications”, Mater. Sci. Eng. B, vol. 127, no. 2-3, pp. 251-254,
2006
[18] P. Roca i Cabarrocas, “New approaches for the production of nano-, micro-, and
polycrystalline silicon thin films”, Phys. Status Solidi, vol. C 1, no. 5, pp. 1115-1130,
2004
[19] S. Kasouit, J. Damon-Lacoste, R. Vanderhaghen, P. Roca i Cabarrocas, “Contribution
of plasma generated nanocrystals to the growth of microcrystalline silicon thin films”,
J. Non-Cryst. Solids, vol. 338-340, pp. 86-90, 2004
[20] S. F. Chen, Y. K. Fang, T. H. Lee, C. Y. Lin, P. J. Lin, S. H. Chang and T. H. Chou,
“Enhancing the crystallization fraction performance of nano-crystalline silicon thin
films with argon and hydrogen annealing”, Thin Solid Films, vol. 515, no. 7-8, pp.
3844–3846, 2007
[21] S-F. Chen, Ph. D., Thesis, National Cheng Kung University, 2006
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[22] C. Blaauw, “Preparation and Characterization of Plasma-Deposited Silicon Nitride”,
J. Electrochem. Soc.: Solid State Science and Technology, vol. 131, no 5, pp. 11141118, 1984
[23] H. Dun, P. Pan, F. R. White, and R. W. Douse, “Mechanisms of Plasma-Enhanced
Silicon Nitride Deposition Using SiH4/N2 Mixture”, J. Electrochem. Soc., vol. 128, no.
7, pp 1555-1563, 1981
[24] H. Gleskova, S. Wagner, V. Gasparik, and P. Kovac, “150 oC amorphous silicon thinfilm transistor technology for polyimide substrates”, J. Electrochem. Soc., vol. 148, pp.
G370-G374, 2001
[25] A. Z. Kattamis, K. H. Cherenack, B. Hekmatshoar, I-C Cheng, H. Gleskova, J. C.
Sturm, and S. Wagner, “Effect of SiNx gate dielectric deposition power and
temperature on a-Si:H TFT stability”, IEEE Electron Dev. Lett., vol. 28, pp. 606-608,
2007
[26] Z. Suo, “Fracture in Thin-Films,” in Encyclopedia of Materials : Sci. and Tech.,
Elsevier, pp. 3290-3296, 2001
[27] I-C. Cheng, A. Z. Kattamis, K. Long, J. C. Sturm, and S. Wagner, “Stress control for
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Inf. Disp., vol. 13, no. 7, pp. 563–568, 2005
[28] K. Long, Ph. D Thesis, Princeton University, 2006
67
Chapter 5
CLEAR PLASTIC SUBSTRATES
5.1 Introduction
In this chapter we discuss the clear plastic (CP) substrates that were used to
implement our 300oC process, including substrate preparation, handling and barrier layer
deposition. For reference, general CP substrate properties are compared to other flexible
substrates that have been considered for display applications in table 1.1.
This chapter is structured as follows: first we characterize the optical transmission
properties of our CP substrates (section 5.2.1) to determine their suitability for use in
transmissive displays as well as to enable self-alignment processes requiring backexposure (as introduced in section 3.3). Then we considered the surface properties of CP
due to the impact of defects in large area processing (section 5.2.2). Next we looked at
the CTE (section 5.2.3) and melting point, Tg (section 5.2.4). Then we investigated the
strain of SiNx layers deposited at 300oC for various RF deposition powers (using PECVD) in section 5.3.1. We investigated the SiNx barrier layer adhesion to the CP
substrate by depositing SiNx films on our substrates at 300oC for deposition powers
ranging from low to high. We discuss substrate handling for deposition in the PE-CVD
system and other handling issues that arise when we use standard photolithography to
pattern device layers deposited on CP (section 5.3.4). We then discuss the substrate
chemical sensitivity to solvents and how this impacts our photolithography steps
(specifically, how we strip the photoresist). Finally, the optimized barrier layers
developed for CP-2 and CP-3 are described in section 5.4.
68
5.2 Substrate properties
As discussed in Chapter 1 we need a substrate that can withstand a process
temperature of 300oC, which has a low CTE and is optically clear. This section provides
the details for the specific CP substrates that were used in our 300oC process. The CP
substrate underwent two major recipe changes during the development of the 300oC
process. Different CP recipes are labeled CP-1, CP-2 and CP-3. The CP substrates used
in this thesis are 75µm thick. It is important to note that the CP substrates provided by
our external collaborator were fabricated in a lab-setting and therefore the material
properties and quality of the substrate varied from shipment to shipment, requiring onthe-fly process adjustments. The substrates were evaluated by looking at their optical
clarity, surface roughness, CTE, and Tg.
5.2.1 Optical transmission
The CP substrates used in this work were optically clear, which makes them
highly suitable for display applications. It also allows us to implement various selfalignment methods. The optical transmission spectra of all substrates used in our lab that
are capable of withstanding a 300oC temperature are shown in Figure 5.1. They are CP-2,
CP-3, Kapton® E polyimide and Corning 1737 glass. CP-1 was not successfully used in a
300oC process due to melting (see section 5.2.5). The CIE diagram [1] for CP-2 is shown
in Figure 5.2, indicating the cut-off line where the CP substrate transmission drops below
85%. As can be seen, CP transmits light well, making it a good choice for transparent
display applications, and processes where self-alignment is implementing by exposing
photoresist through the back of the substrate. Parts of the CP–3 substrates have hazy
69
sections that are correlated to regions of higher CTE, and were therefore not used for
processing. Figure 5.3 shows a piece of plastic from the pilot CP where one can clearly
see the transparent and hazy portions in the plastic.
100
Glass
CP-2
CP-3
Kapton E
90
% Transmission
80
70
60
50
40
30
20
10
0
200
300
400
500
600
700
800
Wavelength (nm)
Figure 5.1 Optical transmission versus wavelength for 75-µm thick CP-2, 50-µm thick
CP-3, 75-µm thick Kapton® E and 1.1-mm thick Corning 1737 glass
70
0.8
CIE chromaticity
diagram
0.6
0.8
650
0.6
0.4
CP3 transmits > 80% above this line
0.0
0
0.2
0.4
0.6
0.8
460
Figure 5.2 A0.6
CIE diagram indicating the cut-off point of CP-3. Above the white line the
CP transmits >80%
Outline of
substrate
Figure 5.3. Photograph of a substrate from CP-3 recipe showing a hazy section at the
bottom
71
5.2.2 Substrate surface properties
This section discusses the surface properties of our CP-2 and CP-3 substrates.
Any defects on the substrate surface serve as areas where local stresses can build up and
can serve as nucleation centers for cracks. These defects become increasingly
problematic as the device area being processed increases. While it is possible to make
individual TFTs on more „dirty‟ substrates it is essential to have clean substrate surfaces
with low defect densities in order to fabricate large-area display backplanes, which is our
stated goal.
CP-2 substrates (as received from our collaborator) were relatively smooth with
occasional particles embedded in the surface as well as scratches due to handling and
shipping. The CP-2 substrates varied greatly from one shipment to another. Figure 5.4 (a)
shows optical micrographs taken with interference contrast of a „clean‟ CP-2 substrate –
i.e. a substrate with a low defect density, while Figure 5.4(b) shows a high-defect density
CP-2 sample surface including scratches and point defects. CP-3 substrates (as received
from our collaborator) generally had more particle inclusions and were more „scratched
up‟ than CP-2 substrates. They also had a „stripe‟ pattern running parallel to the surface
of the substrate. This is pattern is most easy to observe when the surface is coated with a
reflective metal such as chrome as is shown in Figure 5.5. The stripe pattern did not have
any appreciable effect with regard to device layer cracking, although it increased the
overall surface roughness.
We traced the substrate defect density of as-received samples in order to
understand the success/failure rate of our process. Defects were classified as point defects
or scratches.
72
400µm
400µm
(a)
(b)
Figure 5.4 Optical micrograph showing a „clean‟ and a „dirty‟ surface area
~2.5cm
Figure 5.5 Photograph of a CP-3 substrate coated with a layer of chrome, clearly
showing the vertical stripe pattern running parallel along one axis of the substrate.
4
0.5
3
0.375
2
0.25
1
0.125
0
0
CP-1
CP-2
CP-3
Figure 5.6 Summary of substrate cleanliness for a variety of substrate batches from CP1, CP-2 and CP-3.
Figure 5.6 shows the measured defect density measured for random samples for
all three CP recipes. The scratch density is the average total length of scratches per unit
area of the substrate. The point defect density is the average number of defects with
dimensions larger than 2µm per unit area of substrate. As you can see, CP-1 and CP-2 are
generally cleaner than CP-3. The defect density of the substrate needs to be reduced as
much as possible to develop a substrate that is a drop-in replacement for high-quality
display backplanes made on glass.
Scratch density (mm/mm2)
Point defect density (1/mm2)
73
74
5.2.3 Coefficient of thermal expansion (CTE)
The development of TH is described in section 4.2.1. It depends on the mismatch
of the CTE between the substrate and the deposited device layer (see equation 4.2). This
section shows the CP-2 and CP-3 CTE measurements, and the impact of the substrate
CTE on developing a fabrication process at 300oC. As discussed in section 4.4 we need to
minimize the total strain  M in the device layers as much as possible to prevent cracking
in the TFT stack. In order to minimize εTH, the CTE of the plastic substrate needs to be as
close to that of the inorganic layers as possible, which means the plastic CTE needs to be
as low as possible.
The in-plane CTE values for all CP substrates were supplied to us by our
collaborators and the measurement was carried out as follows:
The measured CTE values were extracted using a TA Instruments TMA 2940
thermal mechanical analyzer. In this measurement, the substrate is exposed to two
temperature cycles (both ranging from 50ºC to 300ºC by ramping the temperature at a
rate of 10ºC/min). The first pass is used to remove shrinkage from the sample as well as
to dry it out. The second pass then provides a CTE value characteristic of the film‟s
inherent properties (e.g. minus water absorption and the effect water would have on a
film‟s CTE) by measuring the expansion of the film (change in substrate dimensions)
during the second pass. The ASTM method referenced for measurement of the thermal
coefficient of linear expansion is ASTM D-696-91.
An example of the measured change in length versus temperature for a random
CP-2 sample is shown in Figure 5.7. The CTE is extracted from this figure (for a chosen
75
Dimension change [µm]
800
600
CTE = 4ppm/oC
400
200
CTE = 42ppm/oC
0
250oC
50oC
317oC
317oC
-200
0
50
100
150
200
250
300
350
Temperature [oC]
(b)
Figure 5.7. A sample CTE measurement for a random piece of CP-2 (courtesy of C.
Simone)
temperature range) by fitting a line from the low to high temperature data point and
measuring the gradient. The gradient value in the figure has units of µm/oC and is divided
by the length of the sample (in m) to give a value that has units of m / m  oC. This value
is the CTE, and the units are often expressed as ppm/oC.
In our experience, the CTE for our CP-2 and CP-3 substrates tends to be stable up
to a temperature of around 250oC. At a certain temperature above 250oC the CTE will
start rising rapidly, which we refer to as the „knee‟. In Figure 5.7 you can clearly see a
„knee‟ in the CTE curve at 317oC. However, the knee has been measured at temperatures
from 280oC. This illustrates the difficulty in raising the deposition temperature from
250oC to 300oC. In this particular CTE measurement, the gradient for extracting the CTE
76
for the high temperature range was fitted from 250oC to 317oC and is considerably higher
than the CTE measured from 50 to 250oC (42ppm/oC compared to 4ppm/oC ).
Figure 5.8 shows the measured CTE values for a random sampling of CP-1, and
CP-2 substrates. The CTE was measured over two different temperature ranges: 50 to
250oC and 250 to 300oC. For CP-1 and CP-2 the CTE is roughly around 5ppm/oC all the
way up to 250oC. However, there is a sharp increase in the CTE value when we increase
the deposition temperature up to 300oC. The CTE for CP-1 in the high-temperature
region is anywhere between 14 and 30ppm/oC while the CTE for CP-2 is around 1222ppm/oC. The CTE of the CP-3 substrate (not plotted in Figure 5.8) is ~4 ppm/oC
measured over the temperature range from 0 to 250oC, and ~16 ppm/oC from 250 to
35
Temperature range from 50oC to 250oC
Temperature range from 250oC to 300oC
30
CTE (ppm/oC)
25
20
\
15
10
5
0
1
2
3
4
5
6
7
8
9 10 11
12 13
CP-2
CP-1
(a)
Figure 5.8. Random CTE measurements for several CP1 and CP2 substrates for 2
temperature ranges. The first temperature range s from 50oC to 250oC and the second is
from 250oC to 300oC
77
300oC. In summary – the CTE for CP-1, CP-2 and CP-3 is relatively close to that of SiNx
at temperatures up to 250oC. As the temperature is raised from 250oC to 300oC the CTE
starts rising rapidly. Therefore extra effort needs to be made to ensure crack-free
deposition of device layers at 300oC.
5.2.4 Substrate glass transition temperature
The glass transition temperature (Tg) of the CP-1 recipe was too low to enable a
300oC process and all our attempts to process at this temperature resulted in substrate
melting. The highest deposition temperature achieved on plastic from the CP-1 recipe
was 280oC. After switching to CP-2 we were able to achieve a 300oC process – both
because of a slightly higher Tg, but also because of the generally lower CTE as discussed
in the previous section. The Tg values for CP-1, CP-2 and CP-3 can be found in table 1.1.
It is important to note that the maximum processing temperature is lower than the glass
transition temperature by at least 30oC – this is due to the fact that the plastic substrate
gradually becomes „softer‟ as it approaches the melting point and therefore becomes
unprocessable before it actually starts melting.
The deposition temperature in the nitride deposition chamber (N chamber) is a
critical variable in our process and needs to be calibrated as accurately as possible. Since
our goal is a nitride deposition temperature of 300oC – which is close to the processing
temperature limit of the plastic substrate - any temperature overshoot could easily lead to
substrate melting. As described in Chapter 4, each deposition chamber has three heaters
(two at the top of the chamber, and one at the bottom). We used thermocouples to
measure the actual temperature at the substrate surface for various setpoint combinations
78
in the N-chamber. We also measured the temperature at which the substrate melted and
correlated this to the stated glass transition temperature (melting point) given by our
collaborator to ensure that our temperature settings were correctly calibrated.
The following temperature set-points were used in our PE-CVD system to set the
3 heaters in each deposition chamber to ensure the correct substrate temperature: the
temperature setpoints used for SiNx deposition in the N-chamber were (350,350,330)
which is equivalent to a deposition temperature of 300oC. The setpoints used for a-Si:H
deposition in the I-chamber were (280,280,250) which is equivalent to a deposition
temperature of 250oC and the setpoints for deposition in the P-chamber were
(260,270,200) which is equivalent to a deposition temperature of 230oC.
5.3 Depositing SiNx barrier layers on clear plastic CP-2 and CP-3 at 300oC
All TFT processes developed in this thesis start by coating the front and back of
the CP substrate with a layer of SiNx. The SiNx functions both as a gate dielectric in the
TFT stack and as a barrier layer providing mechanical protection during processing and
protection of the plastic against process chemicals. Most importantly however, the SiNx
layers are used to balance the stresses in the total substrate–TFT-layer structure by
tailoring the stresses in each layer to minimize the total stress in the finished workpiece.
The front and back barrier layer deposition recipes on CP-2 and CP-3 were
developed to ensure crack-free barrier layer deposition at 280oC and a final workpiece
that was as flat as possible. However, to obtain a relatively flat work-piece, the stresses
in the SiNx barrier layers at the front and back of the substrate as well as the gate
dielectric need to be balanced (all other layers are patterned during processing and will
79
not contribute much to the final curvature of the substrate, although they certainly impact
the curvature throughout the process). The stress in the barrier film at the back needs to
balance out the stress in the barrier film at the front as well as the SiNx gate dielectric.
Since the gate dielectric is deposited at 300oC (and ideally at high deposition powers [2])
it is very compressive while the barrier films are deposited at 280oC and are less
compressive (due to the steep rise in CTE from 280oC to 300oC that was presented in
section 5.2.4). Section 5.3.1 investigates the dependence of the built-in strain in SiNx
layers on the deposition power for a 300oC process. A successful (crack-free) deposition
of SiNx barrier layers on CP also depends on achieving good adhesion between the
substrate and the barrier layers. Section 5.3.2 investigates how the adhesion between the
substrate and the SiNx layers is improved for high RF deposition powers. The substrate
loading method that was designed to ensure that the substrate expands freely when
brought from room temperature to the deposition temperature and back is presented in
section 5.3.3. Finally, in section 5.4 we give the detailed results of our optimized barrier
layers for CP-2 and CP-3 substrates.
5.3.1 Adjusting SiNx built-in strain with RF deposition power at 300oC
Previous work in our group studied the mismatch strain  M that develops in SiNx
at 280oC [3]. However, we also need to know  M in SiNx gate dielectric films deposited
at 300oC. In this experiment we coated a series of 2.8‟‟x 2.8‟‟ CP-3 substrates with 100nm-thick SiNx films using RF deposition powers ranging from low to high. Each
substrate was loaded into our PE-CVD using the loading method described in section
5.3.3 and preshrunk in the PE-CVD load lock at 220oC for 2 to 4 hours. The temperature
80
set-points used in our system to obtain the correct temperature (for all chambers) can be
found in Appendix A.1-A.2. We then moved the sample to the PE-CVD N-chamber
which has already been heated to the SiNx deposition temperature. The substrate was left
in the N-chamber (without any deposition) for 30 minutes to allow it to acclimate to the
high temperature. Then the front of the substrate was exposed to an Ar plasma (the
settings in the N-Chamber for our PE-CVD system were: Ar flow rate = 50 sccm, RF
power = 12 W, chamber pressure = 500 mTorr) for 3 minutes. We then deposited 100 nm
of SiNx onto the front of the CP-3 substrate at 300oC using a different RF deposition
power for each individual substrate. After each deposition, the substrate was transferred
back to the load lock and immediately taken out (unloaded without waiting for the
substrate to cool). We then waited for the substrate to cool down to room temperature and
then measured RF. This was then used to calculate  M in the film using the method
described in section 4.3. The resulting  M is plotted in Figure 5.9. The relevant SiNx and
the substrate parameters used to calculate the mismatch strain are summarized in Table
5.1 [3, 13].
From Figure 5.9 it is clear that (as expected)  M in the SiNx layers is always
compressive for a 300oC deposition temperature due to the large  TH after cooling from
this temperature. Therefore, from this experiment it would seem that the SiNx layers
should be deposited at very low powers to minimize the total mismatch strain in the
composite structure.
81
0.0
εM
Mismatch strain [%]
-0.1
-0.2
-0.3
-0.4
-0.5
0
10
20
30
40
50
60
SiNx deposition power [W]
Figure 5.9  M (calculated from curvature 1/Rf) versus deposition power for 100-nm
thick SiNx films deposited on CP-2 at 3000C.
Table 5.1 Device film / substrate material properties used to extract parameters at 300oC
[4]
*
Properties at 300oC
Y [GPa]
ν
CTE [ppm/oK]
d [nm]
SiNx
156
0.25
2.7
100
CP-3
4.26
0.32*
16
75,000
using ν for Kapton®E
82
5.3.2 Adhesion between CP and SiNx films deposited at 300oC
Although the large  M in SiNx layers deposited on plastic at high deposition
temperatures suggests that the optimal deposition conditions correspond to using low
deposition power (as discussed in section 5.3.1), the adhesion of the device layers
improves greatly when high RF deposition power is used. We use this trick to deposit
crack-free SiNx layers at high deposition power, as will be discussed in this section.
We carried out a series of experiments to test the adhesion between SiNx films
deposited at 300oC on CP-substrates: in this experiment we coated a series of 2.8 x 2.8‟‟
CP-3 substrates with 100-nm thick SiNx films using RF deposition powers ranging from
low to high. We loaded each CP-2 substrate using the loading method described in
section 5.3.3 and preshrunk the substrates in the PE-CVD load lock at 220oC for 2 to 4
hours. The temperature set-points used in our system to obtain the correct temperature
(for all chambers) can be found in Appendix A.1-A.2. We then moved the sample to the
PE-CVD N-chamber. The substrate was left in the N-chamber (without any deposition)
for 30 minutes to allow it to acclimate to the high temperature. Then the front of the
substrate was exposed to an Ar plasma (the settings in the N-Chamber for our PE-CVD
system were: Ar flow rate = 50 sccm, RF power = 12 W, chamber pressure = 500 mTorr)
for 3 minutes. We then deposited 200 nm of SiNx on the front of each substrate at 280oC
(using a different RF deposition power for each individual substrate). After each
deposition, the substrate was transferred back to the load lock and unloaded after the
substrate cooled down to ~ 50oC.
83
After unloading the substrate we cut off a random piece of the substrate and
mounted it onto a SEM stub using carbon tape. The sample was coated with 40Å of
iridium using a VCR IBS/TM250 ion beam sputterer and then examined in an XL-30
scanning electron microscope (SEM). Pictures were taken in the XL-30 microscope using
an aperture setting of 3 and an HT setting of 3 keV. Figure 5.10 shows the surfaces of
the samples. Here SiNx films deposited at low deposition power (17 mW/cm2) simply
flake off the substrate and do not stick at all due to very low adhesion between the film
and the substrate. At intermediate deposition power (66 mW/cm2) the films are under
high compressive stress and cracked, and at high deposition power (133 mW/cm2) the
SiNx films become crack-free. In fact the adhesion between the substrate and the SiNx
films deposited at high powers becomes so good that the film starts wrinkling before it
cracks. This can be seen in Figure 5.11 where a 300-nm-thick SiNx film was deposited on
CP-2 at 280oC and a deposition power density of 213 mW/cm2.
Ultimately we used this discovery to promote adhesion of our barrier layers (as
described in section 5.4) as follows: before the actual barrier layer deposition we always
first deposit a 30-nm-thick SiNx layer using a RF deposition power of 213 mW/cm2. This
is a ultra-high deposition power compared to the usual RF deposition power we use in
our PE-CVD system for SiNx deposition. As can be seen in Figure 5.9, this film will have
a high  M and therefore we usually only deposit a thin layer of SiNx at this high power
(for adhesion) and then reduce the RF deposition power to a lower value (to balance out
the total strain in the work-piece).
84
In summary, we can achieve crack-free film deposition by (1) adjusting the film
deposition power to minimize the total strain in the composite structure and/or (2)
improve the adhesion between the substrate and the film. The exact deposition conditions
for the barrier layers and gate dielectric deposition were determined experimentally and
are discussed in section 5.4.
Deposition power
17mW/cm2
2µm
66mW/cm2
2µm
133mW/ cm2
20µm
Figure 5.10 SEM pictures demonstrating the effect of changing the deposition power on
the cracking of various SiNx films.
85
400µm
Figure 5.11 Surface wrinkling of a CP-2 substrate with a ~ 300-nm-thick SiNx film
deposited at 213 W/cm2.
5.3.3 Substrate loading and handling
The way the substrates are loaded has a large impact on how they survive at high
temperatures. Localized heating and temperature gradients in the deposition chamber
require special loading techniques to ensure that the temperature is evenly distributed
across the surface of the workpiece.
In our PE-CVD system the transfer tray is designed to load 3x3 square inch size
substrates. For high temperature processing our plastic workpieces are cut slightly
smaller than 3‟‟x3‟‟ (roughly 2.8‟‟x2.8‟‟) to allow space for the substrate to expand as it
is heated without it hitting the edge of the transfer tray holder. This means that we need to
use a frame to adapt the size of the transfer tray holder to smaller substrates. When we
process substrates at low temperature (< 250oC) we use a 3‟‟x3‟‟ metal „frame‟ for this
86
purpose. This frame is loaded into the transfer tray holder and we then balance the
substrates on top of the frame. The substrates will be facing downward into the plasma
with this loading set-up. After loading the substrate we cover it with a glass slide and a
carbon plate. The glass serves to flatten out the plastic and the carbon serves as black
body absorber for radiative heating in the nominally isothermal PE-CVD pre-heat and
deposition zones.
Glass backing slide
CP after cooling
Cracks in the SiNx film
deposited on top of the
substrate
Edge of CP at 300oC
Place where CP melted
Figure 5.12 Schematic showing how the substrate sticks to glass backing substrates in
high temperature depositions.
87
Figure 5.13 Effect of Kapton substrate holder „sagging‟, causing substrate wrinkling and
deformation
Edge of Kapton holder
Graphite
cover
Glass slide
CP
Kapton backing
Edge of CP substrate
Kapton holder
Figure 5.14 Diagram of loading technique for high temperature deposition
88
However when the edges of the plastic are supported by a metal frame, they start
melting when the substrate is moved into a deposition chamber that is at 300oC. We
believe this is due to the fact that the temperature is not evenly distributed across the CP
surface and that heat is transmitted from the metal holder. What happens in this case is
that the edges of the CP experience higher temperatures than the center of the CP, which
causes the edges to melt and stick to the glass backing slide. When the substrate is then
moved to the load lock, and cooled down it tries to shrink. The edges of the CP substrate
that are stuck to the glass slide are not able to shrink with the rest of the substrate and this
causes the substrate to deform, as well as causing the deposited films on top of the
substrate to crack. When we unload the susbtrate we have the situation shown
schematically in Figure 5.12. This figure shows a CP substrate unloaded from our PECVD system following SiNx deposition at 300oC. The dotted line shows the outer edge of
the CP substrate when it has expanded at 300oC. The dark blue spots are places where the
substrate has melted and the area colored in light blue is the area of the CP after it is
cooled down and has been unloaded. The cracks in SiNx films are due to the substrate
pulling at the melted corners. To solve this problem we replaced the metal holder with a
frame cut from a piece of Kapton, which has a much smaller thermal transmission. Care
must be taken that the Kapton frame is not too „floppy‟ since this can result in waviness
or substrate deformation (Figure 5.13) if the substrate is not supported correctly.
Another problem with our standard loading method is observed when we look at
the surface of the glass backing slide following a 300oC deposition while loading the CP
with the standard method (using a metal frame). The glass surface of the glass backing
slide becomes dirty after a deposition cycle involving moving the substrate from a low
89
temperature to 300oC and subsequent cooling prior to unloading. We believe this is due
to the substrate „rubbing‟ against the top glass as the plastic expands (the glass slide
expands only very little compared to the plastic substrate during a temperature cycle). For
this reason we replaced the metal holder and used a Kapton sheet in-between the plastic
workpiece and the glass slide. This set-up is shown in Figure 5.14.
The impact using different loading techniques on substrate stress (as can be seen
from the curvature) is shown in Figure 5.15. The CP-2 substrates in this experiment were
preshrunk in the PE-CVD load lock at 220oC for 2 to 4 hours. The temperature set-points
used in our system to obtain the correct temperature (for all chambers) can be found in
Appendix A.1-A.2. We then moved the sample to the PE-CVD N-chamber. The substrate
was left in the N-chamber (without any deposition) for 30 minutes to allow it to acclimate
to the high temperature. Then the front of the substrate was exposed to an Ar plasma (the
With Kapton backing
Without Kapton backing
(a)
(b)
Figure 5.15 Two substrates loaded with (a) the new and (b) the old method. See text for
explanation.
90
settings in the N-Chamber for our PE-CVD system were: Ar flow rate = 50 sccm, RF
power = 12 W, chamber pressure = 500 mTorr) for 3 minutes. Then we deposited a 390nm thick silicon nitride film at 48 W and 280oC (set-point 330, 330, 310 for the Nchamber heaters) on a CP-2 substrate. For the substrate in Figure 5.15(a) we used the new
loading method (a Kapton holder and a Kapton backing slide in addition to the usual
glass slide) and in Figure 5.15(b) we used the old loading method (i.e., a metal frame and
a glass backing slide). After film deposition, the CP-2 substrate was moved to the LL and
allowed to cool to ~ 50oC before removing the sample. The curvature of the substrate in
Figure 5.15(b) is more uneven, indicating uneven expansion during heating while the
substrate in Figure 5.15(a) has a cleaner curvature.
Another aspect that is important for implementing photolithography and etching
steps is how we handle the plastic substrate. We temporarily mount the substrate on a
3‟‟x 3‟‟ glass slide to allow us to spin liquids onto the substrate surface using a spinner.
We do this by placing small drops of de-ionized (DI) water onto the surface of a clean
glass slide using a dropper. Then we place the substrate on top of the DI water drops, and
use a N2 gun to gently blow on top of the substrate. This step forces out excess water
trapped between the glass slide and the back of the substrate, and flattens the substrate
onto the glass slide. We can now place the substrate/glass combination onto a chuck in
the spinner and coat the substrate surface with hexamethyldisilazane (HMDS) adhesion
promoter and AZ5214 photoresist (PR) as usual. Next we load the susbtrate (still attached
to the glass slide) onto a hot-plate and bake it at 110oC for 60 to 90 seconds. We then
load the substrate into the mask aligner, leaving it attached to the glass slide. If the
substrate becomes detached from the glass slide at this point (for example if the plastic
91
has a strong curvature following the deposition of highly stressed inorganic device layers)
it can be re-attached to the glass carrier with more DI drops (again followed by blowing
the surface with the N2 gun to remove excess DI water).
After the mask alignment and UV exposure steps, we gently strip the substrate
from the glass slide using tweezers, taking care not to scratch the surface of the substrate.
Now the free-standing substrate is developed in AZ300 for approximately 50 seconds (for
the standard photolithography process). Subsequent wet-etch steps involve dropping the
substrate into a beaker with the etchant and gently swirling the liquid until the required
etch has been completed. Dry etching involves loading the substrate into the tool (in our
Exposed
Unexposed
1000µm
Figure 5.16 Optical micrograph showing the response of clear plastic substrates to
PRS1000 photoresist stripper exposure. The picture on the left is the bare substrate
dipped into PRS1000 for 1 minute
92
lab we use a Plasmatherm 790 and a Plasmatherm 720). The edges of the substrate are
covered with 3‟‟x 1‟‟ glass microscope slides to flatten the substrate and prevent plasma
damage to the back of the substrate.
5.3.4 Substrate chemical resistance
We found that our CP substrates have a higher chemical sensitivity than other
commonly used plastic substrates such as Kapton E polyimide. CP substrates swell up
when exposed to acetone or PRS1000 photoresist stripper, which means we need be
careful to picking chemicals for photoresist removal after photolithography that don‟t
damage the CP substrates. Figure 5.16 shows the swelling of CP-2 when exposed to
PRS1000. Due to this chemical sensitivity we stripped our photoresist by flood exposing
it for 10 minutes in 3.5 mW/cm2 UV-light at a wavelength of 405nm using our maskaligner. This flood-exposure is followed by dipping the substrate into AZ312 photoresist
developer to strip the photoresist. If very clean surface areas are essential we follow the
dip in AZ312 developer with an oxygen plasma surface (descum) treatment. The settings
used in our RIE790 plasma etcher are: O2 flow rate = 40 sccm, pressure = 115 mTorr, RF
power = 60 W, and etch time = 10 min. After the descum step we dip the substrate into a
BOE(1:10) diluted with DI to a BOE:DI(1:100)
93
5.4 Optimized barrier layer deposition at 300oC on CP-2 and CP-3
The optimized barrier layer recipes that were developed for CP-2 and CP-3 are
different due to differences in the substrate CTE, as discussed in section 5.2.3. The exact
deposition conditions for optimized barrier layers (for CP-2 and CP-3) are listed in Table
5.2 and SiNx deposition rates are given in Appendix A.5. We used 5 W and 20 W RF
deposition powers for the gate dielectric in our experiments on CP-2 and therefore two
different barrier layer recipes are listed in table 5.2 (optimized for each gate dielectric
deposition power). Variations in CTE for different CP-2 shipments meant that the barrier
layer deposition conditions had to be adjusted for each shipment to determine the most
effective deposition conditions. Therefore the deposition conditions that are listed in
Table 5.2 for use with CP-2 are intended as guidelines, but would require adjustments for
fabrication runs with any new CP-2 shipments. The CTE for CP-3 is fixed, and therefore
the listed barrier layer conditions are the final optimized conditions for barrier layer
deposition on CP-3 from any shipment.
The following discussion explains barrier layer deposition for generic barrier
layers deposited on the front and back of CP substrates (refer to table 5.2 for the exact
deposition conditions of each barrier layer).

Our substrate is first prepared for barrier layer deposition as follows:
o a 2.8‟‟x2.8‟‟ piece of CP is loaded into the PE-CVD load-lock using the
procedure described in section 5.3.3.
o Following an outgassing anneal at 200ºC in the load lock for 2 to 4 hours, the
substrate is transferred to the N-chamber at 280ºC. The temperature set-points
94
used in our system to obtain the correct temperature (for all chambers) can be
found in Appendix A.1-A.2.
o The substrate was left in the N-chamber (without any deposition) for 30
minutes to allow it to acclimate to the high temperature.
o Then the front of the substrate was exposed to an H2 plasma (the settings in
the N-Chamber for our PE-CVD system were: H2 flow rate = 100 sccm, RF
power = 12 W, chamber pressure = 500 mTorr, time = 180 s) and an Ar
plasma (the settings in the N-Chamber for our P-CVD system were: Ar flow
rate = 50 sccm, RF power = 12 W, chamber pressure = 500 mTorr, time=180s
o Following these plasma treatments 30 nm of SiNx was deposited at 213
mW/cm2 (ultra-high power) for adhesion (see the discussion in section 5.3.2).
Now the front SiNx barrier layer is deposited.
o The substrate is then transferred back to the load lock and flipped so that its
back side is exposed to the plasma during the next deposition step.
o It is returned to the N-chamber at 280ºC and now the back side of the
substrate is also exposed to a H2 and an Ar plasma, and a 30 nm of SiNx is
deposited at 213 mW/cm2 (ultra-high power). Subsequently, the back SiNx
barrier layer is deposited.
95
Table 5.2 Optimized barrier layers for CP-2 and CP-3 deposited at 280oC
CP-2
Barrier
Layer
Deposition power
(W)
Thickness
(nm)
Gate dielectric power
(W)
Front
4
150
5
Back
5
300
Front
4
200
Back
20
300
Barrier
Layer
Deposition power
(W)
Thickness
(nm)
Gate dielectric power
(W)
Front
4
200
48
Back
20
300
20
CP-3
5.6 Summary
This chapter discussed CP substrate properties, stress control and adhesion for
inorganic layers deposited at 280-300oC on CP substrates and substrate loading and
handling. Then the final barrier layers optimized for CP-2 and CP-3 were presented. The
following chapter will proceed to explain how we fabricate a-Si:H TFTs on CP substrates
that have been prepared using the methods discussed in this chapter.
96
REFERENCES
[1] R. W. G. Hunt, “Measuring Color”, Fountain Press, England, 1991
[2] A. Z. Kattamis, K. H. Cherenack, B. Hekmatshoar, I-C Cheng, H. Gleskova, J. C
Sturm, and S. Wagner, “Effect of SiNx gate dielectric deposition power and temperature
on a-Si:H TFT stability”, IEEE Elect. Dev. Lett., vol. 28, pp. 606–608, 2007
[3] K. Long, Ph.D Thesis, Princeton University, 2006
[4] I-C. Cheng, A. Z. Kattamis, K. Long, J. C. Sturm, and S. Wagner, “Stress control for
overlay registration in a-Si:H TFTs on flexible organic-polymer-foil substrates”, J. Soc.
Inf. Disp., vol. 13/7, pp. 563-568, 2005
97
Chapter 6
STANDARD a-Si:H TFTs FABRICATED AT 300oC ON CLEAR PLASTIC
6.1 Introduction
This chapter discusses the 300oC fabrication process that was developed to
fabricate
back-channel
cut
and
back-channel
passivated
TFTs
by
standard
photolithography (without any self-alignment). The CP-2 and CP-3 substrates used in the
processes in this chapter were all prepared and coated on both sides with barrier layers as
described in section 5.4 of Chapter 5. Figure 2.2 in Chapter 2 shows the TFT structure of
both TFT structures that are described here.
This chapter is structured as follows: in Section 6.2 we provide details on making
back-channel cut TFTs and section 6.3 provides the details on making back-channel
passivated TFTs. Then, in section 6.4 we discuss the measured TFT electrical and
stability performance for non-self-aligned TFTs fabricated at 300oC. Section 6.5
discusses back-channel cut and back-channel passivated TFTs fabricated using a SiNx
deposition temperature of 350oC. Finally, section 6.6 discusses how the TFT contact
resistance and mobility was affected by replacing the n+ a-Si:H layer with a n+ nc-Si
layer.
Chapter 7 will build on the work in this chapter in describing how we fabricate
back channel cut and back channel passivated TFTs at 300oC by self-aligning two or
more of the device layers.
98
6.2 Back channel cut a-Si:H TFTs
The schematic of the back-channel cut TFT geometry is shown in Figure 2.2(a).
This is a 4-mask fabrication process. The fabrication steps are illustrated in Figure 6.1
and Appendix C.1 contains a table with the details of each process step. The fabrication is
carried out as follows:
After barrier layer deposition, according to the method discussed in 5.4 (step 1), a
tri-layer of Cr/Al/Cr (15nm/70nm/15nm) is deposited using thermal evaporation (step 2)
and patterned with mask 1 using photolithography (step 3). After wet-etching we deposit
the TFT stack consisting of 300 to 400 nm SiNx gate dielectric, 200 nm thick a-Si:H
active layer and 30 nm n+ doped a-Si layer (step 4). The PE-CVD deposition conditions
used for all the device layers are summarized in Table 6.1. Note that the RF deposition
powers for the gate dielectrics are different for CP-2 and CP-3. For gate dielectric
deposition on CP-2, we used two different SiNx RF deposition powers: 5 W and 20 W
deposition powers (22 mW/cm2 and 88 mW/cm2 power densities). For CP-3 both of these
recipes resulted in cracked TFT stacks, but we were able to obtain a crack-free TFT stack
deposition using a 48 W deposition power (213 mW/cm2 power density). Refer to Section
4.4 for a discussion of how high deposition powers improve device layer adhesion and
can allow the crack-free deposition of device films. The TFT stack deposition conditions
for our PE-CVD system are summarized in Appendix A.1. SiNx deposition rates at 300oC
are summarized in Appendix A.5.
After successful deposition of the TFT stack, a second metal tri-layer consisting
of 15/70/15 nm of Cr/Al/Cr was deposited using thermal evaporation (step 5). It was
99
patterned using mask 2 and wet-etched (step 6). It is important to note that the TFT
channel dimensions are defined by mask 2. The TFT channel area is described by the
W/L ratio, which is indicated in Figure 6.1. (Step 6-9 looks messed up on my computer.)
After patterning the S/D electrodes, the n+ layer was etched using reactive ion etching
(RIE) (step 7), followed by patterning the a-Si:H with mask 3 (using RIE) to define the
islands (step 8). Finally, we pattern the gate via holes with mask 4 and by standard
photolithography (step 9). We etch via holes using RIE. The completed TFTs are then
annealed in the I-chamber of the PE-CVD (under vacuum for) at 250oC for 1 hour.
Figure 6.2 shows an optical micrograph of a set of TFTs fabricated at 300oC on
clear plastic (CP-2), and Figure 6.3 shows a photograph showing a finished workpiece.
This demonstrates our success at depositing crack-free device layers on our clear plastic
substrates at 300oC.
Table 6.1 Back-channel cut a-Si:H TFT stack deposition conditions for CP-2 and CP-3
Layer
Deposition
power (W)
Thickness (nm)
Deposition
temperature (oC)
Substrate
SiNx
5
300
300
CP-2
20
300
300
CP-2
48
360
300
CP-3
a-Si:H
4
25-200
250
CP-2, CP-3
n+ a-Si:H
5
30-75
230
CP-2, CP-3
100
Top View
Side View
Step 1-3
Step 4
Step 5
Step 6-9
n+ a-Si/nc-Si
Source/drain
S/D metal
overlap
a-Si:H
SiNx
W
Clear plastic
L
Figure 6.1 Process sequence for bottom-gate, back-channel cut a-Si:H TFTs
101
500µm
Figure 6.2 Optical micrograph of a-Si:H TFTs fabricated at 300oC on a clear plastic
substrate
Figure 6.3 Photograph of a fully processed sample which is bent under its own weight.
The square substrate measures 7.5cm on its side.
102
6.3 Back channel passivated a-Si:H TFTs
The schematic of the back-channel passivated TFT geometry is shown in Figure
2.2(b). This is a 5-mask fabrication process. The fabrication steps are illustrated in
Figure 6.4 and Appendix C.2 contains a table with the details of each process step. The
fabrication process to make back-channel passivated TFTs includes two extra steps
compared to the process to pattern back-channel cut TFTs. These extra steps are required
to pattern the SiNx channel passivation layer.
After preparing the substrate according to the method in section 5.4 (step 1), the
gate metal (a tri-layer of Cr/Al/Cr which is 15/70/15nm thick) is deposited using thermal
evaporation (step 2) and patterned (step 3) as before (mask 1). After patterning the gates
we deposited the TFT stack consisting of 300-400nm SiNx gate dielectric, 200nm thick aSi:H active layer, and a 150nm thick SiNx layer deposited at low temperature (200oC) to
passivate the channel. We once again used 5W and 20W deposition powers (22 and 88
mW/cm2 deposition power densities) on CP-2 and 213 mW/cm2 on CP-3 (step 4). The
PE-CVD deposition conditions used for all the TFT stack layers in this process are
summarized in Table 6.2.
After depositing the TFT layers we patterned the channel passivation layer using
standard photolithography (mask 2) and wet-etched the SiNx layer with 1:10 buffered
oxide etch (BOE) (step 5). We prepared the substrate surface for the n+ nc-Si deposition
as follows: first we carefully cleaned the surface of the substrate by exposing it to a
piranha etch (1:10 mixture of H2O2 and H2SO4) for 15 minutes, followed by a dip into a
1:100 BOE:DI mixture. The substrate was then briefly rinsed in DI water to remove
103
residual acid from the surface and immediately loaded in the PE-CVD load lock, which
was then pumped down to vacuum. After heating the substrate to 200 oC in the load lock
chamber, the substrate was transferred to the P-chamber and exposed to a short Ar
plasma (the settings in the P-Chamber for our PE-CVD system were: Ar flow rate = 50
sccm, RF power = 12 W, chamber pressure = 500 mTorr, time = 120 s) to promote
adhesion. We then deposited 30 nm n+ a-Si:H (step 6).
Next, the second metal tri-layer consisting of 15/70/15 nm of Cr/Al/Cr was
deposited using thermal evaporation (step 7) and patterned with mask 3 (step 8) using
standard photolithography and wet-etched. The TFT channel dimensions are defined by
the overlap of the S/D electrodes defined by this mask and the channel passivation layer.
The TFT channel area is described by the W/L ratio, which is indicated on Figure 6.4.
After patterning the metal for the S/D electrodes we etch the n+ layer using RIE (step 9),
followed by photolithography (using mask 4) and RIE etching of the a-Si:H to define the
islands (step 10), and etching of the gate via holes (step 11) with mask 5. The completed
TFTs are then annealed in the I-chamber of the PE-CVD (under vacuum) at 250oC for 1
hour.
104
Table 6.2 Back-channel passivated a-Si:H TFT stack deposition conditions for CP-2 and
CP-3
Layer
Deposition
power (W)
Thickness (nm)
Deposition
temperature (oC)
Substrate
SiNx
5
300
300
CP-2
Gate
dielectric
20
300
300
CP-2
48
360
300
CP-3
a-Si:H
4
25-200
250
CP-2, CP-3
SiNx
5
150
280
CP-2,CP-3
5
30-75
230
CP-2, CP-3
passivation
n+ a-Si:H
105
Side View
Steps 1-3
Step 4
Step 5
Top View
106
Step 6-7
Step 8-11
SiNx
S/D metal
n+ a-Si/nc-Si
a-Si:H
SiNx
W
Clear plastic
L
Figure 6.4 Process sequence for bottom-gate, back-channel passivated a-Si:H TFTs
107
6.4 Performance of a-Si:H TFTs fabricated on CP-2 at 300oC
Before carrying out a detailed investigation into high-temperature TFTs on plastic
it is important to investigate the possibility of changes in device performance due to
different substrates and TFT geometries.
To test the effect of the same process with different substrates, we fabricated the
back channel cut a-Si:H TFTs using the process described in section 6.2 on both glass
and plastic (CP-2, using a TFT stack with the gate dielectric deposited at 5 W) and
compared the device performance. The Corning Eagle 2000 glass substrates that were
used by us do not require a barrier layer, and therefore we skip to step 3 of the process
when working with glass substrates. Figure 6.5 compares typical transfer characteristics
for TFTs fabricated on glass and plastic using an identical fabrication process and TFT
geometry. The method used to measure the transfer characteristic, and how we extract
performance parameters from it, is described in Appendix B.1. From the transfer
characteristic in Figure 6.5, it can be seen that the gate-source leakage current increases
for devices made on plastic but the transfer curves overlap very well and there is no
major change in electrical performance when moving from one substrate to another.
We also compared the transfer characteristics of a-Si:H TFTs fabricated using the
process described in section 6.2 (back-channel cut geometry) and section 6.3 (backchannel passivated geometry). Both processes were carried out using a CP-2 substrate,
and the TFT stack recipe with the gate dielectric deposited at 5 W. As can be seen in
Figure 6.6 the transfer characteristics for TFTs fabricated on plastic with different
processes (but with the same deposition conditions for the individual device layers) are
108
virtually identical, and the different TFT geometries seem to have no effect on the
measured transfer characteristics of the devices.
-
W/L=80µm/40 µm
Plastic
Glass
10-5
VDS=10V
VDS=0.1V - 10-8
10-8
-
10-11
-
10-14
-|
|
|
-10
0
10
-
10-11
-|
10-14
Gate-source current IGS [A]
Drain-source current IDS [A]
10-5
20
Gate Voltage VGS (V)
Figure 6.5 Transfer characteristic of back-channel cut a-Si:H TFTs fabricated on CP-2
(red) and glass (blue) using the process described in section 6.2 and the TFT stack
recipe with a 5 W gate dielectric.
Drain-source current IDS [A]
10-5
W/L=80µm/40µm
Process 6.2
Process 6.3
-
10-5
VDS=10V
10-8
-
VDS=0.1V
10-8
10-11
-
-
10-11
10-14
-|
-|
10-14
-10
|
0
|
10
Gate-source current IGS [A]
109
20
Gate Voltage (V)
Figure 6.6 Transfer characteristics of back-channel cut a-Si:H TFTs, fabricated as
described in section 6.2 (blue) and back-channel passivated TFTs, as described in section
6.3 (red). The substrate that was used is a CP-2 substrate, and the TFT stack recipe used
had a 5 W gate dielectric.
110
6.4.1 Electrical performance
After establishing that there is no noticeable effect on the device performance
due to the type of substrate or TFT geometry used we can now examine the performance
parameters for back-channel cut and back-channel passivated TFTs fabricated at 300oC.
Figure 6.7 shows the transfer characteristics for back-channel cut TFTs fabricated
using the process in section 6.2. The substrate used was CP-2, and the deposition power
of the gate dielectric was 20 W. From the transfer characteristics we extract the saturation
mobility µSAT, the linear mobility µLIN, the threshold voltage VTH, the subthreshold slope
S, and the ON/OFF current ratio ION/IOFF, using the method described in Appendix C.1.
The performance parameters are summarized in Table 6.3. From this data we can see that
we obtain TFTs with high mobilities, and low threshold voltages VTH. Therefore, these
TFTs are suitable for integration into display backplanes from an electrical performance
perspective.
There is one TFT mask design issue that could increase the electron field-effect
mobility that we calculate in this thesis. In our TFT masks (for a-Si:H TFTs on plastic
fabricated using high deposition temperatures) we always design a large a-Si:H island
layer. This is to ensure that the island will cover the channel region even if we have large
misalignment between device layers, as discussed in section 3.2. However, a
consequence of such large a-Si:H islands is that there will be more current spreading at
the edge of the channel region, as shown in Figure 6.7. This figure shows the edge of the
channel region for a TFT with a large island. The arrows in the figure show possible
current paths between the S/D terminals. Straight arrows show current in the channel
111
region, while curved arrows show current that spreads beyond the defined channel region.
These additional current paths means that we are measuring a current that is higher than
expected. Therefore the calculated electron mobility could be larger than the true
Drain-source current IDS [A]
10-5
W/L=80µm/40µm
Processed at 300oC
-
10-5
VDS=10V
10-8
-
VDS=0.1V-
10-8
10-11
-
-
10-11
10-14
-|
|
-|
10-14
10
20
-10
|
0
Gate-source current IGS [A]
mobility. This situation requires further study.
Gate voltage VGS (V)
Figure 6.7 Transfer characteristic of a back-channel cut a-Si:H TFT fabricated on clear
plastic at 300oC
112
Table 6.3
Performance parameters of back-channel cut a-Si:H TFT
fabricated at 300oC, W/L = 80 µm/40 µm, fabricated on CP-2, and a gate
dielectric deposition power of 20 W
Linear mobility µLIN
1.08 cm2/Vs
Saturation mobility µSAT
0.86 cm2/Vs
Threshold voltage VTH
Subthreshold slope S
1.21 V
670 mV/decade
> 107
ION/IOFF
a-Si:H island
Drain
Source
Figure 6.8 Schematic of the edge of a TFT channel region, showing possible current
paths between the S/D terminals. The arrows indicate possible current paths between the
S/D terminals
113
6.4.2 Threshold voltage stability
Next, we consider the threshold voltage stability of our TFTs fabricated on CP-2
and CP-3 at 300oC. We changed three parameters in the fabrication process (1) the SiNx
deposition temperature, (2) SiNx deposition power and (3) TFT geometry to investigate
the effect on ∆VTH. Gate bias stressing (as a function of changing gate stress field EST or
changing stress time τST) is carried out on individual TFTs from each process run and
∆VTH is extracted for each stress test using the method described in Appendix B.2.
Past research in our group has proved that higher SiNx deposition temperatures [1]
and deposition powers [2] lead to more stable devices. There is an additional effect: TFTs
fabricated using the process described in 6.3 (back-channel passivated geometry) are also
more stable, especially at higher stress fields. A summary of all process and TFT
geometry effects on ∆VTH is shown in Figure 6.9. This is a plot of ∆VTH versus EST for a
constant TST of 600 s according to the constant τST test described in Appendix B.2. The
stress tests were carried out for back-channel cut TFTs fabricated previously on CP-1 [1]
using process temperatures of 150oC, and 250oC, and the back-channel cut (section 6.2)
and back-channel passivated (section 6.3) TFTs fabricated at 300oC on CP-2, CP-3 and
glass. We also plot ∆VTH obtained from literature for TFTs fabricated on glass substrates
at 350oC [3]. Clearly, ∆VTH of devices fabricated at 150oC and 250oC is larger than ∆VTH
for devices fabricated at 300oC for the same stress conditions. Similarly, if we compare
∆VTH for devices fabricated at the same temperature but using two different gate
dielectric RF deposition powers we find that ∆VTH is larger for devices fabricated using
lower deposition powers. For example, at the stress field of 1x108 V/m, the threshold
114
voltage shift ∆VTH for 150oC TFTs is 4 V, decreases to 2 V for 250oC, and to 1.1 V for
300ºC (for TFTs that have a gate dielectric deposition power of 20 W) or 0.65 V (for
TFTs that have a gate dielectric deposition power of 48 W). There is a large gain in
stability when increasing the SiNx deposition power from 20 to 48 W – in fact the
stability of devices with a SiNx deposition power of 48 W is close to that of TFTs
fabricated on glass at 350oC. Another stress test that demonstrates the low ∆VTH shift for
devices that have a 48 W gate dielectric deposition power is plotted in Figure 6.10. This
Figure shows the result of a constant EST of 1x108 V/m applied to the TFT gate for 100 to
10,000 seconds. The TFTs that were tested were all fabricated at 300oC on CP-2, had
SiNx deposition powers of 5 W, 20 W and 48 W and were back-channel passivated
according to the process described in section 6.3.
115
Figure 6.9 ∆VTH versus EST for a-Si:H TFTs fabricated on clear plastic and glass with
various SiNx deposition temperatures and powers. The label for each plotted line
indicates the substrate type used for the measured TFT, the TFT geometry, the SiN x
deposition temperature and the gate dielectric deposition power where it is known.
Measurements made for TFTs on plastic are plotted with solid lines. Measurements made
for TFTs on glass are plotted with dashed lines.
116
10
Stress field = 1x108 V/m
Threshold voltage shift ∆VTH (V)
W/L = 80 µm / 40 µm
300oC process
5W
1
48W
20W
0.1
|
|
10
100
|
1,000
|
|
10,000
100,000
Stress time (s)
Figure 6.10 Comparison of the threshold voltage shift for a constant applied gate stress
field of 1x108 V/m plotted against τST for a-Si:H TFTs fabricated on clear plastic at 300oC
with gate dielectric deposition powers of 5 W, 20 W and 48 W. All TFTs had a W/L of
80 µm / 40 µm.
117
Clearly, ∆VTH decreases for tests carried out on TFTs that have higher gate
dielectric RF-deposition power. From this data it becomes clear that we are able to
fabricate TFTs with an electrical performance and stability that is equivalent to that of
TFTs on glass. Our 300oC back-channel passivated TFT process promises to enable the
fabrication of ultra-stable TFT backplanes on plastic that are equivalent in performance to
those made on glass. The most stable devices are achieved by fabricating the TFTs using
a high SiNx deposition power, a high deposition temperature and a back-channel
passivated TFT geometry.
118
6.5 Performance of a-Si:H TFTs fabricated on CP-3 at 350oC
At temperatures above 300oC the substrate softens considerably as the glass
transition temperature is approached. As a direct result of this softening the CTE becomes
very large and we were not able to deposit crack-free device layers over the entire
substrate. However, we were still able to process individual devices on substrates where
the SiNx dielectric layer was deposited at 350oC, and measure the TFT performance.
We fabricated both back-channel cut and back-channel passivated TFTs on CP-3
at 350oC using the fabrication process outlined in sections 6.2 and 6.3. The only
difference for depositing the gate dielectric in the processes discussed in this section
(compared to the 300oC processes) is the deposition temperature of the gate dielectric
(350oC). All other layers were deposited using the conditions stated in tables 6.1 and 6.2.
Figure 6.11 shows optical micrographs of completed back-channel cut and back-channel
passivated TFTs fabricated on CP-3 at 350oC. It is clear from these pictures that the
plastic substrate is extremely wrinkled; this process temperature is not suitable for largearea fabrication. Figure 6.12 shows the transfer characteristic for a single a-Si:H TFT
fabricated at 350oC and Table 6.4 lists the performance characteristics extracted from this
curve. Clearly, the low VTH, high µLIN and µSAT, show that these devices have interesting
characteristics. We did not pursue this work further because of the impractically high
process temperature.
119
100µm
100µm
(a)
(b)
Figure 6.11 Optical micrographs of a–Si:H TFTs fabricated on clear plastic at 350oC (a)
Drain-source current IDS (A)
10-5
W/L = 80 µm / 40 µm
Processed at 350oC
-
10-5
-
10-8
-
10-11
10-14
VDS = 10 V
10-8
-
10-11
-
10-14
-|
|
|
-|
-10
0
10
20
VDS = 0.1 V
Gate-source current IGS (A)
back-channel cut and (b) back-channel passivated
Gate voltage VGS (V)
Figure 6.12 Transfer characteristic of a back-channel cut a-Si:H TFTs fabricated on CP-3
at 350oC
120
Table 6.4
Performance parameters of back-channel cut a-Si:H TFT
fabricated at 350oC, W/L = 80 µm / 40 µm, fabricated on CP-3
Linear mobility µLIN
1.49 cm2/Vs
Saturation mobility µSAT
1.18 cm2/Vs
Threshold voltage VTH
Subthreshold slope
ION/IOFF
0.85 V
460 mV/decade
 106
6.6 Decreasing the S/D parasitic contact resistance
This section describes our work to decrease the parasitic contact resistance in the
S/D electrodes. We carried out two experiments to see if we could decrease the contact
resistance: (1) we replaced the n+ a-Si:H in the contacts with n+ nc-Si and (2) we reduced
the thickness of the a-Si:H active layer down to 25 nm. The motivation for these changes
and how they were expected to impact the contact resistance was described in section
2.4.2. The n+ nc-Si deposition method that we developed is described in Appendix A.7
and was characterized according to the method described in Appendix B.4.
121
6.6.1 TFT performance with n+ a-Si:H and nc-Si contacts
We fabricated two process runs of back-channel cut a-Si:H TFTs on CP-2 using
the fabrication method described in 6.2. The gate dielectric was deposited at 20 W
(88 mW/cm2). In the first process run the n+ contact material was the usual n+ a-Si and in
the second process run the n+ a-Si in the S/D contacts was replaced with n+ nc-Si grown
using the LBL method we developed. The thickness of the a-Si:H layer in both TFT
processes was 200 nm. Figure 6.13 compares the transfer characteristics of TFTs from
both process runs with a W/L = 80 µm / 40 µm. The mobility of these TFTs was
extracted from these transfer curves and is compared in Table 6.5. There is a clear
improvement in both the measured linear and saturation mobilities. Therefore, for the rest
of our fabrication runs we replaced the n+ a-Si layer in the contacts with an n+ nc-Si layer.
Drain-source current IDS (A)
Drain-source current IDS [A]
10-5
W/L = 80 µm / 40 µm
n+ nc-Si
n+ a-Si
-
10-5
-
10-8
-
10-11
-|
10-14
VDS = 10 V
10-8
-
10-11
-
10-14
-|
|
|
-10
0
10
VDS = 0.1 V
Gate-source current IGS (A)
122
20
Gate Voltage VGS (V)
Figure 6.13 Transfer characteristic of a-Si:H TFTs fabricated as back-channel cut, with
n+ nc-Si contacts (red) and n+ a-Si contacts (blue). W/L = 80 µm / 40 µm.
Table 6.5 Comparison of back-channel cut TFTs fabricated with
n+ a-Si and n+ nc-Si layers in the S/D contacts. W/L = 80 µm / 40 µm
n+ doped contact
a-Si
nc-Si
Linear mobility µLIN
(cm2/Vs)
0.79
1.01
Saturation mobility
µSAT (cm2/Vs)
0.73
0.91
123
6.6.2 TFT performance with thick and thin a-Si:H active layers
To test the effect of changing the a-Si:H layer thickness, we fabricated two
process runs of back-channel passivated a-Si:H TFTs on clear plastic (batch CP-2) using
the fabrication process in section 6.3 and a 300 nm thick gate dielectric deposited at a
power of 20 W (88 mW/cm2). In the first process run the a-Si:H layer was 200 nm thick
and in the second process run the a-Si:H layer thickness was reduced to 25 nm. Both
processes used n+ nc-Si in the S/D contacts. Figure 6.14 compares the transfer
characteristics of TFTs from both process runs with a W/L = 80 µm / 80µm. The mobility
of these TFTs was extracted from these transfer characteristics and compared in Table
6.6. In this experiment the change in the field-effect mobilities from one process to the
next is less obvious. However, both processes result in high mobilities with a backchannel passivated TFT structure.
Drain-source current IDS (A)
10-5
W/L = 80 µm / 80 µm
Thick a-Si
Thin a-Si
10-8
-
10-11
-
10-14
-|
-10
0
10-5
-
10-8
-
10-11
-
10-14
VDS = 10 V
VDS = 0.1 V
|
-
|
|
10
20
Gate Voltage VGS (V)
Figure 6.14 Transfer characteristic of a-Si:H TFTs fabricated as back-channel
passivated, with a 200 nm a-Si:H active layer (blue) and a thin 25 nm a-Si:H active
layers (red) W/L = 80 µm / 80 µm
Table 6.6 Comparison of back-channel passivated TFTs fabricated with n+
as thick and thin a-Si:H active layers. W/L = 80 µm / 80 µm
a-Si:H layer thickness (nm)
200
25
Linear mobility µLIN (cm2/Vs)
1.07
1.19
Saturation mobility
µSAT (cm2/Vs)
0.98
0.92
Gate-source current IGS (A)
124
125
6.6.3 Discussion of the measured increase of the electron field-effect mobility
We tried to increase the measured electron field-effect mobility by decreasing the
parasitic contact resistance in the S/D terminals. We did this by adjusting our fabrication
process. A lower parasitic contact resistance will reduce the amount of voltage drop
across the S/D parasitic resistance when the TFT is ON (see section 2.4.2). Therefore for
a TFT with smaller parasitic resistances more of the total VDS is applied over the channel;
this means that the TFT will conduct more current and we will measure a higher effective
electron mobility. From the results in sections 4.3.1 and 4.3.2 we see that we can increase
the measured µLIN by adjusting our fabrication process (especially when we replace the n+
a-Si:H layer with a n+ nc-Si layer in the contacts). However, the increase achieved for
µSAT is smaller. To understand this behavior, we consider equation 2.1 which describes
the model used to describe the current, IDS, that flows between the S/D terminals when
2
the TFT is on. We see that if the transistor is operating in the linear regime, I DS  VDS
whereas for a transistor operating in the saturation regime I DS is independent of VDS.
Therefore, we believe that µLIN is more sensitive to changes in the parasitic contact
resistance, and is more strongly affected by small reductions of the parasitic resistance.
126
6.7 Conclusion
In this chapter we discussed how we fabricated back-channel cut and backchannel passivated TFTs at 300oC on CP-2 and CP-3 using standard photolithography to
pattern the device layers. The devices were characterized with respect to electrical and
stability performance and we investigated changes in layer deposition conditions to
potentially increase the processing temperature or reduce the parasitic contact resistance.
As discussed in Chapter 3 we need to consider device layer misalignment when
we want to fabricate a-Si:H TFT circuits over large areas on plastic substrates. This is
especially true for device fabrication at 300oC since εTH becomes very large at this
temperature (refer to 4.3 and 4.4 for a discussion of the strain that develops in device
layers at elevated temperatures). The next chapter will present our work on
reducing/eliminating the misalignment between device layers using stress control as well
as self-alignment between various device layers.
REFERENCES
[1] K. Long, Ph. D., Thesis, Princeton University, 2006
[2] A. Z. Kattamis, K. H. Cherenack, B. Hekmatshoar, I-C Cheng, H. Gleskova, J. C.
Sturm, and S. Wagner. “Effect of SiNx gate dielectric deposition power and
temperature on a-Si:H TFT stability”, IEEE Elect. Dev. Lett, vol. 28, pp. 606-608,
2007
[3] F. R. Libsch and J. Kanicki, “Bias-stress-induced stretched-exponential time
dependence of charge injection and trapping in amorphous thin-film transistors”,
Appl. Phys. Lett., vol. 62, pp. 1286–1288, 1993.
127
Chapter 7
DEVICE LAYER ALIGNMENT
7.1 Introduction
This chapter presents the work done to minimize or eliminate device layer
misalignment. The background theory motivating this research is covered in Chapter 3.
To recap briefly: after depositing the TFT stack at high process temperatures, the
misalignment between device layers (as is discussed in Chapter 4) can become very large,
since εTH has an increasingly large impact on the final dimensions of the substrate. For a
process to tolerate misalignment between device layers due to these changes in substrate
dimensions, we need to design standard photolithography masks with very large overlaps
between the TFT gate, channel passivation and S/D terminals. For back-channel cut TFTs
the critical overlap that needs to be achieved is between the gate and the S/D terminals,
while for back-channel passivated TFTs there are two critical overlaps: 1) between the
channel passivation and the gate, and 2) between the S/D terminals and the gate. The
critical overlaps for back-channel passivated TFTs are indicated in Figure 3.2. The
critical overlap for back-channel cut TFTs is indicated in Figure 7.10.
To reduce the misalignment between device layers we can look at controlling the
total strain in the substrate. This is done by adjusting deposition conditions to reduce the
total stress in the workpiece (as described in section 4.3). Section 7.2 describes how we
reduce misalignment using this method. Another approach that eliminates misalignment
completely is to implement a self-alignment method. We will discuss the self-alignment
methods that were developed between the gate and the channel passivation (section
128
7.3.1), between the gate and the S/D terminals (section 7.3.2), and the gate, the channel
passivation, the S/D terminals, and the a-Si:H island (section 7.3.2). We also present the
performance of a-Si:H TFTs fabricated using these self-alignment methods. Chapter 8
will discuss ring-oscillator circuits that were fabricated using standard photolithography
(discussed in Chapter 6) and the self-alignment methods described in this chapter.
7.2 Strain control
One way to reduce device layer misalignment is to minimize the total strain in the
finished work-piece. This can be done by adjusting the deposition conditions of
individual device layers (see section 4.3), and/or by reducing the layer thickness.
We carried out the following experiment to demonstrate this concept: first we
prepared four CP-2 substrates and coated them with barrier layers as described in section
5.4 (the barrier layers made using a 20 W (88 mW/cm2) gate dielectric deposition power).
Then we deposit a TFT stack for back-channel passivated TFTs as discussed in section
6.3. The deposition conditions for the TFT stack are listed in Table 7.1. The thickness of
the SiNx gate dielectric is 150, 200, 250 or 300 nm, using a 300oC deposition temperature
and an RF deposition power of 215 mW/cm2. The a-Si:H layer thickness is reduced to 50
nm and the channel passivation layer thickness is reduced to 50 nm. Following TFT stack
deposition, the TFTs are completed as described in section 6.3.
The misalignment for completed devices fabricated using the standard process
described in 6.3 as well as for the process described in this section (using thinner device
layers in the TFT stack) was calculated from alignment marks at the edge of the substrate
129
Mark #1
Mark #3
Mark#2
Mark #4
Figure 7.1 Optical micrograph of the four alignment marks at the edge of a substrate
processed using strain control to minimize the total strain in the workpiece for backchannel passivated TFTs fabricated on CP-2 at 300oC. The gate dielectric thickness in the
TFT stack for this example was 200 nm
according to the method described in section 3.2 and appendix B.3. By reducing the TFT
device layer thickness we were able to reduce the misalignment between device layers
from ~60 µm at a distance of 5 cm from the center (= 1200 ppm), obtained by using the
standard process in Chapter 6, to ~ 300 ppm. The alignment marks used to calculate the
300 ppm misalignment at the corners of the substrate (for the process with reduced layer
thicknesses) are shown in Figure 7.1. Refer to Appendix B.4 for the where marks1-4 are
measured.
130
Unfortunately, reducing the thickness of the gate dielectric from 300 nm down to
~200 nm (and lower) decreases the TFT yield, and also degrades TFT performance.
Figure 7.2 shows the TFT transfer characteristic for the TFTs fabricated with a 200-nm
thick gate dielectric, showing poor TFT performance. Once we reduce the SiNx layer
thickness to below 200 nm, the piranha etch starts attacking the gate and passivation
layers, as is shown in Figure 7.3 for the TFTs that have a 150 nm thick gate dielectric
layer. For this reason we decided not to decrease the thickness of our gate dielectric
below 300 nm, and started looking at other methods to decrease or eliminate the
misalignment between critical device layers.
Table 7.1 Back-channel passivated a-Si:H TFT stack deposition conditions when
reducing TFT stack layer thickness. The substrate that was used is CP-2
Layer
Deposition power
(W)
Thickness
(nm)
Deposition
temperature (oC)
SiNx gate dielectric
5
150-300
300
a-Si:H
4
50
250
SiNx
Back-channel
Passivation
5
50
280
n+ a-Si:H
5
30
230
131
10-5
-
- 10
-5
VDS = 10 V
W/L = 80 µm /40 µm
10-8
-
- 10
-8
VDS = 0.1 V
10-11
-
10-14 |
-10
|
0
|
10
- 10
-11
-
-14
| 10
20
Gate-source current IGS (A)
Drain-source current IDS (A)
300oC process
Gate Voltage VGS (V)
Fig. 7.2 Transfer characteristic for a TFT fabricated using a 200-nm thick gate dielectric
200µm
Fig. 7.3 Optical micrographs showing an incomplete TFT with a 150-nm thick gate
dielectric (corrosion caused by the piranha etch)
132
7.3 Implementing self-alignment
The following sections discuss the methods for self-alignment that were
developed between various a-Si:H TFT layers. The background on self-alignment is
covered in Chapter 3. The position of the critical alignment gaps/overlaps between the
gate, the channel passivation and the S/D terminals are shown in Figure 3.3 for a backchannel passivated TFT. The critical overlaps for back-channel cut TFTs are indicated in
Figure 7.10. We developed three self-alignment processes for TFT fabrication on clear
plastic. We refer to them as SA-1, SA-2 and SA-3 for easy reference.
SA-1 - In this process we use a back-channel passivated TFT process to self-align
the gate (mask 1) and the channel passivation (mask 2).
SA-2 - In this process we use a back-channel cut TFT process to align the gate
(mask 1) and the source-drain terminals (mask 2).
SA-3 -This is a simplified version of SA-2.
The mask numbers indicated in the definitions of SA-1, SA-2 and SA-3 are the masks
that would be used to pattern these layers if we were using standard photolithography. In
any of the self-alignment processes that were developed, we spin photoresist onto the
front of the substrate and then expose our substrate from the back. In the areas where the
UV light is blocked, the photoresist will not be exposed, while in regions where the UV
light can pass through to the front of the substrate, the photoresist will be exposed and
can be removed with developer. Therefore, any layer that blocks the UV light will
become a mask that allows us to create a self-aligned pattern on the front of the substrate.
133
Optical transmittance T
0.10
CP coated with standard
barrier layer on both sides
0.08
T at 405 nm
0.06
0.04
0.02
0.00
380
390
400
410
420
Wavelength (nm)
Fig. 7.4 Optical transmittance in the violet and near-UV region of a CP-2 substrate coated
on both sides with the standard SiNx barrier layer, and of a 75-µm thick CP-2 substrate
coated on both sides with the standard barrier layer as well as 20-nm, 40-nm, and 80-nmthick i a-Si:H layers.
An essential requirement for implementing self-alignment is the ability to expose
the photoresist through the back of the substrate. Therefore we need an optically clear
substrate that allows the UV radiation to pass through it. From past experiments we know
that the optical absorption edge of our CP substrates lies at λ ~ 400 nm [1]. From the
transmittance measurements in Figure 5.1 we find that our CP-2 and CP-3 substrates have
a transmittance of ~15% at 405 nm. Therefore for photolithographic exposure in our
mask aligner we selected the mercury line at 405 nm. The optical absorption of SiNx at
405 nm is small but a-Si:H strongly absorbs in this region. This means we need to study
the optical transmission of our clear plastic coated with SiNx and a-Si:H layers.
134
We carried out the following experiment to determine the optimal a-Si:H layer
thickness to use in our TFT stack for self-alignment processes: we started by preparing a
CP-2 substrate as described in 5.3 and coated it with a barrier layer described in 5.4
(depositing the barrier layer using a gate dielectric deposition power of 20 W, a
88 mW/cm2 power density). Then we cut the substrate into four pieces. One piece was
left un-coated, and the front barrier layer for the other three was coated with a-Si:H layers
that were either 20, 40, or 80 nm thick. The optical transmission for each of these four
substrate pieces was measured at wavelengths from 380 to 420 nm and the results are
plotted in Figure 7.4. To keep the exposure time for the self-alignment step relatively
short we chose to use an a-Si:H channel layer thickness of 25 nm for all of our selfaligned TFT processes. This thickness corresponds to an a-Si:H layer deposition time of
150 s, using the 250oC a-Si:H deposition recipe from Appendix A.3-4.
7.3.1 Aligning the channel passivation layer to the gate (SA-1)
The following section discusses the SA-1 method we used to fabricate backchannel passivated a-Si:H TFTs at a process temperature of 300oC on 2.7’’x 2.7’’ CP-2
substrates, while using self-alignment to align the channel passivation layer to the gate.
This fabrication process is essentially the same as the process described in section 6.3 to
fabricate back-channel passivated TFTs except for the way in which we pattern the
channel passivation. In this section we will first focus on how the SA-1 step was
implemented, and then show how it is integrated into the overall process flow.
135
For SA-1 self-alignment we carry out the following steps after depositing the TFT
stack for back-channel passivated TFTs (see Table 7.3 for the layer deposition
conditions). We mount the substrate as described in section 5.3.3 and coat the top SiNx
layer with hexamethyldisilazane (HMDS) and AZ5214 photoresist as usual and prebake
it for 30 seconds (soft-bake). We first spin a layer of photoresist onto the top SiNx layer,
then we flip the substrate around so that the back of the substrate is exposed to the UV
light in the mask aligner. In this situation the gate metal acts as a mask to block UV light.
The exposure time used in our experiment was 15 minutes, using a light intensity of
3.5 mW/cm2 and a wavelength of 405 nm. The SA-1 back-exposure step is shown in
Figure 7.5 (a).
Following back-exposure, we develop the photoresist for 50 seconds using AZ300
developer, removing all areas of the photoresist that were exposed to UV-radiation. This
results in photoresist patches over all surface areas that have underlying metal areas.
Next, the SiNx layer needs to be over-etched to create a gap between the edge of the gate
and the edge of channel passivation as shown in Figure 3.3. This ensures that the S/D
layers will make contact with the portion of the channel layer that is controlled by the
gate. We over-etch the SiNx in buffered oxide etch (BOE = HF:NH4F:H2O) for 90
seconds. The over-etch ensures that the edge of the SiNx passivation layer lies to the
inside of the gate edge as shown in Figure 7.5(b). The extent of channel passivation-gate
electrode overlap can be adjusted by a combination of (i) overexposure of the photoresist,
(ii) overdevelopment of the photoresist and (iii) over-etch of the back-channel SiNx
protection layer.
136
Photoresist
SiNx over-etch
(a)
(b)
Fig. 7.5 Schematic illustrating how we self-align the channel passivation to the gate
electrode: (a) back-exposure of the photoresist on top of the channel passivation layer and
(b) the critical overlap that is achieved by over-etching the channel passivation layer after
the back-exposure
Among these techniques past experience has shown that overexposure of the photoresist
[1] and over-etching provide the best control of the degree of overlap on a large surface
area. Over-development of the photoresist can lead to ragged edges for the channel
passivation. With the back-exposure conditions chosen in this experiment the over-etch
was on the order of ~ 1-2 µm on either side of the gate-edge. The photoresist is stripped
as described in section 5.3.4.
137
Integrating SA-1 into the TFT fabrication process flow of section 6.3 (see Figure 7.6
for the schematic of the process flow):
This is a 4-mask process. The TFT stack deposition conditions are summarized in
Appendix A.1-A.4. The detailed deposition and etch-steps are presented in Appendix C.3.
We first deposit the barrier layers onto both sides of a CP-3 substrate (step 1) using the
barrier layer recipe that was optimized for CP-3 as discussed in 5.4, then we deposit a trilayer of 15/70/15 nm Cr/Al/Cr using thermal evaporation (step 2), pattern the gates with
mask 1 and wet-etch the gate metal (step 3). Next, we deposit the TFT stack (step 4). The
stack layers are the same as those in table 6.2 with one exception: the thickness of the aSi:H layer is reduced to 25 nm to allow us to expose the photoresist on the front through
the back. The device layer deposition conditions are listed in Table 7.2. We now carry out
the SA-1 step (step 5) and over-etch the SiNx channel passivation layer as discussed
above (step 6).
After self-aligning the gate and the channel passivation, we clean the surface
using a piranha etch (H2O2:H2SO4) and followed by a short dip in BOE diluted 1:100 (?,
mentioned before) with DI to ensure clean interfaces between the exposed a-Si:H channel
layer and the subsequently deposited S/D layer. Next, 30-nm n+ a-Si:H (or n+ nc-Si) and a
tri-layer of 20/60/20-nm Cr/Al/Cr film are deposited (steps 7 and 8) and patterned for S/D
contacts (step 9) using mask 2 and wet-etching. This is followed by RIE etching of the n+
layer (step 10), and RIE etching the a-Si:H to isolate individual devices (step 11) using
mask 3. Finally, holes are opened using RIE to contact the bottom gate (step 12) using
mask 4.
138
Step 1
Step 5
Steps 2-3
Step 6
SiNx over-etch
Step 4
Step 7-8
139
Steps 9-12
a-Si:H
Cr/Al/Cr
n+ a-Si
SiNx
Clear plastic
Fig. 7.6 Process flow for back-channel passivated a-Si:H TFTs using self-alignment
between the gate and the channel passivation. See section for process description.
140
Table 7.2 Back-channel passivated a-Si:H TFT stack deposition conditions for CP-3
Layer
Deposition
power (W)
Thickness (nm)
Deposition
temperature (oC)
Substrate
SiNx
Gate insulator
48
360
300
CP-3
a-Si:H
4
25
250
CP-3
SiNx
Gate insulator
5
100
200
CP-3
Table 7.3
Performance of back-channel passivated a-Si:H TFTs fabricated at 300oC
by self-aligning the channel passivation to the gate electrode. W/L = 80 µm /40 µm
Linear mobility µLIN
1.09 cm2/VS
Saturation mobility µSAT
1.05 cm2/VS
Threshold voltage VTH
4.1 V
Subthreshold slope
510 mV/decade
ION/IOFF
> 107
141
Completed TFTs are evaluated by measuring their transfer characteristics and
extracting the performance parameters as described in Appendix B.1. Typical transfer
characteristics for back-channel passivated a-Si:H TFTs made using SA-1 self-alignment
are shown in Figure 7.7. The TFT performance parameters were extracted from this
figure and are listed in Table 7.3. On clear plastic the linear mobility is 1.09cm2/Vs, the
saturation mobility 1.05 cm2/Vs, the threshold voltage 4.1 V, the on/off current ratio >
1x107, and the subthreshold slope 510 mV/decade. Clearly the self-aligned process
results in high-quality TFTs with high mobilities.
-
10-8
-
10-11
-
10-14 |
-10
4
- 10
-5
o
300 C self-aligned process
W/L = 80µm/40µm
VDS = 10V
VDS = 0.1V
Gate current IGS (A)
Drain current IDS (A)
10-5
- 10
-8
- 10
-11
|
|
0
10
-
-14
| 10
20
Gate voltage VGS (V)
Figure 7.7 Transfer characteristics of back-channel passivated a-Si:H TFTs
fabricated on plastic at 300oC. The channel passivation is self-aligned to the gate.
4
142
To consider the impact of self-aligning the channel passivation to the gate we
investigated the misalignment of a-Si:H TFTs over the substrate surface area. Figure
7.8(a) shows a TFT fabricated at 300oC using the standard process described in section
6.3 (without self-alignment). Figure 7.8(b) shows a TFT fabricated with self-alignment
between the channel passivation and the gate electrode. The substrate that was used is
CP-2 and we used a 20-W gate dielectric deposition power. The TFTs of Figure 7.8(a)
and (b) are in the same position on the substrate, at a distance of 2.4 cm from the center.
The same mask set was used for both fabrication runs (therefore the W/L ratio is
different). Due to the misalignment between the gate and the channel passivation the TFT
shown in Figure 7.8(a) is not functional while the TFT in Figure 7.8 (b) will still turn on.
Therefore using self-alignment to align the channel passivation to the gate we have
obtained more functional devices than if we had used standard photolithography to
pattern all layers.
It is important to note that for a process using SA-1 self-alignment we still need to
design very large overlaps between the S/D and the gate electrodes to ensure functional
devices at the edge of the substrate. Figure 7.9 shows a close-up optical micrograph of
the channel region for a TFT at the center of the substrate, where self-alignment is used
to align the channel passivation to the gate. We can clearly see the edges of the selfaligned channel passivation and the gate, and the ~ 1-µm gap created by over-etching the
SiNx layer. The large S/D overlap with the gate is clearly visible in Figure 7.9. The
parasitic capacitance caused by this overlap is detrimental for fabricating high-speed
circuits as discussed in section 3.4. It also means we require a much larger area on the CP
143
surface for each individual TFT as well as for TFT circuits. Therefore it becomes
imperative to develop a method of aligning the S/D electrodes to the gate as well.
Edge of gate
Edge of channel passivation starts to
move off the gate
Source
Drain
Drain
Source
Gate
Gate
200µm
200µm
(a)
(b)
Fig. 7.8 Optical micrograph showing a back-channel passivated TFT (a) patterned using
standard photolithography (b) patterned using self-alignment. Both TFTs are at a distance
of 2.4 cm away from the center of the substrate along the diagonal
144
Channel passivation
Gap between channel
passivation and gate
electrode
10µm
Gate
Figure 7.9 Optical micrograph of a TFT where the channel passivation layer is selfaligned to the gate. The channel passivation is over-etched by ~ 1 µm to create the
overlap.
S/D electrode and n+ layer
S/D overlap with gate
Gate electrode
Figure 7.10 Schematic of a back-channel cut TFT showing the source-drain to gate
overlap
145
7.3.2 Aligning the source-drain layer to the gate (SA-2)
This section discusses the experiments we carried out in order to self-align the
source-drain terminals to the gate of a back-channel cut TFT, with a 300oC process
temperature on ~ 2.8’’x 2.8’’ CP-2 substrates. Figure 7.10 shows a schematic of the final
device overlap that we are self-aligning. We will first discuss how to implement the selfalignment between the S/D electrodes, and then explain how it is integrated into the
overall process flow.
The problem with only using the gate in our TFT process as a mask for self-alignment
is that this will only give us self-alignment in regions where we have TFT gates deposited
on top of the front barrier layer and nowhere else. If we want to start building circuits
from individual TFTs we require a mask that can give us alignment over a larger area of
the surface, not only in the TFT region. When we started developing the process to align
the source-drain terminals to the gate, we therefore started considering other layers as
possible masks for UV radiation. We decided to investigate depositing an a-Si:H layer
on the back of our substrate and patterning it prior to the TFT stack deposition in order to
create a mask for UV-radiation. Therefore, even though the substrate changes its
dimensions after the subsequent TFT stack deposition, the mask in the back will
expand/shrink together with the substrate and the alignment is unaffected by the change
in substrate dimensions. In this case both the gate and the a-Si:H layer in the back act as
masks for the UV radiation.
146
Area of photoresist
Area of photoresist
that is exposed
that is exposed
Photoresist
Gate
TFT stack
CP substrate
Front of
substrate
Back of
substrate
Back a-Si:H layer
UV radiation
radiationradiation
Fig. 7.11. Schematic illustrating a self-alignment process where the gate and an a-Si
layer patterned on the back of the substrate act as masks for self alignment. Here the
substrate includes the clear plastic foil plus the two SiNx passivation layers, front and
back.
147
Figure 7.11 shows a diagram illustrating this concept: after the back-channel cut TFT
stack deposition we spin a layer of photoresist onto the top n+ a-Si (or n+ nc-Si) layer and
then expose the photoresist through the back. The part of the photoresist shadowed by the
gate or the a-Si:H layer (on the back) will not be exposed. Since we planned to use a liftoff process to pattern the second (interconnect) metal layer, we want to remove photo
resist in areas where the metal should remain behind – therefore the pattern on the back is
a negative image of what the top metal pattern should look like. It is also important that
the S/D terminals overlap the gate for the TFT to be functional. For our inverted pattern
this means that the edge of the photoresist pattern on the gate needs to be within the outer
perimeter of the gate or the back a-Si:H mask, as shown in Figure 7.12. The figure shows
the outline of the gate (lightly dotted line), and the outline of the back a-Si:H mask (dark
dashed line). The yellow region shows all parts of the surface in this figure that are
covered with photoresist after the self-alignment step. The blue region in the figure shows
the areas where the photoresist has to be removed beyond the edge of the gate or the back
a-Si:H pattern to create the desired S/D overlap. A photograph showing a CP-2 substrate
after patterning the back a-Si:H layer is shown in Figure 7.13.
We investigated two methods to create the S/D overlap. Method 1 achieves the
overlap between the S/D terminals and the gate by over-developing the photoresist during
development, while method 2 creates the overlap by over-exposing the photoresist at the
edge combined with a special way of positioning the substrate in the mask aligner. Each
method starts at the point in the fabrication process following TFT stack deposition;
therefore the top layer is n+ a-Si:H or n+ nc-Si. We will now discuss the details for these
148
The photoresist
remains here after
back-exposure/
overdevelopment etc.
Edge of the patterned
a-Si:H on the back of
the substrate
Edge of gate contact
Gate contact (covered
by the TFT stack)
The photoresist in this
region is not protected
by the gate/a-Si:H
layer. It is removed
following backexposure
The photoresist in this
region needs to be
removed by overexposure or overdevelopment of the
photoresist
Fig. 7.12. Schematic showing a top view of a back-channel cut TFT following the SA-2
step
2.8’’
Figure 7.13 This photograph of a CP-2 substrate prepared for SA-2 self-alignment shows
the patterned a-Si:H layer at the back of the substrate.
149
two methods, and then indicate how they are integrated into the process flow for making
back-channel cut TFTs that is described in section 6.2. The substrate is mounted on a
carrier glass slide as described in section 5.3.3.
Method 1:
After mounting the substrate as described in section 5.3.3 we coat the top layer
with hexamethyldisilazane (HMDS) and AZ5214 photoresist and prebake it for 30
seconds on a hotplate at 110oC . The substrate is then loaded into the mask aligner so that
the top surface is facing downwards. It is exposed for 30 minutes at a power density of
3.5 mW/cm2 and a wavelength of 405 nm. Now the substrate is overdeveloped in a
mixture of AZ300:AZ400 (6:1). The development time depends on the size of the overlap
that we want to achieve. We usually check the overlap of the photoresist over the gate in
an optical microscope every 30s and stop developing once the desired overlap has been
reached. Figure 7.14(a) shows an optical micrograph of a TFT after the self-alignment
step. The openings created in the photoresist make up the source-drain metal area, and the
overlap onto the gate region is ~ 3 µm. Figure 7.14(b) shows a zoomed image of the TFT.
The W/L ratio for this TFT is 80 µm /40 µm.
This method is not yet optimized and a lot of challenges remain in developing the
correct overlap. The photoresist thickness, pre-bake time, exposure time and amount of
development all have an impact on the success of the process, and need to be fine-tuned
to get good results. Very often, these parameters seem to change from run to run (perhaps
with the optical clarity of the experimental clear plastic available to use) or the different
SiNx barrier layers that we experimented with. Therefore, the self-alignment step could
150
often result in insufficient S/D overlap, bridges between the S/D terminals of the TFT
when two adjacent photoresist openings start merging and ragged edges. Figure 7.15(a)
shows a TFT with a W/L of 150 µm/5 µm and Figure 7.15(b) shows a zoomed view of
the gate region, showing bridges between the S/D terminals. This effect is most
noticeable in short channel devices (and puts a limit on how small the L values can
become using this method) but it has also been seen regularly in larger TFTs with a W/L
of 80 µm / 40 µm. Figure 7.16 shows an example of the ragged edges that are sometimes
observed when creating the overlap using method 1. If the photoresist is much
overdeveloped (i.e. if we have many bridges between the photoresist holes that will
define the S/D terminals), we can strip the photoresist and adjust the self-alignment
conditions (prebake time, exposure time and development time) accordingly. There are
several problems with stripping the photoresist several times. The more we handle the
substrate, the more scratches are caused on the surface due to handling. Additionally, if
there is any exposed gate metal (as is the case for prior patterning of the gate vias in aSi:H oscillator circuits) the gate metal can become damaged due to prolonged exposure to
the developer used in stripping the photoresist. From a processing point of view it is also
desirable to have a more rugged process that enables us to reliably achieve the S/D
overlap. Therefore we investigated an alternative way of creating the overlap (method 2)
which did not involve overdevelopment of the photoresist.
151
Photoresist remaining after
the SA-2 step
Opening in photoresist
Gate
20µm
200µm
(a)
Fig 7.14
Source-drain overlap
(b)
A TFT after the SA-2 step, creating the overlap with method 1. The W/L of
this TFT is 80 µm / 40 µm. The substrate was CP-3.
Bridges in the
photoresist
25µm
100µm
(a)
Fig 7.15
(b)
A TFT after the source-drain self-alignment step (step 9). The overlap is
created using method 1. The W/L of this TFT is 150 µm / 5 µm. The substrate was CP-3.
152
20µm
Fig 7.16
Optical micrograph showing a close up view of the channel region of one TFT
after SA-3 self-alignment, using method 1 to pattern the overlap between the S/D
terminals and the gate. The substrate was CP-3.
Method 2:
This method relies on a special loading technique to expose small sections of the
photoresist beyond the boundary of the masking layers (gate metal and/or the patterned aSi:H layers at the back).
In this method we mount the substrate on a glass slide as described in section
5.3.3. We then coat the top layer with hexamethyldisilazane (HMDS) and AZ5214
photoresist and prebake it for 90 seconds on a hotplate at 110oC. The substrate is loaded
facing downwards into the mask aligner at a 8o angle (using 10 microscope slides with a
thickness of 1.1mm underneath one edge of the glass backing slide which the substrate is
mounted on). The loading set-up is illustrated in Figure 7.17. The substrate is exposed for
153
UV radiation
Plastic substrate
mounted on a
glass slide
1.1 cm
Stack of
microscope slides
Glass slide
Front of substrate faces down
8o
Bottom of mask aligner tray
Figure 7.17 Schematic indicating the loading sequence in method 2.
12 minutes at a power density of 3.5 mW/cm2 and a wavelength of 405 nm. Then the
substrate is rotated by 90o (still facing downwards) and is again exposed for 12 minutes.
The substrate is exposed and rotated 4 times in total, giving a total exposure time of 48
min. Finally the substrate is developed in AZ300 for 40 to 60 seconds. The photoresist
can start thinning rapidly after 30 s so it is importantly to be very careful not to overetch
the photoresist at this point. Generally, we developed the photoresist for 30 s, and then
looked at the photoresist pattern using a microscope. If the overlap was not sufficient, we
developed in steps of 5 seconds, investigating the photoresist pattern in the microscope
after every step. The development was stopped as soon as we achieved the correct
overlap.
154
For the conditions stated above we routinely achieved a S/D overlap of 0.9-1µm
with the gate. This process was very reliable and the photoresist seldom had to be
stripped to correct for overdevelopment. All a-Si:H TFT circuits in the remainder of this
thesis (that employ SA-2 self-alignment) were fabricated using method 2 for the SA-2
step. We were able to reduce the TFT channel length down to 3 µm using this process, as
discussed in section 7.4.
Integrating the SA-2 step (using method 1 or method 2) with the back-channel cut
TFT fabrication process described in Section 6.2 (see Figure 7.18 for the schematic
of the process flow):
This is a 4-mask process. The detailed steps of the PE-CVD deposition conditions
are provided in Appendix A.1 (300oC process) and A.3 (250oC process), and the
fabrication and etch-steps are listed in Appendix C.4. We first prepare a CP-3 substrate as
described in section 5.3.3 and deposit the barrier layers for CP-3 described in section 5.4.
After depositing the back-barrier layer we don’t move the substrate to the load lock for
unloading. Instead, we transfer the substrate to the I-chamber and deposit a 200-nm thick
layer of a-Si:H layer using the PE-CVD deposition conditions stated in Appendix A.1A.3. We then transfer the substrate back to the N-chamber and deposit 50 nm of SiNx at
200oC, using a deposition power of 5 W (this will be referred to as the capping layer
(second back barrier layer in Fig. 7.18) in the following discussion) (step 1). The last
SiNx layer is necessary since the a-Si:H has a tendency to flake off or be attacked by
process chemicals throughout the process. Finally a thermally evaporated tri-layer of 20
155
nm Cr, 60 nm Aℓ, and 20 nm Cr is deposited as gate metal on the front of the substrate
(step 2). Moving to the cleanroom, we first pattern (mask 1) the front tri-layer to define
the gates (step 3). Then we flip the substrate over and pattern the SiNx capping back
barrier layer and the a-Si:H layer (mask 2) to define areas where we want interconnect
metal (step 4).
After patterning the front tri-layer of 15nm/70nm/15nm Cr/Al/Cr, the capping
layer and back a-Si:H layer, the sample surface is cleaned thoroughly and is again loaded
into the PE-CVD system for TFT stack deposition (step 5). The stack consists of a ~ 300
-nm thick SiNx gate dielectric, 25-nm a-Si:H and a 30-nm thick n+ nc/a-Si layer. The
stack deposition conditions are summarized in Table 7.4. Now the sample is removed
from the PE-CVD system and the S/D interconnects are self-aligned to the gates using
SA-2 and method 1 or method 2, described above (step 6). After the self-alignment step,
the substrate surface is dipped in buffered oxide etch (HF:NH4F:H2O):DI mixed 1:100 for
2 to 4 seconds and loaded directly into the thermal evaporator. A 65-nm thick Cr film is
thermally evaporated (step 8) and we pattern the source/drain contacts as follows: first
the sample is placed in a sonicator bath with isopropanol (IPA) for about 20 minutes for
lift-off of the photoresist layer. This should be enough to remove all of the metal regions
that were covered with photoresist after the SA-2 step. Any remnants of photoresist are
then removed by soaking the substrate in AZ400 for about 10 seconds while
156
Table 7.4 Back-channel cut a-Si:H TFT stack deposition conditions for SA on CP-3
substrates
Layer
Deposition power (W)
Thickness (nm)
Deposition temperature (oC)
SiNx
gate insulator
48
360
250/300
a-Si:H
4
25
250
n+ a-Si:H
5
30
230
rubbing the surface gently with two q-tips. The photoresist will be etched away by the
AZ400 leaving the S/D metal self-aligned to the gate. Next we expose the substrate to an
oxygen descum (the conditions in our Plasmatherm 790 are set at O2 flow rate = 40 sccm,
pressure = 115 mT, RF power = 80 W and time = 600 s). Finally the process is completed
by RIE etching the n+ nc a-Si (step 9) and the a-Si:H (step 10) to isolate individual
devices (mask 3). Then we etch via holes in the SiNx gate dielectric over the gate contact
pad (mask 4) (step 11). This completes the TFTs on top of the substrate. The back a-Si:H
mask and capping layer can now be etched away (step 12), although this step is not
necessary for the circuits to function.
157
Step 1
Step 5
Step 1 (continued)
Step 6
Second back
barrier layer
Steps 2-4
a-Si:H
Photoresist
First back
barrier layer
Step 7
Critical
overlap
158
Step 8
Steps 9-12
a-Si:H
Cr
n+ a-Si
SiNx
Clear plastic
Figure 7.18 Process flow for back-channel cut a-Si:H TFTs using SA-2 self-alignment
between the gate and the S/D terminals. See section 7.3.2 for the process description.
.
7.3.3 Simplified process to align the source-drain layer to the gate (SA-3)
(see Figure 7.20 for the schematic of the process flow):
We simplified the SA-2 process described in 7.3.2 to decrease processing time and to
focus on optimizing the source-drain to gate overlap. The fabrication and etch-steps are
listed in Appendix C.5. In the simplified process the extra a-Si:H/SiNx layers at the back
of the substrate were omitted and we only deposited a simple barrier layer at the front and
back of the substrate (step 1), as for the standard non-self-aligned process. We then
deposited and patterned the gate metal (steps 2 and 3) and deposited the usual TFT stack
layers (SiNx, a-Si:H and n+ a-Si) according to the layers in Table 7.4 (step 4). After the
TFT stack deposition we self-align the gate with the S/D terminals as follows: first we
mount the substrate on a glass slide as described in section 5.3.3, coat the top layer with
159
hexamethyldisilazane (HMDS) and AZ5214 photoresist and prebake it for 90 seconds on
a hotplate at 110oC. We pattern the photoresist using standard photolithography, using the
a-Si:H island mask (mask 2). This removes all of the photoresist on the substrate surface,
except for square patches directly over the gate where we want to define the channel
region. Next we use method 2 described in section 7.3.2 to create the S/D overlap with
the gate (step 5). The result is a strip of photoresist on top of the gate region as is shown
in Figure 7.19 (a), which is an optical micrograph of a TFT designed to have W/L = 80
µm / 40 µm after the self-alignment step. Figure 7.19 (b) shows a zoomed view of the
gate region.
After the alignment step, the substrate surface is dipped in buffered oxide etch
(HF:NH4F:H2O):DI mixed 1:100 for 2 to 4 seconds and loaded directly into the thermal
evaporator. A 65-nm thick Cr film is deposited (step 6) and then we remove the
photoresist in the channel region by sonicating the substrate in isopropanol (IPA) for
20minutes as described in section 7.3.2. Any remnants of photoresist are also removed by
soaking the substrate in AZ400 for about 10 seconds while rubbing the surface gently
with two q-tips, followed by an oxygen descum (the conditions in our Plasmatherm 790
are set at O2 flow rate = 40 sccm, pressure = 115 mTorr, RF power = 80 W and time =
600 s). We now need to use standard photolithography and mask 3 to pattern the outline
of the S/D electrodes (step 7). Mask 3 has an outline of the S/D metal and interconnects,
but the gap for the channel region for the S/D is omitted in the lay-out of the mask, as
shown in Figure 7.21.
160
Photoresist Via opening
Photoresist
100µm
Gate
(a)
Fig 7.19
10µm
(b)
A TFT after the source-drain self-alignment step (step 9), using the simplified
process (a) whole TFT (b) close-up of channel region, showing the 1-µm gap between the
edge of the gate and the photoresist created using method 2. The W/L of this TFT is
80 µm / 40 µm
Since the position of the channel region is determined using self-alignment with the gate
(and not by mask 3) the TFT channel is self-aligned and will not be affected by the
change in substrate dimensions, even though we are patterning most of the S/D metal
using a mask, and standard photolithography. Finally the process is completed by RIE
etching the n+ nc a-Si (step 8) and the a-Si:H (step 9) to isolate individual devices (mask
2). Then we etch via holes in the SiNx gate dielectric over the gate contact pad (mask 4)
(step 10). This completes the TFTs on top of the substrate.
161
Step 1
Step 6
Critical overlap
Steps 2-3
Step 7
Step 4
Step 8-10
Cr/Al
a-Si:H
n+ a-Si
SiNx
Clear plastic
Figure 7.20 Process flow for back-channel cut a-Si:H TFTs using SA-3 selfalignment
between the gate and the S/D terminals. See section 7.3.3 for a description of the process.
162
Gate, patterned
with mask 1
Area of S/D metal that
will be removed by liftoff
Photo-resist pattern
created using SA-3,
method 2.
Pattern created in S/D
metal by mask 3 using
standard photolithography
Fig 7.21
Schematic illustrating the simplified process for self-aligning the source-drain
contacts to the gate.
Source/drain-gate overlap
Gate
500µm
(a)
20µm
(b)
Fig 7.22 Optical micrograph of (a) an array of TFTs where the S/D terminals were selfaligned and (b) a close up view of the channel region of one TFT. The S/D overlap was ~
1µm. W/L = 80 µm / 40 µm
163
The gap between the Cr S/D terminals is opened up by lift-off after SA_3 self-alignment.
The S/D metal is defined using standard photolithography and mask 3. For our initial
experiments the SiNx gate dielectric layer was deposited at 250oC to avoid the possibly
adverse effects caused by the increase in substrate CTE as the temperature reaches 300oC.
The PE-CVD deposition conditions and set-points for 250oC used in our PE-CVD
deposition system are outlined in Appendix A.3. Figure 7.22(a) shows a completed array
of TFTs fabricated using a SiNx deposition temperature of 250oC and SA-3 (with method
2) and Figure 7.22(b) shows a zoomed view of the TFT channel region. Figure 7.23
shows transfer characteristics for completed TFTs fabricated on CP-3 with a SiNx
deposition temperature of 250oC. The TFT properties that were extracted from these
transfer characteristics are listed in Table 7.5.
Drain-source current IDS (A)
10-5
250oC self-aligned process
W/L = 80 µm / 40 µm
-
10-5
-
10-8
VDS = 10 V
10-8
-
10-11
-
-
10-11
10-14
-
-
10-14
VDS = 0.1 V
-10
0
20
Gate voltage VGS (V)
Fig 7.23
10
Gate-source current IGS (A)
164
-
Transfer characteristics of a-Si:H TFTs fabricated at 250oC on CP-3 using a
back-channel cut geometry and SA-3 method 2 self-alignment.
Table 7.5
250oC a-Si:H TFT performance parameters, source-drain
terminals self-aligned. W/L = 80 µm / 40 µm
Linear mobility µLIN
1.1 cm2/Vs
Saturation mobility µSAT
0.92 cm2/Vs
Threshold voltage VTH
Subthreshold slope
ION/IOFF
2.25 V
500 mV/decade
> 107
165
We were able to create a very straight overlap between the S/D terminals and the gate
using SA-3 method 2 for the self-alignment step. This method enabled us to reduce the
channel length L from 40 µm down to 5 µm. The TFT shown in Figure 7.24 is a backchannel cut a-Si:H TFT with L = 5 µm and a S/D overlap of ~ 1 µm with the gate.
Unfortunately the TFT performance of these devices was not very good, as can be seen
from the high measured OFF-current in the transfer characteristic shown in Figure 7.25.
The extremely high off-currents are thought to be a result of damage to the thin 25-nm aSi:H layer in the channel region caused by RIE etching. However, there is some
uncertainty as to the exact cause, and this remains a subject of future investigation.
Subsequent annealing steps did not reduce the OFF-current, and we decided to
investigate fabricating a back-channel passivated structure combining SA-1 selfalignment with SA-3 self-alignment to see if we could achieve better TFT performance.
5µm
Fig 7.24 Optical micrograph of the channel region of a back-channel cut TFT fabricated
using SA-3 method 2 at 300oC on CP-3. L = 5 µm
10-4
-
10-6
-
10-8
-
10-10
-
10-12
-
10-14
-10
VDS = 10 V
VDS = 0.1 V
300oC self-aligned process
W/L = 360 µm / 5 µm
0
10
-
10-4
-
10-6
-
10-8
-
10-10
-
10-12
-
10-14
Gate-source current IGS (A)
Drain-source current IDS (A)
166
20
Gate Voltage VGS (V)
Fig 7.25
Transfer characteristic of a-Si:H TFTs fabricated at 300oC using a back-
channel cut geometry and SA-3 method 2 self-alignment on CP-3.
7.4 Combining SA-1 and SA-3 selfalignment
We combined SA-1 and SA-3 self-alignment methods to create back-channel
passivated a-Si:H TFTs using a SiNx dielectric deposition temperature of 300oC. See
Figure 7.26 for a schematic of the process flow. Refer to Appendix C.6 for the details of
the fabrication steps. The SA-1 and SA-3 steps were integrated into the back-channel
passivated process flow described in section 6.3 as follows:
The first steps of this process follow steps 1-7 of the process described in section
7.3.1 (Figure 7.18) for SA-1 (self-aligning the channel passivation to the gate). These
167
Step 1-6
Step 9
Step 7
Step 10
Step 8
Step 11
Photoresist
168
Steps 12-13
a-Si:H
Cr
+
n a-Si
SiNx
Clear plastic
Figure 7.26 Process flow for back-channel passivated a-Si:H TFTs using SA-1 and SA-3
selfalignment between the gate, the channel passivation and the S/D terminals. See
process description in section 7.3.3.
steps involve coating the substrate with barrier layers on both sides (step 1), depositing
and patterning the gate metal (steps 2-3), depositing the TFT stack (step 4), self-aligning
the channel passivation (steps 5-6), and depositing the n+ a-Si:H layer (step 7). After n+ aSi:H deposition in the P-chamber we unload the sample and self-align the S/D channel
region to the gate using SA-3, method 2 (step 8). This is equivalent to step 5 of the
process described in 7.3.3. We now continue to follow steps 6-10 of the fabrication
process in section 7.3.3 to complete the TFTs. This involves depositing the S/D metal
(step 9), opening up the channel region using lift-off and patterning the S/D metal
interconnects with mask 3 (step 10), RIE etching the n+ layer (step 11) and the a-Si:H
169
islands (mask 2, step 12), and finally etching the gate via holes over the gate pads (mask
4, step 13).
We also investigated self-aligning the a-Si:H island to the gate (in addition to aligning
the channel passivation and the S/D electrodes to the gate). This is done by adapting step
10 - after patterning the S/D interconnects (but before stripping the photoresist) we
expose the surface of the substrate to a plasma that etches the exposed n+ a-Si:H followed
by a plasma that etched the exposed a-Si:H layers. Since the channel region is covered
with photoresist at this time we are effectively removing all of the a-Si:H that is not in the
channel region, or covered by S/D metal.
L =3µm
S/D layer
Gate layer
Fig 7.27 Optical micrograph of a back-channel passivated TFT fabricated using SA-3,
method 2 at 300oC on CP-3. The TFT is in the corner of the mask-set, ~ 5cm from the
center of the substrate. W/L = 360 µm / 3 µm. The channel passivation, S/D layer and a-
170
Since we etch the a-Si:H island we can omit mask 3 of the process in 7.3.3 (step 11). An
example of a TFT processed this way is shown in Figure 7.27. The TFT has a designed
W/L = 360 µm / 3 µm. The channel passivation, S/D layer and a-Si:H islands were selfaligned to the gate. The substrate was CP-3. The fabrication process was carried out using
a SiNx deposition temperature of 300oC. From the alignment mark, we measure ~ 50 µm
local misalignment between the TFT gate and S/D terminal for an alignment mark that is
~ 5 cm away from the center of the substrate. This corresponds to misalignment of ∆ ~
1000 ppm (see section 3.2). This picture illustrates the strength of this process: we are
able to pattern TFTs with much smaller gate L values and smaller overlaps than would
have been possible using standard photolithography. Figure 7.28 shows close-up views of
the TFT gate region for TFTs with an L of 5 µm and 3 µm, respectively. The TFTs are
both back-channel passivated,
Channel passivation
1µm overlap
S/D layer
S/D layer
5µm
3µm
Gate
Gate
(a)
Fig 7.28
(b)
Optical micrograph of the channel region of back-channel passivated TFT
fabricated using SA-3 method 2 at 300oC on CP-3 described in Chapter 5 (a) L = 5 µm
(b) L = 3 µm, with the a-Si:H island self-aligned to the gate
171
and were fabricated on CP-3 at 300oC using SA-1 and SA-3 method 2 self-alignment.
The measured transfer characteristics of a TFT with W/L = 360 µm / 5 µm is plotted in
Figure 7.29 and the performance parameters extracted from this figure are listed in Table
7.6. The TFT clearly works and has acceptable mobility values (for a short-channel
length TFT). However, there is still a problem with the off-current for the transfer
characteristic measured at VDS = 10 V. This problem needs to be resolved before we can
integrate these short-channel length TFTs into functional oscillators (such as the ones we
discuss in Chapter 8), but once this issue has been resolved we should be able to make
highly stable high-speed circuits from such TFTs with a S/D overlap of 1 µm and TFT L
values as small as 3 µm.
At this point we have reduced the process for making back-channel passivated
TFTs on CP-3 at 300oC to a process that requires 3 masks (to pattern the gate, the S/D
areas, and the gate via holes) and two self-alignment steps. In total, we have used selfalignment to align 3 layers (the channel passivation, the S/D layers and the a-Si:H island
to the gate).
172
Table 7.6
Performance parameters of back-channel passivated a-Si:H TFT
on CP-3 using SA-1 and SA-3 (method 2) at 300oC, W/L = 360 µm / 5 µm
Linear mobility µLIN
0.36
Saturation mobility µSAT
0.40
Threshold voltage VTH
~2
380 (from the VDS = 0.1 V curve)
10-4
-
o
Drain-source current IDS (A)
300 C self-aligned process
W/L = 360 µm / 5 µm
-6
10
-
10-4
-
10-6
VDS = 10 V
VDS = 0.1 V
10-8
-
-
10-8
10-10
-
-
10-10
10-12
-
-
10-12
10-14
-
-
10-14
-10
0
10
20
Gate voltage VGS (V)
Fig 7.29
Transfer characteristics of a-Si:H TFTs fabricated at 300oC using a back-
channel passivated geometry, SA-3 method 2 self-alignment on CP-3, as described in
section 7.3.3
Gate-source current IGS (A)
Subthreshold slope
173
7.5 Outlook
We have demonstrated self-alignment to align the channel passivation, the S/D
electrodes and the a-Si:H layer to the gate, and reliably achieve a 1-µm S/D overlap with
the gate. The limitation on the minimum L value we can achieve for this process is the
thickness of the metal stripe patterned using mask 1, and so we could conceivably go to
much smaller gate L values. However, the TFTs do not have an ideal performance. The
off-current measured for the transfer characteristic is too high (especially for TFTs with
small L values), and the subthreshold slope are also often rather shallow (for TFTs made
with this process, see Figure 7.25 and 7.29). This problem requires urgent attention.
We speculate that one cause for the high leakage current is plasma damage to the
ultra-thin a-Si:H channel region during RIE etching. However, the reason for the leakage
current could be as simple as photoresist residue remaining in the channel due to
inadequate cleaning after the lift-off step, over-etching of the device layers at some point
or incorrect TFT annealing after completing the fabrication process. Future work in this
area would involve carefully tracing the cause of this problem. Alternatively we could
also investigate using a thicker a-Si:H layer with self-alignment steps. Thicker a-Si:H
layers would of course drastically increase the back-exposure time required for the selfalignment steps, which should still be possible.
It would also be valuable at this point to start integrating the SA-2 selfalignment
method with SA-1, to enable alignment of the S/D metal layer at any point on the
substrate surface, instead of only having alignment dictated by places where there is gate
metal. This would free us up to create more complex structures, and introduce more
versatility to the overall self-alignment process.
174
It should be stressed that we have been able to achieve functional TFTs with very
small L values over the entire 2.8 x 2.8 square inch CP surface area, while using a 300oC
fabrication process. TFTs patterned using conventional photolithography have a
misalignment of 50 to 60 µm between the S/D terminals and the gate device layers at the
edge of a 3’’x 3’’substrate. Therefore we would never have been able to align all TFTs
over the CP surface area for a standard 300oC process. Our self-alignment steps therefore
open up a whole new area of research into high-speed, high performance TFTs on plastic.
Even if we stick to using the TFTs with large L values (for example the TFTs with W/L =
80 µm / 40 µm), we can still achieve a significant improvement in TFT performance over
the surface area since we will now for the first time have functional TFTs covering the
entire surface.
Fig 7.30
Optical micrograph showing a ~ 3 x 2 sq.mm area at the corner of a CP-3
substrate after fabricating TFTs and oscillator circuits using SA-1 and SA-3
selfalignment, combined with method 2 to fabricate back-channel passivated TFTs
175
Figure 7.30 shows the kind of alignment that we are now capable of achieving over
large surface area. This figure shows an array of TFTs with W/L = 80 µm / 40 µm (to the
left of the figure) and a ring oscillator circuit consisting of TFTs with W/L ratios of
36 µm /5 µm and 360 µm /5 µm (on the right of the figure). The TFTs in this image were
at a distance of approximately 5 cm from the center of the substrate. The individual TFTs
visible on this image are all functional (but have high OFF-currents as shown in Figures
7.25 and 7.29). This figure shows that we effectively eliminated TFT failure due to
misalignment. Once the OFF-current issues with our S/D selfalignment step have been
resolved, the next problem to tackle will be how to deal with the scratches and particles
that are inherent to the substrate surface. As you can see from Figure 7.30, the surface is
scratched and incorporates particles. If metal is deposited an patterned on such a surface
and patterned to form interconnect lines, these defects can cause broken interconnect
lines and which means that devices can no longer be addressed. In a display backplane
this situation means that the affected display pixel will no longer be operational.
REFERENCES
[1]I-C. Cheng, A. Z. Kattamis, K. Long, J. C. Sturm and S. Wagner, ”Self-aligned
amorphous-silicon TFTs on clear plastic substrates”, IEEE Electron Dev. Lett, vol.
27, no. 3, pp. 166-168, 2006
176
Chapter 8
A-Si:H TFT RING OSCILLATORS
8.1 Introduction
We designed ring oscillators to test our TFT fabrication processes in a circuit.
Specifically, we were looking for improvements that might have resulted from using selfaligned fabrication methods (in this case an improvement would be higher oscillating
frequencies for the same power dissipation). One culprit decreasing the oscillation
frequency is the capacitance caused by the source-drain overlap (refer to chapter 3). If we
can reduce this capacitance by self-aligning the source-drain terminals to the gate we can
make faster oscillators. The following section discusses our efforts in this area.
8.2 Ring oscillator designs
As discussed in Chapter 3, the geometry design parameter, β, needs to be
optimized while trading off faster oscillation and high output voltage swings.
We
designed the ring oscillators according to the mask design shown in Figure 8.1 (see
Appendix D.4 for the detailed mask lay-out) and fabricated 3 different mask sets:
Design #1: the mask-set was designed for non self-aligned TFTs (see sections 6.2 and
6.3). The driver TFTs in design had a W/L ratio of 360/20, the load TFTs had a W/L ratio
of 80/20, and all TFTs had a source-drain/gate overlap of 10µm
177
Design #2: this design was intended for fabricating back-channel passivated ring
oscillators using SA-1 to self-align the channel passivation to the gate. The back-channel
passivated TFTs were designed to have the same W/L ratios and source-drain/gate
overlap as Design #1.
Design #3: the S/D overlap in designs #1 and #2 (10 µm) was too small to get a large
oscillator yield when implemented on plastic and therefore we increased the S/D/gate
overlap to 15 µm and decreased L to 10 µm (when used in a non-self aligned process).
This design was also specifically designed with an eye towards implementing selfVDD
Load TFT (pull-up)
VOUT
GND
One
 inverter stage

Driving TFT
Output buffer
(pull-down)
Figure 8.1 Mask layout of a completed 5 stage ring oscillator
178
alignment between the S/D contacts and the gate. We had problems achieving the sourcedrain/gate overlap reliably every time when we used SA-3 (method 1) self-alignment to
pattern TFTs with small channel lengths (due to bridges between the S/D electrodes),
therefore the channel length in this mask set was set at 40 µm.
We also had a rather small output oscillation amplitude for oscillators fabricated
using designs #1 and #2 (around 80 mV, see section 8.4) and therefore we increased the β
value from 4 to 10 in the hope that this would increase the output voltage. The driver TFT
in this design had a W/L ratio of 360/10 and the load TFT had a W/L ratio of 36/10 (for
TFTs fabricated using standard photolithography). If we implement SA-3 self-alignment
with this mask-set the TFT L value depends on the S/D overlap with the gate. The metal
stripe defining the gate was 40 µm. For a 1-µm S/D overlap with the gate electrode, this
gives L = (40-2) = 38 µm. The details of the ring oscillator designs and implemented
fabrication processes are summarized in Table 8.1. We modeled the fabricated ring
oscillators in our designs using HPISCE circuit simulation software. Individual a-Si:H
TFTs were modeled using the LEVEL 40 Hewlett-Packard amorphous silicon thin-film
transistor model to model our ring oscillator circuits.
8.3 Ring oscillator fabrication
This section gives the details of the oscillator fabrication. The fabrication
processes for the TFTs in the ring oscillator circuits closely follow the fabrication
processes outlined in Chapters 6 (sections 6.2 and 6.3) and 7 (sections 7.2 and 7.4). The
big difference for fabricating TFT circuits instead of individual TFTs is that we need to
179
connect the bottom gate layer and the top layer. This means we need to etch via holes
down to the gate metal before depositing the metal layer that is patterned to create the
interconnect layer. The simplest way of interconnecting the gate and S/D layers is to first
pattern the via holes, then deposit S/D layer. In this scenario the S/D metal layer is also
the interconnect metal layer. For this reason we replaced the top metal layer in all
oscillator processes with a tri-layer of 15 nm /250 nm /15 nm Cr/Al/Cr.
Table 8.1 Table summarizing the design parameters for the 3-ring oscillator designs
Design number
1
2
3
Fabrication process
implemented
Back
channel
cut, non
selfaligned
Back channel
passivated,
channel
passivation
self-aligned
Back channel
cut, non selfaligned
Back channel
cut, S/D
terminals selfaligned
Stages
5 and 7
5 and 7
5 and 7
5 and 7
W/L (load) (µm)
80/20
80/20
36/10
36/(40-2xS/D
overlap)
W/L (driver) (µm)
360/20
360/20
360/10
360/(40-2xS/D
overlap)
β
4
4
10
10
S/D overlap with gate
(µm)
10
10
15
1-5
180
This process adjustment works well for TFTs fabricated using the standard TFT
process (non self-alignment), and TFTs using SA-1 self-alignment. However, when
implementing self-alignment between the S/D terminals and the gate (SA-2, SA-3) after
we patterned the via holes we saw significant degradation of the gate metal in the contact
pads. This is because the SA-2 and SA-3 steps involve patterning the photoresist in
developer. Therefore the gate metal in the via hole is exposed to developer for much
(a)
(b)
Figure 8.2 Suggested process improvement to increase robustness of self-aligning S/D
contacts to the gate (a) top view and (b) side view: left-to-right is top-to-bottom in (a).
181
longer periods than desirable. For this reason we started looking at a new way to create
the interconnect between the gate and S/D layers such as the suggested structure shown in
Figure 8.2. In this process we pattern individual TFTs without connecting the gate and
S/D layer. After completing the individual TFTs we deposit a thin SiNx passivation layer
on top of the completed structures. Now we open up a via hole over the gate and the S/D
layer contact pads and deposit a third metal layer that is patterned into patches that
connect the desired contact pads. The S/D layer in this process is kept at 65 nm of Cr,
while the third metal layer is a thick tri-layer of 15 nm / 250 nm /15 nm of Cr/Al/Cr.
All functional ring oscillators, whose performance we will discuss in section
8.4, were fabricated with the ‘old’ method – in which the S/D metal forms the metal
interconnects. However, future mask sets will all be designed using the ‘new’ method of
interconnecting the gate and S/D metal layers, since the ‘old’ process is far from reliable.
8.3.1 Fabricating ring oscillators using non self-aligned back-channel cut TFTs
The fabrication process for the TFTs in this section closely follows the
fabrication process in section 6.2. These TFTs were fabricated at 250oC. The detailed
deposition and etch steps are presented in Appendix D-1. After barrier layer deposition
on CP-3 substrates, according to the method discussed in 5.4 (step 1), a tri-layer of
Cr/Al/Cr (15 nm /70 nm /15 nm) is deposited using thermal evaporation (step 2) and
patterned with mask 1 using photolithography (step 3). After wet-etching we deposit the
TFT stack consisting of 360 nm SiNx gate dielectric, 200-nm thick a-Si:H active layer and
182
a 30-nm n+ doped a-Si layer (step 4). The PE-CVD deposition conditions used for all the
device layers are summarized in Table 6.1. The TFT stack deposition conditions for our
PE-CVD system are summarized in Appendix A.3. SiNx deposition rates at 300oC are
summarized in Appendix A.5. After successful deposition of the TFT stack, we pattern
the gate via holes using mask #2 (step 5), then deposit a second metal tri-layer consisting
of 15/250/15 nm of Cr/Al/Cr using thermal evaporation (step 6). It was patterned using
mask 2 and wet-etched (step 7). It is important to note that the TFT channel dimensions
are defined by mask 3. After patterning the S/D electrodes, the n+ layer was etched using
reactive ion etching (RIE) (step 8), followed by patterning the a-Si:H with mask 3 (using
RIE) to define the islands (step 9). The completed TFTs are then annealed in the Ichamber of the PE-CVD (under vacuum) at 200oC for 1 hour.
8.3.2 Fabricating ring oscillators using SA-1 self-aligned back-channel passivated
TFTs
This process was carried out at 250oC. Refer to Appendix A.3 for the PE-CVD
deposition conditions. The detailed deposition and etch-steps are presented in Appendix
D.2. We first deposit the barrier layers onto both sides of a CP-3 substrate (step 1) using
the barrier layer recipe that was optimized for CP-3 as discussed in 5.4. Then we deposit
a tri-layer of 15/70/15 nm Cr/Al/Cr using thermal evaporation (step 2), pattern the gates
with mask 1 and wet-etch the gate metal (step 3). Next, we deposit the TFT stack (step 4).
The stack layers are the same as those in table 6.2 with one exception: the thickness of
the a-Si:H layer is reduced to 25 nm to allow us to expose the photoresist on the front
through the back. The device layer deposition conditions are listed in Table 7.2. We now
183
carry out the SA-1 step (step 5) and over-etch the SiNx channel passivation layer as
discussed above (step 6). After self-aligning the gate and the channel passivation, we
clean the surface using a piranha etch (H2O2:H2SO4) followed by a short dip in BOE
diluted 1:100 with DI-water to ensure clean interfaces between the exposed a-Si:H
channel layer and the subsequently deposited S/D layer. Next, 30-nm n+ a-Si:H (or n+ ncSi) is deposited (step 7). We then etch the gate via holes using mask 2 (step 8), dip the
substrate in a mixture of BOE:DI (1:100) and deposit a tri-layer of 15/250/15-nm
Cr/Al/Cr film (step 9). The S/D metal is then patterned using mask 3 (step 10). This is
followed by reactive ion etching
Channel passivation selfaligned to gate.
W/L = 80 µm /20 µm
80µm
Figure 8.3 Close up view of a section of a completed ring oscillator with the channel
passivation self-aligned to the gate (SA-1, oscillator design #2) on CP-3 fabricated at
250oC.
184
of the n+ layer (step 11), and RIE etching the a-Si:H to isolate individual devices (step
12) using mask 4. The completed TFTs are then annealed in the I-chamber of the PECVD (under vacuum) at 200oC for 1 hour.
8.3.3 Fabricating ring oscillators using SA-3, method 2 self-aligned back-channel cut
TFTs
We fabricated ring oscillators with an L of 38 µm using the simplified SA-3 process
described in 7.3.3 and method 1. We first deposited a barrier layer on the front and back
of the substrate (step 1), as for the standard non-self-aligned process. We then deposited
and patterned a tri-layer of 15/70/15 nm Cr/Al/Cr as the gate metal (steps 2 and 3) and
deposited the usual TFT stack layers (SiNx, a-Si:H and n+ a-Si:H ) according to the layers
in Table 7.4 (step 4). After TFT stack deposition we etch gate via holes (mask 2, step 5)
and carry out self-alignment between the gate and the S/D terminals as follows (step 6) as
described in section 7.3.3. After the alignment step, the substrate surface is dipped in
buffered oxide etch (HF:NH4F:H2O):DI mixed 1:100 for 2-4 seconds and loaded directly
into the thermal evaporator. A tri-layer of 15/280/15 nm Cr/Al/Cr is deposited (step 7)
and then we remove the photoresist in the channel region by sonicating the substrate in
isopropanol (IPA) for 20 minutes, as described in section 7.3.2. Any remnants of
photoresist are also removed by soaking the substrate in AZ400 for about 10 seconds
while rubbing the surface gently with two q-tips, followed by an oxygen descum (the
conditions in our Plasmatherm 790 are set at O2 flow rate = 40 sccm, pressure = 115
mTorr, RF power = 80 W and time = 600 s). We now need to use standard
photolithography and mask 3 to pattern the outline of the S/D electrodes (mask 3, step 8).
185
Finally the process is completed by RIE etching of the n+ nc a-Si (step 9) and the a-Si:H
(mask 4, step 10) to isolate individual devices (mask 4). The completed TFTs are then
annealed in the I-chamber of the PE-CVD (under vacuum) at 200oC for 1 hour.
Figure 8.4 shows the photoresist pattern on top of the substrate for self-aligning
the source-drain terminals (just before depositing the second metal layer). The dark
patches are the gate via holes that were opened in the SiNx layer over the gate contact
pads. The photoresist patterns in this case developed cleanly the first time and the gate
contact pads were not damaged. We achieved a S/D overlap of about 1 um over the gate.
We also started developing ring oscillators with L = 5 µm and L = 3 µm. Figure 8.5
shows a close-up view of an (incomplete) ring oscillator circuit on plastic (for S/D
terminals patterned using SA-3, method 2 self-alignment) made with back-channel cut
TFTs that
Gate via hole
Photoresist
patch
Figure 8.4 Optical micrograph of a 5-stage ring oscillator (design # 3, SA-3) on CP-2
fabricated at 250oC after patterning the photoresist to self-align the source-drain contacts
to the gate electrode. L = 38 µm
186
Figure 8.5 Close up view of a section of a ring oscillator after completing the S/D
terminal patterning. The interconnects were not completed at the point that the picture
was taken. The S/D overlap was created using SA-3, method 2. The substrate was CP-2,
the fabrication temperature was 300oC, and L = 5 µm
Figure 8.6 Completed 5-stage ring oscillator with the S/D contacts self-aligned to the
gate (design #3). The substrate used in this process was CP-2. L = 5 µm, and a fabrication
temperature of 300oC
187
have L = 5 µm. Figure 8.6 shows the completed ring oscillator. Due to the large TFT
OFF-current (discussed in Chapter 7), this ring oscillator is not functional. However, the
figure is included to demonstrate that we are capable of patterning the device layers to
fabricate ring oscillators with very small TFT L values, and as soon as we can resolve the
issue with the TFT OFF-current we should be able to make ring oscillators with very high
oscillation speeds.
8.4 Oscillator performance
The measurement set-up used to obtain ring oscillator performance is described in
Appendix B.5. We fabricated the following ring oscillators on CP-3 and glass:
1. Back channel cut non-self aligned TFTs on glass and CP-3 plastic using design #1
(L = 20 µm, S/D overlap with the gate metal is 10 µm)
2. Back channel cut non-self aligned TFTs on glass and CP-3 plastic using design #3
(L = 10 µm, S/D overlap with the gate metal is 15 µm???)
3. Back channel passivated self-aligned TFTs (channel passivation self-aligned to the
gate using SA-1) on CP-3 using design #2 (L = 20 µm, S/D overlap with the gate metal
is 10 µm)
4. Back channel cut self-aligned TFTs on CP-2 (using SA-3) with design #3 (L = 38 µm)
The ring oscillator fabrication details are summarized in table 8.2. Not surprisingly,
since the W/L ratios and the channel lengths for TFTs in ring oscillator designs #1 and #2
were designed to be the same, there was no noticeable difference in performance for
fabrication runs 1) and 3) for back-channel passivated self-aligned TFT on plastic and on
188
glass. When implementing fabrication run 2) there were two major changes in the device
geometry compared to fabrication run 1): the source-drain overlap capacitance increased
by a factor of 1/3 but the gate length decreased by 1/2. In this case the decrease in
channel length resulted in a faster oscillation (roughly 50% increase in frequency) and a
corresponding increase in power consumption. The measured power dissipation and gate
delay per stage is plotted in Figure 8.7 for oscillators from fabrication runs 1), 2) and 3).
Finally, the ring oscillator made from fabrication run 4 (design 3, self-aligning the
source-drain terminals to the gate) had a gate length of 38 (~ 2x larger than L in design
#1), and a very small source-drain overlap, of ~ 1 µm). The measured time delay and
power consumption per stage is plotted in Figure 8.8. The measured oscillation frequency
was rather low (about 2 ½ times lower than for the TFT with an L value of 10 µm) and
the oscillation amplitude was damped (measured oscillation amplitudes ranged from ~ 5
to 10 mV). These oscillators hardly turned on - therefore, in order to make high
performance ring oscillators with S/D self-alignment we need to decrease the TFT gate
length. This will only be possible once we optimize the source-drain self-alignment
process, and fix the high OFF-current issues that we have been experiencing, as discussed
in Chapter 7, section 7.4.
189
Table 8.2 Table summarizing the ring oscillator fabrication details for oscillators that
were measured and are described in section 8.4
Fabrication run
1
2
3
4
Design number
1
3
2
3
Back channel
cut
Back channel
cut
Back channel
passivated
Back channel cut
TFT geometry
Alignment
Non selfaligned
Non selfaligned
Channel
passivation selfaligned
S/D terminals
self-aligned
Stages
5 and 7
5 and 7
5 and 7
5 and 7
W/L (load) [µm]
80/20
36/10
80/20
36/38
W/L (driver) [µm]
360/20
360/10
360/20
360/38
S/D overlap with
gate [µm]
10
15
10
1
As discussed in section 8.2 we designed the mask-set for design 3 with a larger
β value since we had low output oscillation amplitudes for oscillators from mask designs
1 and 2. The output peak-to-peak oscillation amplitude for fabrication runs 1) and 3)
ranged from 50 to 80 mV, while the output oscillation amplitude for fabrication run 2
ranged from 2.1 to 4 V. The ring oscillators tended to fail when the power consumption
per stage increased above 8 mW. The highest measured oscillation frequency of 220 kHz,
190
was measured for a 5-stage oscillator fabricated from design#1, measured at VDD = 95 V.
Figure 8.9 shows a photograph of the oscillation for an oscillator from this fabrication run
for an applied VDD of 90V (the oscillator stopped working at 95V before we could take a
picture). The oscillation frequency in this photo is 166 kHz. This figure also demonstrates
the rather low output oscillation amplitude that was measured for these devices. Figure
8.10 shows the oscillation of a 7-stage oscillator from design #3 (non-self-aligned). Here
you can see that the measured oscillation amplitude has increased to ~ 5 V for a β of 10.
The oscillation frequency for the oscillation in this photo is 55 kHz.
Table 8.2 shows the measured and simulated oscillation periods for the 3
designs at a supply voltage VDD of 30V. The measured and simulated values match up
pretty well, except for the S/D self-aligned oscillator fabricated with design #3 where the
simulation failed to converge to an answer.
8
8
6
6
4
4
2
2
0
0
20
30
40
50
60
70
Gate delay (µs)
Power Dissipation (mW)
191
.
Supply voltage VDD
Power dissipation per stage, Design 1,2
Delay per stage, Design 1,2
Power dissipation per stage, Design 3
Delay per stage, Design 3
(not self-aligned)
(not self-aligned)
Figure 8.7 Comparison of the power consumption and time delay per stage for ring
oscillators on CP-3 with back-channel cut non-self-aligned TFTs using design 1 (L = 20
µm), ring oscillators with back-channel passivated SA-1 self-aligned TFTs using design 2
(L = 20 µm), and ring oscillators with back-channel cut non-self-aligned TFTs using
design 3 (L = 10 µm)
12
12
10
10
8
8
6
6
4
4
2
2
Gate delay (µs)
Power Dissipation (mW)
192
0
0
20
30
40
50
60
70
Supply voltage VDD
Figure 8.8: Comparison of the power consumption and time delay per stage for ring
oscillators fabricated from design #3 (self-aligned) on CP-2.
Table 8.2 Comparison of the simulated and measured oscillation period for a 7-stage
ring oscillator at a supply voltage of VDD = 30 V
Design
Simulated Period of
Oscillation (1/Hz)
Measured Period of
Oscillation (1/Hz)
1 and 2
27
28
3 (not self-aligned)
19
17
3 (self-aligned)
*doesn’t oscillate*
120
193
20 mV
2 µs
Figure 8.9 Photograph of measured oscillation, at VDD = 90 V, for a 5-stage inverter
fabricated from design #2, with back channel passivated TFTs fabricated on clear plastic.
1V
10 µs
Figure 8.10 Photograph of measured oscillation, at VDD = 30 V, for a 7-stage inverter
fabricated from design #3, with back channel cut non-self-aligned TFTs fabricated on
glass.
194
8.5 Outlook
This chapter has demonstrated the feasibility of making ring oscillator circuits on
plastic. However, the higher oscillation frequencies that our SA-2 and SA-3 selfalignment processes promised were not realized. It certainly seems possible to make
functional ring oscillators built using the short-channel length TFTs by self-aligning the
S/D terminals to the gate using SA-2 or SA-3 (see Figure 8.6). But, in order to do so, the
process to align the source-drain terminals to the gate needs to be optimized. Some of the
steps that we are considering for future experiments in this area were discussed in section
7.5.
From a processing point, we had issues connecting the gate and S/D layers since
the exposed gate metal was damaged by long exposure to developer. We plan to work
around this problem by implementing an alternative way to connect the bottom two metal
layers (see Figure 8.2). In addition to this, the success rate for fabricating functional
devices started being affected by the substrate surface. A substrate that is very scratchy,
or has many particle inclusions (see Figure 5.6) damages the circuits fabricated on that
section of the CP. Therefore, it is imperative to identify substrates with very smooth
surfaces to ensure the success of our process over a large area.
195
Chapter 9
CONCLUSION AND FUTURE WORK
The goal of the work in this thesis has been to develop a rugged, high
performance a-Si:H TFT device and circuit fabrication process on plastic substrates. We
believe that we have been successful in this endeavor. We have improved the
performance of individual TFTs by raising the maximum process temperature to 300oC,
and even fabricated individual devices at 350oC. We also reduced the contact resistance
to raise the measured electron field-effect mobility by decreasing the thickness of the aSi:H active layer to 25 nm and replacing the normal n+ doped a-Si layer with n+ nc-Si.
Chapter 6 summarized the electrical and stability performance of our devices, clearly
demonstrating their competitiveness with commercial a-Si:H TFTs on glass. This means
that fabricating TFT backplanes on CP is technically feasible.
Next, we considered the issues for fabricating large-area circuits on plastic. We
found that our ability for achieving functional devices over the entire surface area was
limited by misalignment between consecutive device layers. This problem was especially
severe for our high temperature (300oC) process due to the large εTH that develops for
high temperature deposition of inorganic device layers on plastic (see chapter 5), but
misalignment is an issue for any fabrication process on plastic substrates. We effectively
minimized layer misalignment and decreased the overlaps between critical device layers
and demonstrated functional back-channel passivated TFTs fabricated on CP with L = 5
196
µm, achieving functional devices over the entire surface area of the 2.8’’x 2.8’’ substrate
at maximum deposition temperature of 300oC. We also started work on TFTs with L =
3µm, and even smaller values.
These devices promise to open up a very exciting new field for us to make highperformance, high-speed circuits on plastic. In the past our TFTs were designed with L
values around 20 to 40µm and generous 5 to 10 µm overlaps to allow for misalignment.
However, as discussed in section 3.4, the large L values and large parasitic overlap
capacitances due to this design geometry will severely limit the switching speed of
fabricated TFTs. With our new self-alignment approach for short-channel TFTs
fabricated at 300oC, we are now on the way to fabricating a-Si:H TFT circuits on flexible
plastic substrates, that are highly competitive with circuits fabricated on glass substrates.
One future application that seems promising for our self-alignment method are
fabrication of matrix-addressed, optical imager arrays using these new a-Si:H TFTs as
pixel switches. One of the important factor in imager array performance is the signal-tonoise ratio. The read-out electronic noise is the dominant source of noise at low
illumination level, and is mainly determined by the input capacitance of the front-end
charge amplifier [1]. The total input capacitance of a charge amplifier while reading out
one pixel is the sum of the sensor capacitance and one source/drain to gate capacitance
from the active pixel. Our self-aligned TFT technology is expected to reduce the
contribution from CTFT since the self-aligned TFTs will not have the usual large
source/drain to gate overlap. An example of this approach was demonstrated by Lu et al.
who fabricated self-aligned a-Si:H TFTs by using a excimer laser doping/annealing
197
technology to form source/drain contacts self-aligned to gates [2,3]. Other applications
would be to fabricate high speed shift inverters, and shift registers to start building highspeed logic circuits, to test the performance that can be achieved for the self-aligned
process.
REFERENCES
[1] J. T. Rahn, F. Lemmi, R. L. Weisfield, R. Lujan, P. Mei, J. P. Lu, J. Ho, S. E. Ready,
R. B. Apte, P. Nylen, J. Boyce, and R. A. Street, “High-resolution High Fill Factor a-Si:H
Sensor Arrays for Medical Imaging”, Proc. of SPIE Conference on Physics of Medical
Imaging, vol. 3659, pp. 510, 1999
[2] J. P. Lu, P. Mei, J. Rahn, J. Ho, Y. Wang, J. B. Boyce and R. A. Street, “The impact
of self-aligned amorphous Si thin film transistors on imager array applications”, J.NonCryst.Sol., vol. 266-269, no. 2, pp. 1294-1298, 2000
[3] P. Mei, J. P. Lu, C. Chua, J. Ho, Y. Wang and J. B. Boyce, “Optical filter for
fabricating self-aligned amorphous silicon TFTs”, in Proc. MRS Symp., vol. 557, pp.
677-682, 1999
198
APPENDICES
Appendix A: PECVD deposition conditions
A.1 Back channel cut TFT geometry, 300oC process
A.2 Back channel passivated TFT geometry, 300oC
A.3 Back channel cut TFT geometry, 250oC
A.4 Back channel passivated TFT geometry, 250oC
A.5 SiNx deposition at 300oC in the N-chamber
A.6 n+ nc-Si deposition (Layer-by-layer)
199
A.1 Back channel cut TFT geometry, PE-CVD deposition conditions for 300oC
process
SiNx gate
i a-Si:H
dielectric
channel
(N-chamber)
(I-chamber)
n+ a-Si:H
S/D
(Pchamber)
Temperature set
Top
350 350
280 280
250 250
point (°C)
Bottom
330
250
230
300
250
250
500
500
500
22 - 213
17
22
SiH4 = 15
SiH4 = 50
SiH4 = 44
Actual substrate temperature
(°C)
Pressure
(mTorr)
Power density
(mW/cm2)
Gas flow rate (sccm)
PH3* = 6
NH3 = 130
Approximate
growth rate
1.8 – 4.5
1.6
1.1
300-400
200
30
(Å/s)
Usual thickness deposited
(nm)
*1% diluted in hydrogen
200
A.2 Back channel passivated TFT geometry, PE-CVD deposition conditions for
300°C process
SiNx gate
dielectric
(Nchamber)
Temperature
set point
(°C)
n+ a-Si:H
i a-Si:H
SiNx channel
S/D
channel
passivation
contact
(I-chamber)
(N-chamber)
(Pchamber)
Top
350 350
280 280
280 280
250 250
Bottom
330
250
250
230
300
250
240
250
500
500
500
500
22 - 213
17
22
22
SiH4 = 50
SiH4 = 15
Actual substrate
temperature
(°C)
Pressure
(mTorr)
Power density
(mW/cm2)
SiH4 =
15
Gas flow rate (sccm)
NH3 =
NH3 = 130
130
SiH4 =
44
PH3* = 6
Approximate
growth rate
1.8– 4.5
1.6
1.5
1.1
300-400
25
100
30
(Å/s)
Usual thickness
deposited
(nm)
*1% diluted in hydrogen
201
A.3 Back channel cut TFT geometry, PE-CVD deposition conditions for 250oC
process
SiNx gate
i a-Si:H
n+ a-Si:H S/D
dielectric
channel
contact
(N-chamber)
(I-chamber)
(P-chamber)
Temperature
Top
290 290
280 280
250 250
setpoint ( oC)
Bottom
270
250
230
250
250
250
500
500
500
22 - 213
17
22
SiH4 = 15
SiH4 = 50
SiH4 = 44
Actual substrate
temperature
(°C)
Pressure
(mTorr)
Power density
(mW/cm2)
Gas flow rate (sccm)
NH3 = 130
PH3* = 6
Approximate
growth rate
1.5-3.3
1.6
1.1
300-400
200
30
(Å/s)
Usual thickness deposited
(nm)
*1% diluted in hydrogen
202
A.4 Back channel passivated TFT geometry, PE-CVD deposition conditions for
250oC process
SiNx gate
i a-Si:H
SiNx channel
dielectric
channel
passivation
(N-chamber)
(I-chamber)
(N-chamber)
n+ a-Si:H S/D
(P-chamber)
Temperature
Top
290 290
280 280
290 290
250 250
set point (°C)
Bottom
270
250
270
230
250
250
250
250
500
500
500
500
22 - 213
17
22
22
SiH4 = 15
SiH4 = 50
SiH4 = 15
SiH4 = 44
NH3 = 130
PH3* = 6
Actual substrate
temperature
(°C)
Pressure (mTorr)
Power density
(mW/cm2)
Gas flow rate (sccm)
NH3 = 130
Approximate
growth rate
1.5 – 3.3
1.6
1.5
1.1
300-400
25
150
30
(Å/s)
Usual thickness
deposited
(nm)
*1% diluted in hydrogen
203
A.5 SiNx deposition rate at 300oC in the N-chamber
Figure A.1: Deposition rate measured in our PE-CVD N-chamber at 300oC. The
electrode area is 225 cm2 under deposition conditions specified in Appendix A.1
204
A.6 n+ nc-Si deposition (Layer-by-layer)
n+ nc-Si LBL deposition is carried out in the PE-CVD P-chamber. A single cycle consists
of a deposition step, followed by an annealing step. In total, 40 cycles are carried out,
resulting in a n+ nc-Si layer thickness of 50nm.
Deposition conditions/cycle
Deposition
Annealing
Temperature set
Top
260 270
260 270
point (°C)
Bottom
200
200
Actual substrate temperature (°C)
250
250
Pressure (mTorr)
900
900
Power density (mW/cm2)
133
53
SiH4 = 2
Gas flow rate (sccm)
H2 = 100
PH3 = 12
Time (s)
60
H2 = 90
Ar = 30
40
205
Appendix B:
B.1 TFT parameter extraction
B.2 Stability measurements
B.3 Measuring misalignment on our substrate
B.4 Characterizing the n+ nc-Si layer
B.5 Measuring ring oscillator performance
206
B.1 TFT parameter extraction
This section describes how the TFT parameters are extracted. Specifically we
discuss how to measure the threshold voltage (VTH), linear and saturation electron fieldeffect mobilities (µLIN and µSAT), the ON to OFF current ratio (ION/IOFF) and the subthreshold slope (S).
All of the TFT parameters can be calculated using a “transfer characteristic”. We
obtain such a transfer characteristic using an HP4155A parameter analyzer to sweep IDS
versus VGS while setting VDS at 0.1V. Then we sweep VGS and measure IDS while setting
VDS at 10V. A schematic of the measurement set-up is shown in Figure B.1. The
measured IDS and IGS for both sweeps are plotted on a semi-log plot (using the same set of
axes). An example of a transfer curve is plotted in Fig. B-2.
Figure B.1 Schematic of the measurement set-up used to measure the TFT transfer
characteristics
207
- 10-5
VDS=10V
W/L=80µm/80 µm
VDS=0.1V
-8
10
Slope = 1/S
-8
- 10
VTH for stress test
-11
-
10
-14
10
-10
0
10
20
10-11
Gate-source current IGS [A]
Drain-source current IDS [A]
10-5
10-14
Gate voltage VGS (V)
Figure B.2 Example of a transfer characteristic for an a-Si:H TFT made on clear plastic
We can now extract the TFT performance parameters from the transfer characteristic. To
understand how to do this, we need to examine the TFT current-model as stated in
Chapter 2 (equation 2.1). This equation is repeated here for easy reference (the linear and
saturation regime are modeled separately)
In the linear regime,
I DS 

V2 
W
μ LIN C i (VGS  VTH )V DS  DS 
L
2 

for
0  VDS  VGS  VTS
In the saturation regime, I DS 
VDS  VGS  VTH ,
W
μ SAT C i (VGS  VTH ) 2
2L
for
208
where Ci 
ε SiNX
t SiNX
is the capacitance per unit area for the SiNx gate dielectric. We
measured a Ci of 2.2x10-8F/cm by fabricating capacitors on glass and measuring the
capacitance per unit area. This gave us εSiNx = 7.4. The linear regime IDS versus VGS is
plotted in Figure B.3(a). ID is proportional to VGS and therefore one can extract VTH from
the slope of the plot in Figure B.3(a). This gate voltage marks the “threshold” where the
transistor changes from the OFF state to the ON state. In our stress tests we define the
threshold voltage to be the VGS value at which IDS = 1x10-8 A for the saturation regime
transfer characteristic ( VDS  VGS  VTH ). This value is indicated in Figure B.2. The
transfer curve in Figure B.3 (a) with VD=100 mV is used to extract the linear µLIN
according to:
μ LIN 
slope
,
Ci (W/L)VDS
The saturation regime IDS versus VGS is plotted in Figure B.3(b). Using this curve, the
mobility in saturation µSAT can be found from:
2L
.
WCi
current ratio is given by the ON current (I ) taken from the transfer curve
μ SAT  slope 2
The ION/IOFF
ON
where VDS = 10 V and VGS = 20 V divided by the minimum leakage current measured
when the TFT is OFF (I
). The subthreshold slope S 
OFF
VGS
is the inverse of
log 10 I DS 
the slope of the linear region of the semi-log plot of Figure B.2. It provides a measure of
the increase in gate voltage required to raise the drain current by one order of magnitude.
209
Smaller S means sharper transition between the off and on states. For the transfer
characteristics in Figure B.2 (for a back-channel passivated a-Si:H made on CP-2 at
300oC using a 5W gate dielectric) the linear mobility µ LIN is 0.81 cm2/Vs and µSAT is 0.47
40
Slope  W / L   LIN CiVDS
Slpe = W/LµLINCiVDS
30
20
10
VDS=0.1V
0
0
5
10
Gate Voltage VGS (V)
15
Square root of Drain-source current IDS (mA0.5)
Drain-source current IDS (nA)
cm2/Vs, the threshold voltage VTH is 1.56V, ION/IOFF is about 107, and S is 450mV/dec.
1
W
SAT Ci
2L
lope = W/LµLINCiVDS
Slope 
0.8
0.6
0.4
0.2
(a)
VDS=10V
0
0
5
Gate Voltage VGS (V)
(b)
Figure B.3 (a) IDS plotted versus VGS for VDS = 100mV, with the slope and VTH labeled.
(b) Square-root of IDS plotted versus VGS for VDS = 10V
10
210
B.2 Measuring TFT stability
We can measure the threshold-voltage stability in TFTs by applying a stress
voltage to the gate and extracting the shift in the threshold voltage ∆VTH. This is known
as gate-bias stressing and is discussed in detail in Chapter 4. This section describes our
method for carrying out typical stress tests. Figure B.4 shows a typical TFT transfer
characteristic measured before and after an applied stress. The stress applied to the TFT
gate is VG = 40V (corresponding to a stress field of 1.21x108 V/m applied over a gate
dielectric thickness of 330nm) for 600 seconds while grounding the S/D electrodes. From
Figure B-4 we can measure the threshold voltage before the stress and after stress – the
difference between these two values gives the threshold voltage shift, ∆VTH. In Figure
B.4, ∆VTH ~ 1.4 V for this particular stress condition.
In this thesis we carry out series of stress experiments, consisting of individual
stress tests. Each stress test is carried out as follows: we first measure the transfer
characteristic of an unstressed TFT (sweeping VGS from right to left). Then we apply the
stress conditions and then we re-plot the transfer curve and extract ∆VTH. The parameter
that we changed from test to test was either the applied stress field EST or the time τST that
a constant stress field was applied for. From the series of stress experiments we extract
(1) ∆VTH as a function of EST while keeping τST constant and (2) the ∆VTH as a function
of τST with EST constant.
For the stress-series measurements in this thesis the parameters used are: (1)
applying an increasing stress voltage from 20 to 60V to the gate for a constant time of
600s and (2) applying a constant stress field (usually 1x108V/m) to the gate while
increasing the stress time from 10 to 10,000 seconds. . We use a new TFT for each stress
211
test and the W/L ratio is kept constant at 80 µm/40 µm to ensure easy comparison of the
stability data generated. In each test a stress voltage is applied to the gate while
grounding the S/D terminals.
VTH
10-5
VDS=10V
W/L=80µm/80 µm
Stress time = 600s
Before
After
-8
10
VDS=0.1V
10-8
10-11
10-11
10-14
10-14
20
-10
0
10
Gate-source current IGS (A)
Drain-source current IDS (A)
10-5
Gate Voltage VGS (V)
Figure B.4 Transfer characteristic of an a-Si:H TFT before (blue) and after (red) a gate
stress field of 1.21x108 V/m is applied at the gate for 600 s while grounding the source
and drain terminals.
212
B.3 Measuring misalignment on our mask-set
The definition of misalignment, λ, can be found in section 3.2. We investigate
misalignment by examining alignment marks at specific positions on our substrate before
and after deposition. Figure B.5(a) shows a cartoon of the substrate surface indicating the
position of the five alignment marks that we usually look at when evaluating
misalignment [1]. Alignment marks 1, 2, 3 and 4 are at the corners of the substrate
surface and alignment mark 5 is at the center. When our TFTs are fabricated using
standard photolithography (without self-alignment) we always align the TFT layers at
position 5. Figure B.5(b) shows an optical micrograph of the alignment marks at position
5, where the mark in the bottom layer (before deposition) and the alignment mark in the
Bottom layer
Roll
axis
80µm
Top layer
(a)
(b)
Figure B.5 (a) Cartoon of substrate showing position of the alignment marks (left) and
(b) an optical micrograph of alignment marks on two layers at the center of the substrate
(right) [1]
213
Bottom layer
80µm
Top layer
(a)
(b)
Figure B.6 Cartoon of a substrate under compression after device layer deposition,
showing how the position of the alignment marks has changed (a) and an optical
micrograph of alignment marks on two different mask layers at corner 2 (b) [1]
top layer (after deposition and substrate dimension change) perfectly overlap. The
misalignment between device layers becomes more pronounced for TFTs lying farther
from the center. In Figure B.6(a) the substrate after device layer deposition is shown,
indicating the change in dimensions (in this example the substrate area decreased), and
Figure B.6.(b) is an optical micrograph of the alignment marks at position 2. The top
mark no longer overlaps the bottom mark since the substrate has shrunk and the gate is
now closer to the center than it was designed to be.
We used the same mask-set to make TFTs for the processes in sections 6.2, 6.3,
7.1, 7.2 and 7.3. This mask set had 6x12 arrays of unit cells spread across its surface, as
shown in Figure B.7. Each unit cell contained 55 individual TFTs (shown in Figure B.8)
214
with the following W/L ratios (if used to fabricate back-channel passivated TFTs): 6 x
80/40, 6 x 80/80 (=80/40, back-channel cut), 2 x (60/30, 60/20, 60/15), 2x (120/80,
120/60, 120/40, 120/30, 120/20, 120/15), 2x(150/80, 150/60 ,150/40, 150/30, 150/20,
150/15), 2x(200/80, 200/60, 200/40, 200/30, 200/20, 200/15). Each unit cell has
dimensions of 4.5mm x 5mm. We usually measure misalignment from an alignment mark
in one of the center unit cells, and an alignment mark in the outer corner of the outer unit
cells, as indicated in Figure B.7.
Outer unit cell from which
we measure
misalignment
~5cm
Figure B.7 Cartoon of the array of unit cells in our TFT mask design
215
Figure B.8 Cartoon of the array of TFTs in a single unit cell
216
B.4 Characterizing the n+ nc-Si layer
We characterized our films by measuring the DC conductance and a UV
reflectance (UVREF) as follows:
DC conductivity was measured in the dark using a collinear four-point probe. The
setup is shown in Fig.B.9. In this set-up constant current, I, is flowing through the two
outer contacts, while the voltage V across the two inner contacts is measured. The
conductivity  averaged over the film thickness t is expressed as:
σ 
1 I
 
F t  V 
where F denotes the geometric correction factor which is dependent on d/s, where d is
shortest length of a rectangular sample or diameter of a circular sample, and s is the
spacing between two adjacent probes (in our set-up s = 1.59mm). For an infinitely large
sample, d >> s, the correction factor F is equal to  / ln 2 ( 4.53). We measured a value
of σ = 12 S/cm using this on our n+ nc-Si films deposited using the LBL method.
+
Keithley Instruments _
225 Current Source
IIN V+ V- IOUT
d
s = 1.59 mm
Keithley Instruments
195 System DMM
(current measurement)
_
+
V/
HP 3478A Multimeter
(voltage measurement)
GND
mA
Figure B.9 The experimental setup for four-point probe measurement [17]
217
We measured UVREF with a Hitachi U-3410 spectrophotometer. This UVREF
measurement gives a semi-quantitative value for the crystallinity of the n+ nc-Si films. At
wavelengths from 200 nm to 450 the UVREF intensity of a-Si:H films decreases
monotonically as the wavelength increases but for crystalline silicon (c-Si) two
pronounced peaks appear around 276 nm and 365 nm [2, 3]. The peak height, which is
the difference between the reflectance of crystalline silicon at 276 nm and the baseline for
the amorphous film, is often used as an indicator for film crystallinity. In our
measurements of Figure B.10 the presence of peaks at these two wavelengths were taken
as proof that the film was no longer fully amorphous.
UV reflectance (arbitrary units)
1
0.8
Peak #1
0.6
Peak #2
0.4
200
250
300
350
400
450
Wavelength (nm)
Figure B.10 Ultraviolet reflectance measurements of the nc-Si deposited using a LBLdeposition method
218
B.5 Measuring ring oscillator performance
We measured the performance of our ring oscillators using the HP4155A
parameter analyzer to supply power to the oscillator (ground and VDD). There were two
places in the oscillator mask that needed to be connected to ground, as shown in the
schematic of the measurement set-up of Figure B.11. The output of the ring oscillator
(after the buffer) was connected to a Tektronix TDS303 oscilloscope.
Tektronix TFS3032 oscilloscope
HP4155A parameter analyzer
Output
VDD
Ground
Figure B.11 Measurement set-up for ring-oscillator circuits
219
REFERENCES
[17]
I-C. Cheng, A. Z. Kattamis, K. Long, J. Sturm, and S. Wagner, “Stress control for
overlay registration in a-Si:H TFTs on flexible organic polymer-foil substrates”, J.
Soc. Inf. Disp., vol. 13, no. 7, pp. 563–568, 2005
[18]
W. C. Dash and R. Newman, “Intrinsic optical absorption in single crystal
germanium and silicon at 77K and 300K”, Phys. Rev., vol. 99, pp. 1151-1155,
1955
[19]
R. Phillips and E. A. Taft, “Optical Constants of Silicon in the Region 1 to 10
eV”, Physical Review, vol. 120, no. 1, pp.37-38, 1960
220
Appendix C: Process sequences
C.1 Back channel cut geometry, non-self-aligned
C.2 Back channel passivated geometry, non-self-aligned
C.3 Back channel passivated geometry, back channel SiNx self-aligned
C.4 Back channel cut geometry, source-drain self-aligned
C.5 Back channel cut geometry (simplified), source-drain self-aligned
221
C.1
Back-channel cut TFT geometry, non-self-aligned
1 Prepare substrate (for details see Chapter 5)
Deposit SiNx Buffer at 300°C (Front and back)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- n+ a-Si or n+ nc-Si contact layer
5 Source/Drain metal deposition:
- 15/70/15nm Cr/Al/Cr
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
6 Mask #2 - Source/ drain and interconnect metal pattern
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum
etchant for 4-7 min. Visual inspection is required as etch rates may vary.
7 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
222
-
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
8 Mask # 3 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
9 Mask # 4 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
223
C.2
Back-channel passivated TFT geometry, non-self-aligned
1 Prepare substrate (for details see Chapter 5)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- SiNx channel passivation
5 Mask # 2 - Back-channel passivation patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 10 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet-etch in BOE(6:1) for 30 sec to 1 min. Rinse with DI water and confirm that the
channel passivation has been etched enough by looking for dewetting.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min. Then
dip in AZ312MIF, 20 sec, q-tip rub if necessary
Clean substrate in a piranha etch: 1:1 mix of H2O2:H2SO4 for 15 min.
Dip in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Immediately load into PE-CVD LL and pump down
6 Deposit n+ doped layer
7 Source/Drain metal deposition:
224
-
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
8 Mask #3 - Source/ drain and interconnect metal pattern
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum
etchant for 4-7 min. Visual inspection is required as etch rates may vary.
9 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
10 Mask # 4 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
225
11 Mask # 5 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
226
C.3 SA-1 : Back-channel passivated TFT geometry, back-channel self-aligned to the
gate
1 Prepare substrate (for details see Chapter 5)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- SiNx channel passivation
5 Self-align channel passivation
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 10 min
Expose in mask aligner using Mask 3 (a-Si:H island definition) to remove PR
everywhere except at the channel area. UV intensity = 2.0 mW/cm2, Time = 40 sec
Expose PR through back of substrate, without a mask:
UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =50 sec
6 Create channel passivation overlap to gate
Over-etch in BOE(6:1) for 1.5-2 min. to create channel passivation overlap.
Rinse with DI water and confirm that the channel passivation has been etched
enough by looking for de-wetting.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
227
-
Clean substrate in a piranha etch: 1:1 mix of H2O2:H2SO4 for 15 min.
Dip in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Immediately load into PE-CVD load lock and pump down
7 Deposit n+ doped layer
8 Source/Drain metal deposition:
- 15/60/15nm Cr/Al/Cr
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
9 Mask #2 - Source/ drain and interconnect metal pattern
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum
etchant for 4-7 min. Visual inspection is required as etch rates may vary.
10 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
11 Mask # 3 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
228
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
12 Mask # 4 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
-
229
C.4
SA-2: Back-channel cut TFT geometry, S/D terminals self-aligned to the
gate
1 Prepare substrate (for details see Chapter 5), deposit barrier layers on front, back
After depositing back barrier layer DO NOT UNLOAD
Deposit 200 nm a-Si:H at 250oC (see Appendix A.1 for PE-CVD deposition conditions)
Next deposit 50 nm SiNx at 200oC, and a deposition power of 5W
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Mask #2 – Back a-Si:H layer patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide face downwards with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720, load facing downwards
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
Etch SiNx: CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr,
Power = 100 W, Time = 1-1.5 min
Etch a-Si: layer: CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ314MIF, 20 sec, q-tip rub if necessary
5 Deposit TFT stack:
230
- SiNx gate dielectric
- a-Si:H active layer
- n+ a-Si:H
6 Create source-drain overlap with gate
- Use Method 1 or Method 2, described in Chapter 7
7 Source/Drain metal deposition:
- 65nm Cr
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
8 Pattern S/D electrodes:
Sonicate the sample in isopropanol (IPA) for 20 minutes.
Then dip in AZ400 and rub gently for 5-10 seconds
Next descum in Plasmatherm 790
Use: O2 = 40 sccm, Power = 80 W, Pressure = 115 mTorr, 10 min,
Now complete source/ drain and interconnect pattern with mask 3:
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 60-120 sec.
Visual inspection is required as etch rates may vary.
9 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
10 Mask # 3 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
231
-
-
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
11 Mask # 4 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
12 Strip back a-Si:H layer patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide face downwards with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720 (load facing downwards)
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
Etch SiNx: CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr,
Power = 100 W, Time = 1-1.5 min
Etch a-Si: layer: CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
232
C.5
SA-3: Back-channel cut TFT geometry, S/D terminals self-aligned to the
gate
1 Prepare substrate (for details see Chapter 5), deposit barrier layers on front, back
After depositing back barrier layer
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- n+ a-Si:H
5 Create source-drain overlap with gate
- Use Method 1 or Method 2, described in Chapter 7, and mask #2 (a-Si:H island
definition)
6 Source/Drain metal deposition:
- 65nm Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
7 Mask #3 -Pattern S/D electrodes:
Sonicate the sample in isopropanol (IPA) for 20 minutes.
Then dip in AZ400 and rub gently for 5-10 seconds
Next descum in Plasmatherm 790
Use: O2 = 40 sccm, Power = 80 W, Pressure = 115 mTorr, 10 min,
Now complete source/ drain and interconnect pattern with mask 3:
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
233
-
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =50 sec
Wet etch: Cr with Cr-7 etchant for 60-120 sec.
Visual inspection is required as etch rates may vary.
8 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
9 Mask # 2 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
10 Mask # 4 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
234
-
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
235
C.6
SA-1 and SA-3: Back-channel passivated TFT geometry, channel
passivation and S/D terminals self-aligned to the gate
1 Prepare substrate (for details see Chapter 5)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =5 0 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- SiNx channel passivation
5 Self-align channel passivation (SA-1)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 10 min
Expose in mask aligner using Mask 3 (a-Si:H island definition) to remove PR
everywhere except at the channel area. UV intensity = 2.0 mW/cm2, Time = 40 sec
Expose PR through back of substrate, without a mask:
UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
6 Create channel passivation overlap to gate
Over-etch in BOE(6:1) for 1.5-2 min. to create channel passivation overlap.
Rinse with DI water and confirm that the channel passivation has been etched
enough by looking for de-wetting.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
Clean substrate in a piranha etch: 1:1 mix of H2O2:H2SO4 for 15 min.
236
-
Dip in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Immediately load into PE-CVD load lock and pump down
7 Deposit n+ doped layer
8 Create source-drain overlap with gate (SA-3)
- Use Method 1 or Method 2, described in Chapter 7, and mask #2 (a-Si:H island
definition)
9 Source/Drain metal deposition:
- 65nm Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
10 Mask # 3 Pattern S/D electrodes:
Sonicate the sample in isopropanol (IPA) for 20 minutes.
Then dip in AZ400 and rub gently for 5-10 seconds
Next descum in Plasmatherm 790
Use: O2 = 40 sccm, Power = 80 W, Pressure = 115 mTorr, 10 min,
Now complete source/ drain and interconnect pattern with mask 3:
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =5 0 sec
Wet etch: Cr with Cr-7 etchant for 60-120 sec.
Visual inspection is required as etch rates may vary.
11 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
12 Mask # 2 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =50 sec
Etch in Plasmatherm 720
237
-
-
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
13 Mask # 4 - Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =5 0 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
238
Appendix D
D.1 Ring oscillator fabrication (back-channel cut, non-self-aligned)
D.2 Ring oscillator fabrication (back-channel passivated, channel passivation SiNx
self-aligned)
D.3 Ring oscillator fabrication (back-channel cut, source-drain self-aligned –
simplified process)
D. 4 Mask layout
239
D.1
Ring-oscillator fabrication (back-channel cut, non-self-aligned)
1 Prepare substrate (for details see Chapter 2)
Deposit SiNx Buffer at 300°C (Front and back)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time =5 0 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- n+ a-Si or n+ nc-Si contact layer
5 Mask # 2: Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CF4 = 70 sccm, O2 = 10 sccm, Pressure = 50 mTorr, Power = 100 W,
Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Dip in AZ312MIF, 20 sec, q-tip rub if necessary
240
-
Clean surface with an O2 descum in the 720: O2 = 40 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 5 min
Clean surface by dipping in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Load immediately into thermal evaporator
6 Source/Drain metal deposition:
- 15/250nm Cr/Al
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
7 Mask #3 - Source/ drain and interconnect metal pattern
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum
etchant for 4-7 min. Visual inspection is required as etch rates may vary.
8 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
Mask # 4 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
241
D.2
Ring-oscillator fabrication (back-channel passivated, channel passivation
self-aligned)
1 Prepare substrate (for details see Chapter 2)
Deposit SiNx Buffer at 300°C (Front and back)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- SiNx channel passivation
5 Self-align channel passivation (SA-1 in chapter 7)
-
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner using Mask 3 (a-Si:H island definition) to remove PR
everywhere except at the channel area. UV intensity = 2.0 mW/cm2, Time = 40 sec
Expose PR through back of substrate, without a mask:
UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
6 Create channel passivation overlap to gate
Over-etch in BOE(6:1) for 1.5-2 min. to create channel passivation overlap.
Rinse with DI water and confirm that the channel passivation has been etched
enough by looking for de-wetting.
242
-
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
Clean substrate in a piranha etch: 1:1 mix of H2O2:H2SO4 for 15 min.
Dip in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Immediately load into PE-CVD load lock and pump down
7 Deposit n+ doped layer
8 Mask # 2: Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720: clean chamber with an O2 descum as follows:
O2 = 40 sccm, Power = 100 W,100 mTorr, 60-90 min, with wafer loaded in
chamber.
Load sample into tool and transfer to chamber. CF4 = 70 sccm, O2 = 10 sccm,
Pressure = 50 mTorr, Power = 100 W, Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Dip in AZ312MIF, 20 sec, q-tip rub if necessary
Clean surface with an O2 descum in the 720: O2 = 40 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 5 min
Clean surface by dipping in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Load immediately into thermal evaporator
9 Source/Drain metal deposition:
- 15/250nm Cr/Al
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
10 Mask #2 - Source/ drain and interconnect metal pattern
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20 -60 sec, Al with Al-11 aluminum
etchant for 4-7 min. Visual inspection is required as etch rates may vary.
11 Dry etch n+ a-Si:H
243
-
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
12 Mask # 3 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
244
D.3
Ring oscillator, back channel cut, source-drain terminals self-aligned using SA-3
1 Prepare substrate (for details see Chapter 2)
Deposit SiNx Buffer at 300°C (Front and back)
2 Gate metal deposition:
15/70/15nm Cr/Al/Cr
Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
3 Mask # 1- Bottom gate patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 20-60 sec, Al with Al-11 aluminum etchant
for 4-7 min. Visual inspection is required as etch rates may vary.
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
4 Deposit TFT stack:
- SiNx gate dielectric
- a-Si:H active layer
- n+ a-Si or n+ nc-Si contact layer
5 Mask # 2: Gate contact via (etch holes in SiNx)
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720: clean chamber with an O2 descum as follows:
O2 = 40 sccm, Power = 100 W,100 mTorr, 60-90 min, with wafer loaded in
chamber.
Load sample into tool and transfer to chamber. CF4 = 70 sccm, O2 = 10 sccm,
Pressure = 50 mTorr, Power = 100 W, Time = 1-1.5 min
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Dip in AZ312MIF, 20 sec, q-tip rub if necessary
Clean surface with an O2 descum in the 720: O2 = 40 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 5 min
Clean surface by dipping in BOE (1:6) diluted to 1:100 in DI for 2-3 seconds
Load immediately into thermal evaporator
245
6 Create source-drain overlap with gate
Use Method 1 or Method 2, described in Chapter 7, and mask #2 (a-Si:H island definition)
7 Source/Drain metal deposition:
- 15/250nm Cr/Al
- Thermal evaporation: Rate = 2.5 – 8 Å/sec, TMAX = 80°C, PBASE = 3-5x10-7 mBarr
8 Mask #3 -Pattern S/D electrodes:
Sonicate the sample in isopropanol (IPA) for 20 minutes.
Then dip in AZ400 and rub gently for 5-10 seconds
Next descum in Plasmatherm 790
Use: O2 = 40 sccm, Power = 80 W, Pressure = 115mT, 10 min,
Now complete source/ drain and interconnect pattern with mask 3:
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Wet etch: Cr with Cr-7 etchant for 60-120 sec.
Visual inspection is required as etch rates may vary.
9 Dry etch n+ a-Si:H
- Etch in Plasmatherm 720
- Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
- Load sample into tool and transfer to chamber.
- Etch with CCl2F2 = 70 sccm, O2 = 10 sccm, Pressure = 100 mTorr,
Power = 100 W, Time = 3-3.5 min
- Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
10 Mask # 3 - i a-Si:H island patterning
Pre-heat sample on hotplate at 110oC for 10 min
Mount on to glass slide with water droplet
Spin on HMDS: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Spin on AZ5214: Speed = 4000 rpm, Ramp = 1000 rpm/sec, Time = 40 sec
Soft-bake on hotplate at 110oC for 1 min
Expose in mask aligner: UV intensity = 2.0 mW/cm2, Time = 40 sec
Develop: AZ300MIF, Time = 50 sec
Etch in Plasmatherm 720
Clean chamber with an O2 descum as follows: O2 = 40 sccm,
Power = 100 W,100 mTorr, 60-90 min, with substrate carrier loaded in chamber
246
-
-
Load sample into tool and transfer to chamber.
CCl2F2 = 20 sccm, SF6 = 60 sccm, Pressure = 100 mTorr, Power = 100 W,
Time = 2-4 min. May require visual inspection
Strip PR: Flood Exposure, UV intensity = 3.5 mW/cm2, Time = 10 min.
Then dip in AZ312MIF, 20 sec, q-tip rub if necessary
247
D.5
Ring-oscillator mask layout (5 inverter stages)
Ring oscillator mask 1 ( pattern gate metal, design 1 )
Gate width = 30µm
Gate width = 30µm
248
Ring oscillator mask 2 ( pattern gate vias, design 1 )
249
Ring oscillator mask 3 ( pattern source-drain metal, design 1 )
Gap = 20 µm
W = 80 µm
W = 360 µm
250
Ring oscillator mask 4 ( a-Si:H islands, design 1)
251
LIST OF PUBLICATIONS FROM THIS WORK
JOURNAL PUBLICATIONS
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
J. Z. Chen, K. H. Cherenack, C. Tsay, I-C. Cheng, and S. Wagner, „Effects of SiNx
passivation layer and gate metal roughness on performance of a-Si:H TFTs on
polyimide foil‟, Electrochemical and Solid State Letters, Volume 11, No. H26,
2008
B. Hekmatshoar, A. Z. Kattamis, K. H Cherenack, K. Long, J. Z. Chen, S.
Wagner, J. C Sturm, K. Rajan, and M. Hack, ’Reliability of Active-Matrix Organic
Light-Emitting-Diode Arrays With Amorphous Silicon Thin-Film Transistor
Backplanes on Clear Plastic‟, IEEE Electron Device Letters, Volume 29, Issue 1,
pp. 63-66, January 2008
B. Hekmatshoar, A. Z. Kattamis, K. H. Cherenack, S. Wagner, and J. C. Sturm, ‟A
novel TFT-OLED integration for OLED-independent pixel programming in
amorphous-Si AMOLED pixels‟, Journal of the Society for Information Display,
Volume 16, Issue 1, pp. 183-188, January 2008
J. Z. Chen, K. H Cherenack, C. Tsay, I-C. Cheng, and S. Wagner, „Effects of SiNx
passivation layer and gate metal roughness on the performance of on-plastic a-Si:H
TFTs‟, Electrochemical Solid-State Letters, Volume 11, No. 2, H26-H28, 2008
K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, and S. Wagner,
„Amorphous silicon thin-film transistors fabricated at 300ºC on a clear plastic
substrate foil‟, IEEE Electron Device Letters, Volume 28, No. 11, pp. 1004-1006,
November 2007
A.. Z. Kattamis, I-C. Cheng, K. Long, B. Hekmatshoar, K. H. Cherenack, S.
Wagner, J. C. Sturm, S. M. Venugopal, D. E. Loy, S. M. O'Rourke, and D. R.
Allee, „Amorphous Silicon Thin-Film Transistor Backplanes Depositied at 200o C
on Clear Plastic for Lamination to Electrophoretic Displays‟, Journal of Display
Technology, Volume 3, pp. 304-309, Sept 2007
A. Z. Kattamis, K. H Cherenack, B. Hekmatshoar, I-C. Cheng, H. Gleskova, J. C.
Sturm, and S. Wagner, „Effect of SiNx Gate Dielectric Deposition Power and
Temperature on a-Si:H TFT stability‟, IEEE Electron Device Letters, Volume 28,
Issue 7, pp. 606-608, July 2007
K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, and S. Wagner,
„Amorphous silicon thin-film transistors fabricated on clear plastic at 300oC ‟,
submitted for publication to the Journal of the Korean Physical Society (JKPS),
2008
252
[9]
B. Hekmatshoar, K. H. Cherenack, A..Z. Kattamis, K. Long, S. Wagner, and J. C.
Sturm, "Highly stable amorphous-silicon thin-film transistors on clear plastic,"
Applied Physics Letters, Volume 93, Issue 3, pp. 032103-1-3 July 2008
CONFERENCE PUBLICATIONS
[1] K. H. Cherenack, A. Z. Kattamis, I-C. Cheng, S. Wagner, „Self-aligned Amorphous
Silicon Thin Film Transistors with Mobility above 1 cm2V-1s-1 fabricated at 300oC
on Clear Plastic Substrates‟, manuscript submitted at the MRS Spring Meeting, San
Francisco, 24-28 March, 2008, paper# 1066-A20-03
[2] I-C. Cheng, K. H. Cherenack, J. Z. Chen, A. Kattamis, B. Hekmatshoar, J. C.
Sturm, and S. Wagner, „Silicon thin-film transistor backplanes on organic polymer
foils for flexible display applications‟, Proc. of ISFED, II-6, pp. 31-32, International
Symposium on Flexible Electronics and Displays, Hsinchu, Taiwan, Dec 2007.
[3] I-C. Cheng, H. Gleskova, J. Z. Chen, K. H. Cherenack, A. Kattamis, B.
Hekmatshoar, J. C. Sturm, and S. Wagner, „Silicon thin-film transistors on plastic
foil‟, presented at 3rd Global Plastic Electronics Conference & Showcase,
Symposium Hybrid Opportunities - Section 12, Frankfurt, Germany, Oct 2007.
[4] J. Z. Chen, K. H. Cherenack, C. Tsay, I-C. Cheng, and S. Wagner, „Effects of SiNx
passivation layer and gate metal roughness on performance of a-Si:H TFTs on
polyimide foil‟, International conference on amorphous and nanocrystalline
semiconductors (ICANS), Aug. 19-24, 2007
[5] J. C. Sturm, K. H. Cherenack, B. Hekmatshoar, A. Z. Kattamis, I-C. Cheng, J. Z.
Chen, S. Wagner, S. Venugopal, D. Toy, D. E. Loy, S. M. O‟Rourke, D. R. Allee,
„Flexible Active Matrix OLED and Electrophoretic Arrays with Amorphous Silicon
TFT Backplanes Processed up to 300ºC on Clear Plastic Substrates‟, 2007
International Symposium, Seminar, and Exhibition, Society of Information Display,
May 20-25, 2007.
[6] S. Wagner, A. Z. Kattamis, B. Hekmatshoar, K. H. Cherenack, I-C. Cheng, H.
Gleskova, J. C. Sturm, ‟Thin-film Transistor Backplanes on flexible polymer and
steel foil substrates‟, Proc.3rd Internat.TFT Conf. (ITC '07), Rome, Italy, Paper 4.1,
pp 58-63, 25-26 Jan. 2007
[7] K. H. Cherenack, A. Z. Kattamis, K. Long, S. Wagner, and J. C Sturm, „SiNx
barrier layers deposited at 250oC on a clear polymer substrate‟, Mat. Res. Soc. Symp.
Proc. Volume 936, paper 0936-L01-05, pp.1-5, 2006
POSTER PRESENTATIONS
253
[1] K. H. Cherenack, A. Kattamis, B. Hekmatshoar, J. C. Sturm and S. Wagner
„Improving the Effective Field Effect Mobility in TFTs Fabricated at 300oC on a
Clear Plastic Substrate‟, second price poster award at the 7th annual United States
Display Consortium Conference on Flexible Electronics, Phoenix, AZ, 21-24 Jan.
2008
[2] K. H. Cherenack, A. Z. Kattamis, I-C. Cheng, S. Wagner, „Back-channel passivated
amorphous slicon TFTs fabricated at 300ºC on a clear plastic substrate‟, poster
presentation A17.3 at the Mat. Res. Soc. Spring Meeting, San Francisco, 8-13 April
2007
[3] B. Hekmatshoar, K. H. Cherenack, A. Z. Kattamis, S. Wagner and J. C. Sturm,
„Dependence of Stability of a-Si TFT's Fabricated on Clear Plastic at 285°C on Gate
Stress Voltage‟, A17.1 prize-winning poster presented at the MRS Spring meeting in
San Francisco, California, April 9-13, 2007
[4] K. H. Cherenack, I-C. Cheng, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, and S.
Wagner, „Amorphous silicon TFTs fabricated at 300ºC on a clear plastic substrate‟,
presented at the 6th annual United States Display Consortium Conference on
Flexible Electronics, Phoenix, AZ, 6-8 Feb. 2007
[5] B.. Hekmatshoar, A.. Z. Kattamis, K. H. Cherenack, S. Wagner and J. C. Sturm,
"Novel Amorphous-Si AMOLED Pixels with OLED-independent Turn-on Voltage
and Driving Current," Device Research Conference, Chicago, IL, May 2007
[6] J. C. Sturm, B. Hekmatoshoar, K. H. Cherenack, A. Z. Kattamis, and S. Wagner,
“Active-Matrix OLED‟s with High-Lifetime Amorphous Silicon Transistors on
Clear Plastic Substrates,” Mat. Res. Soc. Symp., Boston, MA, USA, Nov. 2007,
Proceedings Symposium G (Volume 1030E).
[7] K. H. Cherenack, A. Z. Kattamis, I-C. Cheng, S. Wagner, „SiNx barrier layers
deposited on a clear polymer substrate at high temperatures‟, presented at the 5th
annual United States Display Consortium Conference on Flexible Electronics,
Phoenix, AZ, February 2006
ORAL PRESENTATIONS
[1] K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm and S. Wagner,
„Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V1 -1
s fabricated at 300oC on Clear Plastic Substrates‟, talk A20.3 given at the MRS
Spring Meeting, San Francisco, 24-28 March, 2008
[2] K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm and S. Wagner,
„Amorphous silicon thin-film transistors made on clear plastic at 300ºC‟, talk 7.2
given at the 2008 6th International thin-film conference (ITC) in Seoul, South Korea,
Jan 24-25, 2008
254
[3] K. H. Cherenack, „Fabricating a-Si:H TFTs at 300ºC on a Clear Plastic Substrate‟,
Seminar talks at ETH (Zürich), INESC (Lisbon), INM(Saarbrücken) and IMFII(Karlsruhe), October 15-November 3, 2007
[4] K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, I-C. Cheng, J. C. Sturm, S.
Wagner, „Developing a 300ºC Silicon Transistor Fabrication Process on Clear Plastic
Substrates for Flexible Display Backplanes‟, session 6 talk 2 given at the Fifth
International Symposium on Polyimides and other High Temperature Polymers,
Orlando Florida, Nov 5-7, 2007
[5] K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, I-C. Cheng, J. C. Sturm, S.
Wagner, „Back-Channel Passivated Amorphous Silicon TFTs Fabricated at 300oC on
a Clear Plastic Substrate‟, talk L6 given at the TMS 2007 Electronic Materials
Conference, University of Notre Dame, Indiana, June 20-22, 2007