Vol. 36, No. 11
Journal of Semiconductors
November 2015
Single event transient pulse width measurement of 65-nm bulk CMOS circuits
Yue Suge(岳素格)1; 2; Ž , Zhang Xiaolin(张晓林)1 , and Zhao Xinyuan(赵馨远)2
1 Beijing
2 Beijing
University of Aeronautics & Astronautics, Beijing 100191, China
Microelectronics Technology Institute, Beijing 100076, China
Abstract: Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device
threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that
the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak
phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also
discussed.
Key words: SET; pulsewidth; 65 nm
DOI: 10.1088/1674-4926/36/11/115006
EEACC: 2570
1. Introduction
Single event transients (SETs) have received increased
scrutiny in recent years. The SET with a larger pulse width usually has a greater influence on a circuit or a cell, and eventually
contributes more to the soft error rate (SER). Thus, characterizing the widths of SET pulses is of great importance in the
prediction and mitigation of single-event effects, especially for
an advanced technology.
The width of an SET pulse is determined by many factors,
such as operating voltage and temperature. In this work, a 65nm CMOS SET pulse width testchip was designed, and tested
using heavy ions. The impacts of device threshold voltage and
temperature on SET pulse width were studied. A multi-peak
phenomenon in SET pulse width distribution was found and is
discussed for the first time. The influence of logic type and well
separation is also discussed and compared with former studies.
2. Testchip and experimental setups
The testchip was fabricated with a 65-nm bulk Si CMOS
process, with a regular 1.2 V core voltage and 3.3 V IO voltage.
The structure and its principle of measuring SET pulse width
are similar to that in Reference [1]. To reduce propagation induced pulse broadening (PIPB)Œ2; 3 , we modified the serial target structure as a parallel one, as shown in Figure 1. All the
XOR gates in a target circuit were designed to have a balanced
rising and falling time, reducing the pulse shape change when
a transient passes. The testchip consists of 5 target strings with
different types of target cells, as indicated in Table 1. The first
target string consists of inverters with regular voltage threshold (RVT) devices. The second string is similar to the first one,
except the inverters are of a low voltage threshold (LVT). The
third and fourth target stings consist of NAND and NOR gate
respectively. The fifth target string consists of the same inverters as the first string, but PMOSs of the inverters were built
in separate N-wells. The pulse capture circuit had a wide measurement range of more than 1 ns and a resolution of ˙28.5 ps
at 23 ıC and ˙31.5 ps at 125 ıC, respectively.
The test chip was measured with monoenergetic heavy
ions at normal incidence with a fluence of 1 107 cm 2 . The
ions used and their linear energy transfers (LETs) are shown
in Table 2. The chip was irradiated with a core supply voltage
of 1.08 V at room temperature (23 ıC) and high temperature
(125 ıC) respectively. The temperature was controlled through
a resistive heater attached to the testchip package. Temperature
measurements were taken using a temperature sensor attached
to the package.
3. Results and discussion
This section contains the experimental results of the
testchip and an additional discussion of the results.
3.1. Dependence on device threshold voltage
The SET pulse widths observed in INV and INV_LVT
strings are shown in Figure 2. From Figure 2(a) we can see
that Cl ions induced more SETs in the INV_LVT string than
in the INV string, while the range of SET pulse widths are
the same between the two. Figure 2(b) represents the maximum, minimum and max-amount SET pulse widths (the pulse
width range in which the largest number of SET are located)
Figure 1. Target circuit configuration (inverter target as an example).
† Corresponding author. Email: yuesg9999@163.com
Received 11 June 2015, revised manuscript received 23 July 2015
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J. Semicond. 2015, 36(11)
Yue Suge et al.
Table 1. Different designs in target strings.
Design details
Target name
Logic
gate Device thresh- PMOS built
type
old voltage
in
INV
INV
Regular
Common Nwell
INV_LVT
INV
Low
Common Nwell
NAND
NAND
Regular
Common Nwell
NOR
NOR
Regular
Common Nwell
INV_sw
INV
Regular
Separate
N-well
Ion specy
Cl
Ti
Ge
Kr
Table 2. Ions used in this study.
Energy
LET
(MeV)
(MeVcm2 /mg)
160
13.1
169
21.8
210
37.3
479.8
37.6
Range (m)
46
34.7
30.5
58.5
at four different LETs. The distributions of SET pulse width
of the two strings are almost the same, except for the 500ps-long SET pulse observed in the INV_LVT at the LET of
37.6 MeVm2 /mg. It is reasonable to draw the conclusion that
the device threshold voltage of transistors does have an influence on the SET pulse width, as INV_LVT generate wider and
more SET.
The reason for the difference between two kinds of inverters is unclear at this point. Several factors could contribute to
this. A lower device threshold voltage would have an influence on the critical charge and restoring current. The process
of charge generation, propagation, and collection in a device
of LVT would be different from that in a device of RVT during
heavy ion striking. All the mechanisms would have a different influence on the SET pulse, strengthening or counteracting
each other. The detailed mechanism would be studied in future
work.
3.2. Dependence on temperature
Figure 3 shows the SET pulse width distribution of different logic gates for Ge irradiation at a temperature of 23 ıC
and 125 ıC, respectively. Both the SET number and SET pulse
width increase with the temperature for all logic gates tested.
Results of other ions show a similar trend that the pulse width
distribution shifts toward a higher value as the temperature increases.
The influence of temperature on different logic gates is
slightly different. The influence on NOR is most significant,
followed by INV and NAND. As Figure 3(c) shows, SETs
events (with a pulse width of about 252 ps) were measured at
the main peak of high temperature, compared with that of 23 ıC
with only 57 SET events (the pulse width is about 228 ps). Besides, the number of SETs locating in 378 ˙ 31.5 ps forms a
second peak with 96 SET events measured. At the INV string,
the peak of SET moves from 171 ˙ 28.5 ps at 23 ıC to 189 ˙
Figure 2. Comparison of SET pulse width of INV and INV_LVT
strings. (a) SET distribution as a function of pulse width when irradiated by Cl ions. (b) SET pulse width distribution at four different
LETs.
31.5 ps at 125 ıC and the number of SETs wider than 300 ps
mounts up largely at high temperature (Figure 3(a)). The number of short SETs in NAND around 100 ps increases and several
long SETs are observed (Figure 3(b)).
Previous researchers have found the net effect of temperature on the diffusion current resulting from a heavy ion strike
to be smallŒ4 . As a result, the increase in bipolar amplification
with temperature is the main contributor to the increase of SET
pulse widths. The two PMOSs in a series of NOR are both in
the off state during the P-hit SET event, which would make a
contribution to the bipolar amplification and result in a wider
SET pulse. The two off-state PMOSs also lead to a larger sensitive area, which has been reflected through the SET number.
3.3. Multi-peak phenomenon
An interesting phenomenon was observed through the experiment, which was different from the typical Gauss distribution that more than one peak was found in the SET pulse
width distribution (Figure 4). For example, the number of SETs
within the range of 256.5–313.5 ps and 370.5–427.5 ps overwhelm others in the NOR string, forming two peaks in distribution.
Test results showed that logic gate type, temperature and
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Figure 5. Box plot representing the minimum, maximum and maxamount SET pulse widths for four different LETs for INV and INV_sw
strings.
Figure 3. SET distribution observed in different logic gate strings for
Ge at different temperature. “_NT” stands for 23 ıC and “_HT” for
125 ıC. To simplify the x-axis, only the mean value is placed.
width range than the main one of itself. For LETs, the multipeak is obvious only at LETs higher than 37 MeVcm2 /mg.
The multi-peak phenomenon is aggravated heavily with the increase of the temperature (shown in Figure 3). The height of
the second peaks of the three test strings all grow largely to get
closer to the main one. What is more, the NOR is more affected
at high temperature, as the second peak of the NOR string overtakes the main one (Figure 3(c)). With the biggest increase of
both peaks, NOR shows the most significant multi-peak phenomenon at high temperature.
Normally, the SETs due to P-hit tend to be much longer
than those due to N-hit at higher LETs due to parasitic bipolar amplification of the collected chargeŒ5 . As the multi-peak
phenomenon can only be observed at high LET and is more
significant at high temperature, it would be caused by a parasitic bipolar amplification effect; the difference between the
structure of NOR, NAND and INV lead to different sensitivity
towards the parasitic bipolar effect.
3.4. Dependence on well separation
Figure 4. SET pulse width distribution of INV, NAND and NOR
strings when stricken by Kr. A second peak in the distribution exists
for all three logic gates.
LET all have influence on the multi-peak phenomenon. The
phenomenon is more significant, as shown in Figures 3 and 4,
in NOR than in other logic gates, and its second peak is comparatively higher than that of the others. Being different from INV
and NOR, the second peak of NAND appears at a lower pulse
Figure 5 shows the distribution of SET pulses widths for
INV and INV_sw, the PMOS of which are placed in separate
Nwells. The latter has a larger SET pulse width in general, and
the difference grows significantly as the LET becomes higher.
What is more, the max-amount SET pulse width of INV_sw
is about 100 ps larger than that of INV. The former studies
achieved a similar result to oursŒ6 .
In the common N-well design (INV chain), charge sharing was more prevalent because the transistors sat in the same
N-well allowing charge to diffuse more freely and affect the
adjacent PMOS. For the INV_sw, there is a P-substrate between the N-wells that hinders charge sharing between nearby
PMOS transistors; as more charge is induced by ions with
higher LET, the stricken PMOS in INV_sw is inclined to collect a larger amount of charge. While in the INV, more charge
induced would enhance charge sharing and lead to comparatively shorter SET pulses. It is reasonable to draw the conclusion that in this 65 nm bulk CMOS process, charge sharing
has contributed to the pulse quenching effect and results in a
smaller SET pulse width.
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3.5. Dependence on logic gate types
The distribution of SET pulse width for different logic
gates is shown in Figure 4. In general, heavy ions create wider
SETs in NAND and NOR gates than in INV at both room temperature and high temperature (Figure 3). The NOR tends to
generate wider as well as a larger amount of SET pulses; the
widest SET pulses measured are also observed in NOR.
As the sizes of counterpart transistors of the three logic
gates are the same and the two parallel connected transistors
in the NAND and NOR share a common drain, the sensitive
areas of three logic gates are the same. However, the driven
strength varies among INV, NAND and NOR. The weaker
driven strength takes NAND and NOR longer to recover from
ion strike, causing a wider pulse as a result. The difference of
distribution between N-hit and P-hit SETs would explain the
difference observed in NAND and NORŒ7 .
4. Conclusion
Heavy ion test results of a 65-nm SET pulse width testchip
have been given and analyzed. The multi-peak phenomenon
in the distribution of SET pulse width was first observed. The
phenomenon becomes more significant with increasing temperature and LET. The influence of various factors, including
device threshold voltage, temperature, logic gate type and well
separation on SET pulse width was studied. Low device threshold voltage leads to more SET events as well as wider SETs.
The SET pulse width is larger at high temperature for all the
logic gates tested. The SET distribution varies due to the different logic gate, among which NOR tends to generate wider
SETs. The SETs observed in a string with Nwell separation are
much wider than in a string without separation. Namely, charge
sharing contributes to the pulse quenching effect and results in
a smaller SET pulse width in this 65-nm bulk CMOS process.
The mechanism of the factors working on the SET pulse as well
as the mechanism responsible for the multi-peak phenomenon
would be studied in future works.
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