ISSN 2319-8885
Vol.03,Issue.42
November-2014,
Pages:8537-8542
www.ijsetr.com
A Wide-Range PLL using Self-Healing Prescaler/VCO in 65-nm CMOS
KRISHNA .M1, N. PRAVEEN KUMAR2
1
PG Scholar, Dept of ECE, Stanley Stephen College of Engineering & Technology, India,
Email: krishnachinna023@gmail.com.
2
Asst Prof, Dept of ECE, Stanley Stephen College of Engineering & Technology, India.
Abstract: The Variability and leakage current in nano scale CMOS technology may degrade the circuit performances
significantly. To accommodate the above issues in a wide-range phase-locked loop (PLL), a self-healing prescaler, a selfhealing voltage-controlled oscillator (VCO), and a calibrated charge pump (CP) are presented. This PLL is fabricated in a 65nm CMOS technology and its active area is 0.0182 mm2. For the self-healing VCO, its measured frequency range is from 60 to
1489 MHz. When this PLL operates at 855 MHz, the measured rms and peak-to-peak jitters are 8.03 and 55.6 ps, respectively.
The measured reference spur is -52.89 dBc. This PLL consumes 4.3 mW from 1.2 V supply without buffers.
Keywords: Leakage Current, Nano Scale CMOS Technology, Phased-Locked Loop (PLL).
I. INTRODUCTION
When a CMOS technology approaches to a nanometer
scale, the non-idealities [2], [3], such as variability and
leakage current, may significantly affect the circuit
performances. The process variability leads to the large
variations to degrade the device matching and performances.
It may result in only a few dies on a wafer to meet the target
performance specifications. The undesired leakage currents
also degrade the accuracy and resolution of analog circuits
and make digital dynamic circuits not to work properly [4],
[5]. For a pMOS transistor with W/L = 8 μm 0.06 μm in a 65nm process, its source and gate are connected to the supply
voltage of 1.2 V. Fig. 1(a) shows its simulated drain current
versus the drain voltage under different corners. The drain
current, i.e., leakage current, is 687 nA, 0.12 uA, and 21 uA
for the typical, slow-slow, and fast-fast corners, respectively,
and 400 C. The leakage current is highly dependent upon the
process variations. Fig. 1(b) shows the simulated drain
current under different corners and the temperatures with a
constant VSD = 1.2 V. The leakage current grows very fast in
a high temperature environment.
A phase-locked loop (PLL) is widely employed in wire
line and wireless communication systems. The poor device
matching and leakage current vary the common-mode
voltage of a ring-based voltage-controlled oscillator (VCO)
[6] over a wide frequency range. It may limit the oscillation
frequency range of a VCO and causes a VCO not to oscillate
in a worst case. To realize a wide-range PLL, the divider
following a VCO should operate between the highest and
lowest frequencies. When a PLL works at a higher frequency
which the static circuits cannot operate, dynamic circuits are
needed. A true-single-phase-clocking (TSPC) divider is
widely used to realize a prescaler for this PLL. A TSPC
prescaler must work over a wide frequency range to cover the
Fig.1. the simulated drain current versus (a) the drain
voltage and (b) temperature.
Copyright @ 2014 IJSETR. All rights reserved.
KRISHNA. M, N.PRAVEEN KUMAR
voltage. In frequency demodulation the PLL loop bandwidth
is wide, so that the VCO output frequency tracks the input
frequency but in phase demodulation PLL loop bandwidth is
narrow, so that the output frequency tracks the input carrier
frequency and output phase is the average of input phase. The
PLL output frequency can be either an integer or fractional
times of reference frequency by virtue of which frequency
locking in PLL used the integer-N or fractional-N divider.
Digital PLL generates a clock signal in synchronization with
the incoming signal. Receiver circuits use this clock signal to
provide clock to the shift register to recover the data. This
application of digital PLL is often termed a clock recovery
circuit or bit synchronization circuit. The clock and data
recovery based PLL is to synchronize the random data to a
clock signal generated by VCO in the PLL.
Fig.2.(a) Conventional divide-by4/5 dual-modulus prescaler using TSPC DFFs [8]. (b) Two kinds of
malfunctions occurred at A. (c) the malfunction occurred
at .
process and temperature variations. For a TSPC prescaler, the
undesired leakage currents may limit its frequency range or
alter the original states of the floating nodes to have a
malfunction. The leakage current and current mismatch in a
charge pump (CP) will degrade the reference spur and jitter
significantly. To mitigate the above problems, a self-healing
divide-by-4/5 prescaler and a self-healing VCO are presented
in this paper. A time-to-digital converter (TDC) and a 4-bit
encoder are used to quantize the phase error and digitally
calibrate the CP. This paper is organized as follows. Section
II introduces PLL-FS System. Section III describes the
Circuit Description. The experimental results are given in
Section IV and the conclusion is given in Section V.
II. PLL-FS SYSTEM
Frequency generator is at the heart of every transmitter and
receiver. Digital control and phase-locked loop frequency
synthesis are such a perfect fit it is hard to imagine any
modern frequency agile/fast oscillator without phase lock
control. Analog frequency demodulation uses the basic PLL.
Their demodulated signal is actually the VCO control
In design of direct analog synthesizer (DAS) is realized by
cascading stages of frequency multipliers, dividers, mixers
and band-pass filters (BPF). It generates large number of
separate frequencies from a single reference and rapidly
switched between any set of frequency. Many manufactures
used this design and they report that excellent phase noise
and spurious performance at desired frequency but its sheer
size and power consumption make this synthesizer to limited
application in1960’s. To improve the signal band and reduce
power consumption direct digital synthesizer was presented
in early 1970’s. It has two major components numerically
controlled oscillator (NCO) and a digital to analog converter
(DAC). NCO consists of an adder-register pair (phase
accumulator) and a ramp to sine wave lookup ROM. It
provides a low frequency output with extremely high
resolution and excellent frequency switching speed. But due
to sampling theory DDS can only generate frequency up to
maximum of half of the clock rate of the digital circuit and it
has also high spurious content caused by quantization and
linearity limitation of the DAC. Here a rough rule of thumb is
that the spurious level generated by DAC quantization equals
6dB times the number of input bits.
For large frequency DDS can’t be efficient due limitation
of DAC. In 1990’s integer-N and fractional-N PLL frequency
synthesizer is introduced. It generates frequency in GHz with
robust system. Integer-N PLL consists of phase-frequency
detector (PFD), a charge pump (CP), a loop filter, a voltage
controlled oscillator (VCO), and a programmable frequency
divider. Its output frequency is integral multiple or loop
frequency divider ratio of reference frequency. The
frequency resolution of this synthesizer is equal to reference
frequency. It causes large lock time. Their reference spur and
its harmonic will be located at low offset frequency. For large
frequency, divider ratio also large and causes in-band phase
noise associated with the reference signal. So with low loop
band width, phase noise at low off set frequencies can’t
sufficiently suppress. It required a large loop band width.
To increase the loop band width with same reference
frequency Fractional-N PLL frequency synthesizer is used, it
also overcome the defect and full fill deficiency of
Fractional-N PLL synthesizer. Here frequency divider can be
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.42, November-2014, Pages: 8537-8542
A Wide-Range PLL using Self-Healing Prescaler/VCO in 65-nm CMOS
fractional and a large reference can be used to achieve a
C. Time to Digital Converter
small frequency resolution. However to design the fractional
A time to digital converter (TDC) converts the time it has
divider dual –modulus or multi modulus technique is used
occurred into digital output. TDC depends on phase and a
which have a fixed pattern and it cause unwanted lowfrequency value of PFD. TDC has a 4 bit encoder.
frequency spur. Practically fractional-N synthesizer can’t
D. Loop Filter
suppress in-band spur at negligible level but in literature five
The loop filter’s key function is to filter the interference
main spur reductions techniques are addressed such as DAC
signal. It determines the changes in the reference frequency,
phase estimation, Random jittering, ΣΔ noise shaping, phase
changes of the feedback. It describes the range of the loop to
interpolation and pulse generation. To avoid the large
achieve the lock i.e. lock range or capture range and how
division ratio in an integer-N PLL synthesizer, one
long it will communicate i.e. lock time.
alternative is to use multiple loops to reduce the division
ratio. Dual-loop PLL is frequently used to improve the
E. Self-healing VCO
tradeoff among phase noise, channel spacing, reference
A Self-healing VCO is the most important functional unit
frequency and the locking speed. PLL1 is used to generate
in the PLL which reduces unwanted switching activities of
reference frequencies for PLL2 and PLL1 output is uptransistors in the circuit and achieves a wide tuning range and
converted by PLL2 and a single-sideband (SSB) mixer. PLL1
consumes low power. It reduces oscillation frequency range
generates tunable IF frequencies, while PLL2 generates a
and offers a significant reduction in power dissipation.
fixed RF frequency. Mixer is used to reduce the divide ratio
1. Self-healing VCO with alpha latch
in PLL1.
A Self-healing VCO is designed by an alpha latch, selfRecent works used the dual-loop PLL topology for GSM
bias buffer, a bottom level detector, and a current
receivers. The drawback of the dual-loop PLL is that it may
compensator is shown in Fig.3. A Self-bias buffer (SBB) is a
require two references, and at least one SSB mixer, which
circuit which generates a single output from two different
might introduce additional phase noise. For overcome the
inputs. It expands the output of a VCO. The bottom-level
effect of phase noise in system Delay Lock Loop frequency
detector in self-healing VCO may reduce the wastage of
synthesizer is introduced. It has no phase accumulation and
power and increases the tuning range of PLL, hence
extremely low phase noise can be achieved but the big
consumes low power. A Current Compensator protects the
drawback of the DLL frequency synthesizer is that it is not
device from thermal variations in its operating point. The
programmable. Other problems, such as limited
objective is to provide circuitry for compensating thermal
multiplication factor and high power consumption also limit
variations in the current so that the voltage drop across a
its application. At present time a mixed signal frequency
circuit input of the transistor is due substantially only to the
synthesizer is more popular and many systems incorporate a
input signal.
mixture or hybrid of these basic approaches in order to take
advantage of the benefits of increased speed or improved
resolution that one approach may have over another.
Sometimes a PLL synthesizer may incorporate a DDS in its
reference circuitry to increase resolution or to reduce
switching time. A major drawback of this approach is that the
PLL acts as a multiplier on any phase noise or spurs and a
DDS may have high spurs. The resulting noise at PLL output
can seriously degrade system performance.
III. CIRCUIT DESCRIPTION
A. Phase Frequency Detector
A phase frequency detector (PFD) is device which
compares the phase of reference and feedback signals. The
phase difference between the reference signal and feedback
signal of the PFD is proportional to the output signal, which
describes about the adjustment of lock onto the phase.
B. Lock Detector
The lock detector (LD) works on the aspect of Lock range
concept. It compares the frequencies of reference and
feedback signals. Input will reach lock detector fast. The
phase and frequency from PFD must yet to reach TDC.
Frequency mismatch may occur and increases critical delay
which may degrade the performance of the circuit. Hence it is
designed with inverters to delay the process. The most
significant bit of reference signal is given to TDC.
Fig.3. Self-healing VCO with alpha latch, bottom level
detector and current compensator.
F. Frequency divider
A Frequency divider is a circuit which compresses the
frequency hence it increases the speed by reducing the delay
of the process. It consists of a multiplexer, modulus control,
D flip flop (fig 4).
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.42, November-2014, Pages: 8537-8542
KRISHNA. M, N.PRAVEEN KUMAR
G. Phase-locked loop
(a) the self-healing circuit disabled, and (b) the selfA phase-locked loop (PLL) produces an output signal
healing circuit enabled. (Upper trace: Input; Lower
whose phase is related to input (reference) signal’s phase.
trace: Output).
This PLL consists of a phase-frequency detector (PFD), a
The active area occupies 0.0182 mm2. External capacitors
Charge Pump (CP), a Lock detector (LD), a time to digital
are adopted in the loop filter for this work. The measurement
converter (TDC), an encoder, a self-healing VCO, a
results are discussed as follows.
frequency divider, and a filter. The block diagram of
proposed PLL is shown in the Fig.5. The PFD generates an
A. Self-Healing Divide-by-4/5 Prescaler
output signal by comparing the phases of two input signals.
An additional self-healing divide-by-4/5 prescaler is
The LD works on lock range concept and turns on the TDC
configured
as a divde-by-5 divider. When the self-healing
with an encoder when the PLL locks. The digital code of the
function
is
disabled, this divide-by-5 divider works
TDC is used to calibrate the charge pump. Phase-locked loop
incorrectly
for
an input clock of 150 MHz at 100 C as shown
is broadly used in real time application.
in Fig.6 (a). With the self-healing function is enabled, this
divide-by-5 divider works correctly for an input clock of 150
MHz at 100 C as shown in Fig. 6(b). The operation frequency
ranges of this divde-by-5 divider versus temperature are
summarized in Fig. 7 with and without the self-healing
function, respectively.
Fig.4. A Frequency divider.
Fig.7. Measured frequency range of this divide-by-4/5
prescaler under different temperatures.
Fig.5. Block diagram of proposed PLL.
IV. EXPERIMENTAL RESULTS
This chip is fabricated in a 65-nm CMOS technology.
The die photo is shown in Fig.6.
Fig.6. Measured divide-by-5 output for a divide-by-4/5
prescaler with an input clock of 150 MHz at 100 C, when
B. Self-Healing VCO
Fig. 8(a) shows the simulated tuning ranges of a VCO with
and without the self-healing technique at different
temperatures. The self-healing VCO achieves a wide tuning
range. Fig. 8(b) shows the measured VCO’S transfer curves
with and without the self-healing technique, respectively, at a
room temperature. Without the self-healing function, the
measured frequency range of this VCO is from 105 to 950
MHz. With the self-healing function, the measured frequency
range of this VCO is improved and it is from 60 to 1489
MHz. To extend the tuning range of a VCO, a higher gain of
the VCO is adopted. However, the phase noise or jitter will
be degraded. Assume the current of a VCO is increased to
achieve the same tuning range 60–1489 MHz of a selfhealing one. The power difference for these two VCOs with
and without the self-healing technique is 1.152 mW at 60
MHz. Because of this self-healing technique, the active area
of the proposed VCO will be increased. Additional active
devices lead to a degradation of the jitter performance for a
self-healing VCO, compared to a VCO without a self-healing
technique.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.42, November-2014, Pages: 8537-8542
A Wide-Range PLL using Self-Healing Prescaler/VCO in 65-nm CMOS
Fig.10. (a) Measured spectrum and jitter @ 120 MHz and
1000 C, and (b) The measured spectrum and jitter @ 1320
MHz and 1000 C.
TABLE I: SUMMARY AND COMPARISON
Fig.8. (a) Simulated tuning ranges of a VCO with and
without the self-healing technique at different
temperature and (b) the measured transfer curve of a
VCO with and without the self-healing technique at a
room temperature.
C. Phase-Locked Loop
This PLL is configured with the reference frequency of 15
MHz and the output frequency of 855 MHz. When the selfhealing prescaler/VCO and the TDC/encoder are disabled,
the measured spectrum and jitter are shown in Fig. 9(a). The
measured reference spur is -33.42 dBc. The measured rms
and peak-to-peak jitters are 43.62 and 284.4 ps, respectively.
When the self-healing prescaler/VCO and the TDC/encoder
are enabled, the measured spectrum and jitter are shown in
Fig. 9(b). The measured reference spur is -52.89 dBc. The
measured rms and peak-to-peak jitters are 8.03 and 55.6 ps,
respectively. This PLL consumes 4.3 mW from 1.2 V supply
Fig.9. Measured spectrum and jitter at 855 MHz (a)
without and (b) with the self-healing rescaler/VCO and
the TDC/encoder.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.42, November-2014, Pages: 8537-8542
KRISHNA. M, N.PRAVEEN KUMAR
without buffers. Without the proposed self-healing
IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1568–1571,
techniques, this PLL did not work at 1000 C. When a selfOct. 1998.
healing prescaler, a self-healing VCO, and a calibrated CP
[9] P. Dudek, S. Szczepanski, and J. Hatfield, “A highare turned, the measured spectrum and jitter for this PLL
resolution CMOS time-to-digital converter utilizing a vernier
operating at 120 and 1320 MHz and at 100 C are shown in
delay line,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp.
Fig.10(a) and (b), respectively. Fig.10 (a) shows the
240–247, Feb. 2000.
measured reference spur is -40.97 dBc. The measured rms
[10] C. N. Chuang and S. I. Liu, “A 1 V phase locked loop
and peak-to-peak jitters are 57.71 and 422 ps, respectively.
with leakage compensation in 0.13 m CMOS technology,”
Fig. 10(b) shows the measured reference spur is -41.2 dBc.
IEICE Trans. Electron., vol. E89-C, pp. 295–299, Mar. 2006.
The measured rms and peak-to-peak jitters are 7.02 and 52.4
[11] C. C. Hung and S. I. Liu, “A leakage-suppression
ps, respectively. Table I gives the performance summary of
technique for phase locked systems in 65 nm CMOS
the proposed PLL and other works in literature. The proposed
technology,” in Proc. IEEE Int. Solid-State Circuits Conf.,
presents several techniques to avoid the circuits to degrade by
2009, pp. 400–401.
the process variability and leakage current in nano scale
CMOS technology. Due to additional active devices, the jitter
performance of a self healing PLL will be degraded,
compared to a PLL without a self-healing technique. In
addition, the active area and power of this PLL will be
increased because of these self-healing circuits.
V. CONCLUSION
A wide-range PLL is fabricated in a 65-nm CMOS
process. To deal with the process variability and leakage
current in nano scale CMOS process, a self-healing prescaler,
a self-healing VCO, and a calibrated CP are presented.
Experimental results are given to demonstrate the feasibility.
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International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.42, November-2014, Pages: 8537-8542