University of Florida
ECE Department
Joel D. Schipper
Summer 2007
LECTURE #8.5: Open Collector Gates
EEL 3701: Digital Logic and Computer Systems
Based on lecture notes by Dr. Eric M. Schwartz
Open Collectors:
***Never Connect Chip Outputs Together in the Laboratory***
-There are two types of logic chips where you may connect outputs:
-Tri-state buffers: Enables must be carefully controlled (see Lecture 08)
-Open Collector (O.C.) Logic Gates
-Your lab kit contains neither of these
***Never Connect Chip Outputs Together in the Laboratory***
-Transistor-Transistor Logic (TTL) uses bipolar junction transistors (BJT’s)
5V
OUTPUT
COLLECTOR
INPUT
BASE
EMITTER
Simple Inverter Circuit w/ BJT
-An input of 5V creates a short between collector and emitter (0V output)
-An input of 0V creates an open circuit between collector and emitter (5V output)
-What is this? An inverter.
-Open collector chips have no internal pull-up resistor
-You must add the resistor
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University of Florida
ECE Department
Joel D. Schipper
Summer 2007
-Usually, a vertical bar at the output is used to represent O.C. gates
-Sometimes the gate is simply labeled with the letters “O.C.”
Case 1: Active-High I/O Viewpoint (i.e. Z1, Z0, and Znet are active high)
If Z1 AND Z0 are high => Znet is high
Z net ( H ) = Z 1 ( H ) ⋅ Z 0 ( H )
Known as “wired AND”
“Wired AND” Representation
Case 2: Active-Low I/O Viewpoint (i.e. Z1, Z0, and Znet are active low)
If Z1 OR Z0 is low => Znet is low
Z net ( L) = Z 1 ( L) + Z 0 ( L)
Known as a “wired OR”
“Wired OR” Representation
Note: DeMorgan’s Law shows the two representations to be equivalent.
Note 2: Our figures show 4 inputs, but any number of inputs is allowable.
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University of Florida
ECE Department
Joel D. Schipper
Summer 2007
Example: Determine the equations for the following circuit where:
1) The output is active high
2) The output is active low
5V
A(L)
Z1
B(H)
C(H)
Z0
D(L)
Case 1: Output is active high
Z1 ( H ) = A B
Znet
Z net ( H ) = Z 1 ⋅ Z 0
Z net ( H ) = A B ⋅ (C + D )
Z 0 (H ) = C + D
Case 2: Output is active low
Z 1 ( L) = A B
Z net ( L) = Z 1 + Z 0
Z net ( L) = A B + (C + D )
Z 0 ( L) = C + D
Note: Because active high is the complement of active low, Z net ( H ) = Z net ( L) .
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