58
CHAPTER 4
MODIFIED H- BRIDGE MULTILEVEL INVERTER
USING MPD-SPWM TECHNIQUE
4.1
INTRODUCTION
Conventional voltage source inverter requires high switching
frequency PWM technique to obtain a quality output voltage with a minimum
amount of ripple content. These inverters have some limitations in operating
at high frequency mainly due to switching losses and constraints of device
ratings. This chapter presents a new topology of multilevel inverter with less
number of switching devices. Operation of the modified H-bridge inverter is
presented in section 4.2. Modified Phase Disposition Sinusoidal Pulse Width
Modulation (MPD-SPWM) technique is
explained in
section 4.3.
Performance parameters of the multilevel inverters are given in section 4.4.
MATLAB/Simulink model of three phase modified H-bridge multilevel
inverter with equal DC source is presented in section 4.5. Performance
parameters are analysed for three phase modified H-bridge multilevel
inverter.
4.2
PROPOSED
MODIFIED
H-BRIDGE
MULTILEVEL
INVERTER TOPOLOGY
Modified H-bridge multilevel inverter topology separates the
output voltage into two parts. One part is named as level generation part and
it is responsible for generating levels. The other part is called as polarity
59
generation part and it is responsible for generating the polarity of the output
voltage. Positive levels are generated by the level generation part and the
output of this part is fed to the polarity generation part in order to generate a
complete multilevel output voltage. This will eliminate many of the
semiconductor switches which were responsible to generate the output
voltage levels in positive and negative polarities.
Figure 4.1 Proposed modified H-bridge seven level inverter topology
The new multilevel inverter topology for seven levels is shown in
Figure 4.1. It requires ten controlled power semiconductor switches and three
equal isolated DC sources for the generation of seven level output voltage.
Polarity generation part transfers the required output level to the load with the
same direction or opposite direction. It reverses the voltage direction when
the voltage polarity is required to be changed.
60
It has modular structure and it can be extended to higher levels by
adding the middle part (Vdc, S3, & S6) of level generation part. Modified
H-bridge multilevel inverter topology with h number of equal DC sources
generates the output voltage levels (NL) and maximum output voltage as per
the Equations (4.1) and (4.2). This inverter has less number of switches when
compared with the standard cascaded H-bridge multilevel inverter. Hence, it
is advisable to suggest this topology to replace the existing multilevel
inverters in the industries.
4.2.1
NL= 2h+1
(4.1)
Vomax = hVdc
(4.2)
Number of Components
Cost of the switching device is directly proportional to the
switching frequency. So high switching frequency devices and its driver
circuits are very expensive than low switching frequency devices. As the
number of high frequency components is increased, the reliability of the
inverter is decreased. Number of components in the system is indirectly
proportional to the reliability of the system as per the MIL-HDBK-217F
standard. Switching components required for different multilevel inverters are
given in Table 4.1.
61
Table 4.1
Comparison of switching components for different multilevel
inverter topologies
Inverter type
Flying
Cascaded
Proposed
NPC
capacitor H-bridge
Modified HMultilevel
Multilevel Multilevel bridge Multilevel
Inverter
Inverter
Inverter
Inverter
Main Switches
6(NL-1)
6(NL -1)
6(NL -1)
3((NL -1)+4)
Main diodes
6(NL -1)
6(NL -1)
6(NL -1)
3((NL -1)+4)
0
0
0
(NL -1)
3(NL -1)/2
3(NL -1)/2
0
0
Clamping Diodes
DC bus Capacitors
/isolated supplies
Flying capacitors
3(NL -1)
(NL -2)
(NL -1)
0
3/2 (NL -1)
( NL -2)
Switching components required for different levels are compared
with the modified H-bridge multilevel inverter which is shown in Figure 4.2.
Modified H-bridge multilevel inverter requires fewer components compared
with the conventional multilevel inverters. Thus the reliability of this
multilevel inverter is highly improved and expenses associated with this
system are less. It can be extended to any number of levels as other
topologies. It is clear that the modified H-bridge multilevel inverter uses less
number of devices. Number of components required decreases tremendously
for higher levels.
TOTAL NUMBER OF COMPONENTS
62
1000
900
800
700
600
500
400
300
200
100
0
NPC
FC
CMLI
5
7
9
11
13
15
17
NPC
88
168
272
400
552
728
928
FC
CMLI
70
123
188
265
354
455
568
54
81
108
135
162
189
216
MHMLI
54
69
84
99
114
129
144
MHMLI
LEVELS
Figure 4.2
4.2.2
Comparison of the proposed modified H- bridge multilevel
inverter with the conventional multilevel inverters for
different levels
Switching Sequences
Switching sequences for this proposed multilevel inverter are easier
than its conventional topologies. Full bridge converter reverses the output
voltage. So, it does not require generating negative pulses for negative cycle.
Required level is produced by the level generation part of the inverter. Then
this level is translated to negative or positive according to output voltage
requirements. The switching sequences for the positive levels are shown in
Figure 4.3. This topology is redundant and flexible in the switching sequence.
63
Figure 4.3 Switching sequences for positive levels
By considering the minimal switching transitions during each
levels, the switch sequences (2-3-4), (2-3-5), (2-6-5) and (1-5) are chosen for
0,1,2,3 positive levels respectively. Seven levels of output voltage are
generated as follows.
1)
Zero level output: This level can be produced by two
switching combinations, controlled switches S2, S3, S4, S8 and
S9 are ON or controlled switches S2, S3, S4, S7 and S10 are ON
and all other controlled switches are OFF. Load terminals are
short circuited and the voltage applied to the load terminals
are zero.
64
2)
One-third level positive output (Vdc): The controlled switches
S2, S3 and S9 are ON, connecting the load positive terminal to
the lower DC source Vdc, and controlled switches S8, S5 are
ON, connecting the load negative terminal to ground. All
other controlled switches are OFF. Voltage applied to the load
terminal is Vdc.
3)
Two-third level positive output (2Vdc): The controlled
switches S2, S6, S9 are ON, connecting the load positive
terminal to upper DC sources, and the switches S8, S5 are ON,
connecting the load negative terminal to ground. All other
controlled switches are OFF. Voltage applied to the load
terminal is 2Vdc.
4)
Maximum positive output (3Vdc): The controlled switches S1,
S9 are ON, connecting the load positive terminal to all DC
sources and the controlled switches S8, S5 are ON, connecting
the load negative terminal to ground. All other controlled
switches are OFF. Voltage applied to the load terminal is
3Vdc.
5)
One -third level negative output (-Vdc): The controlled
switches S2, S3 and S7 are ON, connecting the load negative
terminal to lower DC source Vdc and controlled switches S10,
S5 are ON, connecting the load positive terminal to ground.
All other controlled switches are OFF. Voltage applied to the
load terminal is -Vdc.
6)
Two-third level negative output (-2Vdc): The controlled
switches S2, S6, S7 are ON, connecting the load negative
terminal to upper DC sources, and the switches S10, S5 are
ON, connecting the load positive terminal to ground. All other
controlled switches are OFF. Voltage applied to the load
terminal is -2Vdc.
65
7)
Maximum negative output (-3Vdc): The controlled switches
S1, S7 are ON, connecting the load negative terminal to all DC
sources, and the controlled switches S10, S5 are ON,
connecting the load positive terminal to ground. All other
controlled switches are OFF. Voltage applied to the load
terminal is -3Vdc.
The efficiency of the overall multilevel inverter is also decided by
the number of switches that conduct current. The conventional seven level
cascaded inverter requires twelve switches and in each instance, six switches
conduct the current. In the proposed topology, the number of switches that
conduct current varies from four to five switches, out of which two switches
are from the polarity generation part. Therefore the number of switches that
conduct current in the topology is lesser compared with the conventional
topology. Hence, it has better efficiency and reliability.
Producing gating signal for the polarity generation part is simple
and is synchronous with line frequency. Fundamental switching frequency
scheme is used to generate the switching pulse for the polarity generation
part. Low frequency H-bridge inverter operates in forward and reverse modes
to generate polarity. Switches S8 and S9, conduct in forward mode to generate
positive direction. Switches S7 and S10, conduct in reverse mode to generate
negative direction.
4.3
MODIFIED PHASE DISPOSITION SINUSOIDAL PULSE
WIDTH MODULATION
Modified SPWM technique is introduced to generate the switching
signals. It requires half of the conventional carriers for SPWM controller.
SPWM technique for conventional cascaded H-bridge seven level inverter
requires six carriers. Three carriers are sufficient for the modified topology.
66
Proposed multilevel inverter generates only positive polarity whereas the
negative levels are generated by the polarity generation part. Pulses for the
switching devices are generated by comparing the reference and three carrier
signals, which are shown in Figure 4.4. Three triangular carrier signals are
compared with an unidirectional sinusoidal reference signal. The carrier
signals have the same frequency and amplitude and are in phase.
Figure 4.4 Carrier and reference waveform for MPD-SPWM
Carriers in this method do not have any coincidence and they have
definite offset from each other. If the reference signal exceeds the lowest
carrier (Carrier A), middle carrier (Carrier B) is compared with the reference
signal until it exceeds the peak amplitude of the middle carrier signal. Then
the reference signal is compared with the highest carrier (Carrier C) until it
reaches zero. It is possible to generate six switching patterns for switches
S1 to S6. Pulses for the polarity generation part are generated with the line
frequency of 50 Hz.
67
4.4
PERFORMANCE PARAMETERS
The output of the multilevel inverter contains undesirable
harmonics and the quality of the multilevel inverter is normally evaluated in
terms of several distortion criteria and the performance parameters.
Concerning to voltage and current harmonics amplitudes, the parameter used
in the comparative analysis is Harmonic Factors of nth harmonic (HFn), Total
Harmonic Distortion (THD), Distortion Factor (DF), Weighted Total
Harmonic Distortion (WTHD) and Lowest Order Harmonics (LOH)
(Muhammed Rashid 2003).
4.4.1
Harmonic Factor of nth Harmonic
The harmonic factor of the nth harmonic which is a measure of
individual harmonic contribution is in Equation (4.3).
HFn
Vn
V1
for n > 1
(4.3)
where V1 is the rms value of the fundamental component and Vn is the rms
value of the nth harmonic component.
4.4.2
Total Harmonic Distortion
Total harmonic distortion is a measure of closeness in shape
between a waveform and its fundamental component and is given in
Equations (4.4) and (4.5).
THD
THD
1
V1
1
I1
1/ 2
Vn
2
(4.4)
n 2,3
1/2
In
n 2,3
2
(4.5)
68
In expressions (4.4) and (4.5), V1, I1 and n are the fundamental
voltage, current and harmonic order respectively. According to standards on
harmonic distortion the summation operator is evaluated from n=2 to the
harmonic order considered by a specific requirement. THD formula in (4.4)
assumes that there is no DC content in the output voltage.
Linear loads like resistor, inductor and capacitor do not create new
harmonic frequencies. In nonlinear loads, inter-modulation products cause
new harmonic and sub-harmonic components that are added in the spectrum
by superposition. THD value of a voltage signal can be very different from
that of a current signal. This means that harmonic current and harmonic
voltages must be measured individually for the nonlinear loads.
4.4.3
Distortion Factor
THD gives the total harmonic content but it does not indicate the
level of each harmonic component. Higher order harmonics would be
attenuated more effectively when a filter is used at output of the inverters.
Knowledge of both the frequency and magnitude of each harmonic is
important. The DF indicates the amount of harmonic distortion that remains
in a particular waveform after the harmonics of that waveform have been
subjected to a second order attenuation (divided by n2). Thus, DF is a measure
of effectiveness in reducing unwanted harmonics without having to specify
the values of a second order load filter and is defined by Equation (4.6).
DF
1
V1
n 2,3
Vn
n2
2 1/2
(4.6)
The DF of an individual or nth harmonic component is given in
Equation (4.7).
69
DF
4.4.4
Vn
V1n 2
for n > 1
(4.7)
Weighted Total Harmonic Distortion
Weighted total harmonic distortion is superior to THD as a figure
of merit for a non-sinusoidal inverter waveform in which lower portion of the
frequency spectrum is weighted heavily, accurately portraying the expected
harmonic current of an inductive load. The WTHD uses spectral weighting
factor and it is calculated using (4.8). WTHD is usually preferred for the
highly inductive loads such as induction or synchronous machines.
50
WTHD
4.4.5
n 2,3
Vn
n
2
V1
(4.8)
Lowest Order Harmonic
LOH is the harmonic component whose frequency is closest to the
fundamental one and its amplitude is greater than or equal to 3% of the
fundamental component. All the above distortion criteria are used to validate
the results concerning with harmonic performance.
4.5
SIMULATION STUDY
Simulation of modified H-bridge multilevel inverter is done using
MATLAB/Simulink environment. Simulation diagram of a three phase
modified H-bridge seven level inverter is shown in Figure 4.5. The IGBT
switches are used as switching devices because of their lower switching loss
and smaller snubber circuit requirement. All the switches used in the
simulation are considered to be ideal. The frequency of output voltage is
50Hz. The DC voltage sources used in this topology are equal in magnitude.
70
The single phase structure of modified H-bridge seven level inverter is
presented in Figure 4.6.
Figure 4.5
Simulation diagram of the three phase modified H-bridge
seven level inverter using MPD-SPWM
Figure 4.6
Subsystem of three phase modified H-bridge seven level
inverter for phase A
71
This topology consists of level generation part and polarity
generation part. In this modified inverter, only ten switches are required to
obtain the seven level output voltage for each phase. More switches are
required to achieve the same output voltage in the symmetric type where
equal DC sources are used. MPD-SPWM is applied to the proposed topology.
Level generation part uses high switching frequency to generate required
levels. Polarity generation part requires fundamental switching frequency to
generate required polarity in modified H-bridge seven level inverter.
Figure 4.7 Simulation circuit of level generation part
Simulation circuit of level generation part is shown in Figure 4.7.
Six semiconductor switches and three equal DC sources are used in the level
generation part. The simulation parameters of the modified three phase seven
level inverter are furnished in Table 4.2.
72
Table 4.2
Simulation parameters of the proposed modified H-bridge
seven level inverter using MPD-SPWM
Description
Parameter
Value
DC Supply
DC Voltage Sources(Vdc)
107 V
Level Generation Part
Switching Frequency
5 kHz
Polarity Generation Part
Switching Frequency
50Hz
Rated Voltage
400V
Rated Current
10A
Rated Power
5.4HP(4.03KW)
Rated Speed
1430rpm
Three phase Squirrel cage
Rated Torque
26.9 N-m
induction motor Load
Stator Resistance
1.405
Rotor Resistance
1.395
Number of Poles
Moment of Inertia (J)
Friction co-efficient (B)
4
0.0131 kg.m2
0.002985 N-m-s
The switching patterns for MPD-SPWM are produced by
comparing three carrier signals against the unidirectional sinusoidal reference
signal. This comparing process produces switching signals for switches S1 to
S6. Switching frequency used for these switches is 5000 Hz. Fundamental
switching frequency is used to produce the switching pulses for switches S7 to
S10. The value of fundamental switching is 50 Hz. The switches connected in
the same arm of the H-bridge should not be turned ON at the same time. So
that the switches S7, S10 are turned ON at the positive half cycle and the
switches S8, S9 are turned ON at the negative half cycle. These switching
pulse waveforms are shown in Figure 4.8.
73
(a) Switching pulse waveform for switches S1-S6
(b) Switching pulse waveform for switches S7-S10
Figure 4.8
Switching pulse waveforms of seven level inverter using
MPD-SPWM
74
Figure 4.9
Three phase voltage waveform of level generation part using
MPD-SPWM
Figure 4.10 Three phase voltage waveform of modified H-bridge seven
level inverter using MPD-SPWM
75
The simulation results of level generation part are shown in
Figure 4.9. Three positive levels such as 107 V, 214 V and 321 V are
generated using level generation part. Switching frequency of 5000 Hz is used
in this level generation part. Output of the level generation part is fed to the
polarity generation part to produce the desired seven level output voltage.
Switching frequency of 50 Hz is used in the polarity generation part.
Simulation results of phase voltage are shown in Figure 4.10. It can be seen
that each phase is phase shifted by 120o. Seven levels of output voltage are
generated using the modified multilevel inverter. It can be shown that from
the Figure 4.10, semiconductor switches in the modified topology which uses
modified MPD-SPWM scheme is turned ON and OFF many times.
Figure 4.11 Phase current waveform of seven level inverter using
MPD-SPWM
Stator current of the induction motor when it is fed by three phase
modified H-bridge seven level inverter using MPD-SPWM scheme is given in
Figure 4.11. From Figure 4.10 and Figure 4.11, it is clear that the output
current waveform is smoother than the output voltage waveform. It is evident
76
from Figure 4.11 that the currents fluctuate upto 0.1 sec and after that they
reach a constant value. The extremely high value of current at the starting
points of the simulation is due to the fact that before rotor gains some speed,
the motor acts like a transformer with short circuited secondary winding. The
fluctuations in the stator and rotor current values die out at about 0.15 sec and
the currents reach a fairly constant value at the full speed of 1430 rpm.
Figure 4.12 Electromagnetic torque of induction motor fed by modified
H-bridge seven level inverter
Electromagnetic torque characteristic of the induction motor when
supplied by three phase modified seven level inverter using MPD-SPWM
method is shown in Figure 4.12. Torque has an oscillating characteristic at the
starting instant. A nearly constant electromagnetic torque is obtained after a
time of 0.3 sec. It is observed that as the stator currents settle to a constant
value the electromagnetic torque also attains a fairly constant value. It is seen
that the torque has more oscillations while using this scheme. Torque attains a
mean value of about 26.9N-m at steady state.
77
Rated speed of 1430 rpm is reached at 0.3 sec. The speed curve
shows that the motor is started from stall and very quickly reaches its rated
speed of about 1430 rpm at 0.3 sec. The speed then settles down to a fairly
constant value at its rated speed. Observation also shows that the stator
current is quite noisy. The noise introduced by the inverter is also observed in
the electromagnetic torque waveform shown in Figure 4.12. However the
motor inertia prevents this noise from appearing in the motor speed
waveform.
(a) Rotor Speed at no load
(b) Rotor Speed at 50% of full load
78
(c) Rotor Speed at full load
Figure 4.13 Rotor Speed of induction motor fed by modified H-bridge
seven level inverter
Torque applied to the three phase induction motors are gradually
increased from no load to full load. Induction motors operated with no load
have low power factor and also consumes more reactive power. So in the
industries, induction motors are always operated with load. The speed
characteristic of the induction motor fed by modified H-bridge seven level
inverter is shown in Figure 4.13.
THD of the inverter is determined from the line voltages. The
simulation result of line voltages and their corresponding harmonic spectrum
of modified inverter fed by MPD-SPWM are presented in Figures 4.14 and
Figure 4.15. From the harmonic analysis shown in Figure 4.15, it is observed
that the magnitudes of lower order harmonics are very low and the
magnitudes of higher order harmonics are nearly equal to zero. From the
harmonic analysis of line voltage waveform, it is seen that the triplen
harmonics get cancelled automatically in three phase system. It also shows
that the THD content of line voltages are 0.34%, 0.37% and 0.37%
respectively. These numerical values are found to be minimum and within the
79
permissible limit of 5% as per IEEE 519 standard. Settling time of the three
phase induction motor operating at different loading is given in Table 4.3.
From the table 4.3, it is observed that the settling time increases with load.
Table 4.3 Settling time of modified H-bridge seven level inverter fed
induction motor for different loading conditions
Load
Settling Time
No load
0.2s
50% of full load
0.25s
Full load
0.3s
Figure 4.14 Line voltage waveform of modified H-bridge seven level
inverter using MPD-SPWM
80
(a) Harmonic analysis of line voltage VAB
(b) Harmonic analysis of line voltage VBC
(c) Harmonic analysis of line voltage VCA
Figure 4.15 Harmonic analysis of line voltages for modified H-bridge
seven level inverter using MPD-SPWM
81
The simulation results of line current and their corresponding
harmonic spectrum of the modified inverter, when fed by MPD-SPWM
scheme are presented in the Figure 4.16 and Figure 4.17. From the
normalized harmonic analysis shown in Figure 4.17, it can be seen that the
magnitude of low order harmonics are minimized and the magnitude of
higher order harmonics are equal to zero. From the harmonic analysis of line
current waveform, it is seen that the triplen harmonics get cancelled
automatically in three phase system. It also shows that the THD content of
line currents are 0.41%, 0.39% and 0.39% respectively. The improved
harmonic performance which satisfies the IEEE 519 standard is achieved
using the MPD-SPWM scheme with the modified topology.
Figure 4.16 Line current waveform of modified H-bridge seven level
inverter using MPD-SPWM
82
(a) Harmonic analysis of line current IA
(b) Harmonic analysis of line current IB
(c) Harmonic analysis of line current IC
Figure 4.17 Harmonic analysis of line current waveform for modified
H-bridge seven level inverter using MPD-SPWM
83
Table 4.4 Performance parameters of modified H-bridge seven level
inverter
Modified H-Bridge Seven Level Using
MPD-SPWM
Parameters
Phase Voltage Analysis
Line Voltage Analysis
THD (%)
0.39
0.34
V1 in volts
321.2
556.1
WTHD (%)
0.017
0.0203
DF (%)
0.003
0.005
HF3 (%)
0.016
0.015
HF5 (%)
0.063
0.050
HF7 (%)
0.033
0.011
HF9 (%)
0.029
0.023
HF11 (%)
0.021
0.025
HF13 (%)
0.019
0.020
HF15 (%)
0.070
0.062
HF17 (%)
0.022
0.026
HF19 (%)
0.049
0.009
LOH
NIL
NIL
The performance parameters of modified H-bridge seven level
inverter, operated by MPD-SPWM method is shown in Table 4.4. Odd triplen
harmonics such as HF3, HF9 and HF15 cancelled automatically in three phase
system is demonstrated. For the modified seven level inverter, the value of
THD is very less. It is found that there is no lowest order harmonic in the
modified H-bridge seven level inverter, when it is fed by modified MPDSPWM.
84
4.6
SUMMARY
In this chapter, a detailed analysis of modified H-bridge seven level
inverter topology operated by MPD-SPWM is presented. Switching
sequences of the modified multilevel inverter are clearly explained. A
combination of high switching frequency and fundamental switching
frequency schemes is proposed in this chapter. Performance parameters of the
modified H-bridge seven level inverter and simulation results of proposed
topology with MPD-SPWM scheme are discussed.