International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
Asymmetric Cascaded Multilevel Inverter Using
Submultilevel Cells
P. Alagu Sundari1, S. Dhinakaraj2
1
PG Student, 2Asst professor, Department of Electrical Engineering, Sri Lakshmi Ammal Engineering College, Anna
Unniversity, Chennai, India.
Abstract—Multilevel inverters produce a staircase output
voltage from DC voltage sources. Requiring great number of
semiconductor switches is main disadvantage of multilevel
inverters. The multilevel inverters can be divided in two groups:
symmetric and asymmetric converters. Application of multilevel
inverters for higher power purposes is quite increasing in industries
Because of high-quality output waveform of multilevel inverters
incomparison with two-level inverters, they are becoming more
popular. In this paper, initially a submultilevel cell is proposed and
then series connection of the submultilevel cells are proposed. The
proposed multilevel inverter uses reduced number of switching
devices. The proposed method is developed to obtain optimal
structures regarding different criteria such as number of switches,
standing voltage on the switches, number of dc voltage sources, etc.
Comparative study of symmetric and asymmetric condition of sub
multi level cells was performed. By using FFT analysis harmonic
spectrum was analyzed. The proposed multilevel inverter has been
analyzed in both symmetric and asymmetric conditions.
The NPC multilevel inverter, also called diodeclamped, can be considered the first generation of
multilevel inverter introduced by Nabae et al. [7] which
was a three-level inverter. The three-level case of the
NPC multilevel inverters has been widely applied in
different industries. Unlike the NPC type, the FC
multilevel inverter offers some redundant switching
states that can be used to regulate the capacitors voltage.
However, the control scheme becomes complicated.
Moreover, the number of capacitors increases by
increasing the number of voltage levels.
The CHB multilevel inverters use series-connected Hbridge cells with an isolated dc voltage sources
connected to each cell. The CHB multilevel inverters can
be divided into two groups from the viewpoint of values
of the dc voltage sources: the symmetric and the
asymmetric topology. In the symmetric topology, the
values of all of the dc voltage sources are equal. This
characteristic gives the topology good modularity.
However, the number of the switching devices rapidly
increases by increasing the number of output voltage
level. In order to increase the number of output voltage
level, the values of the dc voltage sources are selected to
be different, these topologies are called asymmetric [8],
[9]. The CHB multilevel inverters have been industrially
employed in several applications fields such as pump,
fans, compressors, etc. In addition, they have recently
been proposed for other applications like photovoltaic
power-conversion system and wind power conversion
[10]. The topologies discussed previously are the
conventional topologies. Many other multilevel inverter
topologies have been introduced in recent years. One of
the topologies is the modular multi-level inverter [11].
This topology is simpler than the cascaded four-switch
H-bridge-based inverter and has several advantages, such
as modular extension to any number of levels and
redundancy [12]. However, the topology does not
consider reduction in the number of components used.
Other multilevel inverter topologies have been
introduced in [13]–[15]. The multilevel inverter based on
symmetric topology and uses series/parallel connection
of the dc voltage sources uses lower number of switches
in comparison with the symmetric CHB multilevel
inverter. The topologies presented in [13] and [14]
consider reduction in the components.
Index Terms—Generalized topology, multilevel inverter, Optimal
structure, submultilevel inverter.
I. INTRODUCTION
Multilevel inverters include an array of power semiconductors and dc voltage sources, the output of which
generate voltages with stepped waveforms [2]. In
comparison with a two-level voltage-source inverter
(VSI), the multilevel VSI enables to synthesize output
voltages with reduced harmonic distortion and lower
electromagnetic interference [3].By increasing the
number of levels in the multilevel inverters, the output
voltages have more steps in generating a staircase
waveform, which has a reduced harmonic distortion.
However,a larger number of levels increase the number
of devices that must be controlled and the control
complexity [4].
Multilevel inverters produce a stepped output phase
voltage with a refined harmonic profile when compared
to a two-level inverter. The concept of multilevel
inverters, introduced about 30 years ago, entails
performing power conversion in multiple voltage steps to
obtain improved power quality, lower switching losses,
better electromagnetic compatibility, and higher voltage
capability. Nowadays, there exist three commercial
topologies of multilevel voltage source inverters:There
are three well-known types of multilevel inverters [5],[6]:
the neutral point clamped (NPC) multilevel inverter, the
flying capacitor (FC) multilevel inverter, and the
cascaded H-bridge (CHB) multilevel inverter.
166
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
These topologies are basically based on asymmetric
topologies; hence, the used dc voltage sources have
different values. However, the number of switching
devices still remains high in these topologies. A ninelevel active NPC inverter has been presented in which is
the modification of the standard active NPC converter.
Nami et al.
This paper proposes a new multilevel inverter
topology using series connected submultilevel inverters.
The proposed multi- level inverter uses reduced number
of switches. Initially, the proposed submulti level inverter
is described and then the series connection of them to
form a multilevel inverter is discussed. The optimal
structures of the proposed multilevel inverter regarding
several factors (e.g., number of switches, number of dc
voltage sources, standing voltage on the switches, etc.)
are also obtained.
The unidirectional switches consist of an insulated
gate bipolar transistor (IGBT) with an antiparallel diode.
The switches S1, S1, S(n +2)/2 , and S(n +2)/2 are
unidirectional and the other switches are bidirectional;
hence, they have to withstand both positive and negative
voltages. For instance, when S(n +2)/2 is turned ON, the
voltage Vdc is on the switch Sn /2 , and if the switch S(n
−2)/2 is turned ON, the voltage equal to −Vdc is on the
switch Sn /2 . The same conditions are valid for the other
switches. Therefore, the switches have to withstand both
positive and negative voltages. In addition, the switches
have to conduct backward current that is as a result of
inductive characteristic of the load. It can be concluded
that the switches must be bidirectional. There are several
circuit configurations for bidirectional switches. In this
study, the common emitter topology is used as it needs
one gate driver for a switch. Considering the types of the
switches, 2n IGBTs are required in the proposed
submultilevel inverter. It is worth mentioning that the
number of the antiparallel diodes is equal to the number
of IGBTs.
The proposed submultilevel inverter can only generate
zero and positive voltage levels. The zero output voltage
is obtained when the switches S1 and S1 are turned ON
simultaneously. The other voltage levels are generated by
proper switching between the switches. Table I shows the
states of the switches for each output voltage value[1]. In
this table, 1 means that the corresponding switch is
turned ON and 0 indicates the OFF state.
Table I
Output Voltages For States Of Switches
Fig.1. Proposed generalized submultilevel inverter.
The reliability of a multilevel inverter is proportional
to the number of its components. Clamping diodes and
balancing capacitors are not needed in the Cascaded SubMultilevel Cells. Another advantage of the Cascaded
Sub-Multilevel Cells is circuit layout flexibility and
modularized circuit layout and packaging is possible in it
same as H-bridge cascaded topology. The number of
output voltage levels can be easily adjusted by changing
the number of sub-multilevel inverters.
II. PROPOSED GENERALISED MULTI LEVEL INVERTER
Considering Fig. 1, for each value of the output
voltage of sub-multilevel inverter, two switches must be
turned ON, one from the upper switches and the other
from the lower switches[1]. For example, to get output
voltage of Vdc , the switches S1 and S2 are turned ON.
In order to obtain the output voltage of (n − 1)Vdc , the
switches Sn /2 and S(n +2)/2 should be turned ON.
Considering Fig. 1, the following equations can be
written:
A. Proposed Submultilevel Inverter
Fig. 1 shows the proposed submultilevel inverter[1].
As depicted in Fig. 1, the topology consists of n dc
voltage sources. In general, the dc voltage sources can
have different values. However, in order to have equal
voltage steps, they are considered to be the same and
equal to Vdc . Each submultilevel inverter consists of n +
2 switches. Some of the switches are unidirectional and
the others are bidirectional.
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Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
For this purpose, an H-bridge inverter is added to the
output of the series connected submultilevel inverters. It
is important to note that the switches of the H-bridge
must withstand higher voltage. This should be considered
in the design of the inverter. However, these switches are
turned ON and OFF once during a fundamental cycle. So,
these switches would be high-voltage low-frequency
switches.
Considering that the multilevel inverter shown in Fig.
2 includes m submultilevel inverter (using (1)–(4) and
considering the H-bridge part), . If n dc voltage sources
are used as shown in Fig. 1, then the number of output
voltage levels (S) and switches (Nsw) are given by the
followingequations, respectively,
Where, Nswitch,sub , Ndriver,sub , NIGBT,sub , and
Nsource,sub are the number of switches, number of
switches drivers in one sub-multilevel inverter, number
of IGBTs in one submultilevel inverter, and number of dc
sources in one submultilevel inverter,respectively.
B. Types of Submultilevel inverter
1) Proposed Symmetric Multilevel Inverter:
For the symmetric multilevel inverter, all of the dc
voltage sources are considered to be equal. Therefore, the
following equations can be written for the symmetric
topology:
The suggested topology operates in symmetric state
and some switches (H-bridge) of suggested topology
have high peak inverse voltage.
Vdc,1 = Vdc,2 = ・ ・ ・ = Vdc,m
2) Proposed Asymmetric Multilevel Inverter:
For the asymmetric topology, the value of the dc
voltage sources is different from a sub multilevel inverter
to another. In other words, if the dc sources of the first
sub multilevel inverter is Vdc,1 , the dc sources of the
second sub multilevel inverter is Vdc,2.
To get
maximum number of level for the output voltage, there
must be no redundancy.
III. SYMMETRIC SUB MULTILEVEL INVERTER
Symmetric sub multilevel inverter circuit diagram is
shown in Fig 3. The circuit diagram consists of thirteen
switches, three symmetric voltage source and a load.
a) Operation for 13 level symmetric inverter
The required thirteen levels of output voltage were
generated as follows:
Mode 1(0Vdc): All the switches will be turned OFF and
all other controlled switches are turn OFF. So no current
flows. The voltage applied to the load terminal is zero
(0).
Mode 2(100Vdc): The switch S1, S2, S5, S6, S13 will be
turned ON and all other controlled switches are turn
OFF. So the current flows path from S5, S1, LOAD, S2,
S13, S6 ,V1(100V),S5. The voltage applied to the load
terminal is 100V.
Mode 3(200Vdc): The switch S1,S2,S5, S7and S13 will
be turned ON and all other controlled switches are turn
OFF. So the current flows path from S5, S1, LOAD, S2,
S13, S7, V2, V1, S5. The voltage applied to the load
terminal is 200V.
Mode 4(300Vdc): The switch S1, S2, S5, S8, and S13
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S1, LOAD,
S2, S13, S8, V3, V2, V1, S5 . The voltage applied to the
load terminal is 300V.
C. Proposed Generalized Multilevel Inverter
The proposed submultilevel inverters can be connected
in series to achieve the desired voltage and number of
voltage levels.
Fig. 2. Proposed general multilevel inverter using series connection
of m proposed submultilevel inverters, each one has n dc voltage
sources.
Fig. 2 shows m submultilevel inverters in series. Each
submultilevel inverter has n dc voltage source[1]. The dc
voltage sources in each submultilevel inverter are equal.
The output voltage of the submultilevel inverters (and
series connection of them) is always positive or zero. To
operate as an inverter, it is necessary to change the
voltage polarity in every half cycle.
168
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Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
Mode 5(400Vdc): The switch S1, S2, S5, S8, S9 and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S1, LOAD,
S2, S10, V4, S9, S8, V3, V2, V1, S5. The voltage applied
to the load terminal is 400V.
Mode 6(500Vdc): The switch S1, S2, S5, S8, S9 and S11
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S1, LOAD,
S2, S11, V5, V4, S8, V3, V2, V1 ,S5. The voltage
applied to the load terminal is 500V.
Similarly for all other modes in negative output
voltages. So, we get output voltages as -400V, 500V, and
-600V.
b) Switching patterns
The table 2. shows the Switching pattern of 13 level
inverter for a proposed Symmetric Multilevel inverter
system.
Table 2.
Switching pattern for Symmetric Sub MLI
Symmetric Sub Multi Level Inverter
Fig 3 Circuit diagram of symmetric sub multilevel inverter
Mode 7(600Vdc): The switch S1, S2, S5, S8, S9 and S12
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S1, LOAD,
S2, S12, V6, V5, V4, S9, S8, V3, V2, V1, S5. The
voltage applied to the load terminal is 600V.
Mode 8(-100Vdc): The switch S3, S4, S5, S6, and S13
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S3, LOAD,
S4, S13, S6 ,V1(100V),S5. The voltage applied to the
load terminal is -100V.
Mode 9(-200Vdc): The switch S3,S4 ,S5, S7and S13 will
be turned ON and all other controlled switches are turn
OFF. So the current flows path from S5, S3, LOAD, S4,
S13, S7, V2, V1, S5. The voltage applied to the load
terminal is -200V.
Mode 10(-300Vdc): The switch S3,S4, S5, S8, and S13
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S3, LOAD,
S4, S13, S8, V3, V2, V1 ,S5. The voltage applied to the
load terminal is -300V.
S
S
S
S
S
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
9
10
11
12
13
Voltage
Level(v)
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
100
1
1
0
0
1
0
1
0
0
0
0
0
1
200
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
300
400
500
1
1
0
0
1
0
0
1
1
0
0
1
0
600
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
500
400
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
300
200
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
100
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
-100
-200
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
0
-300
-400
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
-500
-600
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
-500
-400
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
-300
-200
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-100
0
IV. ASYMMETRIC CASCADED MULTI LEVEL INVERTER
Asymmetric sub multilevel inverter circuit diagram is
shown in Fig 4. The circuit diagram consists of ten
switches, three asymmetric voltage source and a load.
169
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
a) Operation for 13 level asymmetric inverter
The required thirteen levels of output voltage were
generated as follows:
Mode 1(0Vdc): All the switches will be turned OFF and
all other controlled switches are turn OFF. So no current
flows. The voltage applied to the load terminal is zero
(0).
Mode 2(100Vdc): The switch S1, S2, S5, S8, and S9 will
be turned ON and all other controlled switches are turn
OFF. So the current flows path from S5, S1, LOAD, S2,
S9, S8, VDC(100V),S5. The voltage applied to the load
terminal is 100V.
Mode 8(-100Vdc): The switch S3, S4, S5, S8, and S9
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S5, S3, LOAD,
S4, S9, S8, VDC(100V),S5. The voltage applied to the
load terminal is -100V.
Mode 9(-200Vdc): The switch S3, S4, S6, S7and S9 will
be turned ON and all other controlled switches are turn
OFF. So the current flows path from S6, S3, LOAD, S4,
S9, 2VDC, S7, S6. The voltage applied to the load
terminal is -200V.
Mode 10(-300Vdc): The switch S3, S4, S6, S8, and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S6, S3, LOAD,
S4,S10, 3VDC,S8,S6 .The voltage applied to the load
terminal is -300V.
Similarly for all other modes in negative output
voltages. So, we get output voltages as -400V,-500V, and
-600V.
b) Switching patterns
The table 3 shows the Switching pattern of 13 level
Asymmetric inverter for a proposed Multilevel inverter
system.
Table 3.
Switching pattern for Symmetric Sub MLI
Asymmetric sub multi level inverter
Fig 4. Circuit diagram of Asymmetric sub multilevel inverter
Mode 3(200Vdc): The switch S1,S2,S6, S7and S9 will be
turned ON and all other controlled switches are turn
OFF. So the current flows path from S6, S1, LOAD,
S2,9,2VDC,S7,S6. The voltage applied to the load
terminal is 200V.
Mode 4(300Vdc): The switch S1, S2, S6, S8, and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S6, S1, LOAD,
S2,S10, 3VDC,S8,S6 .The voltage applied to the load
terminal is 300V.
Mode 5(400Vdc): The switch S1, S2, S5, S8, and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path S5, S1, LOAD, S2,
S10,3VDC,S8,VDC,S5..The voltage applied to the load
terminal is 400V.
Mode 6(500Vdc): The switch S1, S2, S6, S7, and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from S6, S1, LOAD,
S2, S10,3VDC,2VDC,S7,S6. The voltage applied to the
load terminal is 500V.
Mode 7(600Vdc): The switch S1, S2, S5, S7, and S10
will be turned ON and all other controlled switches are
turn OFF. So the current flows path from
S5,S1,LOAD,S2,S10,3VDC,2VDC,VDC,S5.
The
voltage applied to the load terminal is 600V.
170
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
Voltage
Level (v)
0
100
200
300
400
500
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-500
-400
-300
-200
0
0
1
1
1
0
0
1
1
0
-100
0
0
0
0
0
0
0
0
0
0
0
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Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014)
Pulse generation
V. SIMULATION RESULTS
MATLAB is an interactive system whose basic data
element is an array that does not require dimensioning.
This allows you to solve many technical computing
problems, especially those with matrix and vector
formulations, in a fraction of the time it would take to
write a program in a scalar non interactive language such
as C or Fortran.
The name MATLAB stands for matrix laboratory.
MATLAB was originally written to provide easy access
to matrix software developed by the LINPACK and
EISPACK projects. Today, MATLAB engines
incorporate the LAPACK and BLAS libraries,
embedding the state of the art in software for matrix
computation
MATLAB has evolved over a period of years with
input from many users. In university environments, it is
the standard instructional tool for introductory and
advanced courses in mathematics, engineering, and
science. In industry, MATLAB is the tool of choice for
high-productivity research, development, and analysis.
Fig5 b) pulse generation
Proposed symmetric sub multi level inverter:
Fig.5b) shows the simulated gate Triggering pulses,
which is measured by connecting a single scope
measurement.
Circuit diagram:
Using MATLAB 7.3, the proposed inverter is drawn in
a model file as shown in the Fig.5a) and the
semiconductor devices are operated as per the switching
sequence obtained as discussed in the previous chapter.
component values are chosen based on the design
requirement.
Output voltage of symmetric 13-level inverter
Fig. 5c) shows the simulated output voltage, which is
measured across the output of resistive loads by
connecting a voltage measurement with scope.
Fig.5 c) output voltage waveform
FFT analysis
By using multilevel inverter the even harmonics are
eliminated due to its symmetrical. And odd harmonics
are reduced and input cycle is taken as five for a 50HZ
supply.
Fig.5 a) Simulation Diagram of sub multi thirteen-Level Inverter
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Pulse generation
Fig.5 d) FFT analysis
As shown in the fig.5d), the total harmonics distortion
is 14.05% for symmetric sub multi inverter. In
comparison of cascaded and symmetric MLI, the THD
value is minimized.
Proposed asymmetric sub multilevel inverter
Circuit diagram
Fig.6 b) pulse generation
Fig.6b) shows the simulated gate Triggering pulses,
which is measured by connecting a single scope
measurement.
Output voltage of asymmetric 13-level inverter
Fig.6c) shows the simulated output voltage, which is
measured across the output of resistive loads by
connecting a voltage measurement with scope.
Fig.6 c) output voltage waveform
Fig.6 a) Simulation Diagram of a Asymmetric sub multi thirteenLevel Inverter
FFT analysis
By using multilevel inverter the even harmonics are
eliminated due to its symmetrical. And odd harmonics are
reduced and input cycle is taken as five for a 50HZ
supply.
Using MATLAB 7.3, the proposed inverter is drawn in
a model file as shown in the Fig.6a) and the
semiconductor devices are operated as per the switching
sequence obtained as discussed in the previous chapter.
Component values are chosen based on the design
requirement.
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[1]
Fig.6 d) FFT analysis
As shown in the fig.6d), the total harmonics distortion
is 13.83% for asymmetric sub multi inverter. In
comparison of symmetric and asymmetric MLI, the THD
value is minimized.
VI. CONCLUSION
Multilevel inverters are very interesting for high
voltage applications, energy conversion and considerably
improve the output voltage quality. This paper has
proposed a new topology of the cascaded converter
called Cascaded Sub-Multilevel Cells. The main
advantages of the Cascaded Sub-Multilevel Cells are:
 improve the output voltage quality
 reduced number of switching devices
 operates in symmetric an asymmetric states
 small on-state voltage drop and conduction losses
 reduction of dv/dt stresses on the load
Comparison between the conventional topologies of
multilevel inverters and the proposed multilevel inverter
is shown in this paper. In comparison with cascaded and
sub multilevel inverters produce greater number of output
voltage level with less dc sources and less switching
devices. As with asymmetric condition, sub multilevel
inverter produce more output voltages than any other
multilevel inverter. Simulation results exhibit the good
performance and feasibility of the proposed topology.
Harmonics produced also less with this method. This
makes the submulti level inverter more economic.
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