Active Device Modeling flow
: standard to specific
Content
Introduction : A wide panel of Technologies from RF to
mmWave applications
Flow of Modeling and Characterizations
Specific cases of modeling linked to technology
Status & Perspectives
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Content
Introduction : A wide panel of Technologies from RF to
mmWave applications
Flow of Modeling and Characterizations
Specific cases of modeling linked to technology
Status & Perspectives
Keysight tour
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Roadmap – Technology Portfolio – Version 07/2014
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A large panel of technologies with
different modeling objectives ....
An important panel of Technologies
Bipolar HBT / Field Effect HEMT
GaAs based / GaN based
Different range of voltages (up to 250V), current (pA to A)
Low to High periphery (gate / emitter developpment)
Low noise (RF) to High Power technologies
Linearity – different formats (AM-AM / AM-PM / IM3 / NPR / ......
From 1 to 100 GHz
Requires a large diversity of equipment for characterizations and
software
Requires different modeling approaches or class of models
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Modelling Flow
Flow applied during the process development, specific model
extension ....
Validations
Model extraction
1. Data/model @Device
Characterization
Linear/Noise/Non
model
Linear
2. Data/simulation @circuit
level
6,60
Pout(dBm) vs load
5,60
4,60
3,60
-1
2,60
Intrinsec
1,60
Parasitics
0,60
1
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0
1
Characterization Capabilities (1)
Internal
On wafer pulsed [IV+Sij PNA-X] Auriga & AMCAD systems
On wafer Load Pull [2-18] & [8-50] GHz on automatic prober
& thermal chuck
Subcontractors (MC² Technologies, AMCAD…., Academic partners in Eu)
Noise Multi-impedance [0.5-4GHz] and [4-40 GHz]
2 Tone Load Pull (linearity)
1 Tone > 60 GHz
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Characterization Capabilities (2)
Pulsed I-V & S-Parameters technique for Non Linear Modelling
A fast pulse with a low duty cycle is used to move gate and drain biases
from a chosen steady quiescent bias to another point on the I-V plane
S-Parameters measurements are performed in pulses
2 to 40 GHz
It is closer to the operational behaviour
2 to 40 GHz
The thermal and traps conditions are set by the
quiescent bias condition
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Model Extraction (1)
PHEMT non-linear models are based on equivalent circuit approach, which takes
into account the following features :
Equivalent circuit non-linear sources : Ids(Vgs,Vds), Igs and Igd deduced from pulse
measurements ( avoiding thermal and trapping effects ), Cgs and Cgd intrinsic capacitances
extracted from [S] parameters at different working points
UMS develops its own set of equation to describe the Non-linearities
Small signal behaviour : parasitic elements deduced from [S] measurements
Scalable model ( gate length and number of gate fingers )
Model separated in 2 zones ( hot and cold mode ) to improve accuracy
Process spread ( Vt, Rs, Rd...)
Note: Please keep in mind that each model has its validity domain
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Model Extraction (2)
1st step: Extraction of parasitic elements
From cold FET method
Only forward and reverse gate bias S[ij] measurements @Vds=0V are used
Extraction of scaling rules
2nd step: Determination of intrinsic elements
Ids (A)
Non-linear sources : Ids(Vgs,Vds), Igs and Igd deduced from pulse
Non-linear capacitances: Cgs and Cgd extracted from [S] parameters at different working
points
Scalable model (gate length and number of gate fingers)
Implementation of process spread
Vds (V)
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Validation at transistor level
3rd step: Data/Model comparison
Small Signal S-parameters
IV Curves
S12 & S21
S11 & S22
Power Measurement
Power Gain
PAE
Pout
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Complements
Thermal Modeling / Thermal Characterizations
3D Thermal Software + Physical 2D dissipating volume
Measurement : Raman, Infra-Red, ....
Approach
Thermal dependency of the electrical circuit is managed by a RC
network in feedback.
Compromise complexity / accuracy
The R (Thermal resistance) represents the hot spot and not an average
value.
Electro-Magnetic simulation
Use to get a better determination of the parasitics
3D finite element software
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EuMW2013
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Librairies Overview - ADS
The library is a pack of basic element models suitable to design different MMIC
functions such as :
oscillators
phases shifters / attenuators
mixers
amplifiers etc..
Library includes 2 main types of components :
Passive components
Spiral inductors, MIM Capacitors, Microstrip lines, resistors
Active components
Fets, Schottky diodes, parallel and series switches
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Validation at circuit level
Ku Band 3 stage Power Amplifier
S Parameters results: Data/simulation [10 et 18GHz]
S21 (dB)
Simulation with Non-linear Model
Simulation with data file
Data
S22 (dB)
S11 (dB)
Power results: Data/simulation [11 et 17GHz]
Pout
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PAE
Gain
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Content
Introduction : A wide panel of Technologies from RF to
mmWave applications
Flow of Modeling and Characterizations
Specific cases of modeling linked to technology
Status & Perspectives
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GH25-10 Process Development
GH25-10
Full 4 inches power MMIC Technology
Up to 25 GHz
Vds=30V – Operating Voltage
Tj = 200°C
Power density > 4W/mm @ 10 GHz
Nf = 1.7 dB @ 10 GHz
Qualified in October 2014
Modeling
ADS / AWR Design Kits
Measure your hand… it is really 100mm!
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GH25-10 Technology : Devices &
specific electrical behavior
Modeling applied to High Power Technology
Families of models have to address multiple scenarios of use :
Main applications
HPA : CW (linear to compression) and Pulsed (radar) modes
Scalable with medium to high gate periphery development
Models accurate around the recommended operating voltage 30V
Optimums in PAE, Pout, C/I
Temperature dependency (first level)
LNA : CW mode
Transistors
Transistors
Models accurate for appropriate biasing point
Non- linear including noise source
Minimum of Noise found from 10 to 15V associated to medium current density
Small gate periphery development
2 and 3 ports model
Switch
Transistor
Cold FET operation
Specific : Limiter, Mixer, Biasing circuit
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Diode
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Modeling
More complex than GaAs PHEMT
.... Improvement will be considered step by step
Trapping ..... many effects
Pulsed : Long to Short time constant to be considered.
Trapping state : Strongly dependant of the biasing (class), temperature and
period.
Radar (pulsed) : Sensitive to recovery time in between pulsed. No significant
effect observed during the rising time. ” AB becomes B”
CW : Long time constant to be considered
Recovery time after
Linear Power gain walk-out has an influence on the C/I
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Trapping : effect in between pulses
8x75 transistor
10µs pulse length
Effect of compression
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EuMW2013
Time for recovery
in the range off 20 ms
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GaN HEMT & Trapping effect
Disadvantages of widebandgap semiconductor : Locations of
trapping centers
Source of RF limitations
Trapping with very different trapping time constant
From ns to minutes different models !!??
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Transistor Models: NL Hot-FET model
New equations had been developed and implemented
Better accuracy of the source current derivatives (gm/gd) over large
values of Vgs and Vds and operating points (most challenging point to
achieve)
New set of charge equations had been developed to improve the
description from the model of the charge variation over the gate and
drain voltages.
Better consistency between these charge equations and the capacitances and
time delay describing the standard equivalent schematic of a transistor
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Transistor Models: NL Hot-FET model
Model Validation
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Transistor Models: NL Hot-FET model
Small signal model validation for different sizes of transistors
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Transistor Models: NL Hot-FET model
Non-linear Model Validation
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Electro-thermal model : how to do ?
The approach of the electrothermal modeling
Dissipated
power
Channel
temperature
Electrical parts concern by the thermal modeling
Ids current equations were modified to include the thermal dependence
and to fit the pulsed IV measurements
Rs & Rd resistances integrate a thermal dependence
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New Electro-thermal model validation
Tc=30°C
Tc=80°C
Tc=125°C
Blue = Measurements
Red = Simulations
8x125 µm
Ids=110 mA/mm,
Vds=25 V
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Status and perspectives
Type of models extracted :
Linear
Noise
Non-Linear (Hot and Cold modes)
Development of proprietary non-linear equations
GaN HEMT models are very challenging
Future developments
Work on Linearity prediction improvement
Active load-pull tuning up to Ka Band
Electro-thermal aspects(Simulation/Measurement)
Coupling
Models with multi-time trapping constant
Models including reliability degradation laws (“time” dependent)
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Introduction – Millimeter wave Technology
for Telecom applications
Increase of Smartphone
users
Capacity improvement of point-topoint communications
The ever-growing demand
for greater data rates
E-band wireless systems offer the best alternative to buried fiber:
Low cost installation compare to buried fiber optics
High data rates (>1Gbits/s) with guaranteed data rates
100
10
Long distance transmissions: the attenuation
of E-Band frequencies is
around 0.5dB/km close to 38GHz systems
Current point-to-point
radio frequencies
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Attenuation (dB)
1
E-band
frequencies
0.1
0.01
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10
20
30
50 70 100
200 300
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Frequency (GHz)
PH10 Technology – mmWave
applications
Technology summary - GaAs PHEMT – PH10 – 0.1µm gate length
InGaAs/GaAs pseudomorphic-heterostructure
0.1µm gate length
4 inch substrate
T-shaped aluminum gate
Individual source vias
2 metallization layers
Optional protective coating
Hot via option for back side connections
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Specific modelling approach
PH10 process has been developed to be used up to 110GHz
After 40GHz, on wafer characterization at transistor level is
complex
The bench setup at high frequencies becomes difficult →
waveguides use
Calibration and deembedding are tricky
Full band measurement is complicated; limitation due to the
available hardware (Tuners, connecters, bias T …)
Measurement sensitivity to the environment on the wafer itself
Difficulty to get reliable measurement
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Extrapolation method
: from low
to high frequencies
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Modelling approach & Modelling flow
UMS pHEMT non-linear model is based on equivalent circuit
approach
Characterization
Using 2 to 40GHz
measurement
Validations
Model extraction
NL+Noise
1. Data/model up to 40GHz
2. Data/simulation @circuit
level in E-band
PH10 nonnon-linear model
In order to simplify design phase, we decided to make an unique
non linear model including thermal noise
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Modelling approach – model extraction
1st step: Extraction of parasitic elements
From cold FET method
Only forward and reverse gate bias S[ij] measurements @Vds=0V are used
Extraction of scaling rules
2nd step: Determination of intrinsic elements
Non-linear sources : Ids(Vgs,Vds), Igs and Igd deduced from pulse
Non-linear capacitances: Cgs and Cgd extracted from [S] parameters at different working
points
Scalable model (gate length and number of gate fingers)
Implementation of process spread rules
Bias validity domain
Example of pulsed I-V characteristics for a 4x30µm device
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Modelling approach – Modelling
extension
3rd step: Noise model implementation
Thermal noise modelled with 2 correlated current sources
Ids, Gm and Cgs are directly calculated in the non-linear model
ω2
⟨ing ⟩ = 4 ⋅ k ⋅ T ⋅ Cgs ⋅
⋅ R ⋅ ∆f
Gm
2
2
C=
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⟨ind 2⟩ = 4 ⋅ k ⋅ T ⋅ Ids ⋅ P ⋅ ∆f
⟨ig ⋅ id ⟩
⟨id 2⟩⟨ig 2 ⟩
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Modelling approach / extraction
Model validation at transistor level
Small signal behaviour checked through S-parameter up to 40GHz at nominal bias point
S11 & S22
S12 & S21
Load-pull measurement at 35GHz
Our NL model shows a
good agreement for low
frequency
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MMIC design – model validation in
mmWave
Retro simulations analysis shown a good agreement between meas. and
simulation
Replacing the model by S-parameter measurement for each stage,
simulation is far from measurement
This is the evidence of difficulty we have to obtain clean measurement at
transistors level
MMIC Meas.
Model NL LF
MMIC Simulation with
transistors
measurements inside
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